1 files changed, 54 insertions, 0 deletions
diff --git a/arch/powerpc/include/uapi/asm/kvm.h b/arch/powerpc/include/uapi/asm/kvm.h
index 0fb1a6e9ff90..7ed41c0b4045 100644
--- a/arch/powerpc/include/uapi/asm/kvm.h
+++ b/arch/powerpc/include/uapi/asm/kvm.h
@@ -429,6 +429,11 @@ struct kvm_get_htab_header {
 #define KVM_REG_PPC_MMCR0       (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x10)
 #define KVM_REG_PPC_MMCR1       (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x11)
 #define KVM_REG_PPC_MMCRA       (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x12)
+#define KVM_REG_PPC_MMCR2       (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x13)
+#define KVM_REG_PPC_MMCRS       (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x14)
+#define KVM_REG_PPC_SIAR        (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x15)
+#define KVM_REG_PPC_SDAR        (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x16)
+#define KVM_REG_PPC_SIER        (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x17)
 #define KVM_REG_PPC_PMC1        (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x18)
 #define KVM_REG_PPC_PMC2        (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x19)
@@ -499,6 +504,55 @@ struct kvm_get_htab_header {
 #define KVM_REG_PPC_TLB3PS      (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x9a)
 #define KVM_REG_PPC_EPTCFG      (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x9b)
+/* POWER8 registers */
+#define KVM_REG_PPC_SPMC1       (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x9d)
+#define KVM_REG_PPC_SPMC2       (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x9e)
+#define KVM_REG_PPC_IAMR        (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x9f)
+#define KVM_REG_PPC_TFHAR       (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xa0)
+#define KVM_REG_PPC_TFIAR       (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xa1)
+#define KVM_REG_PPC_TEXASR      (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xa2)
+#define KVM_REG_PPC_FSCR        (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xa3)
+#define KVM_REG_PPC_PSPB        (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0xa4)
+#define KVM_REG_PPC_EBBHR       (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xa5)
+#define KVM_REG_PPC_EBBRR       (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xa6)
+#define KVM_REG_PPC_BESCR       (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xa7)
+#define KVM_REG_PPC_TAR         (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xa8)
+#define KVM_REG_PPC_DPDES       (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xa9)
+#define KVM_REG_PPC_DAWR        (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xaa)
+#define KVM_REG_PPC_DAWRX       (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xab)
+#define KVM_REG_PPC_CIABR       (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xac)
+#define KVM_REG_PPC_IC          (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xad)
+#define KVM_REG_PPC_VTB         (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xae)
+#define KVM_REG_PPC_CSIGR       (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xaf)
+#define KVM_REG_PPC_TACR        (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xb0)
+#define KVM_REG_PPC_TCSCR       (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xb1)
+#define KVM_REG_PPC_PID         (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xb2)
+#define KVM_REG_PPC_ACOP        (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xb3)
+/* Transactional Memory checkpointed state:
+ * This is all GPRs, all VSX regs and a subset of SPRs
+ */
+#define KVM_REG_PPC_TM          (KVM_REG_PPC | 0x80000000)
+/* TM GPRs */
+#define KVM_REG_PPC_TM_GPR0     (KVM_REG_PPC_TM | KVM_REG_SIZE_U64 | 0)
+#define KVM_REG_PPC_TM_GPR(n)   (KVM_REG_PPC_TM_GPR0 + (n))
+#define KVM_REG_PPC_TM_GPR31    (KVM_REG_PPC_TM | KVM_REG_SIZE_U64 | 0x1f)
+/* TM VSX */
+#define KVM_REG_PPC_TM_VSR0     (KVM_REG_PPC_TM | KVM_REG_SIZE_U128 | 0x20)
+#define KVM_REG_PPC_TM_VSR(n)   (KVM_REG_PPC_TM_VSR0 + (n))
+#define KVM_REG_PPC_TM_VSR63    (KVM_REG_PPC_TM | KVM_REG_SIZE_U128 | 0x5f)
+/* TM SPRS */
+#define KVM_REG_PPC_TM_CR       (KVM_REG_PPC_TM | KVM_REG_SIZE_U64 | 0x60)
+#define KVM_REG_PPC_TM_LR       (KVM_REG_PPC_TM | KVM_REG_SIZE_U64 | 0x61)
+#define KVM_REG_PPC_TM_CTR      (KVM_REG_PPC_TM | KVM_REG_SIZE_U64 | 0x62)
+#define KVM_REG_PPC_TM_FPSCR    (KVM_REG_PPC_TM | KVM_REG_SIZE_U64 | 0x63)
+#define KVM_REG_PPC_TM_AMR      (KVM_REG_PPC_TM | KVM_REG_SIZE_U64 | 0x64)
+#define KVM_REG_PPC_TM_PPR      (KVM_REG_PPC_TM | KVM_REG_SIZE_U64 | 0x65)
+#define KVM_REG_PPC_TM_VRSAVE   (KVM_REG_PPC_TM | KVM_REG_SIZE_U64 | 0x66)
+#define KVM_REG_PPC_TM_VSCR     (KVM_REG_PPC_TM | KVM_REG_SIZE_U32 | 0x67)
+#define KVM_REG_PPC_TM_DSCR     (KVM_REG_PPC_TM | KVM_REG_SIZE_U64 | 0x68)
+#define KVM_REG_PPC_TM_TAR      (KVM_REG_PPC_TM | KVM_REG_SIZE_U64 | 0x69)
 /* PPC64 eXternal Interrupt Controller Specification */
 #define KVM_DEV_XICS_GRP_SOURCES        1       /* 64-bit source attributes */

diff --git a/arch/powerpc/include/uapi/asm/kvm.h b/arch/powerpc/include/uapi/asm/kvm.h index 0fb1a6e9ff90..7ed41c0b4045 100644 --- a/arch/powerpc/include/uapi/asm/kvm.h +++ b/arch/powerpc/include/uapi/asm/kvm.h
@@ -429,6 +429,11 @@ struct kvm_get_htab_header {
429	#define KVM_REG_PPC_MMCR0 (KVM_REG_PPC \| KVM_REG_SIZE_U64 \| 0x10)	429	#define KVM_REG_PPC_MMCR0 (KVM_REG_PPC \| KVM_REG_SIZE_U64 \| 0x10)
430	#define KVM_REG_PPC_MMCR1 (KVM_REG_PPC \| KVM_REG_SIZE_U64 \| 0x11)	430	#define KVM_REG_PPC_MMCR1 (KVM_REG_PPC \| KVM_REG_SIZE_U64 \| 0x11)
431	#define KVM_REG_PPC_MMCRA (KVM_REG_PPC \| KVM_REG_SIZE_U64 \| 0x12)	431	#define KVM_REG_PPC_MMCRA (KVM_REG_PPC \| KVM_REG_SIZE_U64 \| 0x12)
		432	#define KVM_REG_PPC_MMCR2 (KVM_REG_PPC \| KVM_REG_SIZE_U64 \| 0x13)
		433	#define KVM_REG_PPC_MMCRS (KVM_REG_PPC \| KVM_REG_SIZE_U64 \| 0x14)
		434	#define KVM_REG_PPC_SIAR (KVM_REG_PPC \| KVM_REG_SIZE_U64 \| 0x15)
		435	#define KVM_REG_PPC_SDAR (KVM_REG_PPC \| KVM_REG_SIZE_U64 \| 0x16)
		436	#define KVM_REG_PPC_SIER (KVM_REG_PPC \| KVM_REG_SIZE_U64 \| 0x17)
432		437
433	#define KVM_REG_PPC_PMC1 (KVM_REG_PPC \| KVM_REG_SIZE_U32 \| 0x18)	438	#define KVM_REG_PPC_PMC1 (KVM_REG_PPC \| KVM_REG_SIZE_U32 \| 0x18)
434	#define KVM_REG_PPC_PMC2 (KVM_REG_PPC \| KVM_REG_SIZE_U32 \| 0x19)	439	#define KVM_REG_PPC_PMC2 (KVM_REG_PPC \| KVM_REG_SIZE_U32 \| 0x19)
@@ -499,6 +504,55 @@ struct kvm_get_htab_header {
499	#define KVM_REG_PPC_TLB3PS (KVM_REG_PPC \| KVM_REG_SIZE_U32 \| 0x9a)	504	#define KVM_REG_PPC_TLB3PS (KVM_REG_PPC \| KVM_REG_SIZE_U32 \| 0x9a)
500	#define KVM_REG_PPC_EPTCFG (KVM_REG_PPC \| KVM_REG_SIZE_U32 \| 0x9b)	505	#define KVM_REG_PPC_EPTCFG (KVM_REG_PPC \| KVM_REG_SIZE_U32 \| 0x9b)
501		506
		507	/* POWER8 registers */
		508	#define KVM_REG_PPC_SPMC1 (KVM_REG_PPC \| KVM_REG_SIZE_U32 \| 0x9d)
		509	#define KVM_REG_PPC_SPMC2 (KVM_REG_PPC \| KVM_REG_SIZE_U32 \| 0x9e)
		510	#define KVM_REG_PPC_IAMR (KVM_REG_PPC \| KVM_REG_SIZE_U64 \| 0x9f)
		511	#define KVM_REG_PPC_TFHAR (KVM_REG_PPC \| KVM_REG_SIZE_U64 \| 0xa0)
		512	#define KVM_REG_PPC_TFIAR (KVM_REG_PPC \| KVM_REG_SIZE_U64 \| 0xa1)
		513	#define KVM_REG_PPC_TEXASR (KVM_REG_PPC \| KVM_REG_SIZE_U64 \| 0xa2)
		514	#define KVM_REG_PPC_FSCR (KVM_REG_PPC \| KVM_REG_SIZE_U64 \| 0xa3)
		515	#define KVM_REG_PPC_PSPB (KVM_REG_PPC \| KVM_REG_SIZE_U32 \| 0xa4)
		516	#define KVM_REG_PPC_EBBHR (KVM_REG_PPC \| KVM_REG_SIZE_U64 \| 0xa5)
		517	#define KVM_REG_PPC_EBBRR (KVM_REG_PPC \| KVM_REG_SIZE_U64 \| 0xa6)
		518	#define KVM_REG_PPC_BESCR (KVM_REG_PPC \| KVM_REG_SIZE_U64 \| 0xa7)
		519	#define KVM_REG_PPC_TAR (KVM_REG_PPC \| KVM_REG_SIZE_U64 \| 0xa8)
		520	#define KVM_REG_PPC_DPDES (KVM_REG_PPC \| KVM_REG_SIZE_U64 \| 0xa9)
		521	#define KVM_REG_PPC_DAWR (KVM_REG_PPC \| KVM_REG_SIZE_U64 \| 0xaa)
		522	#define KVM_REG_PPC_DAWRX (KVM_REG_PPC \| KVM_REG_SIZE_U64 \| 0xab)
		523	#define KVM_REG_PPC_CIABR (KVM_REG_PPC \| KVM_REG_SIZE_U64 \| 0xac)
		524	#define KVM_REG_PPC_IC (KVM_REG_PPC \| KVM_REG_SIZE_U64 \| 0xad)
		525	#define KVM_REG_PPC_VTB (KVM_REG_PPC \| KVM_REG_SIZE_U64 \| 0xae)
		526	#define KVM_REG_PPC_CSIGR (KVM_REG_PPC \| KVM_REG_SIZE_U64 \| 0xaf)
		527	#define KVM_REG_PPC_TACR (KVM_REG_PPC \| KVM_REG_SIZE_U64 \| 0xb0)
		528	#define KVM_REG_PPC_TCSCR (KVM_REG_PPC \| KVM_REG_SIZE_U64 \| 0xb1)
		529	#define KVM_REG_PPC_PID (KVM_REG_PPC \| KVM_REG_SIZE_U64 \| 0xb2)
		530	#define KVM_REG_PPC_ACOP (KVM_REG_PPC \| KVM_REG_SIZE_U64 \| 0xb3)
		531
		532	/* Transactional Memory checkpointed state:
		533	* This is all GPRs, all VSX regs and a subset of SPRs
		534	*/
		535	#define KVM_REG_PPC_TM (KVM_REG_PPC \| 0x80000000)
		536	/* TM GPRs */
		537	#define KVM_REG_PPC_TM_GPR0 (KVM_REG_PPC_TM \| KVM_REG_SIZE_U64 \| 0)
		538	#define KVM_REG_PPC_TM_GPR(n) (KVM_REG_PPC_TM_GPR0 + (n))
		539	#define KVM_REG_PPC_TM_GPR31 (KVM_REG_PPC_TM \| KVM_REG_SIZE_U64 \| 0x1f)
		540	/* TM VSX */
		541	#define KVM_REG_PPC_TM_VSR0 (KVM_REG_PPC_TM \| KVM_REG_SIZE_U128 \| 0x20)
		542	#define KVM_REG_PPC_TM_VSR(n) (KVM_REG_PPC_TM_VSR0 + (n))
		543	#define KVM_REG_PPC_TM_VSR63 (KVM_REG_PPC_TM \| KVM_REG_SIZE_U128 \| 0x5f)
		544	/* TM SPRS */
		545	#define KVM_REG_PPC_TM_CR (KVM_REG_PPC_TM \| KVM_REG_SIZE_U64 \| 0x60)
		546	#define KVM_REG_PPC_TM_LR (KVM_REG_PPC_TM \| KVM_REG_SIZE_U64 \| 0x61)
		547	#define KVM_REG_PPC_TM_CTR (KVM_REG_PPC_TM \| KVM_REG_SIZE_U64 \| 0x62)
		548	#define KVM_REG_PPC_TM_FPSCR (KVM_REG_PPC_TM \| KVM_REG_SIZE_U64 \| 0x63)
		549	#define KVM_REG_PPC_TM_AMR (KVM_REG_PPC_TM \| KVM_REG_SIZE_U64 \| 0x64)
		550	#define KVM_REG_PPC_TM_PPR (KVM_REG_PPC_TM \| KVM_REG_SIZE_U64 \| 0x65)
		551	#define KVM_REG_PPC_TM_VRSAVE (KVM_REG_PPC_TM \| KVM_REG_SIZE_U64 \| 0x66)
		552	#define KVM_REG_PPC_TM_VSCR (KVM_REG_PPC_TM \| KVM_REG_SIZE_U32 \| 0x67)
		553	#define KVM_REG_PPC_TM_DSCR (KVM_REG_PPC_TM \| KVM_REG_SIZE_U64 \| 0x68)
		554	#define KVM_REG_PPC_TM_TAR (KVM_REG_PPC_TM \| KVM_REG_SIZE_U64 \| 0x69)
		555
502	/* PPC64 eXternal Interrupt Controller Specification */	556	/* PPC64 eXternal Interrupt Controller Specification */
503	#define KVM_DEV_XICS_GRP_SOURCES 1 /* 64-bit source attributes */	557	#define KVM_DEV_XICS_GRP_SOURCES 1 /* 64-bit source attributes */
504		558