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-rw-r--r--arch/powerpc/kernel/misc_32.S23
1 files changed, 1 insertions, 22 deletions
diff --git a/arch/powerpc/kernel/misc_32.S b/arch/powerpc/kernel/misc_32.S
index 3bedb532aed9..f6d84a75ed26 100644
--- a/arch/powerpc/kernel/misc_32.S
+++ b/arch/powerpc/kernel/misc_32.S
@@ -519,7 +519,7 @@ END_FTR_SECTION_IFCLR(CPU_FTR_SPLIT_ID_CACHE)
519 * 519 *
520 * flush_icache_range(unsigned long start, unsigned long stop) 520 * flush_icache_range(unsigned long start, unsigned long stop)
521 */ 521 */
522_GLOBAL(flush_icache_range) 522_GLOBAL(__flush_icache_range)
523BEGIN_FTR_SECTION 523BEGIN_FTR_SECTION
524 blr /* for 601, do nothing */ 524 blr /* for 601, do nothing */
525END_FTR_SECTION_IFCLR(CPU_FTR_SPLIT_ID_CACHE) 525END_FTR_SECTION_IFCLR(CPU_FTR_SPLIT_ID_CACHE)
@@ -607,27 +607,6 @@ _GLOBAL(invalidate_dcache_range)
607 sync /* wait for dcbi's to get to ram */ 607 sync /* wait for dcbi's to get to ram */
608 blr 608 blr
609 609
610#ifdef CONFIG_NOT_COHERENT_CACHE
611/*
612 * 40x cores have 8K or 16K dcache and 32 byte line size.
613 * 44x has a 32K dcache and 32 byte line size.
614 * 8xx has 1, 2, 4, 8K variants.
615 * For now, cover the worst case of the 44x.
616 * Must be called with external interrupts disabled.
617 */
618#define CACHE_NWAYS 64
619#define CACHE_NLINES 16
620
621_GLOBAL(flush_dcache_all)
622 li r4, (2 * CACHE_NWAYS * CACHE_NLINES)
623 mtctr r4
624 lis r5, KERNELBASE@h
6251: lwz r3, 0(r5) /* Load one word from every line */
626 addi r5, r5, L1_CACHE_BYTES
627 bdnz 1b
628 blr
629#endif /* CONFIG_NOT_COHERENT_CACHE */
630
631/* 610/*
632 * Flush a particular page from the data cache to RAM. 611 * Flush a particular page from the data cache to RAM.
633 * Note: this is necessary because the instruction cache does *not* 612 * Note: this is necessary because the instruction cache does *not*