aboutsummaryrefslogtreecommitdiffstats
path: root/arch/powerpc
diff options
context:
space:
mode:
Diffstat (limited to 'arch/powerpc')
-rw-r--r--arch/powerpc/boot/4xx.c56
-rw-r--r--arch/powerpc/boot/dts/gef_ppc9a.dts1
-rw-r--r--arch/powerpc/include/asm/elf.h1
-rw-r--r--arch/powerpc/include/asm/mmu.h6
-rw-r--r--arch/powerpc/include/asm/ppc-opcode.h11
-rw-r--r--arch/powerpc/kernel/cputable.c2
-rw-r--r--arch/powerpc/mm/tlb_nohash_low.S16
-rw-r--r--arch/powerpc/platforms/cell/Kconfig5
-rw-r--r--arch/powerpc/platforms/ps3/setup.c4
9 files changed, 53 insertions, 49 deletions
diff --git a/arch/powerpc/boot/4xx.c b/arch/powerpc/boot/4xx.c
index 5c878436f348..325b310573b9 100644
--- a/arch/powerpc/boot/4xx.c
+++ b/arch/powerpc/boot/4xx.c
@@ -158,21 +158,33 @@ void ibm440spe_fixup_memsize(void)
158 158
159#define DDR_GET_VAL(val, mask, shift) (((val) >> (shift)) & (mask)) 159#define DDR_GET_VAL(val, mask, shift) (((val) >> (shift)) & (mask))
160 160
161void ibm4xx_denali_fixup_memsize(void) 161/*
162 * Some U-Boot versions set the number of chipselects to two
163 * for Sequoia/Rainier boards while they only have one chipselect
164 * hardwired. Hardcode the number of chipselects to one
165 * for sequioa/rainer board models or read the actual value
166 * from the memory controller register DDR0_10 otherwise.
167 */
168static inline u32 ibm4xx_denali_get_cs(void)
162{ 169{
163 u32 val, max_cs, max_col, max_row; 170 void *devp;
164 u32 cs, col, row, bank, dpath; 171 char model[64];
165 unsigned long memsize; 172 u32 val, cs;
166 173
167 val = SDRAM0_READ(DDR0_02); 174 devp = finddevice("/");
168 if (!DDR_GET_VAL(val, DDR_START, DDR_START_SHIFT)) 175 if (!devp)
169 fatal("DDR controller is not initialized\n"); 176 goto read_cs;
170 177
171 /* get maximum cs col and row values */ 178 if (getprop(devp, "model", model, sizeof(model)) <= 0)
172 max_cs = DDR_GET_VAL(val, DDR_MAX_CS_REG, DDR_MAX_CS_REG_SHIFT); 179 goto read_cs;
173 max_col = DDR_GET_VAL(val, DDR_MAX_COL_REG, DDR_MAX_COL_REG_SHIFT);
174 max_row = DDR_GET_VAL(val, DDR_MAX_ROW_REG, DDR_MAX_ROW_REG_SHIFT);
175 180
181 model[sizeof(model)-1] = 0;
182
183 if (!strcmp(model, "amcc,sequoia") ||
184 !strcmp(model, "amcc,rainier"))
185 return 1;
186
187read_cs:
176 /* get CS value */ 188 /* get CS value */
177 val = SDRAM0_READ(DDR0_10); 189 val = SDRAM0_READ(DDR0_10);
178 190
@@ -183,7 +195,25 @@ void ibm4xx_denali_fixup_memsize(void)
183 cs++; 195 cs++;
184 val = val >> 1; 196 val = val >> 1;
185 } 197 }
198 return cs;
199}
200
201void ibm4xx_denali_fixup_memsize(void)
202{
203 u32 val, max_cs, max_col, max_row;
204 u32 cs, col, row, bank, dpath;
205 unsigned long memsize;
206
207 val = SDRAM0_READ(DDR0_02);
208 if (!DDR_GET_VAL(val, DDR_START, DDR_START_SHIFT))
209 fatal("DDR controller is not initialized\n");
186 210
211 /* get maximum cs col and row values */
212 max_cs = DDR_GET_VAL(val, DDR_MAX_CS_REG, DDR_MAX_CS_REG_SHIFT);
213 max_col = DDR_GET_VAL(val, DDR_MAX_COL_REG, DDR_MAX_COL_REG_SHIFT);
214 max_row = DDR_GET_VAL(val, DDR_MAX_ROW_REG, DDR_MAX_ROW_REG_SHIFT);
215
216 cs = ibm4xx_denali_get_cs();
187 if (!cs) 217 if (!cs)
188 fatal("No memory installed\n"); 218 fatal("No memory installed\n");
189 if (cs > max_cs) 219 if (cs > max_cs)
@@ -193,9 +223,9 @@ void ibm4xx_denali_fixup_memsize(void)
193 val = SDRAM0_READ(DDR0_14); 223 val = SDRAM0_READ(DDR0_14);
194 224
195 if (DDR_GET_VAL(val, DDR_REDUC, DDR_REDUC_SHIFT)) 225 if (DDR_GET_VAL(val, DDR_REDUC, DDR_REDUC_SHIFT))
196 dpath = 8; /* 64 bits */
197 else
198 dpath = 4; /* 32 bits */ 226 dpath = 4; /* 32 bits */
227 else
228 dpath = 8; /* 64 bits */
199 229
200 /* get address pins (rows) */ 230 /* get address pins (rows) */
201 val = SDRAM0_READ(DDR0_42); 231 val = SDRAM0_READ(DDR0_42);
diff --git a/arch/powerpc/boot/dts/gef_ppc9a.dts b/arch/powerpc/boot/dts/gef_ppc9a.dts
index d47ad0718759..53a7a6255909 100644
--- a/arch/powerpc/boot/dts/gef_ppc9a.dts
+++ b/arch/powerpc/boot/dts/gef_ppc9a.dts
@@ -161,6 +161,7 @@
161 #address-cells = <1>; 161 #address-cells = <1>;
162 #size-cells = <1>; 162 #size-cells = <1>;
163 #interrupt-cells = <2>; 163 #interrupt-cells = <2>;
164 device_type = "soc";
164 compatible = "fsl,mpc8641-soc", "simple-bus"; 165 compatible = "fsl,mpc8641-soc", "simple-bus";
165 ranges = <0x0 0xfef00000 0x00100000>; 166 ranges = <0x0 0xfef00000 0x00100000>;
166 reg = <0xfef00000 0x100000>; // CCSRBAR 1M 167 reg = <0xfef00000 0x100000>; // CCSRBAR 1M
diff --git a/arch/powerpc/include/asm/elf.h b/arch/powerpc/include/asm/elf.h
index 087c22f1d368..d6b4a12cdeff 100644
--- a/arch/powerpc/include/asm/elf.h
+++ b/arch/powerpc/include/asm/elf.h
@@ -260,6 +260,7 @@ do { \
260#else 260#else
261# define SET_PERSONALITY(ex) \ 261# define SET_PERSONALITY(ex) \
262 set_personality(PER_LINUX | (current->personality & (~PER_MASK))) 262 set_personality(PER_LINUX | (current->personality & (~PER_MASK)))
263# define elf_read_implies_exec(ex, exec_stk) (exec_stk != EXSTACK_DISABLE_X)
263#endif /* __powerpc64__ */ 264#endif /* __powerpc64__ */
264 265
265extern int dcache_bsize; 266extern int dcache_bsize;
diff --git a/arch/powerpc/include/asm/mmu.h b/arch/powerpc/include/asm/mmu.h
index 86d2366ab6a1..cbf154387091 100644
--- a/arch/powerpc/include/asm/mmu.h
+++ b/arch/powerpc/include/asm/mmu.h
@@ -52,12 +52,6 @@
52 */ 52 */
53#define MMU_FTR_NEED_DTLB_SW_LRU ASM_CONST(0x00200000) 53#define MMU_FTR_NEED_DTLB_SW_LRU ASM_CONST(0x00200000)
54 54
55/* This indicates that the processor uses the wrong opcode for tlbilx
56 * instructions. During the ISA 2.06 development the opcode for tlbilx
57 * changed and some early implementations used to old opcode
58 */
59#define MMU_FTR_TLBILX_EARLY_OPCODE ASM_CONST(0x00400000)
60
61#ifndef __ASSEMBLY__ 55#ifndef __ASSEMBLY__
62#include <asm/cputable.h> 56#include <asm/cputable.h>
63 57
diff --git a/arch/powerpc/include/asm/ppc-opcode.h b/arch/powerpc/include/asm/ppc-opcode.h
index ef4da37f3c10..640ccbbc0977 100644
--- a/arch/powerpc/include/asm/ppc-opcode.h
+++ b/arch/powerpc/include/asm/ppc-opcode.h
@@ -44,7 +44,6 @@
44#define PPC_INST_STSWI 0x7c0005aa 44#define PPC_INST_STSWI 0x7c0005aa
45#define PPC_INST_STSWX 0x7c00052a 45#define PPC_INST_STSWX 0x7c00052a
46#define PPC_INST_TLBILX 0x7c000024 46#define PPC_INST_TLBILX 0x7c000024
47#define PPC_INST_TLBILX_EARLY 0x7c000626
48#define PPC_INST_WAIT 0x7c00007c 47#define PPC_INST_WAIT 0x7c00007c
49 48
50/* macros to insert fields into opcodes */ 49/* macros to insert fields into opcodes */
@@ -64,18 +63,10 @@
64#define PPC_RFDI stringify_in_c(.long PPC_INST_RFDI) 63#define PPC_RFDI stringify_in_c(.long PPC_INST_RFDI)
65#define PPC_RFMCI stringify_in_c(.long PPC_INST_RFMCI) 64#define PPC_RFMCI stringify_in_c(.long PPC_INST_RFMCI)
66#define PPC_TLBILX(t, a, b) stringify_in_c(.long PPC_INST_TLBILX | \ 65#define PPC_TLBILX(t, a, b) stringify_in_c(.long PPC_INST_TLBILX | \
67 __PPC_T_TLB(t) | \ 66 __PPC_T_TLB(t) | __PPC_RA(a) | __PPC_RB(b))
68 __PPC_RA(a) | __PPC_RB(b))
69#define PPC_TLBILX_ALL(a, b) PPC_TLBILX(0, a, b) 67#define PPC_TLBILX_ALL(a, b) PPC_TLBILX(0, a, b)
70#define PPC_TLBILX_PID(a, b) PPC_TLBILX(1, a, b) 68#define PPC_TLBILX_PID(a, b) PPC_TLBILX(1, a, b)
71#define PPC_TLBILX_VA(a, b) PPC_TLBILX(3, a, b) 69#define PPC_TLBILX_VA(a, b) PPC_TLBILX(3, a, b)
72
73#define PPC_TLBILX_EARLY(t, a, b) stringify_in_c(.long PPC_INST_TLBILX_EARLY | \
74 __PPC_T_TLB(t) | \
75 __PPC_RA(a) | __PPC_RB(b))
76#define PPC_TLBILX_ALL_EARLY(a, b) PPC_TLBILX_EARLY(0, a, b)
77#define PPC_TLBILX_PID_EARLY(a, b) PPC_TLBILX_EARLY(1, a, b)
78#define PPC_TLBILX_VA_EARLY(a, b) PPC_TLBILX_EARLY(3, a, b)
79#define PPC_WAIT(w) stringify_in_c(.long PPC_INST_WAIT | \ 70#define PPC_WAIT(w) stringify_in_c(.long PPC_INST_WAIT | \
80 __PPC_WC(w)) 71 __PPC_WC(w))
81 72
diff --git a/arch/powerpc/kernel/cputable.c b/arch/powerpc/kernel/cputable.c
index 57db50f40289..cd1b687544f3 100644
--- a/arch/powerpc/kernel/cputable.c
+++ b/arch/powerpc/kernel/cputable.c
@@ -1766,7 +1766,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
1766 .cpu_features = CPU_FTRS_E500MC, 1766 .cpu_features = CPU_FTRS_E500MC,
1767 .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU, 1767 .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU,
1768 .mmu_features = MMU_FTR_TYPE_FSL_E | MMU_FTR_BIG_PHYS | 1768 .mmu_features = MMU_FTR_TYPE_FSL_E | MMU_FTR_BIG_PHYS |
1769 MMU_FTR_USE_TLBILX | MMU_FTR_TLBILX_EARLY_OPCODE, 1769 MMU_FTR_USE_TLBILX,
1770 .icache_bsize = 64, 1770 .icache_bsize = 64,
1771 .dcache_bsize = 64, 1771 .dcache_bsize = 64,
1772 .num_pmcs = 4, 1772 .num_pmcs = 4,
diff --git a/arch/powerpc/mm/tlb_nohash_low.S b/arch/powerpc/mm/tlb_nohash_low.S
index 45fed3698349..3037911279b1 100644
--- a/arch/powerpc/mm/tlb_nohash_low.S
+++ b/arch/powerpc/mm/tlb_nohash_low.S
@@ -138,11 +138,7 @@ BEGIN_MMU_FTR_SECTION
138 andi. r3,r3,MMUCSR0_TLBFI@l 138 andi. r3,r3,MMUCSR0_TLBFI@l
139 bne 1b 139 bne 1b
140MMU_FTR_SECTION_ELSE 140MMU_FTR_SECTION_ELSE
141 BEGIN_MMU_FTR_SECTION_NESTED(96) 141 PPC_TLBILX_ALL(0,0)
142 PPC_TLBILX_ALL(0,r3)
143 MMU_FTR_SECTION_ELSE_NESTED(96)
144 PPC_TLBILX_ALL_EARLY(0,r3)
145 ALT_MMU_FTR_SECTION_END_NESTED_IFCLR(MMU_FTR_TLBILX_EARLY_OPCODE, 96)
146ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_USE_TLBILX) 142ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_USE_TLBILX)
147 msync 143 msync
148 isync 144 isync
@@ -155,11 +151,7 @@ BEGIN_MMU_FTR_SECTION
155 wrteei 0 151 wrteei 0
156 mfspr r4,SPRN_MAS6 /* save MAS6 */ 152 mfspr r4,SPRN_MAS6 /* save MAS6 */
157 mtspr SPRN_MAS6,r3 153 mtspr SPRN_MAS6,r3
158 BEGIN_MMU_FTR_SECTION_NESTED(96)
159 PPC_TLBILX_PID(0,0) 154 PPC_TLBILX_PID(0,0)
160 MMU_FTR_SECTION_ELSE_NESTED(96)
161 PPC_TLBILX_PID_EARLY(0,0)
162 ALT_MMU_FTR_SECTION_END_NESTED_IFCLR(MMU_FTR_TLBILX_EARLY_OPCODE, 96)
163 mtspr SPRN_MAS6,r4 /* restore MAS6 */ 155 mtspr SPRN_MAS6,r4 /* restore MAS6 */
164 wrtee r10 156 wrtee r10
165MMU_FTR_SECTION_ELSE 157MMU_FTR_SECTION_ELSE
@@ -193,16 +185,12 @@ BEGIN_MMU_FTR_SECTION
193 mtspr SPRN_MAS1,r4 185 mtspr SPRN_MAS1,r4
194 tlbwe 186 tlbwe
195MMU_FTR_SECTION_ELSE 187MMU_FTR_SECTION_ELSE
196 BEGIN_MMU_FTR_SECTION_NESTED(96)
197 PPC_TLBILX_VA(0,r3) 188 PPC_TLBILX_VA(0,r3)
198 MMU_FTR_SECTION_ELSE_NESTED(96)
199 PPC_TLBILX_VA_EARLY(0,r3)
200 ALT_MMU_FTR_SECTION_END_NESTED_IFCLR(MMU_FTR_TLBILX_EARLY_OPCODE, 96)
201ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_USE_TLBILX) 189ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_USE_TLBILX)
202 msync 190 msync
203 isync 191 isync
2041: wrtee r10 1921: wrtee r10
205 blr 193 blr
206#elif 194#else
207#error Unsupported processor type ! 195#error Unsupported processor type !
208#endif 196#endif
diff --git a/arch/powerpc/platforms/cell/Kconfig b/arch/powerpc/platforms/cell/Kconfig
index 40e24c39ad06..50f17bdd3c16 100644
--- a/arch/powerpc/platforms/cell/Kconfig
+++ b/arch/powerpc/platforms/cell/Kconfig
@@ -13,7 +13,6 @@ config PPC_CELL_COMMON
13config PPC_CELL_NATIVE 13config PPC_CELL_NATIVE
14 bool 14 bool
15 select PPC_CELL_COMMON 15 select PPC_CELL_COMMON
16 select PPC_OF_PLATFORM_PCI
17 select MPIC 16 select MPIC
18 select IBM_NEW_EMAC_EMAC4 17 select IBM_NEW_EMAC_EMAC4
19 select IBM_NEW_EMAC_RGMII 18 select IBM_NEW_EMAC_RGMII
@@ -25,6 +24,8 @@ config PPC_IBM_CELL_BLADE
25 bool "IBM Cell Blade" 24 bool "IBM Cell Blade"
26 depends on PPC64 && PPC_BOOK3S 25 depends on PPC64 && PPC_BOOK3S
27 select PPC_CELL_NATIVE 26 select PPC_CELL_NATIVE
27 select PPC_OF_PLATFORM_PCI
28 select PCI
28 select MMIO_NVRAM 29 select MMIO_NVRAM
29 select PPC_UDBG_16550 30 select PPC_UDBG_16550
30 select UDBG_RTAS_CONSOLE 31 select UDBG_RTAS_CONSOLE
@@ -33,6 +34,8 @@ config PPC_CELLEB
33 bool "Toshiba's Cell Reference Set 'Celleb' Architecture" 34 bool "Toshiba's Cell Reference Set 'Celleb' Architecture"
34 depends on PPC64 && PPC_BOOK3S 35 depends on PPC64 && PPC_BOOK3S
35 select PPC_CELL_NATIVE 36 select PPC_CELL_NATIVE
37 select PPC_OF_PLATFORM_PCI
38 select PCI
36 select HAS_TXX9_SERIAL 39 select HAS_TXX9_SERIAL
37 select PPC_UDBG_BEAT 40 select PPC_UDBG_BEAT
38 select USB_OHCI_BIG_ENDIAN_MMIO 41 select USB_OHCI_BIG_ENDIAN_MMIO
diff --git a/arch/powerpc/platforms/ps3/setup.c b/arch/powerpc/platforms/ps3/setup.c
index 66181821322a..1a7b5ae0c83e 100644
--- a/arch/powerpc/platforms/ps3/setup.c
+++ b/arch/powerpc/platforms/ps3/setup.c
@@ -45,10 +45,6 @@
45DEFINE_MUTEX(ps3_gpu_mutex); 45DEFINE_MUTEX(ps3_gpu_mutex);
46EXPORT_SYMBOL_GPL(ps3_gpu_mutex); 46EXPORT_SYMBOL_GPL(ps3_gpu_mutex);
47 47
48#if !defined(CONFIG_SMP)
49static void smp_send_stop(void) {}
50#endif
51
52static union ps3_firmware_version ps3_firmware_version; 48static union ps3_firmware_version ps3_firmware_version;
53 49
54void ps3_get_firmware_version(union ps3_firmware_version *v) 50void ps3_get_firmware_version(union ps3_firmware_version *v)