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-rw-r--r--arch/powerpc/Kconfig20
-rw-r--r--arch/powerpc/boot/dts/mpc7448hpc2.dts190
-rw-r--r--arch/powerpc/boot/dts/mpc8349emds.dts328
-rw-r--r--arch/powerpc/configs/mpc834x_mds_defconfig (renamed from arch/powerpc/configs/mpc834x_sys_defconfig)0
-rw-r--r--arch/powerpc/kernel/fpu.S5
-rw-r--r--arch/powerpc/kernel/irq.c84
-rw-r--r--arch/powerpc/kernel/pci_64.c11
-rw-r--r--arch/powerpc/kernel/prom_init.c10
-rw-r--r--arch/powerpc/kernel/prom_parse.c15
-rw-r--r--arch/powerpc/kernel/smp-tbsync.c5
-rw-r--r--arch/powerpc/kernel/time.c25
-rw-r--r--arch/powerpc/kernel/traps.c2
-rw-r--r--arch/powerpc/lib/memcpy_64.S11
-rw-r--r--arch/powerpc/platforms/83xx/mpc834x_itx.c49
-rw-r--r--arch/powerpc/platforms/83xx/mpc834x_sys.c56
-rw-r--r--arch/powerpc/platforms/83xx/mpc83xx.h1
-rw-r--r--arch/powerpc/platforms/83xx/pci.c9
-rw-r--r--arch/powerpc/platforms/embedded6xx/Kconfig1
-rw-r--r--arch/powerpc/platforms/embedded6xx/mpc7448_hpc2.c2
-rw-r--r--arch/powerpc/sysdev/Makefile4
-rw-r--r--arch/powerpc/sysdev/ipic.c303
-rw-r--r--arch/powerpc/sysdev/ipic.h23
-rw-r--r--arch/powerpc/sysdev/mpic.c223
23 files changed, 1072 insertions, 305 deletions
diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
index 78414afb0c56..904798fd4e74 100644
--- a/arch/powerpc/Kconfig
+++ b/arch/powerpc/Kconfig
@@ -354,6 +354,7 @@ endchoice
354config PPC_PSERIES 354config PPC_PSERIES
355 depends on PPC_MULTIPLATFORM && PPC64 355 depends on PPC_MULTIPLATFORM && PPC64
356 bool "IBM pSeries & new (POWER5-based) iSeries" 356 bool "IBM pSeries & new (POWER5-based) iSeries"
357 select MPIC
357 select PPC_I8259 358 select PPC_I8259
358 select PPC_RTAS 359 select PPC_RTAS
359 select RTAS_ERROR_LOGGING 360 select RTAS_ERROR_LOGGING
@@ -363,6 +364,7 @@ config PPC_PSERIES
363config PPC_CHRP 364config PPC_CHRP
364 bool "Common Hardware Reference Platform (CHRP) based machines" 365 bool "Common Hardware Reference Platform (CHRP) based machines"
365 depends on PPC_MULTIPLATFORM && PPC32 366 depends on PPC_MULTIPLATFORM && PPC32
367 select MPIC
366 select PPC_I8259 368 select PPC_I8259
367 select PPC_INDIRECT_PCI 369 select PPC_INDIRECT_PCI
368 select PPC_RTAS 370 select PPC_RTAS
@@ -373,6 +375,7 @@ config PPC_CHRP
373config PPC_PMAC 375config PPC_PMAC
374 bool "Apple PowerMac based machines" 376 bool "Apple PowerMac based machines"
375 depends on PPC_MULTIPLATFORM 377 depends on PPC_MULTIPLATFORM
378 select MPIC
376 select PPC_INDIRECT_PCI if PPC32 379 select PPC_INDIRECT_PCI if PPC32
377 select PPC_MPC106 if PPC32 380 select PPC_MPC106 if PPC32
378 default y 381 default y
@@ -380,6 +383,7 @@ config PPC_PMAC
380config PPC_PMAC64 383config PPC_PMAC64
381 bool 384 bool
382 depends on PPC_PMAC && POWER4 385 depends on PPC_PMAC && POWER4
386 select MPIC
383 select U3_DART 387 select U3_DART
384 select MPIC_BROKEN_U3 388 select MPIC_BROKEN_U3
385 select GENERIC_TBSYNC 389 select GENERIC_TBSYNC
@@ -389,6 +393,7 @@ config PPC_PMAC64
389config PPC_PREP 393config PPC_PREP
390 bool "PowerPC Reference Platform (PReP) based machines" 394 bool "PowerPC Reference Platform (PReP) based machines"
391 depends on PPC_MULTIPLATFORM && PPC32 && BROKEN 395 depends on PPC_MULTIPLATFORM && PPC32 && BROKEN
396 select MPIC
392 select PPC_I8259 397 select PPC_I8259
393 select PPC_INDIRECT_PCI 398 select PPC_INDIRECT_PCI
394 select PPC_UDBG_16550 399 select PPC_UDBG_16550
@@ -397,6 +402,7 @@ config PPC_PREP
397config PPC_MAPLE 402config PPC_MAPLE
398 depends on PPC_MULTIPLATFORM && PPC64 403 depends on PPC_MULTIPLATFORM && PPC64
399 bool "Maple 970FX Evaluation Board" 404 bool "Maple 970FX Evaluation Board"
405 select MPIC
400 select U3_DART 406 select U3_DART
401 select MPIC_BROKEN_U3 407 select MPIC_BROKEN_U3
402 select GENERIC_TBSYNC 408 select GENERIC_TBSYNC
@@ -440,12 +446,6 @@ config U3_DART
440 depends on PPC_MULTIPLATFORM && PPC64 446 depends on PPC_MULTIPLATFORM && PPC64
441 default n 447 default n
442 448
443config MPIC
444 depends on PPC_PSERIES || PPC_PMAC || PPC_MAPLE || PPC_CHRP \
445 || MPC7448HPC2
446 bool
447 default y
448
449config PPC_RTAS 449config PPC_RTAS
450 bool 450 bool
451 default n 451 default n
@@ -813,6 +813,14 @@ config GENERIC_ISA_DMA
813 depends on PPC64 || POWER4 || 6xx && !CPM2 813 depends on PPC64 || POWER4 || 6xx && !CPM2
814 default y 814 default y
815 815
816config MPIC
817 bool
818 default n
819
820config MPIC_WEIRD
821 bool
822 default n
823
816config PPC_I8259 824config PPC_I8259
817 bool 825 bool
818 default n 826 default n
diff --git a/arch/powerpc/boot/dts/mpc7448hpc2.dts b/arch/powerpc/boot/dts/mpc7448hpc2.dts
new file mode 100644
index 000000000000..d7b985e6bd2f
--- /dev/null
+++ b/arch/powerpc/boot/dts/mpc7448hpc2.dts
@@ -0,0 +1,190 @@
1/*
2 * MPC7448HPC2 (Taiga) board Device Tree Source
3 *
4 * Copyright 2006 Freescale Semiconductor Inc.
5 * 2006 Roy Zang <Roy Zang at freescale.com>.
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 */
12
13
14/ {
15 model = "mpc7448hpc2";
16 compatible = "mpc74xx";
17 #address-cells = <1>;
18 #size-cells = <1>;
19 linux,phandle = <100>;
20
21 cpus {
22 #cpus = <1>;
23 #address-cells = <1>;
24 #size-cells =<0>;
25 linux,phandle = <200>;
26
27 PowerPC,7448@0 {
28 device_type = "cpu";
29 reg = <0>;
30 d-cache-line-size = <20>; // 32 bytes
31 i-cache-line-size = <20>; // 32 bytes
32 d-cache-size = <8000>; // L1, 32K bytes
33 i-cache-size = <8000>; // L1, 32K bytes
34 timebase-frequency = <0>; // 33 MHz, from uboot
35 clock-frequency = <0>; // From U-Boot
36 bus-frequency = <0>; // From U-Boot
37 32-bit;
38 linux,phandle = <201>;
39 linux,boot-cpu;
40 };
41 };
42
43 memory {
44 device_type = "memory";
45 linux,phandle = <300>;
46 reg = <00000000 20000000 // DDR2 512M at 0
47 >;
48 };
49
50 tsi108@c0000000 {
51 #address-cells = <1>;
52 #size-cells = <1>;
53 #interrupt-cells = <2>;
54 device_type = "tsi-bridge";
55 ranges = <00000000 c0000000 00010000>;
56 reg = <c0000000 00010000>;
57 bus-frequency = <0>;
58
59 i2c@7000 {
60 interrupt-parent = <7400>;
61 interrupts = <E 0>;
62 reg = <7000 400>;
63 device_type = "i2c";
64 compatible = "tsi-i2c";
65 };
66
67 mdio@6000 {
68 device_type = "mdio";
69 compatible = "tsi-ethernet";
70
71 ethernet-phy@6000 {
72 linux,phandle = <6000>;
73 interrupt-parent = <7400>;
74 interrupts = <2 1>;
75 reg = <6000 50>;
76 phy-id = <8>;
77 device_type = "ethernet-phy";
78 };
79
80 ethernet-phy@6400 {
81 linux,phandle = <6400>;
82 interrupt-parent = <7400>;
83 interrupts = <2 1>;
84 reg = <6000 50>;
85 phy-id = <9>;
86 device_type = "ethernet-phy";
87 };
88
89 };
90
91 ethernet@6200 {
92 #size-cells = <0>;
93 device_type = "network";
94 model = "TSI-ETH";
95 compatible = "tsi-ethernet";
96 reg = <6000 200>;
97 address = [ 00 06 D2 00 00 01 ];
98 interrupts = <10 2>;
99 interrupt-parent = <7400>;
100 phy-handle = <6000>;
101 };
102
103 ethernet@6600 {
104 #address-cells = <1>;
105 #size-cells = <0>;
106 device_type = "network";
107 model = "TSI-ETH";
108 compatible = "tsi-ethernet";
109 reg = <6400 200>;
110 address = [ 00 06 D2 00 00 02 ];
111 interrupts = <11 2>;
112 interrupt-parent = <7400>;
113 phy-handle = <6400>;
114 };
115
116 serial@7808 {
117 device_type = "serial";
118 compatible = "ns16550";
119 reg = <7808 200>;
120 clock-frequency = <3f6b5a00>;
121 interrupts = <c 0>;
122 interrupt-parent = <7400>;
123 };
124
125 serial@7c08 {
126 device_type = "serial";
127 compatible = "ns16550";
128 reg = <7c08 200>;
129 clock-frequency = <3f6b5a00>;
130 interrupts = <d 0>;
131 interrupt-parent = <7400>;
132 };
133
134 pic@7400 {
135 linux,phandle = <7400>;
136 clock-frequency = <0>;
137 interrupt-controller;
138 #address-cells = <0>;
139 #interrupt-cells = <2>;
140 reg = <7400 400>;
141 built-in;
142 compatible = "chrp,open-pic";
143 device_type = "open-pic";
144 big-endian;
145 };
146 pci@1000 {
147 compatible = "tsi10x";
148 device_type = "pci";
149 linux,phandle = <1000>;
150 #interrupt-cells = <1>;
151 #size-cells = <2>;
152 #address-cells = <3>;
153 reg = <1000 1000>;
154 bus-range = <0 0>;
155 ranges = <02000000 0 e0000000 e0000000 0 1A000000
156 01000000 0 00000000 fa000000 0 00010000>;
157 clock-frequency = <7f28154>;
158 interrupt-parent = <7400>;
159 interrupts = <17 2>;
160 interrupt-map-mask = <f800 0 0 7>;
161 interrupt-map = <
162
163 /* IDSEL 0x11 */
164 0800 0 0 1 7400 24 0
165 0800 0 0 2 7400 25 0
166 0800 0 0 3 7400 26 0
167 0800 0 0 4 7400 27 0
168
169 /* IDSEL 0x12 */
170 1000 0 0 1 7400 25 0
171 1000 0 0 2 7400 26 0
172 1000 0 0 3 7400 27 0
173 1000 0 0 4 7400 24 0
174
175 /* IDSEL 0x13 */
176 1800 0 0 1 7400 26 0
177 1800 0 0 2 7400 27 0
178 1800 0 0 3 7400 24 0
179 1800 0 0 4 7400 25 0
180
181 /* IDSEL 0x14 */
182 2000 0 0 1 7400 27 0
183 2000 0 0 2 7400 24 0
184 2000 0 0 3 7400 25 0
185 2000 0 0 4 7400 26 0
186 >;
187 };
188 };
189
190};
diff --git a/arch/powerpc/boot/dts/mpc8349emds.dts b/arch/powerpc/boot/dts/mpc8349emds.dts
new file mode 100644
index 000000000000..12f5dbf3055f
--- /dev/null
+++ b/arch/powerpc/boot/dts/mpc8349emds.dts
@@ -0,0 +1,328 @@
1/*
2 * MPC8349E MDS Device Tree Source
3 *
4 * Copyright 2005, 2006 Freescale Semiconductor Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
11
12/ {
13 model = "MPC8349EMDS";
14 compatible = "MPC834xMDS";
15 #address-cells = <1>;
16 #size-cells = <1>;
17
18 cpus {
19 #cpus = <1>;
20 #address-cells = <1>;
21 #size-cells = <0>;
22
23 PowerPC,8349@0 {
24 device_type = "cpu";
25 reg = <0>;
26 d-cache-line-size = <20>; // 32 bytes
27 i-cache-line-size = <20>; // 32 bytes
28 d-cache-size = <8000>; // L1, 32K
29 i-cache-size = <8000>; // L1, 32K
30 timebase-frequency = <0>; // from bootloader
31 bus-frequency = <0>; // from bootloader
32 clock-frequency = <0>; // from bootloader
33 32-bit;
34 };
35 };
36
37 memory {
38 device_type = "memory";
39 reg = <00000000 10000000>; // 256MB at 0
40 };
41
42 soc8349@e0000000 {
43 #address-cells = <1>;
44 #size-cells = <1>;
45 #interrupt-cells = <2>;
46 device_type = "soc";
47 ranges = <0 e0000000 00100000>;
48 reg = <e0000000 00000200>;
49 bus-frequency = <0>;
50
51 wdt@200 {
52 device_type = "watchdog";
53 compatible = "mpc83xx_wdt";
54 reg = <200 100>;
55 };
56
57 i2c@3000 {
58 device_type = "i2c";
59 compatible = "fsl-i2c";
60 reg = <3000 100>;
61 interrupts = <e 8>;
62 interrupt-parent = <700>;
63 dfsrr;
64 };
65
66 i2c@3100 {
67 device_type = "i2c";
68 compatible = "fsl-i2c";
69 reg = <3100 100>;
70 interrupts = <f 8>;
71 interrupt-parent = <700>;
72 dfsrr;
73 };
74
75 spi@7000 {
76 device_type = "spi";
77 compatible = "mpc83xx_spi";
78 reg = <7000 1000>;
79 interrupts = <10 8>;
80 interrupt-parent = <700>;
81 mode = <0>;
82 };
83
84 /* phy type (ULPI or SERIAL) are only types supportted for MPH */
85 /* port = 0 or 1 */
86 usb@22000 {
87 device_type = "usb";
88 compatible = "fsl-usb2-mph";
89 reg = <22000 1000>;
90 #address-cells = <1>;
91 #size-cells = <0>;
92 interrupt-parent = <700>;
93 interrupts = <27 2>;
94 phy_type = "ulpi";
95 port1;
96 };
97 /* phy type (ULPI, UTMI, UTMI_WIDE, SERIAL) */
98 usb@23000 {
99 device_type = "usb";
100 compatible = "fsl-usb2-dr";
101 reg = <23000 1000>;
102 #address-cells = <1>;
103 #size-cells = <0>;
104 interrupt-parent = <700>;
105 interrupts = <26 2>;
106 phy_type = "ulpi";
107 };
108
109 mdio@24520 {
110 device_type = "mdio";
111 compatible = "gianfar";
112 reg = <24520 20>;
113 #address-cells = <1>;
114 #size-cells = <0>;
115 linux,phandle = <24520>;
116 ethernet-phy@0 {
117 linux,phandle = <2452000>;
118 interrupt-parent = <700>;
119 interrupts = <11 2>;
120 reg = <0>;
121 device_type = "ethernet-phy";
122 };
123 ethernet-phy@1 {
124 linux,phandle = <2452001>;
125 interrupt-parent = <700>;
126 interrupts = <12 2>;
127 reg = <1>;
128 device_type = "ethernet-phy";
129 };
130 };
131
132 ethernet@24000 {
133 device_type = "network";
134 model = "TSEC";
135 compatible = "gianfar";
136 reg = <24000 1000>;
137 address = [ 00 00 00 00 00 00 ];
138 local-mac-address = [ 00 00 00 00 00 00 ];
139 interrupts = <20 8 21 8 22 8>;
140 interrupt-parent = <700>;
141 phy-handle = <2452000>;
142 };
143
144 ethernet@25000 {
145 #address-cells = <1>;
146 #size-cells = <0>;
147 device_type = "network";
148 model = "TSEC";
149 compatible = "gianfar";
150 reg = <25000 1000>;
151 address = [ 00 00 00 00 00 00 ];
152 local-mac-address = [ 00 00 00 00 00 00 ];
153 interrupts = <23 8 24 8 25 8>;
154 interrupt-parent = <700>;
155 phy-handle = <2452001>;
156 };
157
158 serial@4500 {
159 device_type = "serial";
160 compatible = "ns16550";
161 reg = <4500 100>;
162 clock-frequency = <0>;
163 interrupts = <9 8>;
164 interrupt-parent = <700>;
165 };
166
167 serial@4600 {
168 device_type = "serial";
169 compatible = "ns16550";
170 reg = <4600 100>;
171 clock-frequency = <0>;
172 interrupts = <a 8>;
173 interrupt-parent = <700>;
174 };
175
176 pci@8500 {
177 interrupt-map-mask = <f800 0 0 7>;
178 interrupt-map = <
179
180 /* IDSEL 0x11 */
181 8800 0 0 1 700 14 8
182 8800 0 0 2 700 15 8
183 8800 0 0 3 700 16 8
184 8800 0 0 4 700 17 8
185
186 /* IDSEL 0x12 */
187 9000 0 0 1 700 16 8
188 9000 0 0 2 700 17 8
189 9000 0 0 3 700 14 8
190 9000 0 0 4 700 15 8
191
192 /* IDSEL 0x13 */
193 9800 0 0 1 700 17 8
194 9800 0 0 2 700 14 8
195 9800 0 0 3 700 15 8
196 9800 0 0 4 700 16 8
197
198 /* IDSEL 0x15 */
199 a800 0 0 1 700 14 8
200 a800 0 0 2 700 15 8
201 a800 0 0 3 700 16 8
202 a800 0 0 4 700 17 8
203
204 /* IDSEL 0x16 */
205 b000 0 0 1 700 17 8
206 b000 0 0 2 700 14 8
207 b000 0 0 3 700 15 8
208 b000 0 0 4 700 16 8
209
210 /* IDSEL 0x17 */
211 b800 0 0 1 700 16 8
212 b800 0 0 2 700 17 8
213 b800 0 0 3 700 14 8
214 b800 0 0 4 700 15 8
215
216 /* IDSEL 0x18 */
217 b000 0 0 1 700 15 8
218 b000 0 0 2 700 16 8
219 b000 0 0 3 700 17 8
220 b000 0 0 4 700 14 8>;
221 interrupt-parent = <700>;
222 interrupts = <42 8>;
223 bus-range = <0 0>;
224 ranges = <02000000 0 a0000000 a0000000 0 10000000
225 42000000 0 80000000 80000000 0 10000000
226 01000000 0 00000000 e2000000 0 00100000>;
227 clock-frequency = <3f940aa>;
228 #interrupt-cells = <1>;
229 #size-cells = <2>;
230 #address-cells = <3>;
231 reg = <8500 100>;
232 compatible = "83xx";
233 device_type = "pci";
234 };
235
236 pci@8600 {
237 interrupt-map-mask = <f800 0 0 7>;
238 interrupt-map = <
239
240 /* IDSEL 0x11 */
241 8800 0 0 1 700 14 8
242 8800 0 0 2 700 15 8
243 8800 0 0 3 700 16 8
244 8800 0 0 4 700 17 8
245
246 /* IDSEL 0x12 */
247 9000 0 0 1 700 16 8
248 9000 0 0 2 700 17 8
249 9000 0 0 3 700 14 8
250 9000 0 0 4 700 15 8
251
252 /* IDSEL 0x13 */
253 9800 0 0 1 700 17 8
254 9800 0 0 2 700 14 8
255 9800 0 0 3 700 15 8
256 9800 0 0 4 700 16 8
257
258 /* IDSEL 0x15 */
259 a800 0 0 1 700 14 8
260 a800 0 0 2 700 15 8
261 a800 0 0 3 700 16 8
262 a800 0 0 4 700 17 8
263
264 /* IDSEL 0x16 */
265 b000 0 0 1 700 17 8
266 b000 0 0 2 700 14 8
267 b000 0 0 3 700 15 8
268 b000 0 0 4 700 16 8
269
270 /* IDSEL 0x17 */
271 b800 0 0 1 700 16 8
272 b800 0 0 2 700 17 8
273 b800 0 0 3 700 14 8
274 b800 0 0 4 700 15 8
275
276 /* IDSEL 0x18 */
277 b000 0 0 1 700 15 8
278 b000 0 0 2 700 16 8
279 b000 0 0 3 700 17 8
280 b000 0 0 4 700 14 8>;
281 interrupt-parent = <700>;
282 interrupts = <42 8>;
283 bus-range = <0 0>;
284 ranges = <02000000 0 b0000000 b0000000 0 10000000
285 42000000 0 90000000 90000000 0 10000000
286 01000000 0 00000000 e2100000 0 00100000>;
287 clock-frequency = <3f940aa>;
288 #interrupt-cells = <1>;
289 #size-cells = <2>;
290 #address-cells = <3>;
291 reg = <8600 100>;
292 compatible = "83xx";
293 device_type = "pci";
294 };
295
296 /* May need to remove if on a part without crypto engine */
297 crypto@30000 {
298 device_type = "crypto";
299 model = "SEC2";
300 compatible = "talitos";
301 reg = <30000 10000>;
302 interrupts = <b 8>;
303 interrupt-parent = <700>;
304 num-channels = <4>;
305 channel-fifo-len = <18>;
306 exec-units-mask = <0000007e>;
307 /* desc mask is for rev2.0,
308 * we need runtime fixup for >2.0 */
309 descriptor-types-mask = <01010ebf>;
310 };
311
312 /* IPIC
313 * interrupts cell = <intr #, sense>
314 * sense values match linux IORESOURCE_IRQ_* defines:
315 * sense == 8: Level, low assertion
316 * sense == 2: Edge, high-to-low change
317 */
318 pic@700 {
319 linux,phandle = <700>;
320 interrupt-controller;
321 #address-cells = <0>;
322 #interrupt-cells = <2>;
323 reg = <700 100>;
324 built-in;
325 device_type = "ipic";
326 };
327 };
328};
diff --git a/arch/powerpc/configs/mpc834x_sys_defconfig b/arch/powerpc/configs/mpc834x_mds_defconfig
index 5078b0441d61..5078b0441d61 100644
--- a/arch/powerpc/configs/mpc834x_sys_defconfig
+++ b/arch/powerpc/configs/mpc834x_mds_defconfig
diff --git a/arch/powerpc/kernel/fpu.S b/arch/powerpc/kernel/fpu.S
index 7e2c9fe44ac1..821e152e093c 100644
--- a/arch/powerpc/kernel/fpu.S
+++ b/arch/powerpc/kernel/fpu.S
@@ -2,6 +2,11 @@
2 * FPU support code, moved here from head.S so that it can be used 2 * FPU support code, moved here from head.S so that it can be used
3 * by chips which use other head-whatever.S files. 3 * by chips which use other head-whatever.S files.
4 * 4 *
5 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
6 * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu>
7 * Copyright (C) 1996 Paul Mackerras.
8 * Copyright (C) 1997 Dan Malek (dmalek@jlc.net).
9 *
5 * This program is free software; you can redistribute it and/or 10 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License 11 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 12 * as published by the Free Software Foundation; either version
diff --git a/arch/powerpc/kernel/irq.c b/arch/powerpc/kernel/irq.c
index fd4ddb858dbd..b4432332341f 100644
--- a/arch/powerpc/kernel/irq.c
+++ b/arch/powerpc/kernel/irq.c
@@ -323,7 +323,8 @@ EXPORT_SYMBOL(do_softirq);
323 323
324static LIST_HEAD(irq_hosts); 324static LIST_HEAD(irq_hosts);
325static spinlock_t irq_big_lock = SPIN_LOCK_UNLOCKED; 325static spinlock_t irq_big_lock = SPIN_LOCK_UNLOCKED;
326 326static DEFINE_PER_CPU(unsigned int, irq_radix_reader);
327static unsigned int irq_radix_writer;
327struct irq_map_entry irq_map[NR_IRQS]; 328struct irq_map_entry irq_map[NR_IRQS];
328static unsigned int irq_virq_count = NR_IRQS; 329static unsigned int irq_virq_count = NR_IRQS;
329static struct irq_host *irq_default_host; 330static struct irq_host *irq_default_host;
@@ -456,6 +457,58 @@ void irq_set_virq_count(unsigned int count)
456 irq_virq_count = count; 457 irq_virq_count = count;
457} 458}
458 459
460/* radix tree not lockless safe ! we use a brlock-type mecanism
461 * for now, until we can use a lockless radix tree
462 */
463static void irq_radix_wrlock(unsigned long *flags)
464{
465 unsigned int cpu, ok;
466
467 spin_lock_irqsave(&irq_big_lock, *flags);
468 irq_radix_writer = 1;
469 smp_mb();
470 do {
471 barrier();
472 ok = 1;
473 for_each_possible_cpu(cpu) {
474 if (per_cpu(irq_radix_reader, cpu)) {
475 ok = 0;
476 break;
477 }
478 }
479 if (!ok)
480 cpu_relax();
481 } while(!ok);
482}
483
484static void irq_radix_wrunlock(unsigned long flags)
485{
486 smp_wmb();
487 irq_radix_writer = 0;
488 spin_unlock_irqrestore(&irq_big_lock, flags);
489}
490
491static void irq_radix_rdlock(unsigned long *flags)
492{
493 local_irq_save(*flags);
494 __get_cpu_var(irq_radix_reader) = 1;
495 smp_mb();
496 if (likely(irq_radix_writer == 0))
497 return;
498 __get_cpu_var(irq_radix_reader) = 0;
499 smp_wmb();
500 spin_lock(&irq_big_lock);
501 __get_cpu_var(irq_radix_reader) = 1;
502 spin_unlock(&irq_big_lock);
503}
504
505static void irq_radix_rdunlock(unsigned long flags)
506{
507 __get_cpu_var(irq_radix_reader) = 0;
508 local_irq_restore(flags);
509}
510
511
459unsigned int irq_create_mapping(struct irq_host *host, 512unsigned int irq_create_mapping(struct irq_host *host,
460 irq_hw_number_t hwirq) 513 irq_hw_number_t hwirq)
461{ 514{
@@ -605,13 +658,9 @@ void irq_dispose_mapping(unsigned int virq)
605 /* Check if radix tree allocated yet */ 658 /* Check if radix tree allocated yet */
606 if (host->revmap_data.tree.gfp_mask == 0) 659 if (host->revmap_data.tree.gfp_mask == 0)
607 break; 660 break;
608 /* XXX radix tree not safe ! remove lock whem it becomes safe 661 irq_radix_wrlock(&flags);
609 * and use some RCU sync to make sure everything is ok before we
610 * can re-use that map entry
611 */
612 spin_lock_irqsave(&irq_big_lock, flags);
613 radix_tree_delete(&host->revmap_data.tree, hwirq); 662 radix_tree_delete(&host->revmap_data.tree, hwirq);
614 spin_unlock_irqrestore(&irq_big_lock, flags); 663 irq_radix_wrunlock(flags);
615 break; 664 break;
616 } 665 }
617 666
@@ -678,25 +727,24 @@ unsigned int irq_radix_revmap(struct irq_host *host,
678 if (tree->gfp_mask == 0) 727 if (tree->gfp_mask == 0)
679 return irq_find_mapping(host, hwirq); 728 return irq_find_mapping(host, hwirq);
680 729
681 /* XXX Current radix trees are NOT SMP safe !!! Remove that lock
682 * when that is fixed (when Nick's patch gets in
683 */
684 spin_lock_irqsave(&irq_big_lock, flags);
685
686 /* Now try to resolve */ 730 /* Now try to resolve */
731 irq_radix_rdlock(&flags);
687 ptr = radix_tree_lookup(tree, hwirq); 732 ptr = radix_tree_lookup(tree, hwirq);
733 irq_radix_rdunlock(flags);
734
688 /* Found it, return */ 735 /* Found it, return */
689 if (ptr) { 736 if (ptr) {
690 virq = ptr - irq_map; 737 virq = ptr - irq_map;
691 goto bail; 738 return virq;
692 } 739 }
693 740
694 /* If not there, try to insert it */ 741 /* If not there, try to insert it */
695 virq = irq_find_mapping(host, hwirq); 742 virq = irq_find_mapping(host, hwirq);
696 if (virq != NO_IRQ) 743 if (virq != NO_IRQ) {
744 irq_radix_wrlock(&flags);
697 radix_tree_insert(tree, hwirq, &irq_map[virq]); 745 radix_tree_insert(tree, hwirq, &irq_map[virq]);
698 bail: 746 irq_radix_wrunlock(flags);
699 spin_unlock_irqrestore(&irq_big_lock, flags); 747 }
700 return virq; 748 return virq;
701} 749}
702 750
@@ -807,12 +855,12 @@ static int irq_late_init(void)
807 struct irq_host *h; 855 struct irq_host *h;
808 unsigned long flags; 856 unsigned long flags;
809 857
810 spin_lock_irqsave(&irq_big_lock, flags); 858 irq_radix_wrlock(&flags);
811 list_for_each_entry(h, &irq_hosts, link) { 859 list_for_each_entry(h, &irq_hosts, link) {
812 if (h->revmap_type == IRQ_HOST_MAP_TREE) 860 if (h->revmap_type == IRQ_HOST_MAP_TREE)
813 INIT_RADIX_TREE(&h->revmap_data.tree, GFP_ATOMIC); 861 INIT_RADIX_TREE(&h->revmap_data.tree, GFP_ATOMIC);
814 } 862 }
815 spin_unlock_irqrestore(&irq_big_lock, flags); 863 irq_radix_wrunlock(flags);
816 864
817 return 0; 865 return 0;
818} 866}
diff --git a/arch/powerpc/kernel/pci_64.c b/arch/powerpc/kernel/pci_64.c
index d51be7c7a2ef..c1b1e14775e4 100644
--- a/arch/powerpc/kernel/pci_64.c
+++ b/arch/powerpc/kernel/pci_64.c
@@ -1254,6 +1254,9 @@ int pci_read_irq_line(struct pci_dev *pci_dev)
1254 1254
1255 DBG("Try to map irq for %s...\n", pci_name(pci_dev)); 1255 DBG("Try to map irq for %s...\n", pci_name(pci_dev));
1256 1256
1257#ifdef DEBUG
1258 memset(&oirq, 0xff, sizeof(oirq));
1259#endif
1257 /* Try to get a mapping from the device-tree */ 1260 /* Try to get a mapping from the device-tree */
1258 if (of_irq_map_pci(pci_dev, &oirq)) { 1261 if (of_irq_map_pci(pci_dev, &oirq)) {
1259 u8 line, pin; 1262 u8 line, pin;
@@ -1279,8 +1282,9 @@ int pci_read_irq_line(struct pci_dev *pci_dev)
1279 if (virq != NO_IRQ) 1282 if (virq != NO_IRQ)
1280 set_irq_type(virq, IRQ_TYPE_LEVEL_LOW); 1283 set_irq_type(virq, IRQ_TYPE_LEVEL_LOW);
1281 } else { 1284 } else {
1282 DBG(" -> got one, spec %d cells (0x%08x...) on %s\n", 1285 DBG(" -> got one, spec %d cells (0x%08x 0x%08x...) on %s\n",
1283 oirq.size, oirq.specifier[0], oirq.controller->full_name); 1286 oirq.size, oirq.specifier[0], oirq.specifier[1],
1287 oirq.controller->full_name);
1284 1288
1285 virq = irq_create_of_mapping(oirq.controller, oirq.specifier, 1289 virq = irq_create_of_mapping(oirq.controller, oirq.specifier,
1286 oirq.size); 1290 oirq.size);
@@ -1289,6 +1293,9 @@ int pci_read_irq_line(struct pci_dev *pci_dev)
1289 DBG(" -> failed to map !\n"); 1293 DBG(" -> failed to map !\n");
1290 return -1; 1294 return -1;
1291 } 1295 }
1296
1297 DBG(" -> mapped to linux irq %d\n", virq);
1298
1292 pci_dev->irq = virq; 1299 pci_dev->irq = virq;
1293 pci_write_config_byte(pci_dev, PCI_INTERRUPT_LINE, virq); 1300 pci_write_config_byte(pci_dev, PCI_INTERRUPT_LINE, virq);
1294 1301
diff --git a/arch/powerpc/kernel/prom_init.c b/arch/powerpc/kernel/prom_init.c
index 90972ef6c471..b91761639d96 100644
--- a/arch/powerpc/kernel/prom_init.c
+++ b/arch/powerpc/kernel/prom_init.c
@@ -646,13 +646,13 @@ static unsigned char ibm_architecture_vec[] = {
646 5 - 1, /* 5 option vectors */ 646 5 - 1, /* 5 option vectors */
647 647
648 /* option vector 1: processor architectures supported */ 648 /* option vector 1: processor architectures supported */
649 3 - 1, /* length */ 649 3 - 2, /* length */
650 0, /* don't ignore, don't halt */ 650 0, /* don't ignore, don't halt */
651 OV1_PPC_2_00 | OV1_PPC_2_01 | OV1_PPC_2_02 | OV1_PPC_2_03 | 651 OV1_PPC_2_00 | OV1_PPC_2_01 | OV1_PPC_2_02 | OV1_PPC_2_03 |
652 OV1_PPC_2_04 | OV1_PPC_2_05, 652 OV1_PPC_2_04 | OV1_PPC_2_05,
653 653
654 /* option vector 2: Open Firmware options supported */ 654 /* option vector 2: Open Firmware options supported */
655 34 - 1, /* length */ 655 34 - 2, /* length */
656 OV2_REAL_MODE, 656 OV2_REAL_MODE,
657 0, 0, 657 0, 0,
658 W(0xffffffff), /* real_base */ 658 W(0xffffffff), /* real_base */
@@ -666,16 +666,16 @@ static unsigned char ibm_architecture_vec[] = {
666 48, /* max log_2(hash table size) */ 666 48, /* max log_2(hash table size) */
667 667
668 /* option vector 3: processor options supported */ 668 /* option vector 3: processor options supported */
669 3 - 1, /* length */ 669 3 - 2, /* length */
670 0, /* don't ignore, don't halt */ 670 0, /* don't ignore, don't halt */
671 OV3_FP | OV3_VMX, 671 OV3_FP | OV3_VMX,
672 672
673 /* option vector 4: IBM PAPR implementation */ 673 /* option vector 4: IBM PAPR implementation */
674 2 - 1, /* length */ 674 2 - 2, /* length */
675 0, /* don't halt */ 675 0, /* don't halt */
676 676
677 /* option vector 5: PAPR/OF options */ 677 /* option vector 5: PAPR/OF options */
678 3 - 1, /* length */ 678 3 - 2, /* length */
679 0, /* don't ignore, don't halt */ 679 0, /* don't ignore, don't halt */
680 OV5_LPAR | OV5_SPLPAR | OV5_LARGE_PAGES, 680 OV5_LPAR | OV5_SPLPAR | OV5_LARGE_PAGES,
681}; 681};
diff --git a/arch/powerpc/kernel/prom_parse.c b/arch/powerpc/kernel/prom_parse.c
index 603203276ef6..603dff3ad62a 100644
--- a/arch/powerpc/kernel/prom_parse.c
+++ b/arch/powerpc/kernel/prom_parse.c
@@ -642,7 +642,7 @@ void of_irq_map_init(unsigned int flags)
642 642
643} 643}
644 644
645int of_irq_map_raw(struct device_node *parent, const u32 *intspec, 645int of_irq_map_raw(struct device_node *parent, const u32 *intspec, u32 ointsize,
646 const u32 *addr, struct of_irq *out_irq) 646 const u32 *addr, struct of_irq *out_irq)
647{ 647{
648 struct device_node *ipar, *tnode, *old = NULL, *newpar = NULL; 648 struct device_node *ipar, *tnode, *old = NULL, *newpar = NULL;
@@ -650,6 +650,9 @@ int of_irq_map_raw(struct device_node *parent, const u32 *intspec,
650 u32 intsize = 1, addrsize, newintsize = 0, newaddrsize = 0; 650 u32 intsize = 1, addrsize, newintsize = 0, newaddrsize = 0;
651 int imaplen, match, i; 651 int imaplen, match, i;
652 652
653 DBG("of_irq_map_raw: par=%s,intspec=[0x%08x 0x%08x...],ointsize=%d\n",
654 parent->full_name, intspec[0], intspec[1], ointsize);
655
653 ipar = of_node_get(parent); 656 ipar = of_node_get(parent);
654 657
655 /* First get the #interrupt-cells property of the current cursor 658 /* First get the #interrupt-cells property of the current cursor
@@ -673,6 +676,9 @@ int of_irq_map_raw(struct device_node *parent, const u32 *intspec,
673 676
674 DBG("of_irq_map_raw: ipar=%s, size=%d\n", ipar->full_name, intsize); 677 DBG("of_irq_map_raw: ipar=%s, size=%d\n", ipar->full_name, intsize);
675 678
679 if (ointsize != intsize)
680 return -EINVAL;
681
676 /* Look for this #address-cells. We have to implement the old linux 682 /* Look for this #address-cells. We have to implement the old linux
677 * trick of looking for the parent here as some device-trees rely on it 683 * trick of looking for the parent here as some device-trees rely on it
678 */ 684 */
@@ -879,12 +885,15 @@ int of_irq_map_one(struct device_node *device, int index, struct of_irq *out_irq
879 } 885 }
880 intsize = *tmp; 886 intsize = *tmp;
881 887
888 DBG(" intsize=%d intlen=%d\n", intsize, intlen);
889
882 /* Check index */ 890 /* Check index */
883 if ((index + 1) * intsize > intlen) 891 if ((index + 1) * intsize > intlen)
884 return -EINVAL; 892 return -EINVAL;
885 893
886 /* Get new specifier and map it */ 894 /* Get new specifier and map it */
887 res = of_irq_map_raw(p, intspec + index * intsize, addr, out_irq); 895 res = of_irq_map_raw(p, intspec + index * intsize, intsize,
896 addr, out_irq);
888 of_node_put(p); 897 of_node_put(p);
889 return res; 898 return res;
890} 899}
@@ -969,7 +978,7 @@ int of_irq_map_pci(struct pci_dev *pdev, struct of_irq *out_irq)
969 laddr[0] = (pdev->bus->number << 16) 978 laddr[0] = (pdev->bus->number << 16)
970 | (pdev->devfn << 8); 979 | (pdev->devfn << 8);
971 laddr[1] = laddr[2] = 0; 980 laddr[1] = laddr[2] = 0;
972 return of_irq_map_raw(ppnode, &lspec, laddr, out_irq); 981 return of_irq_map_raw(ppnode, &lspec, 1, laddr, out_irq);
973} 982}
974EXPORT_SYMBOL_GPL(of_irq_map_pci); 983EXPORT_SYMBOL_GPL(of_irq_map_pci);
975#endif /* CONFIG_PCI */ 984#endif /* CONFIG_PCI */
diff --git a/arch/powerpc/kernel/smp-tbsync.c b/arch/powerpc/kernel/smp-tbsync.c
index f19e2e0e61e7..de59c6c31a5b 100644
--- a/arch/powerpc/kernel/smp-tbsync.c
+++ b/arch/powerpc/kernel/smp-tbsync.c
@@ -45,8 +45,9 @@ void __devinit smp_generic_take_timebase(void)
45{ 45{
46 int cmd; 46 int cmd;
47 u64 tb; 47 u64 tb;
48 unsigned long flags;
48 49
49 local_irq_disable(); 50 local_irq_save(flags);
50 while (!running) 51 while (!running)
51 barrier(); 52 barrier();
52 rmb(); 53 rmb();
@@ -70,7 +71,7 @@ void __devinit smp_generic_take_timebase(void)
70 set_tb(tb >> 32, tb & 0xfffffffful); 71 set_tb(tb >> 32, tb & 0xfffffffful);
71 enter_contest(tbsync->mark, -1); 72 enter_contest(tbsync->mark, -1);
72 } 73 }
73 local_irq_enable(); 74 local_irq_restore(flags);
74} 75}
75 76
76static int __devinit start_contest(int cmd, long offset, int num) 77static int __devinit start_contest(int cmd, long offset, int num)
diff --git a/arch/powerpc/kernel/time.c b/arch/powerpc/kernel/time.c
index 272cb826901d..b9a2061cfdb7 100644
--- a/arch/powerpc/kernel/time.c
+++ b/arch/powerpc/kernel/time.c
@@ -125,15 +125,8 @@ static long timezone_offset;
125unsigned long ppc_proc_freq; 125unsigned long ppc_proc_freq;
126unsigned long ppc_tb_freq; 126unsigned long ppc_tb_freq;
127 127
128u64 tb_last_jiffy __cacheline_aligned_in_smp; 128static u64 tb_last_jiffy __cacheline_aligned_in_smp;
129unsigned long tb_last_stamp; 129static DEFINE_PER_CPU(u64, last_jiffy);
130
131/*
132 * Note that on ppc32 this only stores the bottom 32 bits of
133 * the timebase value, but that's enough to tell when a jiffy
134 * has passed.
135 */
136DEFINE_PER_CPU(unsigned long, last_jiffy);
137 130
138#ifdef CONFIG_VIRT_CPU_ACCOUNTING 131#ifdef CONFIG_VIRT_CPU_ACCOUNTING
139/* 132/*
@@ -458,7 +451,7 @@ void do_gettimeofday(struct timeval *tv)
458 do { 451 do {
459 seq = read_seqbegin_irqsave(&xtime_lock, flags); 452 seq = read_seqbegin_irqsave(&xtime_lock, flags);
460 sec = xtime.tv_sec; 453 sec = xtime.tv_sec;
461 nsec = xtime.tv_nsec + tb_ticks_since(tb_last_stamp); 454 nsec = xtime.tv_nsec + tb_ticks_since(tb_last_jiffy);
462 } while (read_seqretry_irqrestore(&xtime_lock, seq, flags)); 455 } while (read_seqretry_irqrestore(&xtime_lock, seq, flags));
463 usec = nsec / 1000; 456 usec = nsec / 1000;
464 while (usec >= 1000000) { 457 while (usec >= 1000000) {
@@ -700,7 +693,6 @@ void timer_interrupt(struct pt_regs * regs)
700 tb_next_jiffy = tb_last_jiffy + tb_ticks_per_jiffy; 693 tb_next_jiffy = tb_last_jiffy + tb_ticks_per_jiffy;
701 if (per_cpu(last_jiffy, cpu) >= tb_next_jiffy) { 694 if (per_cpu(last_jiffy, cpu) >= tb_next_jiffy) {
702 tb_last_jiffy = tb_next_jiffy; 695 tb_last_jiffy = tb_next_jiffy;
703 tb_last_stamp = per_cpu(last_jiffy, cpu);
704 do_timer(regs); 696 do_timer(regs);
705 timer_recalc_offset(tb_last_jiffy); 697 timer_recalc_offset(tb_last_jiffy);
706 timer_check_rtc(); 698 timer_check_rtc();
@@ -749,7 +741,7 @@ void __init smp_space_timers(unsigned int max_cpus)
749 int i; 741 int i;
750 unsigned long half = tb_ticks_per_jiffy / 2; 742 unsigned long half = tb_ticks_per_jiffy / 2;
751 unsigned long offset = tb_ticks_per_jiffy / max_cpus; 743 unsigned long offset = tb_ticks_per_jiffy / max_cpus;
752 unsigned long previous_tb = per_cpu(last_jiffy, boot_cpuid); 744 u64 previous_tb = per_cpu(last_jiffy, boot_cpuid);
753 745
754 /* make sure tb > per_cpu(last_jiffy, cpu) for all cpus always */ 746 /* make sure tb > per_cpu(last_jiffy, cpu) for all cpus always */
755 previous_tb -= tb_ticks_per_jiffy; 747 previous_tb -= tb_ticks_per_jiffy;
@@ -830,7 +822,7 @@ int do_settimeofday(struct timespec *tv)
830 * and therefore the (jiffies - wall_jiffies) computation 822 * and therefore the (jiffies - wall_jiffies) computation
831 * has been removed. 823 * has been removed.
832 */ 824 */
833 tb_delta = tb_ticks_since(tb_last_stamp); 825 tb_delta = tb_ticks_since(tb_last_jiffy);
834 tb_delta = mulhdu(tb_delta, do_gtod.varp->tb_to_xs); /* in xsec */ 826 tb_delta = mulhdu(tb_delta, do_gtod.varp->tb_to_xs); /* in xsec */
835 new_nsec -= SCALE_XSEC(tb_delta, 1000000000); 827 new_nsec -= SCALE_XSEC(tb_delta, 1000000000);
836 828
@@ -950,8 +942,7 @@ void __init time_init(void)
950 if (__USE_RTC()) { 942 if (__USE_RTC()) {
951 /* 601 processor: dec counts down by 128 every 128ns */ 943 /* 601 processor: dec counts down by 128 every 128ns */
952 ppc_tb_freq = 1000000000; 944 ppc_tb_freq = 1000000000;
953 tb_last_stamp = get_rtcl(); 945 tb_last_jiffy = get_rtcl();
954 tb_last_jiffy = tb_last_stamp;
955 } else { 946 } else {
956 /* Normal PowerPC with timebase register */ 947 /* Normal PowerPC with timebase register */
957 ppc_md.calibrate_decr(); 948 ppc_md.calibrate_decr();
@@ -959,7 +950,7 @@ void __init time_init(void)
959 ppc_tb_freq / 1000000, ppc_tb_freq % 1000000); 950 ppc_tb_freq / 1000000, ppc_tb_freq % 1000000);
960 printk(KERN_DEBUG "time_init: processor frequency = %lu.%.6lu MHz\n", 951 printk(KERN_DEBUG "time_init: processor frequency = %lu.%.6lu MHz\n",
961 ppc_proc_freq / 1000000, ppc_proc_freq % 1000000); 952 ppc_proc_freq / 1000000, ppc_proc_freq % 1000000);
962 tb_last_stamp = tb_last_jiffy = get_tb(); 953 tb_last_jiffy = get_tb();
963 } 954 }
964 955
965 tb_ticks_per_jiffy = ppc_tb_freq / HZ; 956 tb_ticks_per_jiffy = ppc_tb_freq / HZ;
@@ -1036,7 +1027,7 @@ void __init time_init(void)
1036 do_gtod.varp = &do_gtod.vars[0]; 1027 do_gtod.varp = &do_gtod.vars[0];
1037 do_gtod.var_idx = 0; 1028 do_gtod.var_idx = 0;
1038 do_gtod.varp->tb_orig_stamp = tb_last_jiffy; 1029 do_gtod.varp->tb_orig_stamp = tb_last_jiffy;
1039 __get_cpu_var(last_jiffy) = tb_last_stamp; 1030 __get_cpu_var(last_jiffy) = tb_last_jiffy;
1040 do_gtod.varp->stamp_xsec = (u64) xtime.tv_sec * XSEC_PER_SEC; 1031 do_gtod.varp->stamp_xsec = (u64) xtime.tv_sec * XSEC_PER_SEC;
1041 do_gtod.tb_ticks_per_sec = tb_ticks_per_sec; 1032 do_gtod.tb_ticks_per_sec = tb_ticks_per_sec;
1042 do_gtod.varp->tb_to_xs = tb_to_xs; 1033 do_gtod.varp->tb_to_xs = tb_to_xs;
diff --git a/arch/powerpc/kernel/traps.c b/arch/powerpc/kernel/traps.c
index 4d0b4e74d579..9b352bd0a460 100644
--- a/arch/powerpc/kernel/traps.c
+++ b/arch/powerpc/kernel/traps.c
@@ -148,7 +148,7 @@ int die(const char *str, struct pt_regs *regs, long err)
148 panic("Fatal exception in interrupt"); 148 panic("Fatal exception in interrupt");
149 149
150 if (panic_on_oops) 150 if (panic_on_oops)
151 panic("Fatal exception: panic_on_oops"); 151 panic("Fatal exception");
152 152
153 do_exit(err); 153 do_exit(err);
154 154
diff --git a/arch/powerpc/lib/memcpy_64.S b/arch/powerpc/lib/memcpy_64.S
index fd66acfd3e3e..7173ba98f427 100644
--- a/arch/powerpc/lib/memcpy_64.S
+++ b/arch/powerpc/lib/memcpy_64.S
@@ -11,6 +11,7 @@
11 11
12 .align 7 12 .align 7
13_GLOBAL(memcpy) 13_GLOBAL(memcpy)
14 std r3,48(r1) /* save destination pointer for return value */
14 mtcrf 0x01,r5 15 mtcrf 0x01,r5
15 cmpldi cr1,r5,16 16 cmpldi cr1,r5,16
16 neg r6,r3 # LS 3 bits = # bytes to 8-byte dest bdry 17 neg r6,r3 # LS 3 bits = # bytes to 8-byte dest bdry
@@ -38,7 +39,7 @@ _GLOBAL(memcpy)
38 stdu r9,16(r3) 39 stdu r9,16(r3)
39 bdnz 1b 40 bdnz 1b
403: std r8,8(r3) 413: std r8,8(r3)
41 beqlr 42 beq 3f
42 addi r3,r3,16 43 addi r3,r3,16
43 ld r9,8(r4) 44 ld r9,8(r4)
44.Ldo_tail: 45.Ldo_tail:
@@ -53,7 +54,8 @@ _GLOBAL(memcpy)
532: bf cr7*4+3,3f 542: bf cr7*4+3,3f
54 rotldi r9,r9,8 55 rotldi r9,r9,8
55 stb r9,0(r3) 56 stb r9,0(r3)
563: blr 573: ld r3,48(r1) /* return dest pointer */
58 blr
57 59
58.Lsrc_unaligned: 60.Lsrc_unaligned:
59 srdi r6,r5,3 61 srdi r6,r5,3
@@ -115,7 +117,7 @@ _GLOBAL(memcpy)
1155: srd r12,r9,r11 1175: srd r12,r9,r11
116 or r12,r8,r12 118 or r12,r8,r12
117 std r12,24(r3) 119 std r12,24(r3)
118 beqlr 120 beq 4f
119 cmpwi cr1,r5,8 121 cmpwi cr1,r5,8
120 addi r3,r3,32 122 addi r3,r3,32
121 sld r9,r9,r10 123 sld r9,r9,r10
@@ -167,4 +169,5 @@ _GLOBAL(memcpy)
1673: bf cr7*4+3,4f 1693: bf cr7*4+3,4f
168 lbz r0,0(r4) 170 lbz r0,0(r4)
169 stb r0,0(r3) 171 stb r0,0(r3)
1704: blr 1724: ld r3,48(r1) /* return dest pointer */
173 blr
diff --git a/arch/powerpc/platforms/83xx/mpc834x_itx.c b/arch/powerpc/platforms/83xx/mpc834x_itx.c
index d9675f9b9766..969fbb6d8c46 100644
--- a/arch/powerpc/platforms/83xx/mpc834x_itx.c
+++ b/arch/powerpc/platforms/83xx/mpc834x_itx.c
@@ -46,26 +46,6 @@ unsigned long isa_io_base = 0;
46unsigned long isa_mem_base = 0; 46unsigned long isa_mem_base = 0;
47#endif 47#endif
48 48
49#ifdef CONFIG_PCI
50static int
51mpc83xx_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
52{
53 static char pci_irq_table[][4] =
54 /*
55 * PCI IDSEL/INTPIN->INTLINE
56 * A B C D
57 */
58 {
59 {PIRQB, PIRQC, PIRQD, PIRQA}, /* idsel 0x0e */
60 {PIRQA, PIRQB, PIRQC, PIRQD}, /* idsel 0x0f */
61 {PIRQC, PIRQD, PIRQA, PIRQB}, /* idsel 0x10 */
62 };
63
64 const long min_idsel = 0x0e, max_idsel = 0x10, irqs_per_slot = 4;
65 return PCI_IRQ_TABLE_LOOKUP;
66}
67#endif /* CONFIG_PCI */
68
69/* ************************************************************************ 49/* ************************************************************************
70 * 50 *
71 * Setup the architecture 51 * Setup the architecture
@@ -92,8 +72,6 @@ static void __init mpc834x_itx_setup_arch(void)
92 for (np = NULL; (np = of_find_node_by_type(np, "pci")) != NULL;) 72 for (np = NULL; (np = of_find_node_by_type(np, "pci")) != NULL;)
93 add_bridge(np); 73 add_bridge(np);
94 74
95 ppc_md.pci_swizzle = common_swizzle;
96 ppc_md.pci_map_irq = mpc83xx_map_irq;
97 ppc_md.pci_exclude_device = mpc83xx_exclude_device; 75 ppc_md.pci_exclude_device = mpc83xx_exclude_device;
98#endif 76#endif
99 77
@@ -106,25 +84,13 @@ static void __init mpc834x_itx_setup_arch(void)
106 84
107void __init mpc834x_itx_init_IRQ(void) 85void __init mpc834x_itx_init_IRQ(void)
108{ 86{
109 u8 senses[8] = { 87 struct device_node *np;
110 0, /* EXT 0 */ 88
111 IRQ_SENSE_LEVEL, /* EXT 1 */ 89 np = of_find_node_by_type(NULL, "ipic");
112 IRQ_SENSE_LEVEL, /* EXT 2 */ 90 if (!np)
113 0, /* EXT 3 */ 91 return;
114#ifdef CONFIG_PCI
115 IRQ_SENSE_LEVEL, /* EXT 4 */
116 IRQ_SENSE_LEVEL, /* EXT 5 */
117 IRQ_SENSE_LEVEL, /* EXT 6 */
118 IRQ_SENSE_LEVEL, /* EXT 7 */
119#else
120 0, /* EXT 4 */
121 0, /* EXT 5 */
122 0, /* EXT 6 */
123 0, /* EXT 7 */
124#endif
125 };
126 92
127 ipic_init(get_immrbase() + 0x00700, 0, 0, senses, 8); 93 ipic_init(np, 0);
128 94
129 /* Initialize the default interrupt mapping priorities, 95 /* Initialize the default interrupt mapping priorities,
130 * in case the boot rom changed something on us. 96 * in case the boot rom changed something on us.
@@ -153,4 +119,7 @@ define_machine(mpc834x_itx) {
153 .time_init = mpc83xx_time_init, 119 .time_init = mpc83xx_time_init,
154 .calibrate_decr = generic_calibrate_decr, 120 .calibrate_decr = generic_calibrate_decr,
155 .progress = udbg_progress, 121 .progress = udbg_progress,
122#ifdef CONFIG_PCI
123 .pcibios_fixup = mpc83xx_pcibios_fixup,
124#endif
156}; 125};
diff --git a/arch/powerpc/platforms/83xx/mpc834x_sys.c b/arch/powerpc/platforms/83xx/mpc834x_sys.c
index 5eadf9d035f1..677196187a4e 100644
--- a/arch/powerpc/platforms/83xx/mpc834x_sys.c
+++ b/arch/powerpc/platforms/83xx/mpc834x_sys.c
@@ -43,33 +43,6 @@ unsigned long isa_io_base = 0;
43unsigned long isa_mem_base = 0; 43unsigned long isa_mem_base = 0;
44#endif 44#endif
45 45
46#ifdef CONFIG_PCI
47static int
48mpc83xx_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
49{
50 static char pci_irq_table[][4] =
51 /*
52 * PCI IDSEL/INTPIN->INTLINE
53 * A B C D
54 */
55 {
56 {PIRQA, PIRQB, PIRQC, PIRQD}, /* idsel 0x11 */
57 {PIRQC, PIRQD, PIRQA, PIRQB}, /* idsel 0x12 */
58 {PIRQD, PIRQA, PIRQB, PIRQC}, /* idsel 0x13 */
59 {0, 0, 0, 0},
60 {PIRQA, PIRQB, PIRQC, PIRQD}, /* idsel 0x15 */
61 {PIRQD, PIRQA, PIRQB, PIRQC}, /* idsel 0x16 */
62 {PIRQC, PIRQD, PIRQA, PIRQB}, /* idsel 0x17 */
63 {PIRQB, PIRQC, PIRQD, PIRQA}, /* idsel 0x18 */
64 {0, 0, 0, 0}, /* idsel 0x19 */
65 {0, 0, 0, 0}, /* idsel 0x20 */
66 };
67
68 const long min_idsel = 0x11, max_idsel = 0x20, irqs_per_slot = 4;
69 return PCI_IRQ_TABLE_LOOKUP;
70}
71#endif /* CONFIG_PCI */
72
73/* ************************************************************************ 46/* ************************************************************************
74 * 47 *
75 * Setup the architecture 48 * Setup the architecture
@@ -96,8 +69,6 @@ static void __init mpc834x_sys_setup_arch(void)
96 for (np = NULL; (np = of_find_node_by_type(np, "pci")) != NULL;) 69 for (np = NULL; (np = of_find_node_by_type(np, "pci")) != NULL;)
97 add_bridge(np); 70 add_bridge(np);
98 71
99 ppc_md.pci_swizzle = common_swizzle;
100 ppc_md.pci_map_irq = mpc83xx_map_irq;
101 ppc_md.pci_exclude_device = mpc83xx_exclude_device; 72 ppc_md.pci_exclude_device = mpc83xx_exclude_device;
102#endif 73#endif
103 74
@@ -110,25 +81,13 @@ static void __init mpc834x_sys_setup_arch(void)
110 81
111void __init mpc834x_sys_init_IRQ(void) 82void __init mpc834x_sys_init_IRQ(void)
112{ 83{
113 u8 senses[8] = { 84 struct device_node *np;
114 0, /* EXT 0 */ 85
115 IRQ_SENSE_LEVEL, /* EXT 1 */ 86 np = of_find_node_by_type(NULL, "ipic");
116 IRQ_SENSE_LEVEL, /* EXT 2 */ 87 if (!np)
117 0, /* EXT 3 */ 88 return;
118#ifdef CONFIG_PCI
119 IRQ_SENSE_LEVEL, /* EXT 4 */
120 IRQ_SENSE_LEVEL, /* EXT 5 */
121 IRQ_SENSE_LEVEL, /* EXT 6 */
122 IRQ_SENSE_LEVEL, /* EXT 7 */
123#else
124 0, /* EXT 4 */
125 0, /* EXT 5 */
126 0, /* EXT 6 */
127 0, /* EXT 7 */
128#endif
129 };
130 89
131 ipic_init(get_immrbase() + 0x00700, 0, 0, senses, 8); 90 ipic_init(np, 0);
132 91
133 /* Initialize the default interrupt mapping priorities, 92 /* Initialize the default interrupt mapping priorities,
134 * in case the boot rom changed something on us. 93 * in case the boot rom changed something on us.
@@ -178,4 +137,7 @@ define_machine(mpc834x_sys) {
178 .time_init = mpc83xx_time_init, 137 .time_init = mpc83xx_time_init,
179 .calibrate_decr = generic_calibrate_decr, 138 .calibrate_decr = generic_calibrate_decr,
180 .progress = udbg_progress, 139 .progress = udbg_progress,
140#ifdef CONFIG_PCI
141 .pcibios_fixup = mpc83xx_pcibios_fixup,
142#endif
181}; 143};
diff --git a/arch/powerpc/platforms/83xx/mpc83xx.h b/arch/powerpc/platforms/83xx/mpc83xx.h
index 01cae106912b..2c82bca9bfbb 100644
--- a/arch/powerpc/platforms/83xx/mpc83xx.h
+++ b/arch/powerpc/platforms/83xx/mpc83xx.h
@@ -11,6 +11,7 @@
11 11
12extern int add_bridge(struct device_node *dev); 12extern int add_bridge(struct device_node *dev);
13extern int mpc83xx_exclude_device(u_char bus, u_char devfn); 13extern int mpc83xx_exclude_device(u_char bus, u_char devfn);
14extern void mpc83xx_pcibios_fixup(void);
14extern void mpc83xx_restart(char *cmd); 15extern void mpc83xx_restart(char *cmd);
15extern long mpc83xx_time_init(void); 16extern long mpc83xx_time_init(void);
16 17
diff --git a/arch/powerpc/platforms/83xx/pci.c b/arch/powerpc/platforms/83xx/pci.c
index 9c3650555144..4557ac5255c1 100644
--- a/arch/powerpc/platforms/83xx/pci.c
+++ b/arch/powerpc/platforms/83xx/pci.c
@@ -45,6 +45,15 @@ int mpc83xx_exclude_device(u_char bus, u_char devfn)
45 return PCIBIOS_SUCCESSFUL; 45 return PCIBIOS_SUCCESSFUL;
46} 46}
47 47
48void __init mpc83xx_pcibios_fixup(void)
49{
50 struct pci_dev *dev = NULL;
51
52 /* map all the PCI irqs */
53 for_each_pci_dev(dev)
54 pci_read_irq_line(dev);
55}
56
48int __init add_bridge(struct device_node *dev) 57int __init add_bridge(struct device_node *dev)
49{ 58{
50 int len; 59 int len;
diff --git a/arch/powerpc/platforms/embedded6xx/Kconfig b/arch/powerpc/platforms/embedded6xx/Kconfig
index ba07a9a7c039..234a861870a8 100644
--- a/arch/powerpc/platforms/embedded6xx/Kconfig
+++ b/arch/powerpc/platforms/embedded6xx/Kconfig
@@ -80,6 +80,7 @@ config MPC7448HPC2
80 select DEFAULT_UIMAGE 80 select DEFAULT_UIMAGE
81 select PPC_UDBG_16550 81 select PPC_UDBG_16550
82 select MPIC 82 select MPIC
83 select MPIC_WEIRD
83 help 84 help
84 Select MPC7448HPC2 if configuring for Freescale MPC7448HPC2 (Taiga) 85 Select MPC7448HPC2 if configuring for Freescale MPC7448HPC2 (Taiga)
85 platform 86 platform
diff --git a/arch/powerpc/platforms/embedded6xx/mpc7448_hpc2.c b/arch/powerpc/platforms/embedded6xx/mpc7448_hpc2.c
index 673ee69c62e3..e4f2b9df5e17 100644
--- a/arch/powerpc/platforms/embedded6xx/mpc7448_hpc2.c
+++ b/arch/powerpc/platforms/embedded6xx/mpc7448_hpc2.c
@@ -215,7 +215,7 @@ static void __init mpc7448_hpc2_init_IRQ(void)
215 215
216 mpic = mpic_alloc(tsi_pic, mpic_paddr, 216 mpic = mpic_alloc(tsi_pic, mpic_paddr,
217 MPIC_PRIMARY | MPIC_BIG_ENDIAN | MPIC_WANTS_RESET | 217 MPIC_PRIMARY | MPIC_BIG_ENDIAN | MPIC_WANTS_RESET |
218 MPIC_SPV_EOI | MPIC_MOD_ID(MPIC_ID_TSI108), 218 MPIC_SPV_EOI | MPIC_NO_PTHROU_DIS | MPIC_REGSET_TSI108,
219 0, /* num_sources used */ 219 0, /* num_sources used */
220 0, /* num_sources used */ 220 0, /* num_sources used */
221 "Tsi108_PIC"); 221 "Tsi108_PIC");
diff --git a/arch/powerpc/sysdev/Makefile b/arch/powerpc/sysdev/Makefile
index cebfae242602..e5e999ea891a 100644
--- a/arch/powerpc/sysdev/Makefile
+++ b/arch/powerpc/sysdev/Makefile
@@ -9,11 +9,11 @@ obj-$(CONFIG_BOOKE) += dcr.o
9obj-$(CONFIG_40x) += dcr.o 9obj-$(CONFIG_40x) += dcr.o
10obj-$(CONFIG_U3_DART) += dart_iommu.o 10obj-$(CONFIG_U3_DART) += dart_iommu.o
11obj-$(CONFIG_MMIO_NVRAM) += mmio_nvram.o 11obj-$(CONFIG_MMIO_NVRAM) += mmio_nvram.o
12obj-$(CONFIG_PPC_83xx) += ipic.o
13obj-$(CONFIG_FSL_SOC) += fsl_soc.o 12obj-$(CONFIG_FSL_SOC) += fsl_soc.o
14obj-$(CONFIG_PPC_TODC) += todc.o 13obj-$(CONFIG_PPC_TODC) += todc.o
15obj-$(CONFIG_TSI108_BRIDGE) += tsi108_pci.o tsi108_dev.o 14obj-$(CONFIG_TSI108_BRIDGE) += tsi108_pci.o tsi108_dev.o
16 15
17ifeq ($(CONFIG_PPC_MERGE),y) 16ifeq ($(CONFIG_PPC_MERGE),y)
18obj-$(CONFIG_PPC_I8259) += i8259.o 17obj-$(CONFIG_PPC_I8259) += i8259.o
19 endif 18obj-$(CONFIG_PPC_83xx) += ipic.o
19endif
diff --git a/arch/powerpc/sysdev/ipic.c b/arch/powerpc/sysdev/ipic.c
index 46801f5ec03f..70e707785d49 100644
--- a/arch/powerpc/sysdev/ipic.c
+++ b/arch/powerpc/sysdev/ipic.c
@@ -19,15 +19,18 @@
19#include <linux/sched.h> 19#include <linux/sched.h>
20#include <linux/signal.h> 20#include <linux/signal.h>
21#include <linux/sysdev.h> 21#include <linux/sysdev.h>
22#include <linux/device.h>
23#include <linux/bootmem.h>
24#include <linux/spinlock.h>
22#include <asm/irq.h> 25#include <asm/irq.h>
23#include <asm/io.h> 26#include <asm/io.h>
27#include <asm/prom.h>
24#include <asm/ipic.h> 28#include <asm/ipic.h>
25#include <asm/mpc83xx.h>
26 29
27#include "ipic.h" 30#include "ipic.h"
28 31
29static struct ipic p_ipic;
30static struct ipic * primary_ipic; 32static struct ipic * primary_ipic;
33static DEFINE_SPINLOCK(ipic_lock);
31 34
32static struct ipic_info ipic_info[] = { 35static struct ipic_info ipic_info[] = {
33 [9] = { 36 [9] = {
@@ -373,74 +376,220 @@ static inline void ipic_write(volatile u32 __iomem *base, unsigned int reg, u32
373 out_be32(base + (reg >> 2), value); 376 out_be32(base + (reg >> 2), value);
374} 377}
375 378
376static inline struct ipic * ipic_from_irq(unsigned int irq) 379static inline struct ipic * ipic_from_irq(unsigned int virq)
377{ 380{
378 return primary_ipic; 381 return primary_ipic;
379} 382}
380 383
381static void ipic_enable_irq(unsigned int irq) 384#define ipic_irq_to_hw(virq) ((unsigned int)irq_map[virq].hwirq)
385
386static void ipic_unmask_irq(unsigned int virq)
382{ 387{
383 struct ipic *ipic = ipic_from_irq(irq); 388 struct ipic *ipic = ipic_from_irq(virq);
384 unsigned int src = irq - ipic->irq_offset; 389 unsigned int src = ipic_irq_to_hw(virq);
390 unsigned long flags;
385 u32 temp; 391 u32 temp;
386 392
393 spin_lock_irqsave(&ipic_lock, flags);
394
387 temp = ipic_read(ipic->regs, ipic_info[src].mask); 395 temp = ipic_read(ipic->regs, ipic_info[src].mask);
388 temp |= (1 << (31 - ipic_info[src].bit)); 396 temp |= (1 << (31 - ipic_info[src].bit));
389 ipic_write(ipic->regs, ipic_info[src].mask, temp); 397 ipic_write(ipic->regs, ipic_info[src].mask, temp);
398
399 spin_unlock_irqrestore(&ipic_lock, flags);
390} 400}
391 401
392static void ipic_disable_irq(unsigned int irq) 402static void ipic_mask_irq(unsigned int virq)
393{ 403{
394 struct ipic *ipic = ipic_from_irq(irq); 404 struct ipic *ipic = ipic_from_irq(virq);
395 unsigned int src = irq - ipic->irq_offset; 405 unsigned int src = ipic_irq_to_hw(virq);
406 unsigned long flags;
396 u32 temp; 407 u32 temp;
397 408
409 spin_lock_irqsave(&ipic_lock, flags);
410
398 temp = ipic_read(ipic->regs, ipic_info[src].mask); 411 temp = ipic_read(ipic->regs, ipic_info[src].mask);
399 temp &= ~(1 << (31 - ipic_info[src].bit)); 412 temp &= ~(1 << (31 - ipic_info[src].bit));
400 ipic_write(ipic->regs, ipic_info[src].mask, temp); 413 ipic_write(ipic->regs, ipic_info[src].mask, temp);
414
415 spin_unlock_irqrestore(&ipic_lock, flags);
401} 416}
402 417
403static void ipic_disable_irq_and_ack(unsigned int irq) 418static void ipic_ack_irq(unsigned int virq)
404{ 419{
405 struct ipic *ipic = ipic_from_irq(irq); 420 struct ipic *ipic = ipic_from_irq(virq);
406 unsigned int src = irq - ipic->irq_offset; 421 unsigned int src = ipic_irq_to_hw(virq);
422 unsigned long flags;
407 u32 temp; 423 u32 temp;
408 424
409 ipic_disable_irq(irq); 425 spin_lock_irqsave(&ipic_lock, flags);
410 426
411 temp = ipic_read(ipic->regs, ipic_info[src].pend); 427 temp = ipic_read(ipic->regs, ipic_info[src].pend);
412 temp |= (1 << (31 - ipic_info[src].bit)); 428 temp |= (1 << (31 - ipic_info[src].bit));
413 ipic_write(ipic->regs, ipic_info[src].pend, temp); 429 ipic_write(ipic->regs, ipic_info[src].pend, temp);
430
431 spin_unlock_irqrestore(&ipic_lock, flags);
414} 432}
415 433
416static void ipic_end_irq(unsigned int irq) 434static void ipic_mask_irq_and_ack(unsigned int virq)
417{ 435{
418 if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) 436 struct ipic *ipic = ipic_from_irq(virq);
419 ipic_enable_irq(irq); 437 unsigned int src = ipic_irq_to_hw(virq);
438 unsigned long flags;
439 u32 temp;
440
441 spin_lock_irqsave(&ipic_lock, flags);
442
443 temp = ipic_read(ipic->regs, ipic_info[src].mask);
444 temp &= ~(1 << (31 - ipic_info[src].bit));
445 ipic_write(ipic->regs, ipic_info[src].mask, temp);
446
447 temp = ipic_read(ipic->regs, ipic_info[src].pend);
448 temp |= (1 << (31 - ipic_info[src].bit));
449 ipic_write(ipic->regs, ipic_info[src].pend, temp);
450
451 spin_unlock_irqrestore(&ipic_lock, flags);
420} 452}
421 453
422struct hw_interrupt_type ipic = { 454static int ipic_set_irq_type(unsigned int virq, unsigned int flow_type)
423 .typename = " IPIC ", 455{
424 .enable = ipic_enable_irq, 456 struct ipic *ipic = ipic_from_irq(virq);
425 .disable = ipic_disable_irq, 457 unsigned int src = ipic_irq_to_hw(virq);
426 .ack = ipic_disable_irq_and_ack, 458 struct irq_desc *desc = get_irq_desc(virq);
427 .end = ipic_end_irq, 459 unsigned int vold, vnew, edibit;
460
461 if (flow_type == IRQ_TYPE_NONE)
462 flow_type = IRQ_TYPE_LEVEL_LOW;
463
464 /* ipic supports only low assertion and high-to-low change senses
465 */
466 if (!(flow_type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_EDGE_FALLING))) {
467 printk(KERN_ERR "ipic: sense type 0x%x not supported\n",
468 flow_type);
469 return -EINVAL;
470 }
471
472 desc->status &= ~(IRQ_TYPE_SENSE_MASK | IRQ_LEVEL);
473 desc->status |= flow_type & IRQ_TYPE_SENSE_MASK;
474 if (flow_type & IRQ_TYPE_LEVEL_LOW) {
475 desc->status |= IRQ_LEVEL;
476 set_irq_handler(virq, handle_level_irq);
477 } else {
478 set_irq_handler(virq, handle_edge_irq);
479 }
480
481 /* only EXT IRQ senses are programmable on ipic
482 * internal IRQ senses are LEVEL_LOW
483 */
484 if (src == IPIC_IRQ_EXT0)
485 edibit = 15;
486 else
487 if (src >= IPIC_IRQ_EXT1 && src <= IPIC_IRQ_EXT7)
488 edibit = (14 - (src - IPIC_IRQ_EXT1));
489 else
490 return (flow_type & IRQ_TYPE_LEVEL_LOW) ? 0 : -EINVAL;
491
492 vold = ipic_read(ipic->regs, IPIC_SECNR);
493 if ((flow_type & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_FALLING) {
494 vnew = vold | (1 << edibit);
495 } else {
496 vnew = vold & ~(1 << edibit);
497 }
498 if (vold != vnew)
499 ipic_write(ipic->regs, IPIC_SECNR, vnew);
500 return 0;
501}
502
503static struct irq_chip ipic_irq_chip = {
504 .typename = " IPIC ",
505 .unmask = ipic_unmask_irq,
506 .mask = ipic_mask_irq,
507 .mask_ack = ipic_mask_irq_and_ack,
508 .ack = ipic_ack_irq,
509 .set_type = ipic_set_irq_type,
510};
511
512static int ipic_host_match(struct irq_host *h, struct device_node *node)
513{
514 struct ipic *ipic = h->host_data;
515
516 /* Exact match, unless ipic node is NULL */
517 return ipic->of_node == NULL || ipic->of_node == node;
518}
519
520static int ipic_host_map(struct irq_host *h, unsigned int virq,
521 irq_hw_number_t hw)
522{
523 struct ipic *ipic = h->host_data;
524 struct irq_chip *chip;
525
526 /* Default chip */
527 chip = &ipic->hc_irq;
528
529 set_irq_chip_data(virq, ipic);
530 set_irq_chip_and_handler(virq, chip, handle_level_irq);
531
532 /* Set default irq type */
533 set_irq_type(virq, IRQ_TYPE_NONE);
534
535 return 0;
536}
537
538static int ipic_host_xlate(struct irq_host *h, struct device_node *ct,
539 u32 *intspec, unsigned int intsize,
540 irq_hw_number_t *out_hwirq, unsigned int *out_flags)
541
542{
543 /* interrupt sense values coming from the device tree equal either
544 * LEVEL_LOW (low assertion) or EDGE_FALLING (high-to-low change)
545 */
546 *out_hwirq = intspec[0];
547 if (intsize > 1)
548 *out_flags = intspec[1];
549 else
550 *out_flags = IRQ_TYPE_NONE;
551 return 0;
552}
553
554static struct irq_host_ops ipic_host_ops = {
555 .match = ipic_host_match,
556 .map = ipic_host_map,
557 .xlate = ipic_host_xlate,
428}; 558};
429 559
430void __init ipic_init(phys_addr_t phys_addr, 560void __init ipic_init(struct device_node *node,
431 unsigned int flags, 561 unsigned int flags)
432 unsigned int irq_offset,
433 unsigned char *senses,
434 unsigned int senses_count)
435{ 562{
436 u32 i, temp = 0; 563 struct ipic *ipic;
564 struct resource res;
565 u32 temp = 0, ret;
566
567 ipic = alloc_bootmem(sizeof(struct ipic));
568 if (ipic == NULL)
569 return;
570
571 memset(ipic, 0, sizeof(struct ipic));
572 ipic->of_node = node ? of_node_get(node) : NULL;
573
574 ipic->irqhost = irq_alloc_host(IRQ_HOST_MAP_LINEAR,
575 NR_IPIC_INTS,
576 &ipic_host_ops, 0);
577 if (ipic->irqhost == NULL) {
578 of_node_put(node);
579 return;
580 }
581
582 ret = of_address_to_resource(node, 0, &res);
583 if (ret)
584 return;
437 585
438 primary_ipic = &p_ipic; 586 ipic->regs = ioremap(res.start, res.end - res.start + 1);
439 primary_ipic->regs = ioremap(phys_addr, MPC83xx_IPIC_SIZE);
440 587
441 primary_ipic->irq_offset = irq_offset; 588 ipic->irqhost->host_data = ipic;
589 ipic->hc_irq = ipic_irq_chip;
442 590
443 ipic_write(primary_ipic->regs, IPIC_SICNR, 0x0); 591 /* init hw */
592 ipic_write(ipic->regs, IPIC_SICNR, 0x0);
444 593
445 /* default priority scheme is grouped. If spread mode is required 594 /* default priority scheme is grouped. If spread mode is required
446 * configure SICFR accordingly */ 595 * configure SICFR accordingly */
@@ -453,49 +602,35 @@ void __init ipic_init(phys_addr_t phys_addr,
453 if (flags & IPIC_SPREADMODE_MIX_B) 602 if (flags & IPIC_SPREADMODE_MIX_B)
454 temp |= SICFR_MPSB; 603 temp |= SICFR_MPSB;
455 604
456 ipic_write(primary_ipic->regs, IPIC_SICNR, temp); 605 ipic_write(ipic->regs, IPIC_SICNR, temp);
457 606
458 /* handle MCP route */ 607 /* handle MCP route */
459 temp = 0; 608 temp = 0;
460 if (flags & IPIC_DISABLE_MCP_OUT) 609 if (flags & IPIC_DISABLE_MCP_OUT)
461 temp = SERCR_MCPR; 610 temp = SERCR_MCPR;
462 ipic_write(primary_ipic->regs, IPIC_SERCR, temp); 611 ipic_write(ipic->regs, IPIC_SERCR, temp);
463 612
464 /* handle routing of IRQ0 to MCP */ 613 /* handle routing of IRQ0 to MCP */
465 temp = ipic_read(primary_ipic->regs, IPIC_SEMSR); 614 temp = ipic_read(ipic->regs, IPIC_SEMSR);
466 615
467 if (flags & IPIC_IRQ0_MCP) 616 if (flags & IPIC_IRQ0_MCP)
468 temp |= SEMSR_SIRQ0; 617 temp |= SEMSR_SIRQ0;
469 else 618 else
470 temp &= ~SEMSR_SIRQ0; 619 temp &= ~SEMSR_SIRQ0;
471 620
472 ipic_write(primary_ipic->regs, IPIC_SEMSR, temp); 621 ipic_write(ipic->regs, IPIC_SEMSR, temp);
473 622
474 for (i = 0 ; i < NR_IPIC_INTS ; i++) { 623 primary_ipic = ipic;
475 irq_desc[i+irq_offset].chip = &ipic; 624 irq_set_default_host(primary_ipic->irqhost);
476 irq_desc[i+irq_offset].status = IRQ_LEVEL;
477 }
478 625
479 temp = 0; 626 printk ("IPIC (%d IRQ sources) at %p\n", NR_IPIC_INTS,
480 for (i = 0 ; i < senses_count ; i++) { 627 primary_ipic->regs);
481 if ((senses[i] & IRQ_SENSE_MASK) == IRQ_SENSE_EDGE) {
482 temp |= 1 << (15 - i);
483 if (i != 0)
484 irq_desc[i + irq_offset + MPC83xx_IRQ_EXT1 - 1].status = 0;
485 else
486 irq_desc[irq_offset + MPC83xx_IRQ_EXT0].status = 0;
487 }
488 }
489 ipic_write(primary_ipic->regs, IPIC_SECNR, temp);
490
491 printk ("IPIC (%d IRQ sources, %d External IRQs) at %p\n", NR_IPIC_INTS,
492 senses_count, primary_ipic->regs);
493} 628}
494 629
495int ipic_set_priority(unsigned int irq, unsigned int priority) 630int ipic_set_priority(unsigned int virq, unsigned int priority)
496{ 631{
497 struct ipic *ipic = ipic_from_irq(irq); 632 struct ipic *ipic = ipic_from_irq(virq);
498 unsigned int src = irq - ipic->irq_offset; 633 unsigned int src = ipic_irq_to_hw(virq);
499 u32 temp; 634 u32 temp;
500 635
501 if (priority > 7) 636 if (priority > 7)
@@ -520,10 +655,10 @@ int ipic_set_priority(unsigned int irq, unsigned int priority)
520 return 0; 655 return 0;
521} 656}
522 657
523void ipic_set_highest_priority(unsigned int irq) 658void ipic_set_highest_priority(unsigned int virq)
524{ 659{
525 struct ipic *ipic = ipic_from_irq(irq); 660 struct ipic *ipic = ipic_from_irq(virq);
526 unsigned int src = irq - ipic->irq_offset; 661 unsigned int src = ipic_irq_to_hw(virq);
527 u32 temp; 662 u32 temp;
528 663
529 temp = ipic_read(ipic->regs, IPIC_SICFR); 664 temp = ipic_read(ipic->regs, IPIC_SICFR);
@@ -537,37 +672,10 @@ void ipic_set_highest_priority(unsigned int irq)
537 672
538void ipic_set_default_priority(void) 673void ipic_set_default_priority(void)
539{ 674{
540 ipic_set_priority(MPC83xx_IRQ_TSEC1_TX, 0); 675 ipic_write(primary_ipic->regs, IPIC_SIPRR_A, IPIC_SIPRR_A_DEFAULT);
541 ipic_set_priority(MPC83xx_IRQ_TSEC1_RX, 1); 676 ipic_write(primary_ipic->regs, IPIC_SIPRR_D, IPIC_SIPRR_D_DEFAULT);
542 ipic_set_priority(MPC83xx_IRQ_TSEC1_ERROR, 2); 677 ipic_write(primary_ipic->regs, IPIC_SMPRR_A, IPIC_SMPRR_A_DEFAULT);
543 ipic_set_priority(MPC83xx_IRQ_TSEC2_TX, 3); 678 ipic_write(primary_ipic->regs, IPIC_SMPRR_B, IPIC_SMPRR_B_DEFAULT);
544 ipic_set_priority(MPC83xx_IRQ_TSEC2_RX, 4);
545 ipic_set_priority(MPC83xx_IRQ_TSEC2_ERROR, 5);
546 ipic_set_priority(MPC83xx_IRQ_USB2_DR, 6);
547 ipic_set_priority(MPC83xx_IRQ_USB2_MPH, 7);
548
549 ipic_set_priority(MPC83xx_IRQ_UART1, 0);
550 ipic_set_priority(MPC83xx_IRQ_UART2, 1);
551 ipic_set_priority(MPC83xx_IRQ_SEC2, 2);
552 ipic_set_priority(MPC83xx_IRQ_IIC1, 5);
553 ipic_set_priority(MPC83xx_IRQ_IIC2, 6);
554 ipic_set_priority(MPC83xx_IRQ_SPI, 7);
555 ipic_set_priority(MPC83xx_IRQ_RTC_SEC, 0);
556 ipic_set_priority(MPC83xx_IRQ_PIT, 1);
557 ipic_set_priority(MPC83xx_IRQ_PCI1, 2);
558 ipic_set_priority(MPC83xx_IRQ_PCI2, 3);
559 ipic_set_priority(MPC83xx_IRQ_EXT0, 4);
560 ipic_set_priority(MPC83xx_IRQ_EXT1, 5);
561 ipic_set_priority(MPC83xx_IRQ_EXT2, 6);
562 ipic_set_priority(MPC83xx_IRQ_EXT3, 7);
563 ipic_set_priority(MPC83xx_IRQ_RTC_ALR, 0);
564 ipic_set_priority(MPC83xx_IRQ_MU, 1);
565 ipic_set_priority(MPC83xx_IRQ_SBA, 2);
566 ipic_set_priority(MPC83xx_IRQ_DMA, 3);
567 ipic_set_priority(MPC83xx_IRQ_EXT4, 4);
568 ipic_set_priority(MPC83xx_IRQ_EXT5, 5);
569 ipic_set_priority(MPC83xx_IRQ_EXT6, 6);
570 ipic_set_priority(MPC83xx_IRQ_EXT7, 7);
571} 679}
572 680
573void ipic_enable_mcp(enum ipic_mcp_irq mcp_irq) 681void ipic_enable_mcp(enum ipic_mcp_irq mcp_irq)
@@ -600,17 +708,20 @@ void ipic_clear_mcp_status(u32 mask)
600 ipic_write(primary_ipic->regs, IPIC_SERMR, mask); 708 ipic_write(primary_ipic->regs, IPIC_SERMR, mask);
601} 709}
602 710
603/* Return an interrupt vector or -1 if no interrupt is pending. */ 711/* Return an interrupt vector or NO_IRQ if no interrupt is pending. */
604int ipic_get_irq(struct pt_regs *regs) 712unsigned int ipic_get_irq(struct pt_regs *regs)
605{ 713{
606 int irq; 714 int irq;
607 715
608 irq = ipic_read(primary_ipic->regs, IPIC_SIVCR) & 0x7f; 716 BUG_ON(primary_ipic == NULL);
717
718#define IPIC_SIVCR_VECTOR_MASK 0x7f
719 irq = ipic_read(primary_ipic->regs, IPIC_SIVCR) & IPIC_SIVCR_VECTOR_MASK;
609 720
610 if (irq == 0) /* 0 --> no irq is pending */ 721 if (irq == 0) /* 0 --> no irq is pending */
611 irq = -1; 722 return NO_IRQ;
612 723
613 return irq; 724 return irq_linear_revmap(primary_ipic->irqhost, irq);
614} 725}
615 726
616static struct sysdev_class ipic_sysclass = { 727static struct sysdev_class ipic_sysclass = {
diff --git a/arch/powerpc/sysdev/ipic.h b/arch/powerpc/sysdev/ipic.h
index a60c9d18bb7f..c28e589877eb 100644
--- a/arch/powerpc/sysdev/ipic.h
+++ b/arch/powerpc/sysdev/ipic.h
@@ -15,7 +15,18 @@
15 15
16#include <asm/ipic.h> 16#include <asm/ipic.h>
17 17
18#define MPC83xx_IPIC_SIZE (0x00100) 18#define NR_IPIC_INTS 128
19
20/* External IRQS */
21#define IPIC_IRQ_EXT0 48
22#define IPIC_IRQ_EXT1 17
23#define IPIC_IRQ_EXT7 23
24
25/* Default Priority Registers */
26#define IPIC_SIPRR_A_DEFAULT 0x05309770
27#define IPIC_SIPRR_D_DEFAULT 0x05309770
28#define IPIC_SMPRR_A_DEFAULT 0x05309770
29#define IPIC_SMPRR_B_DEFAULT 0x05309770
19 30
20/* System Global Interrupt Configuration Register */ 31/* System Global Interrupt Configuration Register */
21#define SICFR_IPSA 0x00010000 32#define SICFR_IPSA 0x00010000
@@ -31,7 +42,15 @@
31 42
32struct ipic { 43struct ipic {
33 volatile u32 __iomem *regs; 44 volatile u32 __iomem *regs;
34 unsigned int irq_offset; 45
46 /* The remapper for this IPIC */
47 struct irq_host *irqhost;
48
49 /* The "linux" controller struct */
50 struct irq_chip hc_irq;
51
52 /* The device node of the interrupt controller */
53 struct device_node *of_node;
35}; 54};
36 55
37struct ipic_info { 56struct ipic_info {
diff --git a/arch/powerpc/sysdev/mpic.c b/arch/powerpc/sysdev/mpic.c
index 6e0281afa6c3..b604926401f5 100644
--- a/arch/powerpc/sysdev/mpic.c
+++ b/arch/powerpc/sysdev/mpic.c
@@ -54,6 +54,94 @@ static DEFINE_SPINLOCK(mpic_lock);
54#endif 54#endif
55#endif 55#endif
56 56
57#ifdef CONFIG_MPIC_WEIRD
58static u32 mpic_infos[][MPIC_IDX_END] = {
59 [0] = { /* Original OpenPIC compatible MPIC */
60 MPIC_GREG_BASE,
61 MPIC_GREG_FEATURE_0,
62 MPIC_GREG_GLOBAL_CONF_0,
63 MPIC_GREG_VENDOR_ID,
64 MPIC_GREG_IPI_VECTOR_PRI_0,
65 MPIC_GREG_IPI_STRIDE,
66 MPIC_GREG_SPURIOUS,
67 MPIC_GREG_TIMER_FREQ,
68
69 MPIC_TIMER_BASE,
70 MPIC_TIMER_STRIDE,
71 MPIC_TIMER_CURRENT_CNT,
72 MPIC_TIMER_BASE_CNT,
73 MPIC_TIMER_VECTOR_PRI,
74 MPIC_TIMER_DESTINATION,
75
76 MPIC_CPU_BASE,
77 MPIC_CPU_STRIDE,
78 MPIC_CPU_IPI_DISPATCH_0,
79 MPIC_CPU_IPI_DISPATCH_STRIDE,
80 MPIC_CPU_CURRENT_TASK_PRI,
81 MPIC_CPU_WHOAMI,
82 MPIC_CPU_INTACK,
83 MPIC_CPU_EOI,
84
85 MPIC_IRQ_BASE,
86 MPIC_IRQ_STRIDE,
87 MPIC_IRQ_VECTOR_PRI,
88 MPIC_VECPRI_VECTOR_MASK,
89 MPIC_VECPRI_POLARITY_POSITIVE,
90 MPIC_VECPRI_POLARITY_NEGATIVE,
91 MPIC_VECPRI_SENSE_LEVEL,
92 MPIC_VECPRI_SENSE_EDGE,
93 MPIC_VECPRI_POLARITY_MASK,
94 MPIC_VECPRI_SENSE_MASK,
95 MPIC_IRQ_DESTINATION
96 },
97 [1] = { /* Tsi108/109 PIC */
98 TSI108_GREG_BASE,
99 TSI108_GREG_FEATURE_0,
100 TSI108_GREG_GLOBAL_CONF_0,
101 TSI108_GREG_VENDOR_ID,
102 TSI108_GREG_IPI_VECTOR_PRI_0,
103 TSI108_GREG_IPI_STRIDE,
104 TSI108_GREG_SPURIOUS,
105 TSI108_GREG_TIMER_FREQ,
106
107 TSI108_TIMER_BASE,
108 TSI108_TIMER_STRIDE,
109 TSI108_TIMER_CURRENT_CNT,
110 TSI108_TIMER_BASE_CNT,
111 TSI108_TIMER_VECTOR_PRI,
112 TSI108_TIMER_DESTINATION,
113
114 TSI108_CPU_BASE,
115 TSI108_CPU_STRIDE,
116 TSI108_CPU_IPI_DISPATCH_0,
117 TSI108_CPU_IPI_DISPATCH_STRIDE,
118 TSI108_CPU_CURRENT_TASK_PRI,
119 TSI108_CPU_WHOAMI,
120 TSI108_CPU_INTACK,
121 TSI108_CPU_EOI,
122
123 TSI108_IRQ_BASE,
124 TSI108_IRQ_STRIDE,
125 TSI108_IRQ_VECTOR_PRI,
126 TSI108_VECPRI_VECTOR_MASK,
127 TSI108_VECPRI_POLARITY_POSITIVE,
128 TSI108_VECPRI_POLARITY_NEGATIVE,
129 TSI108_VECPRI_SENSE_LEVEL,
130 TSI108_VECPRI_SENSE_EDGE,
131 TSI108_VECPRI_POLARITY_MASK,
132 TSI108_VECPRI_SENSE_MASK,
133 TSI108_IRQ_DESTINATION
134 },
135};
136
137#define MPIC_INFO(name) mpic->hw_set[MPIC_IDX_##name]
138
139#else /* CONFIG_MPIC_WEIRD */
140
141#define MPIC_INFO(name) MPIC_##name
142
143#endif /* CONFIG_MPIC_WEIRD */
144
57/* 145/*
58 * Register accessor functions 146 * Register accessor functions
59 */ 147 */
@@ -80,7 +168,8 @@ static inline void _mpic_write(unsigned int be, volatile u32 __iomem *base,
80static inline u32 _mpic_ipi_read(struct mpic *mpic, unsigned int ipi) 168static inline u32 _mpic_ipi_read(struct mpic *mpic, unsigned int ipi)
81{ 169{
82 unsigned int be = (mpic->flags & MPIC_BIG_ENDIAN) != 0; 170 unsigned int be = (mpic->flags & MPIC_BIG_ENDIAN) != 0;
83 unsigned int offset = MPIC_GREG_IPI_VECTOR_PRI_0 + (ipi * 0x10); 171 unsigned int offset = MPIC_INFO(GREG_IPI_VECTOR_PRI_0) +
172 (ipi * MPIC_INFO(GREG_IPI_STRIDE));
84 173
85 if (mpic->flags & MPIC_BROKEN_IPI) 174 if (mpic->flags & MPIC_BROKEN_IPI)
86 be = !be; 175 be = !be;
@@ -89,7 +178,8 @@ static inline u32 _mpic_ipi_read(struct mpic *mpic, unsigned int ipi)
89 178
90static inline void _mpic_ipi_write(struct mpic *mpic, unsigned int ipi, u32 value) 179static inline void _mpic_ipi_write(struct mpic *mpic, unsigned int ipi, u32 value)
91{ 180{
92 unsigned int offset = MPIC_GREG_IPI_VECTOR_PRI_0 + (ipi * 0x10); 181 unsigned int offset = MPIC_INFO(GREG_IPI_VECTOR_PRI_0) +
182 (ipi * MPIC_INFO(GREG_IPI_STRIDE));
93 183
94 _mpic_write(mpic->flags & MPIC_BIG_ENDIAN, mpic->gregs, offset, value); 184 _mpic_write(mpic->flags & MPIC_BIG_ENDIAN, mpic->gregs, offset, value);
95} 185}
@@ -120,7 +210,7 @@ static inline u32 _mpic_irq_read(struct mpic *mpic, unsigned int src_no, unsigne
120 unsigned int idx = src_no & mpic->isu_mask; 210 unsigned int idx = src_no & mpic->isu_mask;
121 211
122 return _mpic_read(mpic->flags & MPIC_BIG_ENDIAN, mpic->isus[isu], 212 return _mpic_read(mpic->flags & MPIC_BIG_ENDIAN, mpic->isus[isu],
123 reg + (idx * MPIC_IRQ_STRIDE)); 213 reg + (idx * MPIC_INFO(IRQ_STRIDE)));
124} 214}
125 215
126static inline void _mpic_irq_write(struct mpic *mpic, unsigned int src_no, 216static inline void _mpic_irq_write(struct mpic *mpic, unsigned int src_no,
@@ -130,7 +220,7 @@ static inline void _mpic_irq_write(struct mpic *mpic, unsigned int src_no,
130 unsigned int idx = src_no & mpic->isu_mask; 220 unsigned int idx = src_no & mpic->isu_mask;
131 221
132 _mpic_write(mpic->flags & MPIC_BIG_ENDIAN, mpic->isus[isu], 222 _mpic_write(mpic->flags & MPIC_BIG_ENDIAN, mpic->isus[isu],
133 reg + (idx * MPIC_IRQ_STRIDE), value); 223 reg + (idx * MPIC_INFO(IRQ_STRIDE)), value);
134} 224}
135 225
136#define mpic_read(b,r) _mpic_read(mpic->flags & MPIC_BIG_ENDIAN,(b),(r)) 226#define mpic_read(b,r) _mpic_read(mpic->flags & MPIC_BIG_ENDIAN,(b),(r))
@@ -156,8 +246,8 @@ static void __init mpic_test_broken_ipi(struct mpic *mpic)
156{ 246{
157 u32 r; 247 u32 r;
158 248
159 mpic_write(mpic->gregs, MPIC_GREG_IPI_VECTOR_PRI_0, MPIC_VECPRI_MASK); 249 mpic_write(mpic->gregs, MPIC_INFO(GREG_IPI_VECTOR_PRI_0), MPIC_VECPRI_MASK);
160 r = mpic_read(mpic->gregs, MPIC_GREG_IPI_VECTOR_PRI_0); 250 r = mpic_read(mpic->gregs, MPIC_INFO(GREG_IPI_VECTOR_PRI_0));
161 251
162 if (r == le32_to_cpu(MPIC_VECPRI_MASK)) { 252 if (r == le32_to_cpu(MPIC_VECPRI_MASK)) {
163 printk(KERN_INFO "mpic: Detected reversed IPI registers\n"); 253 printk(KERN_INFO "mpic: Detected reversed IPI registers\n");
@@ -394,8 +484,8 @@ static inline struct mpic * mpic_from_irq(unsigned int irq)
394/* Send an EOI */ 484/* Send an EOI */
395static inline void mpic_eoi(struct mpic *mpic) 485static inline void mpic_eoi(struct mpic *mpic)
396{ 486{
397 mpic_cpu_write(MPIC_CPU_EOI, 0); 487 mpic_cpu_write(MPIC_INFO(CPU_EOI), 0);
398 (void)mpic_cpu_read(MPIC_CPU_WHOAMI); 488 (void)mpic_cpu_read(MPIC_INFO(CPU_WHOAMI));
399} 489}
400 490
401#ifdef CONFIG_SMP 491#ifdef CONFIG_SMP
@@ -419,8 +509,8 @@ static void mpic_unmask_irq(unsigned int irq)
419 509
420 DBG("%p: %s: enable_irq: %d (src %d)\n", mpic, mpic->name, irq, src); 510 DBG("%p: %s: enable_irq: %d (src %d)\n", mpic, mpic->name, irq, src);
421 511
422 mpic_irq_write(src, MPIC_IRQ_VECTOR_PRI, 512 mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI),
423 mpic_irq_read(src, MPIC_IRQ_VECTOR_PRI) & 513 mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) &
424 ~MPIC_VECPRI_MASK); 514 ~MPIC_VECPRI_MASK);
425 /* make sure mask gets to controller before we return to user */ 515 /* make sure mask gets to controller before we return to user */
426 do { 516 do {
@@ -428,7 +518,7 @@ static void mpic_unmask_irq(unsigned int irq)
428 printk(KERN_ERR "mpic_enable_irq timeout\n"); 518 printk(KERN_ERR "mpic_enable_irq timeout\n");
429 break; 519 break;
430 } 520 }
431 } while(mpic_irq_read(src, MPIC_IRQ_VECTOR_PRI) & MPIC_VECPRI_MASK); 521 } while(mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) & MPIC_VECPRI_MASK);
432} 522}
433 523
434static void mpic_mask_irq(unsigned int irq) 524static void mpic_mask_irq(unsigned int irq)
@@ -439,8 +529,8 @@ static void mpic_mask_irq(unsigned int irq)
439 529
440 DBG("%s: disable_irq: %d (src %d)\n", mpic->name, irq, src); 530 DBG("%s: disable_irq: %d (src %d)\n", mpic->name, irq, src);
441 531
442 mpic_irq_write(src, MPIC_IRQ_VECTOR_PRI, 532 mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI),
443 mpic_irq_read(src, MPIC_IRQ_VECTOR_PRI) | 533 mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) |
444 MPIC_VECPRI_MASK); 534 MPIC_VECPRI_MASK);
445 535
446 /* make sure mask gets to controller before we return to user */ 536 /* make sure mask gets to controller before we return to user */
@@ -449,7 +539,7 @@ static void mpic_mask_irq(unsigned int irq)
449 printk(KERN_ERR "mpic_enable_irq timeout\n"); 539 printk(KERN_ERR "mpic_enable_irq timeout\n");
450 break; 540 break;
451 } 541 }
452 } while(!(mpic_irq_read(src, MPIC_IRQ_VECTOR_PRI) & MPIC_VECPRI_MASK)); 542 } while(!(mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) & MPIC_VECPRI_MASK));
453} 543}
454 544
455static void mpic_end_irq(unsigned int irq) 545static void mpic_end_irq(unsigned int irq)
@@ -560,24 +650,28 @@ static void mpic_set_affinity(unsigned int irq, cpumask_t cpumask)
560 650
561 cpus_and(tmp, cpumask, cpu_online_map); 651 cpus_and(tmp, cpumask, cpu_online_map);
562 652
563 mpic_irq_write(src, MPIC_IRQ_DESTINATION, 653 mpic_irq_write(src, MPIC_INFO(IRQ_DESTINATION),
564 mpic_physmask(cpus_addr(tmp)[0])); 654 mpic_physmask(cpus_addr(tmp)[0]));
565} 655}
566 656
567static unsigned int mpic_type_to_vecpri(unsigned int type) 657static unsigned int mpic_type_to_vecpri(struct mpic *mpic, unsigned int type)
568{ 658{
569 /* Now convert sense value */ 659 /* Now convert sense value */
570 switch(type & IRQ_TYPE_SENSE_MASK) { 660 switch(type & IRQ_TYPE_SENSE_MASK) {
571 case IRQ_TYPE_EDGE_RISING: 661 case IRQ_TYPE_EDGE_RISING:
572 return MPIC_VECPRI_SENSE_EDGE | MPIC_VECPRI_POLARITY_POSITIVE; 662 return MPIC_INFO(VECPRI_SENSE_EDGE) |
663 MPIC_INFO(VECPRI_POLARITY_POSITIVE);
573 case IRQ_TYPE_EDGE_FALLING: 664 case IRQ_TYPE_EDGE_FALLING:
574 case IRQ_TYPE_EDGE_BOTH: 665 case IRQ_TYPE_EDGE_BOTH:
575 return MPIC_VECPRI_SENSE_EDGE | MPIC_VECPRI_POLARITY_NEGATIVE; 666 return MPIC_INFO(VECPRI_SENSE_EDGE) |
667 MPIC_INFO(VECPRI_POLARITY_NEGATIVE);
576 case IRQ_TYPE_LEVEL_HIGH: 668 case IRQ_TYPE_LEVEL_HIGH:
577 return MPIC_VECPRI_SENSE_LEVEL | MPIC_VECPRI_POLARITY_POSITIVE; 669 return MPIC_INFO(VECPRI_SENSE_LEVEL) |
670 MPIC_INFO(VECPRI_POLARITY_POSITIVE);
578 case IRQ_TYPE_LEVEL_LOW: 671 case IRQ_TYPE_LEVEL_LOW:
579 default: 672 default:
580 return MPIC_VECPRI_SENSE_LEVEL | MPIC_VECPRI_POLARITY_NEGATIVE; 673 return MPIC_INFO(VECPRI_SENSE_LEVEL) |
674 MPIC_INFO(VECPRI_POLARITY_NEGATIVE);
581 } 675 }
582} 676}
583 677
@@ -609,13 +703,14 @@ static int mpic_set_irq_type(unsigned int virq, unsigned int flow_type)
609 vecpri = MPIC_VECPRI_POLARITY_POSITIVE | 703 vecpri = MPIC_VECPRI_POLARITY_POSITIVE |
610 MPIC_VECPRI_SENSE_EDGE; 704 MPIC_VECPRI_SENSE_EDGE;
611 else 705 else
612 vecpri = mpic_type_to_vecpri(flow_type); 706 vecpri = mpic_type_to_vecpri(mpic, flow_type);
613 707
614 vold = mpic_irq_read(src, MPIC_IRQ_VECTOR_PRI); 708 vold = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI));
615 vnew = vold & ~(MPIC_VECPRI_POLARITY_MASK | MPIC_VECPRI_SENSE_MASK); 709 vnew = vold & ~(MPIC_INFO(VECPRI_POLARITY_MASK) |
710 MPIC_INFO(VECPRI_SENSE_MASK));
616 vnew |= vecpri; 711 vnew |= vecpri;
617 if (vold != vnew) 712 if (vold != vnew)
618 mpic_irq_write(src, MPIC_IRQ_VECTOR_PRI, vnew); 713 mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI), vnew);
619 714
620 return 0; 715 return 0;
621} 716}
@@ -798,17 +893,22 @@ struct mpic * __init mpic_alloc(struct device_node *node,
798 mpic->irq_count = irq_count; 893 mpic->irq_count = irq_count;
799 mpic->num_sources = 0; /* so far */ 894 mpic->num_sources = 0; /* so far */
800 895
896#ifdef CONFIG_MPIC_WEIRD
897 mpic->hw_set = mpic_infos[MPIC_GET_REGSET(flags)];
898#endif
899
801 /* Map the global registers */ 900 /* Map the global registers */
802 mpic->gregs = ioremap(phys_addr + MPIC_GREG_BASE, 0x1000); 901 mpic->gregs = ioremap(phys_addr + MPIC_INFO(GREG_BASE), 0x1000);
803 mpic->tmregs = mpic->gregs + ((MPIC_TIMER_BASE - MPIC_GREG_BASE) >> 2); 902 mpic->tmregs = mpic->gregs +
903 ((MPIC_INFO(TIMER_BASE) - MPIC_INFO(GREG_BASE)) >> 2);
804 BUG_ON(mpic->gregs == NULL); 904 BUG_ON(mpic->gregs == NULL);
805 905
806 /* Reset */ 906 /* Reset */
807 if (flags & MPIC_WANTS_RESET) { 907 if (flags & MPIC_WANTS_RESET) {
808 mpic_write(mpic->gregs, MPIC_GREG_GLOBAL_CONF_0, 908 mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
809 mpic_read(mpic->gregs, MPIC_GREG_GLOBAL_CONF_0) 909 mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
810 | MPIC_GREG_GCONF_RESET); 910 | MPIC_GREG_GCONF_RESET);
811 while( mpic_read(mpic->gregs, MPIC_GREG_GLOBAL_CONF_0) 911 while( mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
812 & MPIC_GREG_GCONF_RESET) 912 & MPIC_GREG_GCONF_RESET)
813 mb(); 913 mb();
814 } 914 }
@@ -817,7 +917,7 @@ struct mpic * __init mpic_alloc(struct device_node *node,
817 * MPICs, num sources as well. On ISU MPICs, sources are counted 917 * MPICs, num sources as well. On ISU MPICs, sources are counted
818 * as ISUs are added 918 * as ISUs are added
819 */ 919 */
820 reg = mpic_read(mpic->gregs, MPIC_GREG_FEATURE_0); 920 reg = mpic_read(mpic->gregs, MPIC_INFO(GREG_FEATURE_0));
821 mpic->num_cpus = ((reg & MPIC_GREG_FEATURE_LAST_CPU_MASK) 921 mpic->num_cpus = ((reg & MPIC_GREG_FEATURE_LAST_CPU_MASK)
822 >> MPIC_GREG_FEATURE_LAST_CPU_SHIFT) + 1; 922 >> MPIC_GREG_FEATURE_LAST_CPU_SHIFT) + 1;
823 if (isu_size == 0) 923 if (isu_size == 0)
@@ -826,16 +926,16 @@ struct mpic * __init mpic_alloc(struct device_node *node,
826 926
827 /* Map the per-CPU registers */ 927 /* Map the per-CPU registers */
828 for (i = 0; i < mpic->num_cpus; i++) { 928 for (i = 0; i < mpic->num_cpus; i++) {
829 mpic->cpuregs[i] = ioremap(phys_addr + MPIC_CPU_BASE + 929 mpic->cpuregs[i] = ioremap(phys_addr + MPIC_INFO(CPU_BASE) +
830 i * MPIC_CPU_STRIDE, 0x1000); 930 i * MPIC_INFO(CPU_STRIDE), 0x1000);
831 BUG_ON(mpic->cpuregs[i] == NULL); 931 BUG_ON(mpic->cpuregs[i] == NULL);
832 } 932 }
833 933
834 /* Initialize main ISU if none provided */ 934 /* Initialize main ISU if none provided */
835 if (mpic->isu_size == 0) { 935 if (mpic->isu_size == 0) {
836 mpic->isu_size = mpic->num_sources; 936 mpic->isu_size = mpic->num_sources;
837 mpic->isus[0] = ioremap(phys_addr + MPIC_IRQ_BASE, 937 mpic->isus[0] = ioremap(phys_addr + MPIC_INFO(IRQ_BASE),
838 MPIC_IRQ_STRIDE * mpic->isu_size); 938 MPIC_INFO(IRQ_STRIDE) * mpic->isu_size);
839 BUG_ON(mpic->isus[0] == NULL); 939 BUG_ON(mpic->isus[0] == NULL);
840 } 940 }
841 mpic->isu_shift = 1 + __ilog2(mpic->isu_size - 1); 941 mpic->isu_shift = 1 + __ilog2(mpic->isu_size - 1);
@@ -879,7 +979,8 @@ void __init mpic_assign_isu(struct mpic *mpic, unsigned int isu_num,
879 979
880 BUG_ON(isu_num >= MPIC_MAX_ISU); 980 BUG_ON(isu_num >= MPIC_MAX_ISU);
881 981
882 mpic->isus[isu_num] = ioremap(phys_addr, MPIC_IRQ_STRIDE * mpic->isu_size); 982 mpic->isus[isu_num] = ioremap(phys_addr,
983 MPIC_INFO(IRQ_STRIDE) * mpic->isu_size);
883 if ((isu_first + mpic->isu_size) > mpic->num_sources) 984 if ((isu_first + mpic->isu_size) > mpic->num_sources)
884 mpic->num_sources = isu_first + mpic->isu_size; 985 mpic->num_sources = isu_first + mpic->isu_size;
885} 986}
@@ -904,14 +1005,16 @@ void __init mpic_init(struct mpic *mpic)
904 printk(KERN_INFO "mpic: Initializing for %d sources\n", mpic->num_sources); 1005 printk(KERN_INFO "mpic: Initializing for %d sources\n", mpic->num_sources);
905 1006
906 /* Set current processor priority to max */ 1007 /* Set current processor priority to max */
907 mpic_cpu_write(MPIC_CPU_CURRENT_TASK_PRI, 0xf); 1008 mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0xf);
908 1009
909 /* Initialize timers: just disable them all */ 1010 /* Initialize timers: just disable them all */
910 for (i = 0; i < 4; i++) { 1011 for (i = 0; i < 4; i++) {
911 mpic_write(mpic->tmregs, 1012 mpic_write(mpic->tmregs,
912 i * MPIC_TIMER_STRIDE + MPIC_TIMER_DESTINATION, 0); 1013 i * MPIC_INFO(TIMER_STRIDE) +
1014 MPIC_INFO(TIMER_DESTINATION), 0);
913 mpic_write(mpic->tmregs, 1015 mpic_write(mpic->tmregs,
914 i * MPIC_TIMER_STRIDE + MPIC_TIMER_VECTOR_PRI, 1016 i * MPIC_INFO(TIMER_STRIDE) +
1017 MPIC_INFO(TIMER_VECTOR_PRI),
915 MPIC_VECPRI_MASK | 1018 MPIC_VECPRI_MASK |
916 (MPIC_VEC_TIMER_0 + i)); 1019 (MPIC_VEC_TIMER_0 + i));
917 } 1020 }
@@ -940,21 +1043,22 @@ void __init mpic_init(struct mpic *mpic)
940 (8 << MPIC_VECPRI_PRIORITY_SHIFT); 1043 (8 << MPIC_VECPRI_PRIORITY_SHIFT);
941 1044
942 /* init hw */ 1045 /* init hw */
943 mpic_irq_write(i, MPIC_IRQ_VECTOR_PRI, vecpri); 1046 mpic_irq_write(i, MPIC_INFO(IRQ_VECTOR_PRI), vecpri);
944 mpic_irq_write(i, MPIC_IRQ_DESTINATION, 1047 mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION),
945 1 << hard_smp_processor_id()); 1048 1 << hard_smp_processor_id());
946 } 1049 }
947 1050
948 /* Init spurrious vector */ 1051 /* Init spurrious vector */
949 mpic_write(mpic->gregs, MPIC_GREG_SPURIOUS, MPIC_VEC_SPURRIOUS); 1052 mpic_write(mpic->gregs, MPIC_INFO(GREG_SPURIOUS), MPIC_VEC_SPURRIOUS);
950 1053
951 /* Disable 8259 passthrough */ 1054 /* Disable 8259 passthrough, if supported */
952 mpic_write(mpic->gregs, MPIC_GREG_GLOBAL_CONF_0, 1055 if (!(mpic->flags & MPIC_NO_PTHROU_DIS))
953 mpic_read(mpic->gregs, MPIC_GREG_GLOBAL_CONF_0) 1056 mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
954 | MPIC_GREG_GCONF_8259_PTHROU_DIS); 1057 mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
1058 | MPIC_GREG_GCONF_8259_PTHROU_DIS);
955 1059
956 /* Set current processor priority to 0 */ 1060 /* Set current processor priority to 0 */
957 mpic_cpu_write(MPIC_CPU_CURRENT_TASK_PRI, 0); 1061 mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0);
958} 1062}
959 1063
960void __init mpic_set_clk_ratio(struct mpic *mpic, u32 clock_ratio) 1064void __init mpic_set_clk_ratio(struct mpic *mpic, u32 clock_ratio)
@@ -997,9 +1101,9 @@ void mpic_irq_set_priority(unsigned int irq, unsigned int pri)
997 mpic_ipi_write(src - MPIC_VEC_IPI_0, 1101 mpic_ipi_write(src - MPIC_VEC_IPI_0,
998 reg | (pri << MPIC_VECPRI_PRIORITY_SHIFT)); 1102 reg | (pri << MPIC_VECPRI_PRIORITY_SHIFT));
999 } else { 1103 } else {
1000 reg = mpic_irq_read(src, MPIC_IRQ_VECTOR_PRI) 1104 reg = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI))
1001 & ~MPIC_VECPRI_PRIORITY_MASK; 1105 & ~MPIC_VECPRI_PRIORITY_MASK;
1002 mpic_irq_write(src, MPIC_IRQ_VECTOR_PRI, 1106 mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI),
1003 reg | (pri << MPIC_VECPRI_PRIORITY_SHIFT)); 1107 reg | (pri << MPIC_VECPRI_PRIORITY_SHIFT));
1004 } 1108 }
1005 spin_unlock_irqrestore(&mpic_lock, flags); 1109 spin_unlock_irqrestore(&mpic_lock, flags);
@@ -1017,7 +1121,7 @@ unsigned int mpic_irq_get_priority(unsigned int irq)
1017 if (is_ipi) 1121 if (is_ipi)
1018 reg = mpic_ipi_read(src = MPIC_VEC_IPI_0); 1122 reg = mpic_ipi_read(src = MPIC_VEC_IPI_0);
1019 else 1123 else
1020 reg = mpic_irq_read(src, MPIC_IRQ_VECTOR_PRI); 1124 reg = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI));
1021 spin_unlock_irqrestore(&mpic_lock, flags); 1125 spin_unlock_irqrestore(&mpic_lock, flags);
1022 return (reg & MPIC_VECPRI_PRIORITY_MASK) >> MPIC_VECPRI_PRIORITY_SHIFT; 1126 return (reg & MPIC_VECPRI_PRIORITY_MASK) >> MPIC_VECPRI_PRIORITY_SHIFT;
1023} 1127}
@@ -1043,12 +1147,12 @@ void mpic_setup_this_cpu(void)
1043 */ 1147 */
1044 if (distribute_irqs) { 1148 if (distribute_irqs) {
1045 for (i = 0; i < mpic->num_sources ; i++) 1149 for (i = 0; i < mpic->num_sources ; i++)
1046 mpic_irq_write(i, MPIC_IRQ_DESTINATION, 1150 mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION),
1047 mpic_irq_read(i, MPIC_IRQ_DESTINATION) | msk); 1151 mpic_irq_read(i, MPIC_INFO(IRQ_DESTINATION)) | msk);
1048 } 1152 }
1049 1153
1050 /* Set current processor priority to 0 */ 1154 /* Set current processor priority to 0 */
1051 mpic_cpu_write(MPIC_CPU_CURRENT_TASK_PRI, 0); 1155 mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0);
1052 1156
1053 spin_unlock_irqrestore(&mpic_lock, flags); 1157 spin_unlock_irqrestore(&mpic_lock, flags);
1054#endif /* CONFIG_SMP */ 1158#endif /* CONFIG_SMP */
@@ -1058,7 +1162,7 @@ int mpic_cpu_get_priority(void)
1058{ 1162{
1059 struct mpic *mpic = mpic_primary; 1163 struct mpic *mpic = mpic_primary;
1060 1164
1061 return mpic_cpu_read(MPIC_CPU_CURRENT_TASK_PRI); 1165 return mpic_cpu_read(MPIC_INFO(CPU_CURRENT_TASK_PRI));
1062} 1166}
1063 1167
1064void mpic_cpu_set_priority(int prio) 1168void mpic_cpu_set_priority(int prio)
@@ -1066,7 +1170,7 @@ void mpic_cpu_set_priority(int prio)
1066 struct mpic *mpic = mpic_primary; 1170 struct mpic *mpic = mpic_primary;
1067 1171
1068 prio &= MPIC_CPU_TASKPRI_MASK; 1172 prio &= MPIC_CPU_TASKPRI_MASK;
1069 mpic_cpu_write(MPIC_CPU_CURRENT_TASK_PRI, prio); 1173 mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), prio);
1070} 1174}
1071 1175
1072/* 1176/*
@@ -1088,11 +1192,11 @@ void mpic_teardown_this_cpu(int secondary)
1088 1192
1089 /* let the mpic know we don't want intrs. */ 1193 /* let the mpic know we don't want intrs. */
1090 for (i = 0; i < mpic->num_sources ; i++) 1194 for (i = 0; i < mpic->num_sources ; i++)
1091 mpic_irq_write(i, MPIC_IRQ_DESTINATION, 1195 mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION),
1092 mpic_irq_read(i, MPIC_IRQ_DESTINATION) & ~msk); 1196 mpic_irq_read(i, MPIC_INFO(IRQ_DESTINATION)) & ~msk);
1093 1197
1094 /* Set current processor priority to max */ 1198 /* Set current processor priority to max */
1095 mpic_cpu_write(MPIC_CPU_CURRENT_TASK_PRI, 0xf); 1199 mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0xf);
1096 1200
1097 spin_unlock_irqrestore(&mpic_lock, flags); 1201 spin_unlock_irqrestore(&mpic_lock, flags);
1098} 1202}
@@ -1108,7 +1212,8 @@ void mpic_send_ipi(unsigned int ipi_no, unsigned int cpu_mask)
1108 DBG("%s: send_ipi(ipi_no: %d)\n", mpic->name, ipi_no); 1212 DBG("%s: send_ipi(ipi_no: %d)\n", mpic->name, ipi_no);
1109#endif 1213#endif
1110 1214
1111 mpic_cpu_write(MPIC_CPU_IPI_DISPATCH_0 + ipi_no * 0x10, 1215 mpic_cpu_write(MPIC_INFO(CPU_IPI_DISPATCH_0) +
1216 ipi_no * MPIC_INFO(CPU_IPI_DISPATCH_STRIDE),
1112 mpic_physmask(cpu_mask & cpus_addr(cpu_online_map)[0])); 1217 mpic_physmask(cpu_mask & cpus_addr(cpu_online_map)[0]));
1113} 1218}
1114 1219
@@ -1116,7 +1221,7 @@ unsigned int mpic_get_one_irq(struct mpic *mpic, struct pt_regs *regs)
1116{ 1221{
1117 u32 src; 1222 u32 src;
1118 1223
1119 src = mpic_cpu_read(MPIC_CPU_INTACK) & MPIC_VECPRI_VECTOR_MASK; 1224 src = mpic_cpu_read(MPIC_INFO(CPU_INTACK)) & MPIC_INFO(VECPRI_VECTOR_MASK);
1120#ifdef DEBUG_LOW 1225#ifdef DEBUG_LOW
1121 DBG("%s: get_one_irq(): %d\n", mpic->name, src); 1226 DBG("%s: get_one_irq(): %d\n", mpic->name, src);
1122#endif 1227#endif
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-19 13:58:30 -0500