4 files changed, 34 insertions, 46 deletions

diff --git a/arch/powerpc/include/asm/local64.h b/arch/powerpc/include/asm/local64.h
new file mode 100644
index 000000000000..36c93b5cc239
--- /dev/null
+++ b/arch/powerpc/include/asm/local64.h
@@ -0,0 +1 @@
+#include <asm-generic/local64.h>
diff --git a/arch/powerpc/include/asm/perf_event.h b/arch/powerpc/include/asm/perf_event.h
index e6d4ce69b126..5c16b891d501 100644
--- a/arch/powerpc/include/asm/perf_event.h
+++ b/arch/powerpc/include/asm/perf_event.h
@@ -21,3 +21,15 @@
 #ifdef CONFIG_FSL_EMB_PERF_EVENT
 #include <asm/perf_event_fsl_emb.h>
 #endif
+
+#ifdef CONFIG_PERF_EVENTS
+#include <asm/ptrace.h>
+#include <asm/reg.h>
+
+#define perf_arch_fetch_caller_regs(regs, __ip)                 \
+        do {                                                    \
+                (regs)->nip = __ip;                             \
+                (regs)->gpr[1] = *(unsigned long *)__get_SP();  \
+                asm volatile("mfmsr %0" : "=r" ((regs)->msr));  \
+        } while (0)
+#endif
diff --git a/arch/powerpc/kernel/misc.S b/arch/powerpc/kernel/misc.S
index 22e507c8a556..2d29752cbe16 100644
--- a/arch/powerpc/kernel/misc.S
+++ b/arch/powerpc/kernel/misc.S
@@ -127,29 +127,3 @@ _GLOBAL(__setup_cpu_power7)
 _GLOBAL(__restore_cpu_power7)
         /* place holder */
         blr
-
-/*
- * Get a minimal set of registers for our caller's nth caller.
- * r3 = regs pointer, r5 = n.
- *
- * We only get R1 (stack pointer), NIP (next instruction pointer)
- * and LR (link register).  These are all we can get in the
- * general case without doing complicated stack unwinding, but
- * fortunately they are enough to do a stack backtrace, which
- * is all we need them for.
- */
-_GLOBAL(perf_arch_fetch_caller_regs)
-        mr      r6,r1
-        cmpwi   r5,0
-        mflr    r4
-        ble     2f
-        mtctr   r5
-1:      PPC_LL  r6,0(r6)
-        bdnz    1b
-        PPC_LL  r4,PPC_LR_STKOFF(r6)
-2:      PPC_LL  r7,0(r6)
-        PPC_LL  r7,PPC_LR_STKOFF(r7)
-        PPC_STL r6,GPR1-STACK_FRAME_OVERHEAD(r3)
-        PPC_STL r4,_NIP-STACK_FRAME_OVERHEAD(r3)
-        PPC_STL r7,_LINK-STACK_FRAME_OVERHEAD(r3)
-        blr
diff --git a/arch/powerpc/kernel/perf_event.c b/arch/powerpc/kernel/perf_event.c
index 5c14ffe51258..d301a30445e0 100644
--- a/arch/powerpc/kernel/perf_event.c
+++ b/arch/powerpc/kernel/perf_event.c
@@ -410,15 +410,15 @@ static void power_pmu_read(struct perf_event *event)
          * Therefore we treat them like NMIs.
          */
         do {
-                prev = atomic64_read(&event->hw.prev_count);
+                prev = local64_read(&event->hw.prev_count);
                 barrier();
                 val = read_pmc(event->hw.idx);
-        } while (atomic64_cmpxchg(&event->hw.prev_count, prev, val) != prev);
+        } while (local64_cmpxchg(&event->hw.prev_count, prev, val) != prev);
 
         /* The counters are only 32 bits wide */
         delta = (val - prev) & 0xfffffffful;
-        atomic64_add(delta, &event->count);
-        atomic64_sub(delta, &event->hw.period_left);
+        local64_add(delta, &event->count);
+        local64_sub(delta, &event->hw.period_left);
 }
 
 /*
@@ -444,10 +444,10 @@ static void freeze_limited_counters(struct cpu_hw_events *cpuhw,
                 if (!event->hw.idx)
                         continue;
                 val = (event->hw.idx == 5) ? pmc5 : pmc6;
-                prev = atomic64_read(&event->hw.prev_count);
+                prev = local64_read(&event->hw.prev_count);
                 event->hw.idx = 0;
                 delta = (val - prev) & 0xfffffffful;
-                atomic64_add(delta, &event->count);
+                local64_add(delta, &event->count);
         }
 }
 
@@ -462,7 +462,7 @@ static void thaw_limited_counters(struct cpu_hw_events *cpuhw,
                 event = cpuhw->limited_counter[i];
                 event->hw.idx = cpuhw->limited_hwidx[i];
                 val = (event->hw.idx == 5) ? pmc5 : pmc6;
-                atomic64_set(&event->hw.prev_count, val);
+                local64_set(&event->hw.prev_count, val);
                 perf_event_update_userpage(event);
         }
 }
@@ -666,11 +666,11 @@ void hw_perf_enable(void)
                 }
                 val = 0;
                 if (event->hw.sample_period) {
-                        left = atomic64_read(&event->hw.period_left);
+                        left = local64_read(&event->hw.period_left);
                         if (left < 0x80000000L)
                                 val = 0x80000000L - left;
                 }
-                atomic64_set(&event->hw.prev_count, val);
+                local64_set(&event->hw.prev_count, val);
                 event->hw.idx = idx;
                 write_pmc(idx, val);
                 perf_event_update_userpage(event);
@@ -754,7 +754,7 @@ static int power_pmu_enable(struct perf_event *event)
          * skip the schedulability test here, it will be peformed
          * at commit time(->commit_txn) as a whole
          */
-        if (cpuhw->group_flag & PERF_EVENT_TXN_STARTED)
+        if (cpuhw->group_flag & PERF_EVENT_TXN)
                 goto nocheck;
 
         if (check_excludes(cpuhw->event, cpuhw->flags, n0, 1))
@@ -845,8 +845,8 @@ static void power_pmu_unthrottle(struct perf_event *event)
         if (left < 0x80000000L)
                 val = 0x80000000L - left;
         write_pmc(event->hw.idx, val);
-        atomic64_set(&event->hw.prev_count, val);
-        atomic64_set(&event->hw.period_left, left);
+        local64_set(&event->hw.prev_count, val);
+        local64_set(&event->hw.period_left, left);
         perf_event_update_userpage(event);
         perf_enable();
         local_irq_restore(flags);
@@ -861,7 +861,7 @@ void power_pmu_start_txn(const struct pmu *pmu)
 {
         struct cpu_hw_events *cpuhw = &__get_cpu_var(cpu_hw_events);
 
-        cpuhw->group_flag |= PERF_EVENT_TXN_STARTED;
+        cpuhw->group_flag |= PERF_EVENT_TXN;
         cpuhw->n_txn_start = cpuhw->n_events;
 }
 
@@ -874,7 +874,7 @@ void power_pmu_cancel_txn(const struct pmu *pmu)
 {
         struct cpu_hw_events *cpuhw = &__get_cpu_var(cpu_hw_events);
 
-        cpuhw->group_flag &= ~PERF_EVENT_TXN_STARTED;
+        cpuhw->group_flag &= ~PERF_EVENT_TXN;
 }
 
 /*
@@ -900,6 +900,7 @@ int power_pmu_commit_txn(const struct pmu *pmu)
         for (i = cpuhw->n_txn_start; i < n; ++i)
                 cpuhw->event[i]->hw.config = cpuhw->events[i];
 
+        cpuhw->group_flag &= ~PERF_EVENT_TXN;
         return 0;
 }
 
@@ -1111,7 +1112,7 @@ const struct pmu *hw_perf_event_init(struct perf_event *event)
         event->hw.config = events[n];
         event->hw.event_base = cflags[n];
         event->hw.last_period = event->hw.sample_period;
-        atomic64_set(&event->hw.period_left, event->hw.last_period);
+        local64_set(&event->hw.period_left, event->hw.last_period);
 
         /*
          * See if we need to reserve the PMU.
@@ -1149,16 +1150,16 @@ static void record_and_restart(struct perf_event *event, unsigned long val,
         int record = 0;
 
         /* we don't have to worry about interrupts here */
-        prev = atomic64_read(&event->hw.prev_count);
+        prev = local64_read(&event->hw.prev_count);
         delta = (val - prev) & 0xfffffffful;
-        atomic64_add(delta, &event->count);
+        local64_add(delta, &event->count);
 
         /*
          * See if the total period for this event has expired,
          * and update for the next period.
          */
         val = 0;
-        left = atomic64_read(&event->hw.period_left) - delta;
+        left = local64_read(&event->hw.period_left) - delta;
         if (period) {
                 if (left <= 0) {
                         left += period;
@@ -1196,8 +1197,8 @@ static void record_and_restart(struct perf_event *event, unsigned long val,
         }
 
         write_pmc(event->hw.idx, val);
-        atomic64_set(&event->hw.prev_count, val);
-        atomic64_set(&event->hw.period_left, left);
+        local64_set(&event->hw.prev_count, val);
+        local64_set(&event->hw.period_left, left);
         perf_event_update_userpage(event);
 }