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-rw-r--r--arch/powerpc/platforms/85xx/mpc85xx_mds.c13
1 files changed, 13 insertions, 0 deletions
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_mds.c b/arch/powerpc/platforms/85xx/mpc85xx_mds.c
index 60ed9c067b1d..bfb32834ab0c 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_mds.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_mds.c
@@ -233,6 +233,19 @@ static void __init mpc85xx_mds_setup_arch(void)
233 /* Turn UCC1 & UCC2 on */ 233 /* Turn UCC1 & UCC2 on */
234 setbits8(&bcsr_regs[8], BCSR_UCC1_GETH_EN); 234 setbits8(&bcsr_regs[8], BCSR_UCC1_GETH_EN);
235 setbits8(&bcsr_regs[9], BCSR_UCC2_GETH_EN); 235 setbits8(&bcsr_regs[9], BCSR_UCC2_GETH_EN);
236 } else if (machine_is(mpc8569_mds)) {
237#define BCSR7_UCC12_GETHnRST (0x1 << 2)
238#define BCSR8_UEM_MARVELL_RST (0x1 << 1)
239 /*
240 * U-Boot mangles interrupt polarity for Marvell PHYs,
241 * so reset built-in and UEM Marvell PHYs, this puts
242 * the PHYs into their normal state.
243 */
244 clrbits8(&bcsr_regs[7], BCSR7_UCC12_GETHnRST);
245 setbits8(&bcsr_regs[8], BCSR8_UEM_MARVELL_RST);
246
247 setbits8(&bcsr_regs[7], BCSR7_UCC12_GETHnRST);
248 clrbits8(&bcsr_regs[8], BCSR8_UEM_MARVELL_RST);
236 } 249 }
237 iounmap(bcsr_regs); 250 iounmap(bcsr_regs);
238 } 251 }