diff options
Diffstat (limited to 'arch/powerpc')
69 files changed, 460 insertions, 595 deletions
diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig index 71ba04721beb..d0e8a1dbf822 100644 --- a/arch/powerpc/Kconfig +++ b/arch/powerpc/Kconfig | |||
@@ -95,6 +95,10 @@ config GENERIC_FIND_NEXT_BIT | |||
95 | bool | 95 | bool |
96 | default y | 96 | default y |
97 | 97 | ||
98 | config GENERIC_FIND_BIT_LE | ||
99 | bool | ||
100 | default y | ||
101 | |||
98 | config GENERIC_GPIO | 102 | config GENERIC_GPIO |
99 | bool | 103 | bool |
100 | help | 104 | help |
@@ -135,6 +139,8 @@ config PPC | |||
135 | select HAVE_SPARSE_IRQ | 139 | select HAVE_SPARSE_IRQ |
136 | select IRQ_PER_CPU | 140 | select IRQ_PER_CPU |
137 | select GENERIC_HARDIRQS_NO_DEPRECATED | 141 | select GENERIC_HARDIRQS_NO_DEPRECATED |
142 | select GENERIC_IRQ_SHOW | ||
143 | select GENERIC_IRQ_SHOW_LEVEL | ||
138 | 144 | ||
139 | config EARLY_PRINTK | 145 | config EARLY_PRINTK |
140 | bool | 146 | bool |
@@ -768,11 +774,19 @@ config HAS_RAPIDIO | |||
768 | 774 | ||
769 | config RAPIDIO | 775 | config RAPIDIO |
770 | bool "RapidIO support" | 776 | bool "RapidIO support" |
771 | depends on HAS_RAPIDIO | 777 | depends on HAS_RAPIDIO || PCI |
772 | help | 778 | help |
773 | If you say Y here, the kernel will include drivers and | 779 | If you say Y here, the kernel will include drivers and |
774 | infrastructure code to support RapidIO interconnect devices. | 780 | infrastructure code to support RapidIO interconnect devices. |
775 | 781 | ||
782 | config FSL_RIO | ||
783 | bool "Freescale Embedded SRIO Controller support" | ||
784 | depends on RAPIDIO && HAS_RAPIDIO | ||
785 | default "n" | ||
786 | ---help--- | ||
787 | Include support for RapidIO controller on Freescale embedded | ||
788 | processors (MPC8548, MPC8641, etc). | ||
789 | |||
776 | source "drivers/rapidio/Kconfig" | 790 | source "drivers/rapidio/Kconfig" |
777 | 791 | ||
778 | endmenu | 792 | endmenu |
diff --git a/arch/powerpc/include/asm/bitops.h b/arch/powerpc/include/asm/bitops.h index 8a7e9314c68a..2e561876fc89 100644 --- a/arch/powerpc/include/asm/bitops.h +++ b/arch/powerpc/include/asm/bitops.h | |||
@@ -281,68 +281,56 @@ unsigned long __arch_hweight64(__u64 w); | |||
281 | 281 | ||
282 | /* Little-endian versions */ | 282 | /* Little-endian versions */ |
283 | 283 | ||
284 | static __inline__ int test_le_bit(unsigned long nr, | 284 | static __inline__ int test_bit_le(unsigned long nr, |
285 | __const__ unsigned long *addr) | 285 | __const__ void *addr) |
286 | { | 286 | { |
287 | __const__ unsigned char *tmp = (__const__ unsigned char *) addr; | 287 | __const__ unsigned char *tmp = (__const__ unsigned char *) addr; |
288 | return (tmp[nr >> 3] >> (nr & 7)) & 1; | 288 | return (tmp[nr >> 3] >> (nr & 7)) & 1; |
289 | } | 289 | } |
290 | 290 | ||
291 | #define __set_le_bit(nr, addr) \ | 291 | static inline void __set_bit_le(int nr, void *addr) |
292 | __set_bit((nr) ^ BITOP_LE_SWIZZLE, (addr)) | 292 | { |
293 | #define __clear_le_bit(nr, addr) \ | 293 | __set_bit(nr ^ BITOP_LE_SWIZZLE, addr); |
294 | __clear_bit((nr) ^ BITOP_LE_SWIZZLE, (addr)) | 294 | } |
295 | |||
296 | static inline void __clear_bit_le(int nr, void *addr) | ||
297 | { | ||
298 | __clear_bit(nr ^ BITOP_LE_SWIZZLE, addr); | ||
299 | } | ||
300 | |||
301 | static inline int test_and_set_bit_le(int nr, void *addr) | ||
302 | { | ||
303 | return test_and_set_bit(nr ^ BITOP_LE_SWIZZLE, addr); | ||
304 | } | ||
295 | 305 | ||
296 | #define test_and_set_le_bit(nr, addr) \ | 306 | static inline int test_and_clear_bit_le(int nr, void *addr) |
297 | test_and_set_bit((nr) ^ BITOP_LE_SWIZZLE, (addr)) | 307 | { |
298 | #define test_and_clear_le_bit(nr, addr) \ | 308 | return test_and_clear_bit(nr ^ BITOP_LE_SWIZZLE, addr); |
299 | test_and_clear_bit((nr) ^ BITOP_LE_SWIZZLE, (addr)) | 309 | } |
310 | |||
311 | static inline int __test_and_set_bit_le(int nr, void *addr) | ||
312 | { | ||
313 | return __test_and_set_bit(nr ^ BITOP_LE_SWIZZLE, addr); | ||
314 | } | ||
300 | 315 | ||
301 | #define __test_and_set_le_bit(nr, addr) \ | 316 | static inline int __test_and_clear_bit_le(int nr, void *addr) |
302 | __test_and_set_bit((nr) ^ BITOP_LE_SWIZZLE, (addr)) | 317 | { |
303 | #define __test_and_clear_le_bit(nr, addr) \ | 318 | return __test_and_clear_bit(nr ^ BITOP_LE_SWIZZLE, addr); |
304 | __test_and_clear_bit((nr) ^ BITOP_LE_SWIZZLE, (addr)) | 319 | } |
305 | 320 | ||
306 | #define find_first_zero_le_bit(addr, size) generic_find_next_zero_le_bit((addr), (size), 0) | 321 | #define find_first_zero_bit_le(addr, size) \ |
307 | unsigned long generic_find_next_zero_le_bit(const unsigned long *addr, | 322 | find_next_zero_bit_le((addr), (size), 0) |
323 | unsigned long find_next_zero_bit_le(const void *addr, | ||
308 | unsigned long size, unsigned long offset); | 324 | unsigned long size, unsigned long offset); |
309 | 325 | ||
310 | unsigned long generic_find_next_le_bit(const unsigned long *addr, | 326 | unsigned long find_next_bit_le(const void *addr, |
311 | unsigned long size, unsigned long offset); | 327 | unsigned long size, unsigned long offset); |
312 | /* Bitmap functions for the ext2 filesystem */ | 328 | /* Bitmap functions for the ext2 filesystem */ |
313 | 329 | ||
314 | #define ext2_set_bit(nr,addr) \ | ||
315 | __test_and_set_le_bit((nr), (unsigned long*)addr) | ||
316 | #define ext2_clear_bit(nr, addr) \ | ||
317 | __test_and_clear_le_bit((nr), (unsigned long*)addr) | ||
318 | |||
319 | #define ext2_set_bit_atomic(lock, nr, addr) \ | 330 | #define ext2_set_bit_atomic(lock, nr, addr) \ |
320 | test_and_set_le_bit((nr), (unsigned long*)addr) | 331 | test_and_set_bit_le((nr), (unsigned long*)addr) |
321 | #define ext2_clear_bit_atomic(lock, nr, addr) \ | 332 | #define ext2_clear_bit_atomic(lock, nr, addr) \ |
322 | test_and_clear_le_bit((nr), (unsigned long*)addr) | 333 | test_and_clear_bit_le((nr), (unsigned long*)addr) |
323 | |||
324 | #define ext2_test_bit(nr, addr) test_le_bit((nr),(unsigned long*)addr) | ||
325 | |||
326 | #define ext2_find_first_zero_bit(addr, size) \ | ||
327 | find_first_zero_le_bit((unsigned long*)addr, size) | ||
328 | #define ext2_find_next_zero_bit(addr, size, off) \ | ||
329 | generic_find_next_zero_le_bit((unsigned long*)addr, size, off) | ||
330 | |||
331 | #define ext2_find_next_bit(addr, size, off) \ | ||
332 | generic_find_next_le_bit((unsigned long *)addr, size, off) | ||
333 | /* Bitmap functions for the minix filesystem. */ | ||
334 | |||
335 | #define minix_test_and_set_bit(nr,addr) \ | ||
336 | __test_and_set_le_bit(nr, (unsigned long *)addr) | ||
337 | #define minix_set_bit(nr,addr) \ | ||
338 | __set_le_bit(nr, (unsigned long *)addr) | ||
339 | #define minix_test_and_clear_bit(nr,addr) \ | ||
340 | __test_and_clear_le_bit(nr, (unsigned long *)addr) | ||
341 | #define minix_test_bit(nr,addr) \ | ||
342 | test_le_bit(nr, (unsigned long *)addr) | ||
343 | |||
344 | #define minix_find_first_zero_bit(addr,size) \ | ||
345 | find_first_zero_le_bit((unsigned long *)addr, size) | ||
346 | 334 | ||
347 | #include <asm-generic/bitops/sched.h> | 335 | #include <asm-generic/bitops/sched.h> |
348 | 336 | ||
diff --git a/arch/powerpc/include/asm/mpic.h b/arch/powerpc/include/asm/mpic.h index 946ec4947da2..7005ee0b074d 100644 --- a/arch/powerpc/include/asm/mpic.h +++ b/arch/powerpc/include/asm/mpic.h | |||
@@ -367,6 +367,10 @@ struct mpic | |||
367 | #define MPIC_SINGLE_DEST_CPU 0x00001000 | 367 | #define MPIC_SINGLE_DEST_CPU 0x00001000 |
368 | /* Enable CoreInt delivery of interrupts */ | 368 | /* Enable CoreInt delivery of interrupts */ |
369 | #define MPIC_ENABLE_COREINT 0x00002000 | 369 | #define MPIC_ENABLE_COREINT 0x00002000 |
370 | /* Disable resetting of the MPIC. | ||
371 | * NOTE: This flag trumps MPIC_WANTS_RESET. | ||
372 | */ | ||
373 | #define MPIC_NO_RESET 0x00004000 | ||
370 | 374 | ||
371 | /* MPIC HW modification ID */ | 375 | /* MPIC HW modification ID */ |
372 | #define MPIC_REGSET_MASK 0xf0000000 | 376 | #define MPIC_REGSET_MASK 0xf0000000 |
diff --git a/arch/powerpc/include/asm/ptrace.h b/arch/powerpc/include/asm/ptrace.h index 0175a676b34b..48223f9b8728 100644 --- a/arch/powerpc/include/asm/ptrace.h +++ b/arch/powerpc/include/asm/ptrace.h | |||
@@ -125,8 +125,10 @@ extern int ptrace_put_reg(struct task_struct *task, int regno, | |||
125 | #endif /* ! __powerpc64__ */ | 125 | #endif /* ! __powerpc64__ */ |
126 | #define TRAP(regs) ((regs)->trap & ~0xF) | 126 | #define TRAP(regs) ((regs)->trap & ~0xF) |
127 | #ifdef __powerpc64__ | 127 | #ifdef __powerpc64__ |
128 | #define NV_REG_POISON 0xdeadbeefdeadbeefUL | ||
128 | #define CHECK_FULL_REGS(regs) BUG_ON(regs->trap & 1) | 129 | #define CHECK_FULL_REGS(regs) BUG_ON(regs->trap & 1) |
129 | #else | 130 | #else |
131 | #define NV_REG_POISON 0xdeadbeef | ||
130 | #define CHECK_FULL_REGS(regs) \ | 132 | #define CHECK_FULL_REGS(regs) \ |
131 | do { \ | 133 | do { \ |
132 | if ((regs)->trap & 1) \ | 134 | if ((regs)->trap & 1) \ |
diff --git a/arch/powerpc/include/asm/thread_info.h b/arch/powerpc/include/asm/thread_info.h index 65eb85976a03..d8529ef13b23 100644 --- a/arch/powerpc/include/asm/thread_info.h +++ b/arch/powerpc/include/asm/thread_info.h | |||
@@ -72,7 +72,7 @@ struct thread_info { | |||
72 | 72 | ||
73 | #define __HAVE_ARCH_THREAD_INFO_ALLOCATOR | 73 | #define __HAVE_ARCH_THREAD_INFO_ALLOCATOR |
74 | 74 | ||
75 | extern struct thread_info *alloc_thread_info(struct task_struct *tsk); | 75 | extern struct thread_info *alloc_thread_info_node(struct task_struct *tsk, int node); |
76 | extern void free_thread_info(struct thread_info *ti); | 76 | extern void free_thread_info(struct thread_info *ti); |
77 | 77 | ||
78 | #endif /* THREAD_SHIFT < PAGE_SHIFT */ | 78 | #endif /* THREAD_SHIFT < PAGE_SHIFT */ |
diff --git a/arch/powerpc/include/asm/types.h b/arch/powerpc/include/asm/types.h index a5aea0ca34e9..8947b9827bc4 100644 --- a/arch/powerpc/include/asm/types.h +++ b/arch/powerpc/include/asm/types.h | |||
@@ -44,13 +44,6 @@ typedef struct { | |||
44 | 44 | ||
45 | typedef __vector128 vector128; | 45 | typedef __vector128 vector128; |
46 | 46 | ||
47 | #if defined(__powerpc64__) || defined(CONFIG_PHYS_64BIT) | ||
48 | typedef u64 dma_addr_t; | ||
49 | #else | ||
50 | typedef u32 dma_addr_t; | ||
51 | #endif | ||
52 | typedef u64 dma64_addr_t; | ||
53 | |||
54 | typedef struct { | 47 | typedef struct { |
55 | unsigned long entry; | 48 | unsigned long entry; |
56 | unsigned long toc; | 49 | unsigned long toc; |
diff --git a/arch/powerpc/kernel/cpu_setup_fsl_booke.S b/arch/powerpc/kernel/cpu_setup_fsl_booke.S index 5c518ad3445c..913611105c1f 100644 --- a/arch/powerpc/kernel/cpu_setup_fsl_booke.S +++ b/arch/powerpc/kernel/cpu_setup_fsl_booke.S | |||
@@ -64,7 +64,7 @@ _GLOBAL(__setup_cpu_e500v2) | |||
64 | bl __e500_icache_setup | 64 | bl __e500_icache_setup |
65 | bl __e500_dcache_setup | 65 | bl __e500_dcache_setup |
66 | bl __setup_e500_ivors | 66 | bl __setup_e500_ivors |
67 | #ifdef CONFIG_RAPIDIO | 67 | #ifdef CONFIG_FSL_RIO |
68 | /* Ensure that RFXE is set */ | 68 | /* Ensure that RFXE is set */ |
69 | mfspr r3,SPRN_HID1 | 69 | mfspr r3,SPRN_HID1 |
70 | oris r3,r3,HID1_RFXE@h | 70 | oris r3,r3,HID1_RFXE@h |
diff --git a/arch/powerpc/kernel/crash_dump.c b/arch/powerpc/kernel/crash_dump.c index 0a2af50243cb..424afb6b8fba 100644 --- a/arch/powerpc/kernel/crash_dump.c +++ b/arch/powerpc/kernel/crash_dump.c | |||
@@ -28,9 +28,6 @@ | |||
28 | #define DBG(fmt...) | 28 | #define DBG(fmt...) |
29 | #endif | 29 | #endif |
30 | 30 | ||
31 | /* Stores the physical address of elf header of crash image. */ | ||
32 | unsigned long long elfcorehdr_addr = ELFCORE_ADDR_MAX; | ||
33 | |||
34 | #ifndef CONFIG_RELOCATABLE | 31 | #ifndef CONFIG_RELOCATABLE |
35 | void __init reserve_kdump_trampoline(void) | 32 | void __init reserve_kdump_trampoline(void) |
36 | { | 33 | { |
@@ -72,20 +69,6 @@ void __init setup_kdump_trampoline(void) | |||
72 | } | 69 | } |
73 | #endif /* CONFIG_RELOCATABLE */ | 70 | #endif /* CONFIG_RELOCATABLE */ |
74 | 71 | ||
75 | /* | ||
76 | * Note: elfcorehdr_addr is not just limited to vmcore. It is also used by | ||
77 | * is_kdump_kernel() to determine if we are booting after a panic. Hence | ||
78 | * ifdef it under CONFIG_CRASH_DUMP and not CONFIG_PROC_VMCORE. | ||
79 | */ | ||
80 | static int __init parse_elfcorehdr(char *p) | ||
81 | { | ||
82 | if (p) | ||
83 | elfcorehdr_addr = memparse(p, &p); | ||
84 | |||
85 | return 1; | ||
86 | } | ||
87 | __setup("elfcorehdr=", parse_elfcorehdr); | ||
88 | |||
89 | static int __init parse_savemaxmem(char *p) | 72 | static int __init parse_savemaxmem(char *p) |
90 | { | 73 | { |
91 | if (p) | 74 | if (p) |
diff --git a/arch/powerpc/kernel/irq.c b/arch/powerpc/kernel/irq.c index 0a5570338b96..63625e0650b5 100644 --- a/arch/powerpc/kernel/irq.c +++ b/arch/powerpc/kernel/irq.c | |||
@@ -195,7 +195,7 @@ notrace void arch_local_irq_restore(unsigned long en) | |||
195 | EXPORT_SYMBOL(arch_local_irq_restore); | 195 | EXPORT_SYMBOL(arch_local_irq_restore); |
196 | #endif /* CONFIG_PPC64 */ | 196 | #endif /* CONFIG_PPC64 */ |
197 | 197 | ||
198 | static int show_other_interrupts(struct seq_file *p, int prec) | 198 | int arch_show_interrupts(struct seq_file *p, int prec) |
199 | { | 199 | { |
200 | int j; | 200 | int j; |
201 | 201 | ||
@@ -231,65 +231,6 @@ static int show_other_interrupts(struct seq_file *p, int prec) | |||
231 | return 0; | 231 | return 0; |
232 | } | 232 | } |
233 | 233 | ||
234 | int show_interrupts(struct seq_file *p, void *v) | ||
235 | { | ||
236 | unsigned long flags, any_count = 0; | ||
237 | int i = *(loff_t *) v, j, prec; | ||
238 | struct irqaction *action; | ||
239 | struct irq_desc *desc; | ||
240 | struct irq_chip *chip; | ||
241 | |||
242 | if (i > nr_irqs) | ||
243 | return 0; | ||
244 | |||
245 | for (prec = 3, j = 1000; prec < 10 && j <= nr_irqs; ++prec) | ||
246 | j *= 10; | ||
247 | |||
248 | if (i == nr_irqs) | ||
249 | return show_other_interrupts(p, prec); | ||
250 | |||
251 | /* print header */ | ||
252 | if (i == 0) { | ||
253 | seq_printf(p, "%*s", prec + 8, ""); | ||
254 | for_each_online_cpu(j) | ||
255 | seq_printf(p, "CPU%-8d", j); | ||
256 | seq_putc(p, '\n'); | ||
257 | } | ||
258 | |||
259 | desc = irq_to_desc(i); | ||
260 | if (!desc) | ||
261 | return 0; | ||
262 | |||
263 | raw_spin_lock_irqsave(&desc->lock, flags); | ||
264 | for_each_online_cpu(j) | ||
265 | any_count |= kstat_irqs_cpu(i, j); | ||
266 | action = desc->action; | ||
267 | if (!action && !any_count) | ||
268 | goto out; | ||
269 | |||
270 | seq_printf(p, "%*d: ", prec, i); | ||
271 | for_each_online_cpu(j) | ||
272 | seq_printf(p, "%10u ", kstat_irqs_cpu(i, j)); | ||
273 | |||
274 | chip = get_irq_desc_chip(desc); | ||
275 | if (chip) | ||
276 | seq_printf(p, " %-16s", chip->name); | ||
277 | else | ||
278 | seq_printf(p, " %-16s", "None"); | ||
279 | seq_printf(p, " %-8s", (desc->status & IRQ_LEVEL) ? "Level" : "Edge"); | ||
280 | |||
281 | if (action) { | ||
282 | seq_printf(p, " %s", action->name); | ||
283 | while ((action = action->next) != NULL) | ||
284 | seq_printf(p, ", %s", action->name); | ||
285 | } | ||
286 | |||
287 | seq_putc(p, '\n'); | ||
288 | out: | ||
289 | raw_spin_unlock_irqrestore(&desc->lock, flags); | ||
290 | return 0; | ||
291 | } | ||
292 | |||
293 | /* | 234 | /* |
294 | * /proc/stat helpers | 235 | * /proc/stat helpers |
295 | */ | 236 | */ |
@@ -315,24 +256,26 @@ void fixup_irqs(const struct cpumask *map) | |||
315 | alloc_cpumask_var(&mask, GFP_KERNEL); | 256 | alloc_cpumask_var(&mask, GFP_KERNEL); |
316 | 257 | ||
317 | for_each_irq(irq) { | 258 | for_each_irq(irq) { |
259 | struct irq_data *data; | ||
318 | struct irq_chip *chip; | 260 | struct irq_chip *chip; |
319 | 261 | ||
320 | desc = irq_to_desc(irq); | 262 | desc = irq_to_desc(irq); |
321 | if (!desc) | 263 | if (!desc) |
322 | continue; | 264 | continue; |
323 | 265 | ||
324 | if (desc->status & IRQ_PER_CPU) | 266 | data = irq_desc_get_irq_data(desc); |
267 | if (irqd_is_per_cpu(data)) | ||
325 | continue; | 268 | continue; |
326 | 269 | ||
327 | chip = get_irq_desc_chip(desc); | 270 | chip = irq_data_get_irq_chip(data); |
328 | 271 | ||
329 | cpumask_and(mask, desc->irq_data.affinity, map); | 272 | cpumask_and(mask, data->affinity, map); |
330 | if (cpumask_any(mask) >= nr_cpu_ids) { | 273 | if (cpumask_any(mask) >= nr_cpu_ids) { |
331 | printk("Breaking affinity for irq %i\n", irq); | 274 | printk("Breaking affinity for irq %i\n", irq); |
332 | cpumask_copy(mask, map); | 275 | cpumask_copy(mask, map); |
333 | } | 276 | } |
334 | if (chip->irq_set_affinity) | 277 | if (chip->irq_set_affinity) |
335 | chip->irq_set_affinity(&desc->irq_data, mask, true); | 278 | chip->irq_set_affinity(data, mask, true); |
336 | else if (desc->action && !(warned++)) | 279 | else if (desc->action && !(warned++)) |
337 | printk("Cannot set affinity for irq %i\n", irq); | 280 | printk("Cannot set affinity for irq %i\n", irq); |
338 | } | 281 | } |
@@ -618,7 +561,7 @@ struct irq_host *irq_alloc_host(struct device_node *of_node, | |||
618 | smp_wmb(); | 561 | smp_wmb(); |
619 | 562 | ||
620 | /* Clear norequest flags */ | 563 | /* Clear norequest flags */ |
621 | irq_to_desc(i)->status &= ~IRQ_NOREQUEST; | 564 | irq_clear_status_flags(i, IRQ_NOREQUEST); |
622 | 565 | ||
623 | /* Legacy flags are left to default at this point, | 566 | /* Legacy flags are left to default at this point, |
624 | * one can then use irq_create_mapping() to | 567 | * one can then use irq_create_mapping() to |
@@ -827,8 +770,8 @@ unsigned int irq_create_of_mapping(struct device_node *controller, | |||
827 | 770 | ||
828 | /* Set type if specified and different than the current one */ | 771 | /* Set type if specified and different than the current one */ |
829 | if (type != IRQ_TYPE_NONE && | 772 | if (type != IRQ_TYPE_NONE && |
830 | type != (irq_to_desc(virq)->status & IRQF_TRIGGER_MASK)) | 773 | type != (irqd_get_trigger_type(irq_get_irq_data(virq)))) |
831 | set_irq_type(virq, type); | 774 | irq_set_irq_type(virq, type); |
832 | return virq; | 775 | return virq; |
833 | } | 776 | } |
834 | EXPORT_SYMBOL_GPL(irq_create_of_mapping); | 777 | EXPORT_SYMBOL_GPL(irq_create_of_mapping); |
@@ -851,7 +794,7 @@ void irq_dispose_mapping(unsigned int virq) | |||
851 | return; | 794 | return; |
852 | 795 | ||
853 | /* remove chip and handler */ | 796 | /* remove chip and handler */ |
854 | set_irq_chip_and_handler(virq, NULL, NULL); | 797 | irq_set_chip_and_handler(virq, NULL, NULL); |
855 | 798 | ||
856 | /* Make sure it's completed */ | 799 | /* Make sure it's completed */ |
857 | synchronize_irq(virq); | 800 | synchronize_irq(virq); |
@@ -1156,7 +1099,7 @@ static int virq_debug_show(struct seq_file *m, void *private) | |||
1156 | seq_printf(m, "%5d ", i); | 1099 | seq_printf(m, "%5d ", i); |
1157 | seq_printf(m, "0x%05lx ", virq_to_hw(i)); | 1100 | seq_printf(m, "0x%05lx ", virq_to_hw(i)); |
1158 | 1101 | ||
1159 | chip = get_irq_desc_chip(desc); | 1102 | chip = irq_desc_get_chip(desc); |
1160 | if (chip && chip->name) | 1103 | if (chip && chip->name) |
1161 | p = chip->name; | 1104 | p = chip->name; |
1162 | else | 1105 | else |
diff --git a/arch/powerpc/kernel/machine_kexec.c b/arch/powerpc/kernel/machine_kexec.c index bd1e1ff17b2d..7ee50f0547cb 100644 --- a/arch/powerpc/kernel/machine_kexec.c +++ b/arch/powerpc/kernel/machine_kexec.c | |||
@@ -31,17 +31,17 @@ void machine_kexec_mask_interrupts(void) { | |||
31 | if (!desc) | 31 | if (!desc) |
32 | continue; | 32 | continue; |
33 | 33 | ||
34 | chip = get_irq_desc_chip(desc); | 34 | chip = irq_desc_get_chip(desc); |
35 | if (!chip) | 35 | if (!chip) |
36 | continue; | 36 | continue; |
37 | 37 | ||
38 | if (chip->irq_eoi && desc->status & IRQ_INPROGRESS) | 38 | if (chip->irq_eoi && irqd_irq_inprogress(&desc->irq_data)) |
39 | chip->irq_eoi(&desc->irq_data); | 39 | chip->irq_eoi(&desc->irq_data); |
40 | 40 | ||
41 | if (chip->irq_mask) | 41 | if (chip->irq_mask) |
42 | chip->irq_mask(&desc->irq_data); | 42 | chip->irq_mask(&desc->irq_data); |
43 | 43 | ||
44 | if (chip->irq_disable && !(desc->status & IRQ_DISABLED)) | 44 | if (chip->irq_disable && !irqd_irq_disabled(&desc->irq_data)) |
45 | chip->irq_disable(&desc->irq_data); | 45 | chip->irq_disable(&desc->irq_data); |
46 | } | 46 | } |
47 | } | 47 | } |
diff --git a/arch/powerpc/kernel/pci-common.c b/arch/powerpc/kernel/pci-common.c index 3cd85faa8ac6..893af2a9cd03 100644 --- a/arch/powerpc/kernel/pci-common.c +++ b/arch/powerpc/kernel/pci-common.c | |||
@@ -261,7 +261,7 @@ int pci_read_irq_line(struct pci_dev *pci_dev) | |||
261 | 261 | ||
262 | virq = irq_create_mapping(NULL, line); | 262 | virq = irq_create_mapping(NULL, line); |
263 | if (virq != NO_IRQ) | 263 | if (virq != NO_IRQ) |
264 | set_irq_type(virq, IRQ_TYPE_LEVEL_LOW); | 264 | irq_set_irq_type(virq, IRQ_TYPE_LEVEL_LOW); |
265 | } else { | 265 | } else { |
266 | pr_debug(" Got one, spec %d cells (0x%08x 0x%08x...) on %s\n", | 266 | pr_debug(" Got one, spec %d cells (0x%08x 0x%08x...) on %s\n", |
267 | oirq.size, oirq.specifier[0], oirq.specifier[1], | 267 | oirq.size, oirq.specifier[0], oirq.specifier[1], |
diff --git a/arch/powerpc/kernel/pci_dn.c b/arch/powerpc/kernel/pci_dn.c index 29852688ceaa..d225d99fe39d 100644 --- a/arch/powerpc/kernel/pci_dn.c +++ b/arch/powerpc/kernel/pci_dn.c | |||
@@ -176,11 +176,14 @@ static void *is_devfn_node(struct device_node *dn, void *data) | |||
176 | */ | 176 | */ |
177 | struct device_node *fetch_dev_dn(struct pci_dev *dev) | 177 | struct device_node *fetch_dev_dn(struct pci_dev *dev) |
178 | { | 178 | { |
179 | struct device_node *orig_dn = dev->dev.of_node; | 179 | struct pci_controller *phb = dev->sysdata; |
180 | struct device_node *dn; | 180 | struct device_node *dn; |
181 | unsigned long searchval = (dev->bus->number << 8) | dev->devfn; | 181 | unsigned long searchval = (dev->bus->number << 8) | dev->devfn; |
182 | 182 | ||
183 | dn = traverse_pci_devices(orig_dn, is_devfn_node, (void *)searchval); | 183 | if (WARN_ON(!phb)) |
184 | return NULL; | ||
185 | |||
186 | dn = traverse_pci_devices(phb->dn, is_devfn_node, (void *)searchval); | ||
184 | if (dn) | 187 | if (dn) |
185 | dev->dev.of_node = dn; | 188 | dev->dev.of_node = dn; |
186 | return dn; | 189 | return dn; |
diff --git a/arch/powerpc/kernel/process.c b/arch/powerpc/kernel/process.c index 8303a6c65ef7..f74f355a9617 100644 --- a/arch/powerpc/kernel/process.c +++ b/arch/powerpc/kernel/process.c | |||
@@ -1218,11 +1218,11 @@ void __ppc64_runlatch_off(void) | |||
1218 | 1218 | ||
1219 | static struct kmem_cache *thread_info_cache; | 1219 | static struct kmem_cache *thread_info_cache; |
1220 | 1220 | ||
1221 | struct thread_info *alloc_thread_info(struct task_struct *tsk) | 1221 | struct thread_info *alloc_thread_info_node(struct task_struct *tsk, int node) |
1222 | { | 1222 | { |
1223 | struct thread_info *ti; | 1223 | struct thread_info *ti; |
1224 | 1224 | ||
1225 | ti = kmem_cache_alloc(thread_info_cache, GFP_KERNEL); | 1225 | ti = kmem_cache_alloc_node(thread_info_cache, GFP_KERNEL, node); |
1226 | if (unlikely(ti == NULL)) | 1226 | if (unlikely(ti == NULL)) |
1227 | return NULL; | 1227 | return NULL; |
1228 | #ifdef CONFIG_DEBUG_STACK_USAGE | 1228 | #ifdef CONFIG_DEBUG_STACK_USAGE |
diff --git a/arch/powerpc/kernel/ptrace.c b/arch/powerpc/kernel/ptrace.c index 906536998291..895b082f1e48 100644 --- a/arch/powerpc/kernel/ptrace.c +++ b/arch/powerpc/kernel/ptrace.c | |||
@@ -229,12 +229,16 @@ static int gpr_get(struct task_struct *target, const struct user_regset *regset, | |||
229 | unsigned int pos, unsigned int count, | 229 | unsigned int pos, unsigned int count, |
230 | void *kbuf, void __user *ubuf) | 230 | void *kbuf, void __user *ubuf) |
231 | { | 231 | { |
232 | int ret; | 232 | int i, ret; |
233 | 233 | ||
234 | if (target->thread.regs == NULL) | 234 | if (target->thread.regs == NULL) |
235 | return -EIO; | 235 | return -EIO; |
236 | 236 | ||
237 | CHECK_FULL_REGS(target->thread.regs); | 237 | if (!FULL_REGS(target->thread.regs)) { |
238 | /* We have a partial register set. Fill 14-31 with bogus values */ | ||
239 | for (i = 14; i < 32; i++) | ||
240 | target->thread.regs->gpr[i] = NV_REG_POISON; | ||
241 | } | ||
238 | 242 | ||
239 | ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf, | 243 | ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf, |
240 | target->thread.regs, | 244 | target->thread.regs, |
@@ -641,11 +645,16 @@ static int gpr32_get(struct task_struct *target, | |||
641 | compat_ulong_t *k = kbuf; | 645 | compat_ulong_t *k = kbuf; |
642 | compat_ulong_t __user *u = ubuf; | 646 | compat_ulong_t __user *u = ubuf; |
643 | compat_ulong_t reg; | 647 | compat_ulong_t reg; |
648 | int i; | ||
644 | 649 | ||
645 | if (target->thread.regs == NULL) | 650 | if (target->thread.regs == NULL) |
646 | return -EIO; | 651 | return -EIO; |
647 | 652 | ||
648 | CHECK_FULL_REGS(target->thread.regs); | 653 | if (!FULL_REGS(target->thread.regs)) { |
654 | /* We have a partial register set. Fill 14-31 with bogus values */ | ||
655 | for (i = 14; i < 32; i++) | ||
656 | target->thread.regs->gpr[i] = NV_REG_POISON; | ||
657 | } | ||
649 | 658 | ||
650 | pos /= sizeof(reg); | 659 | pos /= sizeof(reg); |
651 | count /= sizeof(reg); | 660 | count /= sizeof(reg); |
diff --git a/arch/powerpc/kernel/vdso.c b/arch/powerpc/kernel/vdso.c index fd8728729abc..142ab1008c3b 100644 --- a/arch/powerpc/kernel/vdso.c +++ b/arch/powerpc/kernel/vdso.c | |||
@@ -820,17 +820,17 @@ static int __init vdso_init(void) | |||
820 | } | 820 | } |
821 | arch_initcall(vdso_init); | 821 | arch_initcall(vdso_init); |
822 | 822 | ||
823 | int in_gate_area_no_task(unsigned long addr) | 823 | int in_gate_area_no_mm(unsigned long addr) |
824 | { | 824 | { |
825 | return 0; | 825 | return 0; |
826 | } | 826 | } |
827 | 827 | ||
828 | int in_gate_area(struct task_struct *task, unsigned long addr) | 828 | int in_gate_area(struct mm_struct *mm, unsigned long addr) |
829 | { | 829 | { |
830 | return 0; | 830 | return 0; |
831 | } | 831 | } |
832 | 832 | ||
833 | struct vm_area_struct *get_gate_vma(struct task_struct *tsk) | 833 | struct vm_area_struct *get_gate_vma(struct mm_struct *mm) |
834 | { | 834 | { |
835 | return NULL; | 835 | return NULL; |
836 | } | 836 | } |
diff --git a/arch/powerpc/platforms/512x/mpc5121_ads_cpld.c b/arch/powerpc/platforms/512x/mpc5121_ads_cpld.c index fde0ea50c97d..cfc4b2009982 100644 --- a/arch/powerpc/platforms/512x/mpc5121_ads_cpld.c +++ b/arch/powerpc/platforms/512x/mpc5121_ads_cpld.c | |||
@@ -132,8 +132,8 @@ static int | |||
132 | cpld_pic_host_map(struct irq_host *h, unsigned int virq, | 132 | cpld_pic_host_map(struct irq_host *h, unsigned int virq, |
133 | irq_hw_number_t hw) | 133 | irq_hw_number_t hw) |
134 | { | 134 | { |
135 | irq_to_desc(virq)->status |= IRQ_LEVEL; | 135 | irq_set_status_flags(virq, IRQ_LEVEL); |
136 | set_irq_chip_and_handler(virq, &cpld_pic, handle_level_irq); | 136 | irq_set_chip_and_handler(virq, &cpld_pic, handle_level_irq); |
137 | return 0; | 137 | return 0; |
138 | } | 138 | } |
139 | 139 | ||
@@ -198,7 +198,7 @@ mpc5121_ads_cpld_pic_init(void) | |||
198 | goto end; | 198 | goto end; |
199 | } | 199 | } |
200 | 200 | ||
201 | set_irq_chained_handler(cascade_irq, cpld_pic_cascade); | 201 | irq_set_chained_handler(cascade_irq, cpld_pic_cascade); |
202 | end: | 202 | end: |
203 | of_node_put(np); | 203 | of_node_put(np); |
204 | } | 204 | } |
diff --git a/arch/powerpc/platforms/52xx/media5200.c b/arch/powerpc/platforms/52xx/media5200.c index 2bd1e6cf1f58..57a6a349e932 100644 --- a/arch/powerpc/platforms/52xx/media5200.c +++ b/arch/powerpc/platforms/52xx/media5200.c | |||
@@ -82,7 +82,7 @@ static struct irq_chip media5200_irq_chip = { | |||
82 | 82 | ||
83 | void media5200_irq_cascade(unsigned int virq, struct irq_desc *desc) | 83 | void media5200_irq_cascade(unsigned int virq, struct irq_desc *desc) |
84 | { | 84 | { |
85 | struct irq_chip *chip = get_irq_desc_chip(desc); | 85 | struct irq_chip *chip = irq_desc_get_chip(desc); |
86 | int sub_virq, val; | 86 | int sub_virq, val; |
87 | u32 status, enable; | 87 | u32 status, enable; |
88 | 88 | ||
@@ -107,7 +107,7 @@ void media5200_irq_cascade(unsigned int virq, struct irq_desc *desc) | |||
107 | /* Processing done; can reenable the cascade now */ | 107 | /* Processing done; can reenable the cascade now */ |
108 | raw_spin_lock(&desc->lock); | 108 | raw_spin_lock(&desc->lock); |
109 | chip->irq_ack(&desc->irq_data); | 109 | chip->irq_ack(&desc->irq_data); |
110 | if (!(desc->status & IRQ_DISABLED)) | 110 | if (!irqd_irq_disabled(&desc->irq_data)) |
111 | chip->irq_unmask(&desc->irq_data); | 111 | chip->irq_unmask(&desc->irq_data); |
112 | raw_spin_unlock(&desc->lock); | 112 | raw_spin_unlock(&desc->lock); |
113 | } | 113 | } |
@@ -115,15 +115,10 @@ void media5200_irq_cascade(unsigned int virq, struct irq_desc *desc) | |||
115 | static int media5200_irq_map(struct irq_host *h, unsigned int virq, | 115 | static int media5200_irq_map(struct irq_host *h, unsigned int virq, |
116 | irq_hw_number_t hw) | 116 | irq_hw_number_t hw) |
117 | { | 117 | { |
118 | struct irq_desc *desc = irq_to_desc(virq); | ||
119 | |||
120 | pr_debug("%s: h=%p, virq=%i, hwirq=%i\n", __func__, h, virq, (int)hw); | 118 | pr_debug("%s: h=%p, virq=%i, hwirq=%i\n", __func__, h, virq, (int)hw); |
121 | set_irq_chip_data(virq, &media5200_irq); | 119 | irq_set_chip_data(virq, &media5200_irq); |
122 | set_irq_chip_and_handler(virq, &media5200_irq_chip, handle_level_irq); | 120 | irq_set_chip_and_handler(virq, &media5200_irq_chip, handle_level_irq); |
123 | set_irq_type(virq, IRQ_TYPE_LEVEL_LOW); | 121 | irq_set_status_flags(virq, IRQ_LEVEL); |
124 | desc->status &= ~(IRQ_TYPE_SENSE_MASK | IRQ_LEVEL); | ||
125 | desc->status |= IRQ_TYPE_LEVEL_LOW | IRQ_LEVEL; | ||
126 | |||
127 | return 0; | 122 | return 0; |
128 | } | 123 | } |
129 | 124 | ||
@@ -187,8 +182,8 @@ static void __init media5200_init_irq(void) | |||
187 | 182 | ||
188 | media5200_irq.irqhost->host_data = &media5200_irq; | 183 | media5200_irq.irqhost->host_data = &media5200_irq; |
189 | 184 | ||
190 | set_irq_data(cascade_virq, &media5200_irq); | 185 | irq_set_handler_data(cascade_virq, &media5200_irq); |
191 | set_irq_chained_handler(cascade_virq, media5200_irq_cascade); | 186 | irq_set_chained_handler(cascade_virq, media5200_irq_cascade); |
192 | 187 | ||
193 | return; | 188 | return; |
194 | 189 | ||
diff --git a/arch/powerpc/platforms/52xx/mpc52xx_gpt.c b/arch/powerpc/platforms/52xx/mpc52xx_gpt.c index 6da44f0f2934..6c39b9cc2fa3 100644 --- a/arch/powerpc/platforms/52xx/mpc52xx_gpt.c +++ b/arch/powerpc/platforms/52xx/mpc52xx_gpt.c | |||
@@ -192,7 +192,7 @@ static struct irq_chip mpc52xx_gpt_irq_chip = { | |||
192 | 192 | ||
193 | void mpc52xx_gpt_irq_cascade(unsigned int virq, struct irq_desc *desc) | 193 | void mpc52xx_gpt_irq_cascade(unsigned int virq, struct irq_desc *desc) |
194 | { | 194 | { |
195 | struct mpc52xx_gpt_priv *gpt = get_irq_data(virq); | 195 | struct mpc52xx_gpt_priv *gpt = irq_get_handler_data(virq); |
196 | int sub_virq; | 196 | int sub_virq; |
197 | u32 status; | 197 | u32 status; |
198 | 198 | ||
@@ -209,8 +209,8 @@ static int mpc52xx_gpt_irq_map(struct irq_host *h, unsigned int virq, | |||
209 | struct mpc52xx_gpt_priv *gpt = h->host_data; | 209 | struct mpc52xx_gpt_priv *gpt = h->host_data; |
210 | 210 | ||
211 | dev_dbg(gpt->dev, "%s: h=%p, virq=%i\n", __func__, h, virq); | 211 | dev_dbg(gpt->dev, "%s: h=%p, virq=%i\n", __func__, h, virq); |
212 | set_irq_chip_data(virq, gpt); | 212 | irq_set_chip_data(virq, gpt); |
213 | set_irq_chip_and_handler(virq, &mpc52xx_gpt_irq_chip, handle_edge_irq); | 213 | irq_set_chip_and_handler(virq, &mpc52xx_gpt_irq_chip, handle_edge_irq); |
214 | 214 | ||
215 | return 0; | 215 | return 0; |
216 | } | 216 | } |
@@ -259,8 +259,8 @@ mpc52xx_gpt_irq_setup(struct mpc52xx_gpt_priv *gpt, struct device_node *node) | |||
259 | } | 259 | } |
260 | 260 | ||
261 | gpt->irqhost->host_data = gpt; | 261 | gpt->irqhost->host_data = gpt; |
262 | set_irq_data(cascade_virq, gpt); | 262 | irq_set_handler_data(cascade_virq, gpt); |
263 | set_irq_chained_handler(cascade_virq, mpc52xx_gpt_irq_cascade); | 263 | irq_set_chained_handler(cascade_virq, mpc52xx_gpt_irq_cascade); |
264 | 264 | ||
265 | /* If the GPT is currently disabled, then change it to be in Input | 265 | /* If the GPT is currently disabled, then change it to be in Input |
266 | * Capture mode. If the mode is non-zero, then the pin could be | 266 | * Capture mode. If the mode is non-zero, then the pin could be |
diff --git a/arch/powerpc/platforms/52xx/mpc52xx_pic.c b/arch/powerpc/platforms/52xx/mpc52xx_pic.c index 9f3ed582d082..3ddea96273ca 100644 --- a/arch/powerpc/platforms/52xx/mpc52xx_pic.c +++ b/arch/powerpc/platforms/52xx/mpc52xx_pic.c | |||
@@ -214,7 +214,7 @@ static int mpc52xx_extirq_set_type(struct irq_data *d, unsigned int flow_type) | |||
214 | ctrl_reg |= (type << (22 - (l2irq * 2))); | 214 | ctrl_reg |= (type << (22 - (l2irq * 2))); |
215 | out_be32(&intr->ctrl, ctrl_reg); | 215 | out_be32(&intr->ctrl, ctrl_reg); |
216 | 216 | ||
217 | __set_irq_handler_unlocked(d->irq, handler); | 217 | __irq_set_handler_locked(d->irq, handler); |
218 | 218 | ||
219 | return 0; | 219 | return 0; |
220 | } | 220 | } |
@@ -414,7 +414,7 @@ static int mpc52xx_irqhost_map(struct irq_host *h, unsigned int virq, | |||
414 | else | 414 | else |
415 | hndlr = handle_level_irq; | 415 | hndlr = handle_level_irq; |
416 | 416 | ||
417 | set_irq_chip_and_handler(virq, &mpc52xx_extirq_irqchip, hndlr); | 417 | irq_set_chip_and_handler(virq, &mpc52xx_extirq_irqchip, hndlr); |
418 | pr_debug("%s: External IRQ%i virq=%x, hw=%x. type=%x\n", | 418 | pr_debug("%s: External IRQ%i virq=%x, hw=%x. type=%x\n", |
419 | __func__, l2irq, virq, (int)irq, type); | 419 | __func__, l2irq, virq, (int)irq, type); |
420 | return 0; | 420 | return 0; |
@@ -431,7 +431,7 @@ static int mpc52xx_irqhost_map(struct irq_host *h, unsigned int virq, | |||
431 | return -EINVAL; | 431 | return -EINVAL; |
432 | } | 432 | } |
433 | 433 | ||
434 | set_irq_chip_and_handler(virq, irqchip, handle_level_irq); | 434 | irq_set_chip_and_handler(virq, irqchip, handle_level_irq); |
435 | pr_debug("%s: virq=%x, l1=%i, l2=%i\n", __func__, virq, l1irq, l2irq); | 435 | pr_debug("%s: virq=%x, l1=%i, l2=%i\n", __func__, virq, l1irq, l2irq); |
436 | 436 | ||
437 | return 0; | 437 | return 0; |
diff --git a/arch/powerpc/platforms/82xx/pq2ads-pci-pic.c b/arch/powerpc/platforms/82xx/pq2ads-pci-pic.c index 926dfdaaf57a..4a4eb6ffa12f 100644 --- a/arch/powerpc/platforms/82xx/pq2ads-pci-pic.c +++ b/arch/powerpc/platforms/82xx/pq2ads-pci-pic.c | |||
@@ -81,7 +81,7 @@ static struct irq_chip pq2ads_pci_ic = { | |||
81 | 81 | ||
82 | static void pq2ads_pci_irq_demux(unsigned int irq, struct irq_desc *desc) | 82 | static void pq2ads_pci_irq_demux(unsigned int irq, struct irq_desc *desc) |
83 | { | 83 | { |
84 | struct pq2ads_pci_pic *priv = get_irq_desc_data(desc); | 84 | struct pq2ads_pci_pic *priv = irq_desc_get_handler_data(desc); |
85 | u32 stat, mask, pend; | 85 | u32 stat, mask, pend; |
86 | int bit; | 86 | int bit; |
87 | 87 | ||
@@ -106,17 +106,17 @@ static void pq2ads_pci_irq_demux(unsigned int irq, struct irq_desc *desc) | |||
106 | static int pci_pic_host_map(struct irq_host *h, unsigned int virq, | 106 | static int pci_pic_host_map(struct irq_host *h, unsigned int virq, |
107 | irq_hw_number_t hw) | 107 | irq_hw_number_t hw) |
108 | { | 108 | { |
109 | irq_to_desc(virq)->status |= IRQ_LEVEL; | 109 | irq_set_status_flags(virq, IRQ_LEVEL); |
110 | set_irq_chip_data(virq, h->host_data); | 110 | irq_set_chip_data(virq, h->host_data); |
111 | set_irq_chip_and_handler(virq, &pq2ads_pci_ic, handle_level_irq); | 111 | irq_set_chip_and_handler(virq, &pq2ads_pci_ic, handle_level_irq); |
112 | return 0; | 112 | return 0; |
113 | } | 113 | } |
114 | 114 | ||
115 | static void pci_host_unmap(struct irq_host *h, unsigned int virq) | 115 | static void pci_host_unmap(struct irq_host *h, unsigned int virq) |
116 | { | 116 | { |
117 | /* remove chip and handler */ | 117 | /* remove chip and handler */ |
118 | set_irq_chip_data(virq, NULL); | 118 | irq_set_chip_data(virq, NULL); |
119 | set_irq_chip(virq, NULL); | 119 | irq_set_chip(virq, NULL); |
120 | } | 120 | } |
121 | 121 | ||
122 | static struct irq_host_ops pci_pic_host_ops = { | 122 | static struct irq_host_ops pci_pic_host_ops = { |
@@ -175,8 +175,8 @@ int __init pq2ads_pci_init_irq(void) | |||
175 | 175 | ||
176 | priv->host = host; | 176 | priv->host = host; |
177 | host->host_data = priv; | 177 | host->host_data = priv; |
178 | set_irq_data(irq, priv); | 178 | irq_set_handler_data(irq, priv); |
179 | set_irq_chained_handler(irq, pq2ads_pci_irq_demux); | 179 | irq_set_chained_handler(irq, pq2ads_pci_irq_demux); |
180 | 180 | ||
181 | of_node_put(np); | 181 | of_node_put(np); |
182 | return 0; | 182 | return 0; |
diff --git a/arch/powerpc/platforms/85xx/ksi8560.c b/arch/powerpc/platforms/85xx/ksi8560.c index 64447e48f3d5..c46f9359be15 100644 --- a/arch/powerpc/platforms/85xx/ksi8560.c +++ b/arch/powerpc/platforms/85xx/ksi8560.c | |||
@@ -56,7 +56,7 @@ static void machine_restart(char *cmd) | |||
56 | 56 | ||
57 | static void cpm2_cascade(unsigned int irq, struct irq_desc *desc) | 57 | static void cpm2_cascade(unsigned int irq, struct irq_desc *desc) |
58 | { | 58 | { |
59 | struct irq_chip *chip = get_irq_desc_chip(desc); | 59 | struct irq_chip *chip = irq_desc_get_chip(desc); |
60 | int cascade_irq; | 60 | int cascade_irq; |
61 | 61 | ||
62 | while ((cascade_irq = cpm2_get_irq()) >= 0) | 62 | while ((cascade_irq = cpm2_get_irq()) >= 0) |
@@ -106,7 +106,7 @@ static void __init ksi8560_pic_init(void) | |||
106 | 106 | ||
107 | cpm2_pic_init(np); | 107 | cpm2_pic_init(np); |
108 | of_node_put(np); | 108 | of_node_put(np); |
109 | set_irq_chained_handler(irq, cpm2_cascade); | 109 | irq_set_chained_handler(irq, cpm2_cascade); |
110 | #endif | 110 | #endif |
111 | } | 111 | } |
112 | 112 | ||
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_ads.c b/arch/powerpc/platforms/85xx/mpc85xx_ads.c index 1352d1107bfd..3b2c9bb66199 100644 --- a/arch/powerpc/platforms/85xx/mpc85xx_ads.c +++ b/arch/powerpc/platforms/85xx/mpc85xx_ads.c | |||
@@ -50,7 +50,7 @@ static int mpc85xx_exclude_device(struct pci_controller *hose, | |||
50 | 50 | ||
51 | static void cpm2_cascade(unsigned int irq, struct irq_desc *desc) | 51 | static void cpm2_cascade(unsigned int irq, struct irq_desc *desc) |
52 | { | 52 | { |
53 | struct irq_chip *chip = get_irq_desc_chip(desc); | 53 | struct irq_chip *chip = irq_desc_get_chip(desc); |
54 | int cascade_irq; | 54 | int cascade_irq; |
55 | 55 | ||
56 | while ((cascade_irq = cpm2_get_irq()) >= 0) | 56 | while ((cascade_irq = cpm2_get_irq()) >= 0) |
@@ -101,7 +101,7 @@ static void __init mpc85xx_ads_pic_init(void) | |||
101 | 101 | ||
102 | cpm2_pic_init(np); | 102 | cpm2_pic_init(np); |
103 | of_node_put(np); | 103 | of_node_put(np); |
104 | set_irq_chained_handler(irq, cpm2_cascade); | 104 | irq_set_chained_handler(irq, cpm2_cascade); |
105 | #endif | 105 | #endif |
106 | } | 106 | } |
107 | 107 | ||
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_cds.c b/arch/powerpc/platforms/85xx/mpc85xx_cds.c index 458d91fba91d..6299a2a51ae8 100644 --- a/arch/powerpc/platforms/85xx/mpc85xx_cds.c +++ b/arch/powerpc/platforms/85xx/mpc85xx_cds.c | |||
@@ -255,7 +255,7 @@ static int mpc85xx_cds_8259_attach(void) | |||
255 | } | 255 | } |
256 | 256 | ||
257 | /* Success. Connect our low-level cascade handler. */ | 257 | /* Success. Connect our low-level cascade handler. */ |
258 | set_irq_handler(cascade_irq, mpc85xx_8259_cascade_handler); | 258 | irq_set_handler(cascade_irq, mpc85xx_8259_cascade_handler); |
259 | 259 | ||
260 | return 0; | 260 | return 0; |
261 | } | 261 | } |
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_ds.c b/arch/powerpc/platforms/85xx/mpc85xx_ds.c index 793ead7993ab..c7b97f70312e 100644 --- a/arch/powerpc/platforms/85xx/mpc85xx_ds.c +++ b/arch/powerpc/platforms/85xx/mpc85xx_ds.c | |||
@@ -47,7 +47,7 @@ | |||
47 | #ifdef CONFIG_PPC_I8259 | 47 | #ifdef CONFIG_PPC_I8259 |
48 | static void mpc85xx_8259_cascade(unsigned int irq, struct irq_desc *desc) | 48 | static void mpc85xx_8259_cascade(unsigned int irq, struct irq_desc *desc) |
49 | { | 49 | { |
50 | struct irq_chip *chip = get_irq_desc_chip(desc); | 50 | struct irq_chip *chip = irq_desc_get_chip(desc); |
51 | unsigned int cascade_irq = i8259_irq(); | 51 | unsigned int cascade_irq = i8259_irq(); |
52 | 52 | ||
53 | if (cascade_irq != NO_IRQ) { | 53 | if (cascade_irq != NO_IRQ) { |
@@ -122,7 +122,7 @@ void __init mpc85xx_ds_pic_init(void) | |||
122 | i8259_init(cascade_node, 0); | 122 | i8259_init(cascade_node, 0); |
123 | of_node_put(cascade_node); | 123 | of_node_put(cascade_node); |
124 | 124 | ||
125 | set_irq_chained_handler(cascade_irq, mpc85xx_8259_cascade); | 125 | irq_set_chained_handler(cascade_irq, mpc85xx_8259_cascade); |
126 | #endif /* CONFIG_PPC_I8259 */ | 126 | #endif /* CONFIG_PPC_I8259 */ |
127 | } | 127 | } |
128 | 128 | ||
diff --git a/arch/powerpc/platforms/85xx/sbc8560.c b/arch/powerpc/platforms/85xx/sbc8560.c index d7e28ec3e072..d2dfd465fbf6 100644 --- a/arch/powerpc/platforms/85xx/sbc8560.c +++ b/arch/powerpc/platforms/85xx/sbc8560.c | |||
@@ -41,7 +41,7 @@ | |||
41 | 41 | ||
42 | static void cpm2_cascade(unsigned int irq, struct irq_desc *desc) | 42 | static void cpm2_cascade(unsigned int irq, struct irq_desc *desc) |
43 | { | 43 | { |
44 | struct irq_chip *chip = get_irq_desc_chip(desc); | 44 | struct irq_chip *chip = irq_desc_get_chip(desc); |
45 | int cascade_irq; | 45 | int cascade_irq; |
46 | 46 | ||
47 | while ((cascade_irq = cpm2_get_irq()) >= 0) | 47 | while ((cascade_irq = cpm2_get_irq()) >= 0) |
@@ -92,7 +92,7 @@ static void __init sbc8560_pic_init(void) | |||
92 | 92 | ||
93 | cpm2_pic_init(np); | 93 | cpm2_pic_init(np); |
94 | of_node_put(np); | 94 | of_node_put(np); |
95 | set_irq_chained_handler(irq, cpm2_cascade); | 95 | irq_set_chained_handler(irq, cpm2_cascade); |
96 | #endif | 96 | #endif |
97 | } | 97 | } |
98 | 98 | ||
diff --git a/arch/powerpc/platforms/85xx/socrates_fpga_pic.c b/arch/powerpc/platforms/85xx/socrates_fpga_pic.c index 79d85aca4767..db864623b4ae 100644 --- a/arch/powerpc/platforms/85xx/socrates_fpga_pic.c +++ b/arch/powerpc/platforms/85xx/socrates_fpga_pic.c | |||
@@ -93,7 +93,7 @@ static inline unsigned int socrates_fpga_pic_get_irq(unsigned int irq) | |||
93 | 93 | ||
94 | void socrates_fpga_pic_cascade(unsigned int irq, struct irq_desc *desc) | 94 | void socrates_fpga_pic_cascade(unsigned int irq, struct irq_desc *desc) |
95 | { | 95 | { |
96 | struct irq_chip *chip = get_irq_desc_chip(desc); | 96 | struct irq_chip *chip = irq_desc_get_chip(desc); |
97 | unsigned int cascade_irq; | 97 | unsigned int cascade_irq; |
98 | 98 | ||
99 | /* | 99 | /* |
@@ -245,9 +245,9 @@ static int socrates_fpga_pic_host_map(struct irq_host *h, unsigned int virq, | |||
245 | irq_hw_number_t hwirq) | 245 | irq_hw_number_t hwirq) |
246 | { | 246 | { |
247 | /* All interrupts are LEVEL sensitive */ | 247 | /* All interrupts are LEVEL sensitive */ |
248 | irq_to_desc(virq)->status |= IRQ_LEVEL; | 248 | irq_set_status_flags(virq, IRQ_LEVEL); |
249 | set_irq_chip_and_handler(virq, &socrates_fpga_pic_chip, | 249 | irq_set_chip_and_handler(virq, &socrates_fpga_pic_chip, |
250 | handle_fasteoi_irq); | 250 | handle_fasteoi_irq); |
251 | 251 | ||
252 | return 0; | 252 | return 0; |
253 | } | 253 | } |
@@ -308,8 +308,8 @@ void socrates_fpga_pic_init(struct device_node *pic) | |||
308 | pr_warning("FPGA PIC: can't get irq%d.\n", i); | 308 | pr_warning("FPGA PIC: can't get irq%d.\n", i); |
309 | continue; | 309 | continue; |
310 | } | 310 | } |
311 | set_irq_chained_handler(socrates_fpga_irqs[i], | 311 | irq_set_chained_handler(socrates_fpga_irqs[i], |
312 | socrates_fpga_pic_cascade); | 312 | socrates_fpga_pic_cascade); |
313 | } | 313 | } |
314 | 314 | ||
315 | socrates_fpga_pic_iobase = of_iomap(pic, 0); | 315 | socrates_fpga_pic_iobase = of_iomap(pic, 0); |
diff --git a/arch/powerpc/platforms/85xx/stx_gp3.c b/arch/powerpc/platforms/85xx/stx_gp3.c index 2b62b064eac7..5387e9f06bdb 100644 --- a/arch/powerpc/platforms/85xx/stx_gp3.c +++ b/arch/powerpc/platforms/85xx/stx_gp3.c | |||
@@ -46,7 +46,7 @@ | |||
46 | 46 | ||
47 | static void cpm2_cascade(unsigned int irq, struct irq_desc *desc) | 47 | static void cpm2_cascade(unsigned int irq, struct irq_desc *desc) |
48 | { | 48 | { |
49 | struct irq_chip *chip = get_irq_desc_chip(desc); | 49 | struct irq_chip *chip = irq_desc_get_chip(desc); |
50 | int cascade_irq; | 50 | int cascade_irq; |
51 | 51 | ||
52 | while ((cascade_irq = cpm2_get_irq()) >= 0) | 52 | while ((cascade_irq = cpm2_get_irq()) >= 0) |
@@ -102,7 +102,7 @@ static void __init stx_gp3_pic_init(void) | |||
102 | 102 | ||
103 | cpm2_pic_init(np); | 103 | cpm2_pic_init(np); |
104 | of_node_put(np); | 104 | of_node_put(np); |
105 | set_irq_chained_handler(irq, cpm2_cascade); | 105 | irq_set_chained_handler(irq, cpm2_cascade); |
106 | #endif | 106 | #endif |
107 | } | 107 | } |
108 | 108 | ||
diff --git a/arch/powerpc/platforms/85xx/tqm85xx.c b/arch/powerpc/platforms/85xx/tqm85xx.c index 2265b68e3279..325de772725a 100644 --- a/arch/powerpc/platforms/85xx/tqm85xx.c +++ b/arch/powerpc/platforms/85xx/tqm85xx.c | |||
@@ -44,7 +44,7 @@ | |||
44 | 44 | ||
45 | static void cpm2_cascade(unsigned int irq, struct irq_desc *desc) | 45 | static void cpm2_cascade(unsigned int irq, struct irq_desc *desc) |
46 | { | 46 | { |
47 | struct irq_chip *chip = get_irq_desc_chip(desc); | 47 | struct irq_chip *chip = irq_desc_get_chip(desc); |
48 | int cascade_irq; | 48 | int cascade_irq; |
49 | 49 | ||
50 | while ((cascade_irq = cpm2_get_irq()) >= 0) | 50 | while ((cascade_irq = cpm2_get_irq()) >= 0) |
@@ -100,7 +100,7 @@ static void __init tqm85xx_pic_init(void) | |||
100 | 100 | ||
101 | cpm2_pic_init(np); | 101 | cpm2_pic_init(np); |
102 | of_node_put(np); | 102 | of_node_put(np); |
103 | set_irq_chained_handler(irq, cpm2_cascade); | 103 | irq_set_chained_handler(irq, cpm2_cascade); |
104 | #endif | 104 | #endif |
105 | } | 105 | } |
106 | 106 | ||
diff --git a/arch/powerpc/platforms/86xx/gef_pic.c b/arch/powerpc/platforms/86xx/gef_pic.c index 0adfe3b740cd..0beec7d5566b 100644 --- a/arch/powerpc/platforms/86xx/gef_pic.c +++ b/arch/powerpc/platforms/86xx/gef_pic.c | |||
@@ -95,7 +95,7 @@ static int gef_pic_cascade_irq; | |||
95 | 95 | ||
96 | void gef_pic_cascade(unsigned int irq, struct irq_desc *desc) | 96 | void gef_pic_cascade(unsigned int irq, struct irq_desc *desc) |
97 | { | 97 | { |
98 | struct irq_chip *chip = get_irq_desc_chip(desc); | 98 | struct irq_chip *chip = irq_desc_get_chip(desc); |
99 | unsigned int cascade_irq; | 99 | unsigned int cascade_irq; |
100 | 100 | ||
101 | /* | 101 | /* |
@@ -163,8 +163,8 @@ static int gef_pic_host_map(struct irq_host *h, unsigned int virq, | |||
163 | irq_hw_number_t hwirq) | 163 | irq_hw_number_t hwirq) |
164 | { | 164 | { |
165 | /* All interrupts are LEVEL sensitive */ | 165 | /* All interrupts are LEVEL sensitive */ |
166 | irq_to_desc(virq)->status |= IRQ_LEVEL; | 166 | irq_set_status_flags(virq, IRQ_LEVEL); |
167 | set_irq_chip_and_handler(virq, &gef_pic_chip, handle_level_irq); | 167 | irq_set_chip_and_handler(virq, &gef_pic_chip, handle_level_irq); |
168 | 168 | ||
169 | return 0; | 169 | return 0; |
170 | } | 170 | } |
@@ -225,7 +225,7 @@ void __init gef_pic_init(struct device_node *np) | |||
225 | return; | 225 | return; |
226 | 226 | ||
227 | /* Chain with parent controller */ | 227 | /* Chain with parent controller */ |
228 | set_irq_chained_handler(gef_pic_cascade_irq, gef_pic_cascade); | 228 | irq_set_chained_handler(gef_pic_cascade_irq, gef_pic_cascade); |
229 | } | 229 | } |
230 | 230 | ||
231 | /* | 231 | /* |
diff --git a/arch/powerpc/platforms/86xx/pic.c b/arch/powerpc/platforms/86xx/pic.c index cbe33639b478..8ef8960abda6 100644 --- a/arch/powerpc/platforms/86xx/pic.c +++ b/arch/powerpc/platforms/86xx/pic.c | |||
@@ -19,7 +19,7 @@ | |||
19 | #ifdef CONFIG_PPC_I8259 | 19 | #ifdef CONFIG_PPC_I8259 |
20 | static void mpc86xx_8259_cascade(unsigned int irq, struct irq_desc *desc) | 20 | static void mpc86xx_8259_cascade(unsigned int irq, struct irq_desc *desc) |
21 | { | 21 | { |
22 | struct irq_chip *chip = get_irq_desc_chip(desc); | 22 | struct irq_chip *chip = irq_desc_get_chip(desc); |
23 | unsigned int cascade_irq = i8259_irq(); | 23 | unsigned int cascade_irq = i8259_irq(); |
24 | 24 | ||
25 | if (cascade_irq != NO_IRQ) | 25 | if (cascade_irq != NO_IRQ) |
@@ -77,6 +77,6 @@ void __init mpc86xx_init_irq(void) | |||
77 | i8259_init(cascade_node, 0); | 77 | i8259_init(cascade_node, 0); |
78 | of_node_put(cascade_node); | 78 | of_node_put(cascade_node); |
79 | 79 | ||
80 | set_irq_chained_handler(cascade_irq, mpc86xx_8259_cascade); | 80 | irq_set_chained_handler(cascade_irq, mpc86xx_8259_cascade); |
81 | #endif | 81 | #endif |
82 | } | 82 | } |
diff --git a/arch/powerpc/platforms/8xx/m8xx_setup.c b/arch/powerpc/platforms/8xx/m8xx_setup.c index fabb108e8744..9ecce995dd4b 100644 --- a/arch/powerpc/platforms/8xx/m8xx_setup.c +++ b/arch/powerpc/platforms/8xx/m8xx_setup.c | |||
@@ -226,11 +226,11 @@ static void cpm_cascade(unsigned int irq, struct irq_desc *desc) | |||
226 | 226 | ||
227 | generic_handle_irq(cascade_irq); | 227 | generic_handle_irq(cascade_irq); |
228 | 228 | ||
229 | chip = get_irq_desc_chip(cdesc); | 229 | chip = irq_desc_get_chip(cdesc); |
230 | chip->irq_eoi(&cdesc->irq_data); | 230 | chip->irq_eoi(&cdesc->irq_data); |
231 | } | 231 | } |
232 | 232 | ||
233 | chip = get_irq_desc_chip(desc); | 233 | chip = irq_desc_get_chip(desc); |
234 | chip->irq_eoi(&desc->irq_data); | 234 | chip->irq_eoi(&desc->irq_data); |
235 | } | 235 | } |
236 | 236 | ||
@@ -251,5 +251,5 @@ void __init mpc8xx_pics_init(void) | |||
251 | 251 | ||
252 | irq = cpm_pic_init(); | 252 | irq = cpm_pic_init(); |
253 | if (irq != NO_IRQ) | 253 | if (irq != NO_IRQ) |
254 | set_irq_chained_handler(irq, cpm_cascade); | 254 | irq_set_chained_handler(irq, cpm_cascade); |
255 | } | 255 | } |
diff --git a/arch/powerpc/platforms/cell/Kconfig b/arch/powerpc/platforms/cell/Kconfig index 48cd7d2e1b75..81239ebed83f 100644 --- a/arch/powerpc/platforms/cell/Kconfig +++ b/arch/powerpc/platforms/cell/Kconfig | |||
@@ -9,6 +9,7 @@ config PPC_CELL_COMMON | |||
9 | select PPC_INDIRECT_IO | 9 | select PPC_INDIRECT_IO |
10 | select PPC_NATIVE | 10 | select PPC_NATIVE |
11 | select PPC_RTAS | 11 | select PPC_RTAS |
12 | select IRQ_EDGE_EOI_HANDLER | ||
12 | 13 | ||
13 | config PPC_CELL_NATIVE | 14 | config PPC_CELL_NATIVE |
14 | bool | 15 | bool |
diff --git a/arch/powerpc/platforms/cell/axon_msi.c b/arch/powerpc/platforms/cell/axon_msi.c index c48b66a67e42..bb5ebf8fa80b 100644 --- a/arch/powerpc/platforms/cell/axon_msi.c +++ b/arch/powerpc/platforms/cell/axon_msi.c | |||
@@ -93,8 +93,8 @@ static void msic_dcr_write(struct axon_msic *msic, unsigned int dcr_n, u32 val) | |||
93 | 93 | ||
94 | static void axon_msi_cascade(unsigned int irq, struct irq_desc *desc) | 94 | static void axon_msi_cascade(unsigned int irq, struct irq_desc *desc) |
95 | { | 95 | { |
96 | struct irq_chip *chip = get_irq_desc_chip(desc); | 96 | struct irq_chip *chip = irq_desc_get_chip(desc); |
97 | struct axon_msic *msic = get_irq_data(irq); | 97 | struct axon_msic *msic = irq_get_handler_data(irq); |
98 | u32 write_offset, msi; | 98 | u32 write_offset, msi; |
99 | int idx; | 99 | int idx; |
100 | int retry = 0; | 100 | int retry = 0; |
@@ -287,7 +287,7 @@ static int axon_msi_setup_msi_irqs(struct pci_dev *dev, int nvec, int type) | |||
287 | } | 287 | } |
288 | dev_dbg(&dev->dev, "axon_msi: allocated virq 0x%x\n", virq); | 288 | dev_dbg(&dev->dev, "axon_msi: allocated virq 0x%x\n", virq); |
289 | 289 | ||
290 | set_irq_msi(virq, entry); | 290 | irq_set_msi_desc(virq, entry); |
291 | msg.data = virq; | 291 | msg.data = virq; |
292 | write_msi_msg(virq, &msg); | 292 | write_msi_msg(virq, &msg); |
293 | } | 293 | } |
@@ -305,7 +305,7 @@ static void axon_msi_teardown_msi_irqs(struct pci_dev *dev) | |||
305 | if (entry->irq == NO_IRQ) | 305 | if (entry->irq == NO_IRQ) |
306 | continue; | 306 | continue; |
307 | 307 | ||
308 | set_irq_msi(entry->irq, NULL); | 308 | irq_set_msi_desc(entry->irq, NULL); |
309 | irq_dispose_mapping(entry->irq); | 309 | irq_dispose_mapping(entry->irq); |
310 | } | 310 | } |
311 | } | 311 | } |
@@ -320,7 +320,7 @@ static struct irq_chip msic_irq_chip = { | |||
320 | static int msic_host_map(struct irq_host *h, unsigned int virq, | 320 | static int msic_host_map(struct irq_host *h, unsigned int virq, |
321 | irq_hw_number_t hw) | 321 | irq_hw_number_t hw) |
322 | { | 322 | { |
323 | set_irq_chip_and_handler(virq, &msic_irq_chip, handle_simple_irq); | 323 | irq_set_chip_and_handler(virq, &msic_irq_chip, handle_simple_irq); |
324 | 324 | ||
325 | return 0; | 325 | return 0; |
326 | } | 326 | } |
@@ -400,8 +400,8 @@ static int axon_msi_probe(struct platform_device *device) | |||
400 | 400 | ||
401 | msic->irq_host->host_data = msic; | 401 | msic->irq_host->host_data = msic; |
402 | 402 | ||
403 | set_irq_data(virq, msic); | 403 | irq_set_handler_data(virq, msic); |
404 | set_irq_chained_handler(virq, axon_msi_cascade); | 404 | irq_set_chained_handler(virq, axon_msi_cascade); |
405 | pr_devel("axon_msi: irq 0x%x setup for axon_msi\n", virq); | 405 | pr_devel("axon_msi: irq 0x%x setup for axon_msi\n", virq); |
406 | 406 | ||
407 | /* Enable the MSIC hardware */ | 407 | /* Enable the MSIC hardware */ |
diff --git a/arch/powerpc/platforms/cell/beat_interrupt.c b/arch/powerpc/platforms/cell/beat_interrupt.c index 0b8f7d7135c5..4cb9e147c307 100644 --- a/arch/powerpc/platforms/cell/beat_interrupt.c +++ b/arch/powerpc/platforms/cell/beat_interrupt.c | |||
@@ -136,15 +136,14 @@ static void beatic_pic_host_unmap(struct irq_host *h, unsigned int virq) | |||
136 | static int beatic_pic_host_map(struct irq_host *h, unsigned int virq, | 136 | static int beatic_pic_host_map(struct irq_host *h, unsigned int virq, |
137 | irq_hw_number_t hw) | 137 | irq_hw_number_t hw) |
138 | { | 138 | { |
139 | struct irq_desc *desc = irq_to_desc(virq); | ||
140 | int64_t err; | 139 | int64_t err; |
141 | 140 | ||
142 | err = beat_construct_and_connect_irq_plug(virq, hw); | 141 | err = beat_construct_and_connect_irq_plug(virq, hw); |
143 | if (err < 0) | 142 | if (err < 0) |
144 | return -EIO; | 143 | return -EIO; |
145 | 144 | ||
146 | desc->status |= IRQ_LEVEL; | 145 | irq_set_status_flags(virq, IRQ_LEVEL); |
147 | set_irq_chip_and_handler(virq, &beatic_pic, handle_fasteoi_irq); | 146 | irq_set_chip_and_handler(virq, &beatic_pic, handle_fasteoi_irq); |
148 | return 0; | 147 | return 0; |
149 | } | 148 | } |
150 | 149 | ||
diff --git a/arch/powerpc/platforms/cell/interrupt.c b/arch/powerpc/platforms/cell/interrupt.c index 624d26e72f1d..a19bec078703 100644 --- a/arch/powerpc/platforms/cell/interrupt.c +++ b/arch/powerpc/platforms/cell/interrupt.c | |||
@@ -101,9 +101,9 @@ static void iic_ioexc_eoi(struct irq_data *d) | |||
101 | 101 | ||
102 | static void iic_ioexc_cascade(unsigned int irq, struct irq_desc *desc) | 102 | static void iic_ioexc_cascade(unsigned int irq, struct irq_desc *desc) |
103 | { | 103 | { |
104 | struct irq_chip *chip = get_irq_desc_chip(desc); | 104 | struct irq_chip *chip = irq_desc_get_chip(desc); |
105 | struct cbe_iic_regs __iomem *node_iic = | 105 | struct cbe_iic_regs __iomem *node_iic = |
106 | (void __iomem *)get_irq_desc_data(desc); | 106 | (void __iomem *)irq_desc_get_handler_data(desc); |
107 | unsigned int base = (irq & 0xffffff00) | IIC_IRQ_TYPE_IOEXC; | 107 | unsigned int base = (irq & 0xffffff00) | IIC_IRQ_TYPE_IOEXC; |
108 | unsigned long bits, ack; | 108 | unsigned long bits, ack; |
109 | int cascade; | 109 | int cascade; |
@@ -235,67 +235,19 @@ static int iic_host_match(struct irq_host *h, struct device_node *node) | |||
235 | "IBM,CBEA-Internal-Interrupt-Controller"); | 235 | "IBM,CBEA-Internal-Interrupt-Controller"); |
236 | } | 236 | } |
237 | 237 | ||
238 | extern int noirqdebug; | ||
239 | |||
240 | static void handle_iic_irq(unsigned int irq, struct irq_desc *desc) | ||
241 | { | ||
242 | struct irq_chip *chip = get_irq_desc_chip(desc); | ||
243 | |||
244 | raw_spin_lock(&desc->lock); | ||
245 | |||
246 | desc->status &= ~(IRQ_REPLAY | IRQ_WAITING); | ||
247 | |||
248 | /* | ||
249 | * If we're currently running this IRQ, or its disabled, | ||
250 | * we shouldn't process the IRQ. Mark it pending, handle | ||
251 | * the necessary masking and go out | ||
252 | */ | ||
253 | if (unlikely((desc->status & (IRQ_INPROGRESS | IRQ_DISABLED)) || | ||
254 | !desc->action)) { | ||
255 | desc->status |= IRQ_PENDING; | ||
256 | goto out_eoi; | ||
257 | } | ||
258 | |||
259 | kstat_incr_irqs_this_cpu(irq, desc); | ||
260 | |||
261 | /* Mark the IRQ currently in progress.*/ | ||
262 | desc->status |= IRQ_INPROGRESS; | ||
263 | |||
264 | do { | ||
265 | struct irqaction *action = desc->action; | ||
266 | irqreturn_t action_ret; | ||
267 | |||
268 | if (unlikely(!action)) | ||
269 | goto out_eoi; | ||
270 | |||
271 | desc->status &= ~IRQ_PENDING; | ||
272 | raw_spin_unlock(&desc->lock); | ||
273 | action_ret = handle_IRQ_event(irq, action); | ||
274 | if (!noirqdebug) | ||
275 | note_interrupt(irq, desc, action_ret); | ||
276 | raw_spin_lock(&desc->lock); | ||
277 | |||
278 | } while ((desc->status & (IRQ_PENDING | IRQ_DISABLED)) == IRQ_PENDING); | ||
279 | |||
280 | desc->status &= ~IRQ_INPROGRESS; | ||
281 | out_eoi: | ||
282 | chip->irq_eoi(&desc->irq_data); | ||
283 | raw_spin_unlock(&desc->lock); | ||
284 | } | ||
285 | |||
286 | static int iic_host_map(struct irq_host *h, unsigned int virq, | 238 | static int iic_host_map(struct irq_host *h, unsigned int virq, |
287 | irq_hw_number_t hw) | 239 | irq_hw_number_t hw) |
288 | { | 240 | { |
289 | switch (hw & IIC_IRQ_TYPE_MASK) { | 241 | switch (hw & IIC_IRQ_TYPE_MASK) { |
290 | case IIC_IRQ_TYPE_IPI: | 242 | case IIC_IRQ_TYPE_IPI: |
291 | set_irq_chip_and_handler(virq, &iic_chip, handle_percpu_irq); | 243 | irq_set_chip_and_handler(virq, &iic_chip, handle_percpu_irq); |
292 | break; | 244 | break; |
293 | case IIC_IRQ_TYPE_IOEXC: | 245 | case IIC_IRQ_TYPE_IOEXC: |
294 | set_irq_chip_and_handler(virq, &iic_ioexc_chip, | 246 | irq_set_chip_and_handler(virq, &iic_ioexc_chip, |
295 | handle_iic_irq); | 247 | handle_iic_irq); |
296 | break; | 248 | break; |
297 | default: | 249 | default: |
298 | set_irq_chip_and_handler(virq, &iic_chip, handle_iic_irq); | 250 | irq_set_chip_and_handler(virq, &iic_chip, handle_edge_eoi_irq); |
299 | } | 251 | } |
300 | return 0; | 252 | return 0; |
301 | } | 253 | } |
@@ -412,8 +364,8 @@ static int __init setup_iic(void) | |||
412 | * irq_data is a generic pointer that gets passed back | 364 | * irq_data is a generic pointer that gets passed back |
413 | * to us later, so the forced cast is fine. | 365 | * to us later, so the forced cast is fine. |
414 | */ | 366 | */ |
415 | set_irq_data(cascade, (void __force *)node_iic); | 367 | irq_set_handler_data(cascade, (void __force *)node_iic); |
416 | set_irq_chained_handler(cascade , iic_ioexc_cascade); | 368 | irq_set_chained_handler(cascade, iic_ioexc_cascade); |
417 | out_be64(&node_iic->iic_ir, | 369 | out_be64(&node_iic->iic_ir, |
418 | (1 << 12) /* priority */ | | 370 | (1 << 12) /* priority */ | |
419 | (node << 4) /* dest node */ | | 371 | (node << 4) /* dest node */ | |
diff --git a/arch/powerpc/platforms/cell/setup.c b/arch/powerpc/platforms/cell/setup.c index 6a28d027d959..fd57bfe00edf 100644 --- a/arch/powerpc/platforms/cell/setup.c +++ b/arch/powerpc/platforms/cell/setup.c | |||
@@ -187,8 +187,8 @@ machine_subsys_initcall(cell, cell_publish_devices); | |||
187 | 187 | ||
188 | static void cell_mpic_cascade(unsigned int irq, struct irq_desc *desc) | 188 | static void cell_mpic_cascade(unsigned int irq, struct irq_desc *desc) |
189 | { | 189 | { |
190 | struct irq_chip *chip = get_irq_desc_chip(desc); | 190 | struct irq_chip *chip = irq_desc_get_chip(desc); |
191 | struct mpic *mpic = get_irq_desc_data(desc); | 191 | struct mpic *mpic = irq_desc_get_handler_data(desc); |
192 | unsigned int virq; | 192 | unsigned int virq; |
193 | 193 | ||
194 | virq = mpic_get_one_irq(mpic); | 194 | virq = mpic_get_one_irq(mpic); |
@@ -223,8 +223,8 @@ static void __init mpic_init_IRQ(void) | |||
223 | 223 | ||
224 | printk(KERN_INFO "%s : hooking up to IRQ %d\n", | 224 | printk(KERN_INFO "%s : hooking up to IRQ %d\n", |
225 | dn->full_name, virq); | 225 | dn->full_name, virq); |
226 | set_irq_data(virq, mpic); | 226 | irq_set_handler_data(virq, mpic); |
227 | set_irq_chained_handler(virq, cell_mpic_cascade); | 227 | irq_set_chained_handler(virq, cell_mpic_cascade); |
228 | } | 228 | } |
229 | } | 229 | } |
230 | 230 | ||
diff --git a/arch/powerpc/platforms/cell/spider-pic.c b/arch/powerpc/platforms/cell/spider-pic.c index b38cdfc1deb8..c5cf50e6b45a 100644 --- a/arch/powerpc/platforms/cell/spider-pic.c +++ b/arch/powerpc/platforms/cell/spider-pic.c | |||
@@ -102,7 +102,7 @@ static void spider_ack_irq(struct irq_data *d) | |||
102 | 102 | ||
103 | /* Reset edge detection logic if necessary | 103 | /* Reset edge detection logic if necessary |
104 | */ | 104 | */ |
105 | if (irq_to_desc(d->irq)->status & IRQ_LEVEL) | 105 | if (irqd_is_level_type(d)) |
106 | return; | 106 | return; |
107 | 107 | ||
108 | /* Only interrupts 47 to 50 can be set to edge */ | 108 | /* Only interrupts 47 to 50 can be set to edge */ |
@@ -119,7 +119,6 @@ static int spider_set_irq_type(struct irq_data *d, unsigned int type) | |||
119 | struct spider_pic *pic = spider_virq_to_pic(d->irq); | 119 | struct spider_pic *pic = spider_virq_to_pic(d->irq); |
120 | unsigned int hw = irq_map[d->irq].hwirq; | 120 | unsigned int hw = irq_map[d->irq].hwirq; |
121 | void __iomem *cfg = spider_get_irq_config(pic, hw); | 121 | void __iomem *cfg = spider_get_irq_config(pic, hw); |
122 | struct irq_desc *desc = irq_to_desc(d->irq); | ||
123 | u32 old_mask; | 122 | u32 old_mask; |
124 | u32 ic; | 123 | u32 ic; |
125 | 124 | ||
@@ -147,12 +146,6 @@ static int spider_set_irq_type(struct irq_data *d, unsigned int type) | |||
147 | return -EINVAL; | 146 | return -EINVAL; |
148 | } | 147 | } |
149 | 148 | ||
150 | /* Update irq_desc */ | ||
151 | desc->status &= ~(IRQ_TYPE_SENSE_MASK | IRQ_LEVEL); | ||
152 | desc->status |= type & IRQ_TYPE_SENSE_MASK; | ||
153 | if (type & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) | ||
154 | desc->status |= IRQ_LEVEL; | ||
155 | |||
156 | /* Configure the source. One gross hack that was there before and | 149 | /* Configure the source. One gross hack that was there before and |
157 | * that I've kept around is the priority to the BE which I set to | 150 | * that I've kept around is the priority to the BE which I set to |
158 | * be the same as the interrupt source number. I don't know wether | 151 | * be the same as the interrupt source number. I don't know wether |
@@ -178,10 +171,10 @@ static struct irq_chip spider_pic = { | |||
178 | static int spider_host_map(struct irq_host *h, unsigned int virq, | 171 | static int spider_host_map(struct irq_host *h, unsigned int virq, |
179 | irq_hw_number_t hw) | 172 | irq_hw_number_t hw) |
180 | { | 173 | { |
181 | set_irq_chip_and_handler(virq, &spider_pic, handle_level_irq); | 174 | irq_set_chip_and_handler(virq, &spider_pic, handle_level_irq); |
182 | 175 | ||
183 | /* Set default irq type */ | 176 | /* Set default irq type */ |
184 | set_irq_type(virq, IRQ_TYPE_NONE); | 177 | irq_set_irq_type(virq, IRQ_TYPE_NONE); |
185 | 178 | ||
186 | return 0; | 179 | return 0; |
187 | } | 180 | } |
@@ -207,8 +200,8 @@ static struct irq_host_ops spider_host_ops = { | |||
207 | 200 | ||
208 | static void spider_irq_cascade(unsigned int irq, struct irq_desc *desc) | 201 | static void spider_irq_cascade(unsigned int irq, struct irq_desc *desc) |
209 | { | 202 | { |
210 | struct irq_chip *chip = get_irq_desc_chip(desc); | 203 | struct irq_chip *chip = irq_desc_get_chip(desc); |
211 | struct spider_pic *pic = get_irq_desc_data(desc); | 204 | struct spider_pic *pic = irq_desc_get_handler_data(desc); |
212 | unsigned int cs, virq; | 205 | unsigned int cs, virq; |
213 | 206 | ||
214 | cs = in_be32(pic->regs + TIR_CS) >> 24; | 207 | cs = in_be32(pic->regs + TIR_CS) >> 24; |
@@ -328,8 +321,8 @@ static void __init spider_init_one(struct device_node *of_node, int chip, | |||
328 | virq = spider_find_cascade_and_node(pic); | 321 | virq = spider_find_cascade_and_node(pic); |
329 | if (virq == NO_IRQ) | 322 | if (virq == NO_IRQ) |
330 | return; | 323 | return; |
331 | set_irq_data(virq, pic); | 324 | irq_set_handler_data(virq, pic); |
332 | set_irq_chained_handler(virq, spider_irq_cascade); | 325 | irq_set_chained_handler(virq, spider_irq_cascade); |
333 | 326 | ||
334 | printk(KERN_INFO "spider_pic: node %d, addr: 0x%lx %s\n", | 327 | printk(KERN_INFO "spider_pic: node %d, addr: 0x%lx %s\n", |
335 | pic->node_id, addr, of_node->full_name); | 328 | pic->node_id, addr, of_node->full_name); |
diff --git a/arch/powerpc/platforms/chrp/setup.c b/arch/powerpc/platforms/chrp/setup.c index 4c1288451a21..122786498419 100644 --- a/arch/powerpc/platforms/chrp/setup.c +++ b/arch/powerpc/platforms/chrp/setup.c | |||
@@ -365,7 +365,7 @@ void __init chrp_setup_arch(void) | |||
365 | 365 | ||
366 | static void chrp_8259_cascade(unsigned int irq, struct irq_desc *desc) | 366 | static void chrp_8259_cascade(unsigned int irq, struct irq_desc *desc) |
367 | { | 367 | { |
368 | struct irq_chip *chip = get_irq_desc_chip(desc); | 368 | struct irq_chip *chip = irq_desc_get_chip(desc); |
369 | unsigned int cascade_irq = i8259_irq(); | 369 | unsigned int cascade_irq = i8259_irq(); |
370 | 370 | ||
371 | if (cascade_irq != NO_IRQ) | 371 | if (cascade_irq != NO_IRQ) |
@@ -517,7 +517,7 @@ static void __init chrp_find_8259(void) | |||
517 | if (cascade_irq == NO_IRQ) | 517 | if (cascade_irq == NO_IRQ) |
518 | printk(KERN_ERR "i8259: failed to map cascade irq\n"); | 518 | printk(KERN_ERR "i8259: failed to map cascade irq\n"); |
519 | else | 519 | else |
520 | set_irq_chained_handler(cascade_irq, | 520 | irq_set_chained_handler(cascade_irq, |
521 | chrp_8259_cascade); | 521 | chrp_8259_cascade); |
522 | } | 522 | } |
523 | } | 523 | } |
diff --git a/arch/powerpc/platforms/embedded6xx/flipper-pic.c b/arch/powerpc/platforms/embedded6xx/flipper-pic.c index 0aca0e28a8e5..12aa62b6f227 100644 --- a/arch/powerpc/platforms/embedded6xx/flipper-pic.c +++ b/arch/powerpc/platforms/embedded6xx/flipper-pic.c | |||
@@ -101,16 +101,16 @@ static struct irq_host *flipper_irq_host; | |||
101 | static int flipper_pic_map(struct irq_host *h, unsigned int virq, | 101 | static int flipper_pic_map(struct irq_host *h, unsigned int virq, |
102 | irq_hw_number_t hwirq) | 102 | irq_hw_number_t hwirq) |
103 | { | 103 | { |
104 | set_irq_chip_data(virq, h->host_data); | 104 | irq_set_chip_data(virq, h->host_data); |
105 | irq_to_desc(virq)->status |= IRQ_LEVEL; | 105 | irq_set_status_flags(virq, IRQ_LEVEL); |
106 | set_irq_chip_and_handler(virq, &flipper_pic, handle_level_irq); | 106 | irq_set_chip_and_handler(virq, &flipper_pic, handle_level_irq); |
107 | return 0; | 107 | return 0; |
108 | } | 108 | } |
109 | 109 | ||
110 | static void flipper_pic_unmap(struct irq_host *h, unsigned int irq) | 110 | static void flipper_pic_unmap(struct irq_host *h, unsigned int irq) |
111 | { | 111 | { |
112 | set_irq_chip_data(irq, NULL); | 112 | irq_set_chip_data(irq, NULL); |
113 | set_irq_chip(irq, NULL); | 113 | irq_set_chip(irq, NULL); |
114 | } | 114 | } |
115 | 115 | ||
116 | static int flipper_pic_match(struct irq_host *h, struct device_node *np) | 116 | static int flipper_pic_match(struct irq_host *h, struct device_node *np) |
diff --git a/arch/powerpc/platforms/embedded6xx/hlwd-pic.c b/arch/powerpc/platforms/embedded6xx/hlwd-pic.c index 35e448bd8479..2bdddfc9d520 100644 --- a/arch/powerpc/platforms/embedded6xx/hlwd-pic.c +++ b/arch/powerpc/platforms/embedded6xx/hlwd-pic.c | |||
@@ -94,16 +94,16 @@ static struct irq_host *hlwd_irq_host; | |||
94 | static int hlwd_pic_map(struct irq_host *h, unsigned int virq, | 94 | static int hlwd_pic_map(struct irq_host *h, unsigned int virq, |
95 | irq_hw_number_t hwirq) | 95 | irq_hw_number_t hwirq) |
96 | { | 96 | { |
97 | set_irq_chip_data(virq, h->host_data); | 97 | irq_set_chip_data(virq, h->host_data); |
98 | irq_to_desc(virq)->status |= IRQ_LEVEL; | 98 | irq_set_status_flags(virq, IRQ_LEVEL); |
99 | set_irq_chip_and_handler(virq, &hlwd_pic, handle_level_irq); | 99 | irq_set_chip_and_handler(virq, &hlwd_pic, handle_level_irq); |
100 | return 0; | 100 | return 0; |
101 | } | 101 | } |
102 | 102 | ||
103 | static void hlwd_pic_unmap(struct irq_host *h, unsigned int irq) | 103 | static void hlwd_pic_unmap(struct irq_host *h, unsigned int irq) |
104 | { | 104 | { |
105 | set_irq_chip_data(irq, NULL); | 105 | irq_set_chip_data(irq, NULL); |
106 | set_irq_chip(irq, NULL); | 106 | irq_set_chip(irq, NULL); |
107 | } | 107 | } |
108 | 108 | ||
109 | static struct irq_host_ops hlwd_irq_host_ops = { | 109 | static struct irq_host_ops hlwd_irq_host_ops = { |
@@ -129,8 +129,8 @@ static unsigned int __hlwd_pic_get_irq(struct irq_host *h) | |||
129 | static void hlwd_pic_irq_cascade(unsigned int cascade_virq, | 129 | static void hlwd_pic_irq_cascade(unsigned int cascade_virq, |
130 | struct irq_desc *desc) | 130 | struct irq_desc *desc) |
131 | { | 131 | { |
132 | struct irq_chip *chip = get_irq_desc_chip(desc); | 132 | struct irq_chip *chip = irq_desc_get_chip(desc); |
133 | struct irq_host *irq_host = get_irq_data(cascade_virq); | 133 | struct irq_host *irq_host = irq_get_handler_data(cascade_virq); |
134 | unsigned int virq; | 134 | unsigned int virq; |
135 | 135 | ||
136 | raw_spin_lock(&desc->lock); | 136 | raw_spin_lock(&desc->lock); |
@@ -145,7 +145,7 @@ static void hlwd_pic_irq_cascade(unsigned int cascade_virq, | |||
145 | 145 | ||
146 | raw_spin_lock(&desc->lock); | 146 | raw_spin_lock(&desc->lock); |
147 | chip->irq_ack(&desc->irq_data); /* IRQ_LEVEL */ | 147 | chip->irq_ack(&desc->irq_data); /* IRQ_LEVEL */ |
148 | if (!(desc->status & IRQ_DISABLED) && chip->irq_unmask) | 148 | if (!irqd_irq_disabled(&desc->irq_data) && chip->irq_unmask) |
149 | chip->irq_unmask(&desc->irq_data); | 149 | chip->irq_unmask(&desc->irq_data); |
150 | raw_spin_unlock(&desc->lock); | 150 | raw_spin_unlock(&desc->lock); |
151 | } | 151 | } |
@@ -218,8 +218,8 @@ void hlwd_pic_probe(void) | |||
218 | host = hlwd_pic_init(np); | 218 | host = hlwd_pic_init(np); |
219 | BUG_ON(!host); | 219 | BUG_ON(!host); |
220 | cascade_virq = irq_of_parse_and_map(np, 0); | 220 | cascade_virq = irq_of_parse_and_map(np, 0); |
221 | set_irq_data(cascade_virq, host); | 221 | irq_set_handler_data(cascade_virq, host); |
222 | set_irq_chained_handler(cascade_virq, | 222 | irq_set_chained_handler(cascade_virq, |
223 | hlwd_pic_irq_cascade); | 223 | hlwd_pic_irq_cascade); |
224 | hlwd_irq_host = host; | 224 | hlwd_irq_host = host; |
225 | break; | 225 | break; |
diff --git a/arch/powerpc/platforms/embedded6xx/holly.c b/arch/powerpc/platforms/embedded6xx/holly.c index b21fde589ca7..487bda0d18d8 100644 --- a/arch/powerpc/platforms/embedded6xx/holly.c +++ b/arch/powerpc/platforms/embedded6xx/holly.c | |||
@@ -198,8 +198,8 @@ static void __init holly_init_IRQ(void) | |||
198 | cascade_pci_irq = irq_of_parse_and_map(tsi_pci, 0); | 198 | cascade_pci_irq = irq_of_parse_and_map(tsi_pci, 0); |
199 | pr_debug("%s: tsi108 cascade_pci_irq = 0x%x\n", __func__, (u32) cascade_pci_irq); | 199 | pr_debug("%s: tsi108 cascade_pci_irq = 0x%x\n", __func__, (u32) cascade_pci_irq); |
200 | tsi108_pci_int_init(cascade_node); | 200 | tsi108_pci_int_init(cascade_node); |
201 | set_irq_data(cascade_pci_irq, mpic); | 201 | irq_set_handler_data(cascade_pci_irq, mpic); |
202 | set_irq_chained_handler(cascade_pci_irq, tsi108_irq_cascade); | 202 | irq_set_chained_handler(cascade_pci_irq, tsi108_irq_cascade); |
203 | #endif | 203 | #endif |
204 | /* Configure MPIC outputs to CPU0 */ | 204 | /* Configure MPIC outputs to CPU0 */ |
205 | tsi108_write_reg(TSI108_MPIC_OFFSET + 0x30c, 0); | 205 | tsi108_write_reg(TSI108_MPIC_OFFSET + 0x30c, 0); |
diff --git a/arch/powerpc/platforms/embedded6xx/mpc7448_hpc2.c b/arch/powerpc/platforms/embedded6xx/mpc7448_hpc2.c index 7a2ba39d7811..1cb907c94359 100644 --- a/arch/powerpc/platforms/embedded6xx/mpc7448_hpc2.c +++ b/arch/powerpc/platforms/embedded6xx/mpc7448_hpc2.c | |||
@@ -153,8 +153,8 @@ static void __init mpc7448_hpc2_init_IRQ(void) | |||
153 | DBG("%s: tsi108 cascade_pci_irq = 0x%x\n", __func__, | 153 | DBG("%s: tsi108 cascade_pci_irq = 0x%x\n", __func__, |
154 | (u32) cascade_pci_irq); | 154 | (u32) cascade_pci_irq); |
155 | tsi108_pci_int_init(cascade_node); | 155 | tsi108_pci_int_init(cascade_node); |
156 | set_irq_data(cascade_pci_irq, mpic); | 156 | irq_set_handler_data(cascade_pci_irq, mpic); |
157 | set_irq_chained_handler(cascade_pci_irq, tsi108_irq_cascade); | 157 | irq_set_chained_handler(cascade_pci_irq, tsi108_irq_cascade); |
158 | #endif | 158 | #endif |
159 | /* Configure MPIC outputs to CPU0 */ | 159 | /* Configure MPIC outputs to CPU0 */ |
160 | tsi108_write_reg(TSI108_MPIC_OFFSET + 0x30c, 0); | 160 | tsi108_write_reg(TSI108_MPIC_OFFSET + 0x30c, 0); |
diff --git a/arch/powerpc/platforms/iseries/irq.c b/arch/powerpc/platforms/iseries/irq.c index 4fb96f0b2df6..52a6889832c7 100644 --- a/arch/powerpc/platforms/iseries/irq.c +++ b/arch/powerpc/platforms/iseries/irq.c | |||
@@ -220,7 +220,7 @@ void __init iSeries_activate_IRQs() | |||
220 | if (!desc) | 220 | if (!desc) |
221 | continue; | 221 | continue; |
222 | 222 | ||
223 | chip = get_irq_desc_chip(desc); | 223 | chip = irq_desc_get_chip(desc); |
224 | if (chip && chip->irq_startup) { | 224 | if (chip && chip->irq_startup) { |
225 | raw_spin_lock_irqsave(&desc->lock, flags); | 225 | raw_spin_lock_irqsave(&desc->lock, flags); |
226 | chip->irq_startup(&desc->irq_data); | 226 | chip->irq_startup(&desc->irq_data); |
@@ -346,7 +346,7 @@ unsigned int iSeries_get_irq(void) | |||
346 | static int iseries_irq_host_map(struct irq_host *h, unsigned int virq, | 346 | static int iseries_irq_host_map(struct irq_host *h, unsigned int virq, |
347 | irq_hw_number_t hw) | 347 | irq_hw_number_t hw) |
348 | { | 348 | { |
349 | set_irq_chip_and_handler(virq, &iseries_pic, handle_fasteoi_irq); | 349 | irq_set_chip_and_handler(virq, &iseries_pic, handle_fasteoi_irq); |
350 | 350 | ||
351 | return 0; | 351 | return 0; |
352 | } | 352 | } |
diff --git a/arch/powerpc/platforms/maple/pci.c b/arch/powerpc/platforms/maple/pci.c index 04296ffff8bf..dd2e48b28508 100644 --- a/arch/powerpc/platforms/maple/pci.c +++ b/arch/powerpc/platforms/maple/pci.c | |||
@@ -498,7 +498,7 @@ void __devinit maple_pci_irq_fixup(struct pci_dev *dev) | |||
498 | printk(KERN_DEBUG "Fixup U4 PCIe IRQ\n"); | 498 | printk(KERN_DEBUG "Fixup U4 PCIe IRQ\n"); |
499 | dev->irq = irq_create_mapping(NULL, 1); | 499 | dev->irq = irq_create_mapping(NULL, 1); |
500 | if (dev->irq != NO_IRQ) | 500 | if (dev->irq != NO_IRQ) |
501 | set_irq_type(dev->irq, IRQ_TYPE_LEVEL_LOW); | 501 | irq_set_irq_type(dev->irq, IRQ_TYPE_LEVEL_LOW); |
502 | } | 502 | } |
503 | 503 | ||
504 | /* Hide AMD8111 IDE interrupt when in legacy mode so | 504 | /* Hide AMD8111 IDE interrupt when in legacy mode so |
diff --git a/arch/powerpc/platforms/pasemi/setup.c b/arch/powerpc/platforms/pasemi/setup.c index a6067b38d2ca..7c858e6f843c 100644 --- a/arch/powerpc/platforms/pasemi/setup.c +++ b/arch/powerpc/platforms/pasemi/setup.c | |||
@@ -239,7 +239,7 @@ static __init void pas_init_IRQ(void) | |||
239 | if (nmiprop) { | 239 | if (nmiprop) { |
240 | nmi_virq = irq_create_mapping(NULL, *nmiprop); | 240 | nmi_virq = irq_create_mapping(NULL, *nmiprop); |
241 | mpic_irq_set_priority(nmi_virq, 15); | 241 | mpic_irq_set_priority(nmi_virq, 15); |
242 | set_irq_type(nmi_virq, IRQ_TYPE_EDGE_RISING); | 242 | irq_set_irq_type(nmi_virq, IRQ_TYPE_EDGE_RISING); |
243 | mpic_unmask_irq(irq_get_irq_data(nmi_virq)); | 243 | mpic_unmask_irq(irq_get_irq_data(nmi_virq)); |
244 | } | 244 | } |
245 | 245 | ||
diff --git a/arch/powerpc/platforms/powermac/pci.c b/arch/powerpc/platforms/powermac/pci.c index 3bc075c788ef..ab6898942700 100644 --- a/arch/powerpc/platforms/powermac/pci.c +++ b/arch/powerpc/platforms/powermac/pci.c | |||
@@ -988,7 +988,7 @@ void __devinit pmac_pci_irq_fixup(struct pci_dev *dev) | |||
988 | dev->vendor == PCI_VENDOR_ID_DEC && | 988 | dev->vendor == PCI_VENDOR_ID_DEC && |
989 | dev->device == PCI_DEVICE_ID_DEC_TULIP_PLUS) { | 989 | dev->device == PCI_DEVICE_ID_DEC_TULIP_PLUS) { |
990 | dev->irq = irq_create_mapping(NULL, 60); | 990 | dev->irq = irq_create_mapping(NULL, 60); |
991 | set_irq_type(dev->irq, IRQ_TYPE_LEVEL_LOW); | 991 | irq_set_irq_type(dev->irq, IRQ_TYPE_LEVEL_LOW); |
992 | } | 992 | } |
993 | #endif /* CONFIG_PPC32 */ | 993 | #endif /* CONFIG_PPC32 */ |
994 | } | 994 | } |
diff --git a/arch/powerpc/platforms/powermac/pic.c b/arch/powerpc/platforms/powermac/pic.c index c55812bb6a51..023f24086a0a 100644 --- a/arch/powerpc/platforms/powermac/pic.c +++ b/arch/powerpc/platforms/powermac/pic.c | |||
@@ -157,7 +157,7 @@ static unsigned int pmac_startup_irq(struct irq_data *d) | |||
157 | int i = src >> 5; | 157 | int i = src >> 5; |
158 | 158 | ||
159 | raw_spin_lock_irqsave(&pmac_pic_lock, flags); | 159 | raw_spin_lock_irqsave(&pmac_pic_lock, flags); |
160 | if ((irq_to_desc(d->irq)->status & IRQ_LEVEL) == 0) | 160 | if (!irqd_is_level_type(d)) |
161 | out_le32(&pmac_irq_hw[i]->ack, bit); | 161 | out_le32(&pmac_irq_hw[i]->ack, bit); |
162 | __set_bit(src, ppc_cached_irq_mask); | 162 | __set_bit(src, ppc_cached_irq_mask); |
163 | __pmac_set_irq_mask(src, 0); | 163 | __pmac_set_irq_mask(src, 0); |
@@ -289,7 +289,6 @@ static int pmac_pic_host_match(struct irq_host *h, struct device_node *node) | |||
289 | static int pmac_pic_host_map(struct irq_host *h, unsigned int virq, | 289 | static int pmac_pic_host_map(struct irq_host *h, unsigned int virq, |
290 | irq_hw_number_t hw) | 290 | irq_hw_number_t hw) |
291 | { | 291 | { |
292 | struct irq_desc *desc = irq_to_desc(virq); | ||
293 | int level; | 292 | int level; |
294 | 293 | ||
295 | if (hw >= max_irqs) | 294 | if (hw >= max_irqs) |
@@ -300,9 +299,9 @@ static int pmac_pic_host_map(struct irq_host *h, unsigned int virq, | |||
300 | */ | 299 | */ |
301 | level = !!(level_mask[hw >> 5] & (1UL << (hw & 0x1f))); | 300 | level = !!(level_mask[hw >> 5] & (1UL << (hw & 0x1f))); |
302 | if (level) | 301 | if (level) |
303 | desc->status |= IRQ_LEVEL; | 302 | irq_set_status_flags(virq, IRQ_LEVEL); |
304 | set_irq_chip_and_handler(virq, &pmac_pic, level ? | 303 | irq_set_chip_and_handler(virq, &pmac_pic, |
305 | handle_level_irq : handle_edge_irq); | 304 | level ? handle_level_irq : handle_edge_irq); |
306 | return 0; | 305 | return 0; |
307 | } | 306 | } |
308 | 307 | ||
@@ -472,8 +471,8 @@ int of_irq_map_oldworld(struct device_node *device, int index, | |||
472 | 471 | ||
473 | static void pmac_u3_cascade(unsigned int irq, struct irq_desc *desc) | 472 | static void pmac_u3_cascade(unsigned int irq, struct irq_desc *desc) |
474 | { | 473 | { |
475 | struct irq_chip *chip = get_irq_desc_chip(desc); | 474 | struct irq_chip *chip = irq_desc_get_chip(desc); |
476 | struct mpic *mpic = get_irq_desc_data(desc); | 475 | struct mpic *mpic = irq_desc_get_handler_data(desc); |
477 | unsigned int cascade_irq = mpic_get_one_irq(mpic); | 476 | unsigned int cascade_irq = mpic_get_one_irq(mpic); |
478 | 477 | ||
479 | if (cascade_irq != NO_IRQ) | 478 | if (cascade_irq != NO_IRQ) |
@@ -591,8 +590,8 @@ static int __init pmac_pic_probe_mpic(void) | |||
591 | of_node_put(slave); | 590 | of_node_put(slave); |
592 | return 0; | 591 | return 0; |
593 | } | 592 | } |
594 | set_irq_data(cascade, mpic2); | 593 | irq_set_handler_data(cascade, mpic2); |
595 | set_irq_chained_handler(cascade, pmac_u3_cascade); | 594 | irq_set_chained_handler(cascade, pmac_u3_cascade); |
596 | 595 | ||
597 | of_node_put(slave); | 596 | of_node_put(slave); |
598 | return 0; | 597 | return 0; |
diff --git a/arch/powerpc/platforms/ps3/interrupt.c b/arch/powerpc/platforms/ps3/interrupt.c index 3988c86682a5..f2f6413b81d3 100644 --- a/arch/powerpc/platforms/ps3/interrupt.c +++ b/arch/powerpc/platforms/ps3/interrupt.c | |||
@@ -194,7 +194,7 @@ static int ps3_virq_setup(enum ps3_cpu_binding cpu, unsigned long outlet, | |||
194 | pr_debug("%s:%d: outlet %lu => cpu %u, virq %u\n", __func__, __LINE__, | 194 | pr_debug("%s:%d: outlet %lu => cpu %u, virq %u\n", __func__, __LINE__, |
195 | outlet, cpu, *virq); | 195 | outlet, cpu, *virq); |
196 | 196 | ||
197 | result = set_irq_chip_data(*virq, pd); | 197 | result = irq_set_chip_data(*virq, pd); |
198 | 198 | ||
199 | if (result) { | 199 | if (result) { |
200 | pr_debug("%s:%d: set_irq_chip_data failed\n", | 200 | pr_debug("%s:%d: set_irq_chip_data failed\n", |
@@ -221,12 +221,12 @@ fail_create: | |||
221 | 221 | ||
222 | static int ps3_virq_destroy(unsigned int virq) | 222 | static int ps3_virq_destroy(unsigned int virq) |
223 | { | 223 | { |
224 | const struct ps3_private *pd = get_irq_chip_data(virq); | 224 | const struct ps3_private *pd = irq_get_chip_data(virq); |
225 | 225 | ||
226 | pr_debug("%s:%d: ppe_id %llu, thread_id %llu, virq %u\n", __func__, | 226 | pr_debug("%s:%d: ppe_id %llu, thread_id %llu, virq %u\n", __func__, |
227 | __LINE__, pd->ppe_id, pd->thread_id, virq); | 227 | __LINE__, pd->ppe_id, pd->thread_id, virq); |
228 | 228 | ||
229 | set_irq_chip_data(virq, NULL); | 229 | irq_set_chip_data(virq, NULL); |
230 | irq_dispose_mapping(virq); | 230 | irq_dispose_mapping(virq); |
231 | 231 | ||
232 | pr_debug("%s:%d <-\n", __func__, __LINE__); | 232 | pr_debug("%s:%d <-\n", __func__, __LINE__); |
@@ -256,7 +256,7 @@ int ps3_irq_plug_setup(enum ps3_cpu_binding cpu, unsigned long outlet, | |||
256 | goto fail_setup; | 256 | goto fail_setup; |
257 | } | 257 | } |
258 | 258 | ||
259 | pd = get_irq_chip_data(*virq); | 259 | pd = irq_get_chip_data(*virq); |
260 | 260 | ||
261 | /* Binds outlet to cpu + virq. */ | 261 | /* Binds outlet to cpu + virq. */ |
262 | 262 | ||
@@ -291,7 +291,7 @@ EXPORT_SYMBOL_GPL(ps3_irq_plug_setup); | |||
291 | int ps3_irq_plug_destroy(unsigned int virq) | 291 | int ps3_irq_plug_destroy(unsigned int virq) |
292 | { | 292 | { |
293 | int result; | 293 | int result; |
294 | const struct ps3_private *pd = get_irq_chip_data(virq); | 294 | const struct ps3_private *pd = irq_get_chip_data(virq); |
295 | 295 | ||
296 | pr_debug("%s:%d: ppe_id %llu, thread_id %llu, virq %u\n", __func__, | 296 | pr_debug("%s:%d: ppe_id %llu, thread_id %llu, virq %u\n", __func__, |
297 | __LINE__, pd->ppe_id, pd->thread_id, virq); | 297 | __LINE__, pd->ppe_id, pd->thread_id, virq); |
@@ -661,7 +661,7 @@ static void dump_bmp(struct ps3_private* pd) {}; | |||
661 | 661 | ||
662 | static void ps3_host_unmap(struct irq_host *h, unsigned int virq) | 662 | static void ps3_host_unmap(struct irq_host *h, unsigned int virq) |
663 | { | 663 | { |
664 | set_irq_chip_data(virq, NULL); | 664 | irq_set_chip_data(virq, NULL); |
665 | } | 665 | } |
666 | 666 | ||
667 | static int ps3_host_map(struct irq_host *h, unsigned int virq, | 667 | static int ps3_host_map(struct irq_host *h, unsigned int virq, |
@@ -670,7 +670,7 @@ static int ps3_host_map(struct irq_host *h, unsigned int virq, | |||
670 | pr_debug("%s:%d: hwirq %lu, virq %u\n", __func__, __LINE__, hwirq, | 670 | pr_debug("%s:%d: hwirq %lu, virq %u\n", __func__, __LINE__, hwirq, |
671 | virq); | 671 | virq); |
672 | 672 | ||
673 | set_irq_chip_and_handler(virq, &ps3_irq_chip, handle_fasteoi_irq); | 673 | irq_set_chip_and_handler(virq, &ps3_irq_chip, handle_fasteoi_irq); |
674 | 674 | ||
675 | return 0; | 675 | return 0; |
676 | } | 676 | } |
diff --git a/arch/powerpc/platforms/pseries/msi.c b/arch/powerpc/platforms/pseries/msi.c index 18ac801f8e90..38d24e7e7bb1 100644 --- a/arch/powerpc/platforms/pseries/msi.c +++ b/arch/powerpc/platforms/pseries/msi.c | |||
@@ -137,7 +137,7 @@ static void rtas_teardown_msi_irqs(struct pci_dev *pdev) | |||
137 | if (entry->irq == NO_IRQ) | 137 | if (entry->irq == NO_IRQ) |
138 | continue; | 138 | continue; |
139 | 139 | ||
140 | set_irq_msi(entry->irq, NULL); | 140 | irq_set_msi_desc(entry->irq, NULL); |
141 | irq_dispose_mapping(entry->irq); | 141 | irq_dispose_mapping(entry->irq); |
142 | } | 142 | } |
143 | 143 | ||
@@ -437,7 +437,7 @@ static int rtas_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type) | |||
437 | } | 437 | } |
438 | 438 | ||
439 | dev_dbg(&pdev->dev, "rtas_msi: allocated virq %d\n", virq); | 439 | dev_dbg(&pdev->dev, "rtas_msi: allocated virq %d\n", virq); |
440 | set_irq_msi(virq, entry); | 440 | irq_set_msi_desc(virq, entry); |
441 | 441 | ||
442 | /* Read config space back so we can restore after reset */ | 442 | /* Read config space back so we can restore after reset */ |
443 | read_msi_msg(virq, &msg); | 443 | read_msi_msg(virq, &msg); |
diff --git a/arch/powerpc/platforms/pseries/setup.c b/arch/powerpc/platforms/pseries/setup.c index 2a0089a2c829..c319d04aa799 100644 --- a/arch/powerpc/platforms/pseries/setup.c +++ b/arch/powerpc/platforms/pseries/setup.c | |||
@@ -114,7 +114,7 @@ static void __init fwnmi_init(void) | |||
114 | 114 | ||
115 | static void pseries_8259_cascade(unsigned int irq, struct irq_desc *desc) | 115 | static void pseries_8259_cascade(unsigned int irq, struct irq_desc *desc) |
116 | { | 116 | { |
117 | struct irq_chip *chip = get_irq_desc_chip(desc); | 117 | struct irq_chip *chip = irq_desc_get_chip(desc); |
118 | unsigned int cascade_irq = i8259_irq(); | 118 | unsigned int cascade_irq = i8259_irq(); |
119 | 119 | ||
120 | if (cascade_irq != NO_IRQ) | 120 | if (cascade_irq != NO_IRQ) |
@@ -169,7 +169,7 @@ static void __init pseries_setup_i8259_cascade(void) | |||
169 | printk(KERN_DEBUG "pic: PCI 8259 intack at 0x%016lx\n", intack); | 169 | printk(KERN_DEBUG "pic: PCI 8259 intack at 0x%016lx\n", intack); |
170 | i8259_init(found, intack); | 170 | i8259_init(found, intack); |
171 | of_node_put(found); | 171 | of_node_put(found); |
172 | set_irq_chained_handler(cascade, pseries_8259_cascade); | 172 | irq_set_chained_handler(cascade, pseries_8259_cascade); |
173 | } | 173 | } |
174 | 174 | ||
175 | static void __init pseries_mpic_init_IRQ(void) | 175 | static void __init pseries_mpic_init_IRQ(void) |
diff --git a/arch/powerpc/platforms/pseries/xics.c b/arch/powerpc/platforms/pseries/xics.c index 01fea46c0335..6c1e638f0ce9 100644 --- a/arch/powerpc/platforms/pseries/xics.c +++ b/arch/powerpc/platforms/pseries/xics.c | |||
@@ -470,8 +470,8 @@ static int xics_host_map(struct irq_host *h, unsigned int virq, | |||
470 | /* Insert the interrupt mapping into the radix tree for fast lookup */ | 470 | /* Insert the interrupt mapping into the radix tree for fast lookup */ |
471 | irq_radix_revmap_insert(xics_host, virq, hw); | 471 | irq_radix_revmap_insert(xics_host, virq, hw); |
472 | 472 | ||
473 | irq_to_desc(virq)->status |= IRQ_LEVEL; | 473 | irq_set_status_flags(virq, IRQ_LEVEL); |
474 | set_irq_chip_and_handler(virq, xics_irq_chip, handle_fasteoi_irq); | 474 | irq_set_chip_and_handler(virq, xics_irq_chip, handle_fasteoi_irq); |
475 | return 0; | 475 | return 0; |
476 | } | 476 | } |
477 | 477 | ||
@@ -600,7 +600,7 @@ static void xics_request_ipi(void) | |||
600 | * IPIs are marked IRQF_DISABLED as they must run with irqs | 600 | * IPIs are marked IRQF_DISABLED as they must run with irqs |
601 | * disabled | 601 | * disabled |
602 | */ | 602 | */ |
603 | set_irq_handler(ipi, handle_percpu_irq); | 603 | irq_set_handler(ipi, handle_percpu_irq); |
604 | if (firmware_has_feature(FW_FEATURE_LPAR)) | 604 | if (firmware_has_feature(FW_FEATURE_LPAR)) |
605 | rc = request_irq(ipi, xics_ipi_action_lpar, | 605 | rc = request_irq(ipi, xics_ipi_action_lpar, |
606 | IRQF_DISABLED|IRQF_PERCPU, "IPI", NULL); | 606 | IRQF_DISABLED|IRQF_PERCPU, "IPI", NULL); |
@@ -912,7 +912,7 @@ void xics_migrate_irqs_away(void) | |||
912 | if (desc == NULL || desc->action == NULL) | 912 | if (desc == NULL || desc->action == NULL) |
913 | continue; | 913 | continue; |
914 | 914 | ||
915 | chip = get_irq_desc_chip(desc); | 915 | chip = irq_desc_get_chip(desc); |
916 | if (chip == NULL || chip->irq_set_affinity == NULL) | 916 | if (chip == NULL || chip->irq_set_affinity == NULL) |
917 | continue; | 917 | continue; |
918 | 918 | ||
diff --git a/arch/powerpc/sysdev/Makefile b/arch/powerpc/sysdev/Makefile index 9c2973479142..1e0c933ef772 100644 --- a/arch/powerpc/sysdev/Makefile +++ b/arch/powerpc/sysdev/Makefile | |||
@@ -20,7 +20,7 @@ obj-$(CONFIG_FSL_GTM) += fsl_gtm.o | |||
20 | obj-$(CONFIG_MPC8xxx_GPIO) += mpc8xxx_gpio.o | 20 | obj-$(CONFIG_MPC8xxx_GPIO) += mpc8xxx_gpio.o |
21 | obj-$(CONFIG_FSL_85XX_CACHE_SRAM) += fsl_85xx_l2ctlr.o fsl_85xx_cache_sram.o | 21 | obj-$(CONFIG_FSL_85XX_CACHE_SRAM) += fsl_85xx_l2ctlr.o fsl_85xx_cache_sram.o |
22 | obj-$(CONFIG_SIMPLE_GPIO) += simple_gpio.o | 22 | obj-$(CONFIG_SIMPLE_GPIO) += simple_gpio.o |
23 | obj-$(CONFIG_RAPIDIO) += fsl_rio.o | 23 | obj-$(CONFIG_FSL_RIO) += fsl_rio.o |
24 | obj-$(CONFIG_TSI108_BRIDGE) += tsi108_pci.o tsi108_dev.o | 24 | obj-$(CONFIG_TSI108_BRIDGE) += tsi108_pci.o tsi108_dev.o |
25 | obj-$(CONFIG_QUICC_ENGINE) += qe_lib/ | 25 | obj-$(CONFIG_QUICC_ENGINE) += qe_lib/ |
26 | obj-$(CONFIG_PPC_BESTCOMM) += bestcomm/ | 26 | obj-$(CONFIG_PPC_BESTCOMM) += bestcomm/ |
diff --git a/arch/powerpc/sysdev/cpm1.c b/arch/powerpc/sysdev/cpm1.c index 0476bcc7c3e1..8b5aba263323 100644 --- a/arch/powerpc/sysdev/cpm1.c +++ b/arch/powerpc/sysdev/cpm1.c | |||
@@ -103,8 +103,8 @@ static int cpm_pic_host_map(struct irq_host *h, unsigned int virq, | |||
103 | { | 103 | { |
104 | pr_debug("cpm_pic_host_map(%d, 0x%lx)\n", virq, hw); | 104 | pr_debug("cpm_pic_host_map(%d, 0x%lx)\n", virq, hw); |
105 | 105 | ||
106 | irq_to_desc(virq)->status |= IRQ_LEVEL; | 106 | irq_set_status_flags(virq, IRQ_LEVEL); |
107 | set_irq_chip_and_handler(virq, &cpm_pic, handle_fasteoi_irq); | 107 | irq_set_chip_and_handler(virq, &cpm_pic, handle_fasteoi_irq); |
108 | return 0; | 108 | return 0; |
109 | } | 109 | } |
110 | 110 | ||
diff --git a/arch/powerpc/sysdev/cpm2_pic.c b/arch/powerpc/sysdev/cpm2_pic.c index 473032556715..5495c1be472b 100644 --- a/arch/powerpc/sysdev/cpm2_pic.c +++ b/arch/powerpc/sysdev/cpm2_pic.c | |||
@@ -115,32 +115,25 @@ static void cpm2_ack(struct irq_data *d) | |||
115 | 115 | ||
116 | static void cpm2_end_irq(struct irq_data *d) | 116 | static void cpm2_end_irq(struct irq_data *d) |
117 | { | 117 | { |
118 | struct irq_desc *desc; | ||
119 | int bit, word; | 118 | int bit, word; |
120 | unsigned int irq_nr = virq_to_hw(d->irq); | 119 | unsigned int irq_nr = virq_to_hw(d->irq); |
121 | 120 | ||
122 | desc = irq_to_desc(irq_nr); | 121 | bit = irq_to_siubit[irq_nr]; |
123 | if (!(desc->status & (IRQ_DISABLED|IRQ_INPROGRESS)) | 122 | word = irq_to_siureg[irq_nr]; |
124 | && desc->action) { | ||
125 | |||
126 | bit = irq_to_siubit[irq_nr]; | ||
127 | word = irq_to_siureg[irq_nr]; | ||
128 | 123 | ||
129 | ppc_cached_irq_mask[word] |= 1 << bit; | 124 | ppc_cached_irq_mask[word] |= 1 << bit; |
130 | out_be32(&cpm2_intctl->ic_simrh + word, ppc_cached_irq_mask[word]); | 125 | out_be32(&cpm2_intctl->ic_simrh + word, ppc_cached_irq_mask[word]); |
131 | 126 | ||
132 | /* | 127 | /* |
133 | * Work around large numbers of spurious IRQs on PowerPC 82xx | 128 | * Work around large numbers of spurious IRQs on PowerPC 82xx |
134 | * systems. | 129 | * systems. |
135 | */ | 130 | */ |
136 | mb(); | 131 | mb(); |
137 | } | ||
138 | } | 132 | } |
139 | 133 | ||
140 | static int cpm2_set_irq_type(struct irq_data *d, unsigned int flow_type) | 134 | static int cpm2_set_irq_type(struct irq_data *d, unsigned int flow_type) |
141 | { | 135 | { |
142 | unsigned int src = virq_to_hw(d->irq); | 136 | unsigned int src = virq_to_hw(d->irq); |
143 | struct irq_desc *desc = irq_to_desc(d->irq); | ||
144 | unsigned int vold, vnew, edibit; | 137 | unsigned int vold, vnew, edibit; |
145 | 138 | ||
146 | /* Port C interrupts are either IRQ_TYPE_EDGE_FALLING or | 139 | /* Port C interrupts are either IRQ_TYPE_EDGE_FALLING or |
@@ -162,13 +155,11 @@ static int cpm2_set_irq_type(struct irq_data *d, unsigned int flow_type) | |||
162 | goto err_sense; | 155 | goto err_sense; |
163 | } | 156 | } |
164 | 157 | ||
165 | desc->status &= ~(IRQ_TYPE_SENSE_MASK | IRQ_LEVEL); | 158 | irqd_set_trigger_type(d, flow_type); |
166 | desc->status |= flow_type & IRQ_TYPE_SENSE_MASK; | 159 | if (flow_type & IRQ_TYPE_LEVEL_LOW) |
167 | if (flow_type & IRQ_TYPE_LEVEL_LOW) { | 160 | __irq_set_handler_locked(d->irq, handle_level_irq); |
168 | desc->status |= IRQ_LEVEL; | 161 | else |
169 | desc->handle_irq = handle_level_irq; | 162 | __irq_set_handler_locked(d->irq, handle_edge_irq); |
170 | } else | ||
171 | desc->handle_irq = handle_edge_irq; | ||
172 | 163 | ||
173 | /* internal IRQ senses are LEVEL_LOW | 164 | /* internal IRQ senses are LEVEL_LOW |
174 | * EXT IRQ and Port C IRQ senses are programmable | 165 | * EXT IRQ and Port C IRQ senses are programmable |
@@ -179,7 +170,8 @@ static int cpm2_set_irq_type(struct irq_data *d, unsigned int flow_type) | |||
179 | if (src >= CPM2_IRQ_PORTC15 && src <= CPM2_IRQ_PORTC0) | 170 | if (src >= CPM2_IRQ_PORTC15 && src <= CPM2_IRQ_PORTC0) |
180 | edibit = (31 - (CPM2_IRQ_PORTC0 - src)); | 171 | edibit = (31 - (CPM2_IRQ_PORTC0 - src)); |
181 | else | 172 | else |
182 | return (flow_type & IRQ_TYPE_LEVEL_LOW) ? 0 : -EINVAL; | 173 | return (flow_type & IRQ_TYPE_LEVEL_LOW) ? |
174 | IRQ_SET_MASK_OK_NOCOPY : -EINVAL; | ||
183 | 175 | ||
184 | vold = in_be32(&cpm2_intctl->ic_siexr); | 176 | vold = in_be32(&cpm2_intctl->ic_siexr); |
185 | 177 | ||
@@ -190,7 +182,7 @@ static int cpm2_set_irq_type(struct irq_data *d, unsigned int flow_type) | |||
190 | 182 | ||
191 | if (vold != vnew) | 183 | if (vold != vnew) |
192 | out_be32(&cpm2_intctl->ic_siexr, vnew); | 184 | out_be32(&cpm2_intctl->ic_siexr, vnew); |
193 | return 0; | 185 | return IRQ_SET_MASK_OK_NOCOPY; |
194 | 186 | ||
195 | err_sense: | 187 | err_sense: |
196 | pr_err("CPM2 PIC: sense type 0x%x not supported\n", flow_type); | 188 | pr_err("CPM2 PIC: sense type 0x%x not supported\n", flow_type); |
@@ -204,6 +196,7 @@ static struct irq_chip cpm2_pic = { | |||
204 | .irq_ack = cpm2_ack, | 196 | .irq_ack = cpm2_ack, |
205 | .irq_eoi = cpm2_end_irq, | 197 | .irq_eoi = cpm2_end_irq, |
206 | .irq_set_type = cpm2_set_irq_type, | 198 | .irq_set_type = cpm2_set_irq_type, |
199 | .flags = IRQCHIP_EOI_IF_HANDLED, | ||
207 | }; | 200 | }; |
208 | 201 | ||
209 | unsigned int cpm2_get_irq(void) | 202 | unsigned int cpm2_get_irq(void) |
@@ -226,8 +219,8 @@ static int cpm2_pic_host_map(struct irq_host *h, unsigned int virq, | |||
226 | { | 219 | { |
227 | pr_debug("cpm2_pic_host_map(%d, 0x%lx)\n", virq, hw); | 220 | pr_debug("cpm2_pic_host_map(%d, 0x%lx)\n", virq, hw); |
228 | 221 | ||
229 | irq_to_desc(virq)->status |= IRQ_LEVEL; | 222 | irq_set_status_flags(virq, IRQ_LEVEL); |
230 | set_irq_chip_and_handler(virq, &cpm2_pic, handle_level_irq); | 223 | irq_set_chip_and_handler(virq, &cpm2_pic, handle_level_irq); |
231 | return 0; | 224 | return 0; |
232 | } | 225 | } |
233 | 226 | ||
diff --git a/arch/powerpc/sysdev/fsl_msi.c b/arch/powerpc/sysdev/fsl_msi.c index 58e09b2833f2..d5679dc1e20f 100644 --- a/arch/powerpc/sysdev/fsl_msi.c +++ b/arch/powerpc/sysdev/fsl_msi.c | |||
@@ -64,10 +64,10 @@ static int fsl_msi_host_map(struct irq_host *h, unsigned int virq, | |||
64 | struct fsl_msi *msi_data = h->host_data; | 64 | struct fsl_msi *msi_data = h->host_data; |
65 | struct irq_chip *chip = &fsl_msi_chip; | 65 | struct irq_chip *chip = &fsl_msi_chip; |
66 | 66 | ||
67 | irq_to_desc(virq)->status |= IRQ_TYPE_EDGE_FALLING; | 67 | irq_set_status_flags(virq, IRQ_TYPE_EDGE_FALLING); |
68 | 68 | ||
69 | set_irq_chip_data(virq, msi_data); | 69 | irq_set_chip_data(virq, msi_data); |
70 | set_irq_chip_and_handler(virq, chip, handle_edge_irq); | 70 | irq_set_chip_and_handler(virq, chip, handle_edge_irq); |
71 | 71 | ||
72 | return 0; | 72 | return 0; |
73 | } | 73 | } |
@@ -110,8 +110,8 @@ static void fsl_teardown_msi_irqs(struct pci_dev *pdev) | |||
110 | list_for_each_entry(entry, &pdev->msi_list, list) { | 110 | list_for_each_entry(entry, &pdev->msi_list, list) { |
111 | if (entry->irq == NO_IRQ) | 111 | if (entry->irq == NO_IRQ) |
112 | continue; | 112 | continue; |
113 | msi_data = get_irq_data(entry->irq); | 113 | msi_data = irq_get_handler_data(entry->irq); |
114 | set_irq_msi(entry->irq, NULL); | 114 | irq_set_msi_desc(entry->irq, NULL); |
115 | msi_bitmap_free_hwirqs(&msi_data->bitmap, | 115 | msi_bitmap_free_hwirqs(&msi_data->bitmap, |
116 | virq_to_hw(entry->irq), 1); | 116 | virq_to_hw(entry->irq), 1); |
117 | irq_dispose_mapping(entry->irq); | 117 | irq_dispose_mapping(entry->irq); |
@@ -168,8 +168,8 @@ static int fsl_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type) | |||
168 | rc = -ENOSPC; | 168 | rc = -ENOSPC; |
169 | goto out_free; | 169 | goto out_free; |
170 | } | 170 | } |
171 | set_irq_data(virq, msi_data); | 171 | irq_set_handler_data(virq, msi_data); |
172 | set_irq_msi(virq, entry); | 172 | irq_set_msi_desc(virq, entry); |
173 | 173 | ||
174 | fsl_compose_msi_msg(pdev, hwirq, &msg, msi_data); | 174 | fsl_compose_msi_msg(pdev, hwirq, &msg, msi_data); |
175 | write_msi_msg(virq, &msg); | 175 | write_msi_msg(virq, &msg); |
@@ -183,7 +183,8 @@ out_free: | |||
183 | 183 | ||
184 | static void fsl_msi_cascade(unsigned int irq, struct irq_desc *desc) | 184 | static void fsl_msi_cascade(unsigned int irq, struct irq_desc *desc) |
185 | { | 185 | { |
186 | struct irq_chip *chip = get_irq_desc_chip(desc); | 186 | struct irq_chip *chip = irq_desc_get_chip(desc); |
187 | struct irq_data *idata = irq_desc_get_irq_data(desc); | ||
187 | unsigned int cascade_irq; | 188 | unsigned int cascade_irq; |
188 | struct fsl_msi *msi_data; | 189 | struct fsl_msi *msi_data; |
189 | int msir_index = -1; | 190 | int msir_index = -1; |
@@ -192,20 +193,20 @@ static void fsl_msi_cascade(unsigned int irq, struct irq_desc *desc) | |||
192 | u32 have_shift = 0; | 193 | u32 have_shift = 0; |
193 | struct fsl_msi_cascade_data *cascade_data; | 194 | struct fsl_msi_cascade_data *cascade_data; |
194 | 195 | ||
195 | cascade_data = (struct fsl_msi_cascade_data *)get_irq_data(irq); | 196 | cascade_data = (struct fsl_msi_cascade_data *)irq_get_handler_data(irq); |
196 | msi_data = cascade_data->msi_data; | 197 | msi_data = cascade_data->msi_data; |
197 | 198 | ||
198 | raw_spin_lock(&desc->lock); | 199 | raw_spin_lock(&desc->lock); |
199 | if ((msi_data->feature & FSL_PIC_IP_MASK) == FSL_PIC_IP_IPIC) { | 200 | if ((msi_data->feature & FSL_PIC_IP_MASK) == FSL_PIC_IP_IPIC) { |
200 | if (chip->irq_mask_ack) | 201 | if (chip->irq_mask_ack) |
201 | chip->irq_mask_ack(&desc->irq_data); | 202 | chip->irq_mask_ack(idata); |
202 | else { | 203 | else { |
203 | chip->irq_mask(&desc->irq_data); | 204 | chip->irq_mask(idata); |
204 | chip->irq_ack(&desc->irq_data); | 205 | chip->irq_ack(idata); |
205 | } | 206 | } |
206 | } | 207 | } |
207 | 208 | ||
208 | if (unlikely(desc->status & IRQ_INPROGRESS)) | 209 | if (unlikely(irqd_irq_inprogress(idata))) |
209 | goto unlock; | 210 | goto unlock; |
210 | 211 | ||
211 | msir_index = cascade_data->index; | 212 | msir_index = cascade_data->index; |
@@ -213,7 +214,7 @@ static void fsl_msi_cascade(unsigned int irq, struct irq_desc *desc) | |||
213 | if (msir_index >= NR_MSI_REG) | 214 | if (msir_index >= NR_MSI_REG) |
214 | cascade_irq = NO_IRQ; | 215 | cascade_irq = NO_IRQ; |
215 | 216 | ||
216 | desc->status |= IRQ_INPROGRESS; | 217 | irqd_set_chained_irq_inprogress(idata); |
217 | switch (msi_data->feature & FSL_PIC_IP_MASK) { | 218 | switch (msi_data->feature & FSL_PIC_IP_MASK) { |
218 | case FSL_PIC_IP_MPIC: | 219 | case FSL_PIC_IP_MPIC: |
219 | msir_value = fsl_msi_read(msi_data->msi_regs, | 220 | msir_value = fsl_msi_read(msi_data->msi_regs, |
@@ -235,15 +236,15 @@ static void fsl_msi_cascade(unsigned int irq, struct irq_desc *desc) | |||
235 | have_shift += intr_index + 1; | 236 | have_shift += intr_index + 1; |
236 | msir_value = msir_value >> (intr_index + 1); | 237 | msir_value = msir_value >> (intr_index + 1); |
237 | } | 238 | } |
238 | desc->status &= ~IRQ_INPROGRESS; | 239 | irqd_clr_chained_irq_inprogress(idata); |
239 | 240 | ||
240 | switch (msi_data->feature & FSL_PIC_IP_MASK) { | 241 | switch (msi_data->feature & FSL_PIC_IP_MASK) { |
241 | case FSL_PIC_IP_MPIC: | 242 | case FSL_PIC_IP_MPIC: |
242 | chip->irq_eoi(&desc->irq_data); | 243 | chip->irq_eoi(idata); |
243 | break; | 244 | break; |
244 | case FSL_PIC_IP_IPIC: | 245 | case FSL_PIC_IP_IPIC: |
245 | if (!(desc->status & IRQ_DISABLED) && chip->irq_unmask) | 246 | if (!irqd_irq_disabled(idata) && chip->irq_unmask) |
246 | chip->irq_unmask(&desc->irq_data); | 247 | chip->irq_unmask(idata); |
247 | break; | 248 | break; |
248 | } | 249 | } |
249 | unlock: | 250 | unlock: |
@@ -261,7 +262,7 @@ static int fsl_of_msi_remove(struct platform_device *ofdev) | |||
261 | for (i = 0; i < NR_MSI_REG; i++) { | 262 | for (i = 0; i < NR_MSI_REG; i++) { |
262 | virq = msi->msi_virqs[i]; | 263 | virq = msi->msi_virqs[i]; |
263 | if (virq != NO_IRQ) { | 264 | if (virq != NO_IRQ) { |
264 | cascade_data = get_irq_data(virq); | 265 | cascade_data = irq_get_handler_data(virq); |
265 | kfree(cascade_data); | 266 | kfree(cascade_data); |
266 | irq_dispose_mapping(virq); | 267 | irq_dispose_mapping(virq); |
267 | } | 268 | } |
@@ -297,8 +298,8 @@ static int __devinit fsl_msi_setup_hwirq(struct fsl_msi *msi, | |||
297 | msi->msi_virqs[irq_index] = virt_msir; | 298 | msi->msi_virqs[irq_index] = virt_msir; |
298 | cascade_data->index = offset + irq_index; | 299 | cascade_data->index = offset + irq_index; |
299 | cascade_data->msi_data = msi; | 300 | cascade_data->msi_data = msi; |
300 | set_irq_data(virt_msir, cascade_data); | 301 | irq_set_handler_data(virt_msir, cascade_data); |
301 | set_irq_chained_handler(virt_msir, fsl_msi_cascade); | 302 | irq_set_chained_handler(virt_msir, fsl_msi_cascade); |
302 | 303 | ||
303 | return 0; | 304 | return 0; |
304 | } | 305 | } |
diff --git a/arch/powerpc/sysdev/fsl_rio.c b/arch/powerpc/sysdev/fsl_rio.c index 3eff2c3a9ad5..14232d57369c 100644 --- a/arch/powerpc/sysdev/fsl_rio.c +++ b/arch/powerpc/sysdev/fsl_rio.c | |||
@@ -482,7 +482,7 @@ fsl_rio_config_write(struct rio_mport *mport, int index, u16 destid, | |||
482 | } | 482 | } |
483 | 483 | ||
484 | /** | 484 | /** |
485 | * rio_hw_add_outb_message - Add message to the MPC85xx outbound message queue | 485 | * fsl_add_outb_message - Add message to the MPC85xx outbound message queue |
486 | * @mport: Master port with outbound message queue | 486 | * @mport: Master port with outbound message queue |
487 | * @rdev: Target of outbound message | 487 | * @rdev: Target of outbound message |
488 | * @mbox: Outbound mailbox | 488 | * @mbox: Outbound mailbox |
@@ -492,8 +492,8 @@ fsl_rio_config_write(struct rio_mport *mport, int index, u16 destid, | |||
492 | * Adds the @buffer message to the MPC85xx outbound message queue. Returns | 492 | * Adds the @buffer message to the MPC85xx outbound message queue. Returns |
493 | * %0 on success or %-EINVAL on failure. | 493 | * %0 on success or %-EINVAL on failure. |
494 | */ | 494 | */ |
495 | int | 495 | static int |
496 | rio_hw_add_outb_message(struct rio_mport *mport, struct rio_dev *rdev, int mbox, | 496 | fsl_add_outb_message(struct rio_mport *mport, struct rio_dev *rdev, int mbox, |
497 | void *buffer, size_t len) | 497 | void *buffer, size_t len) |
498 | { | 498 | { |
499 | struct rio_priv *priv = mport->priv; | 499 | struct rio_priv *priv = mport->priv; |
@@ -502,9 +502,8 @@ rio_hw_add_outb_message(struct rio_mport *mport, struct rio_dev *rdev, int mbox, | |||
502 | + priv->msg_tx_ring.tx_slot; | 502 | + priv->msg_tx_ring.tx_slot; |
503 | int ret = 0; | 503 | int ret = 0; |
504 | 504 | ||
505 | pr_debug | 505 | pr_debug("RIO: fsl_add_outb_message(): destid %4.4x mbox %d buffer " \ |
506 | ("RIO: rio_hw_add_outb_message(): destid %4.4x mbox %d buffer %8.8x len %8.8x\n", | 506 | "%8.8x len %8.8x\n", rdev->destid, mbox, (int)buffer, len); |
507 | rdev->destid, mbox, (int)buffer, len); | ||
508 | 507 | ||
509 | if ((len < 8) || (len > RIO_MAX_MSG_SIZE)) { | 508 | if ((len < 8) || (len > RIO_MAX_MSG_SIZE)) { |
510 | ret = -EINVAL; | 509 | ret = -EINVAL; |
@@ -554,8 +553,6 @@ rio_hw_add_outb_message(struct rio_mport *mport, struct rio_dev *rdev, int mbox, | |||
554 | return ret; | 553 | return ret; |
555 | } | 554 | } |
556 | 555 | ||
557 | EXPORT_SYMBOL_GPL(rio_hw_add_outb_message); | ||
558 | |||
559 | /** | 556 | /** |
560 | * fsl_rio_tx_handler - MPC85xx outbound message interrupt handler | 557 | * fsl_rio_tx_handler - MPC85xx outbound message interrupt handler |
561 | * @irq: Linux interrupt number | 558 | * @irq: Linux interrupt number |
@@ -600,7 +597,7 @@ fsl_rio_tx_handler(int irq, void *dev_instance) | |||
600 | } | 597 | } |
601 | 598 | ||
602 | /** | 599 | /** |
603 | * rio_open_outb_mbox - Initialize MPC85xx outbound mailbox | 600 | * fsl_open_outb_mbox - Initialize MPC85xx outbound mailbox |
604 | * @mport: Master port implementing the outbound message unit | 601 | * @mport: Master port implementing the outbound message unit |
605 | * @dev_id: Device specific pointer to pass on event | 602 | * @dev_id: Device specific pointer to pass on event |
606 | * @mbox: Mailbox to open | 603 | * @mbox: Mailbox to open |
@@ -610,7 +607,8 @@ fsl_rio_tx_handler(int irq, void *dev_instance) | |||
610 | * and enables the outbound message unit. Returns %0 on success and | 607 | * and enables the outbound message unit. Returns %0 on success and |
611 | * %-EINVAL or %-ENOMEM on failure. | 608 | * %-EINVAL or %-ENOMEM on failure. |
612 | */ | 609 | */ |
613 | int rio_open_outb_mbox(struct rio_mport *mport, void *dev_id, int mbox, int entries) | 610 | static int |
611 | fsl_open_outb_mbox(struct rio_mport *mport, void *dev_id, int mbox, int entries) | ||
614 | { | 612 | { |
615 | int i, j, rc = 0; | 613 | int i, j, rc = 0; |
616 | struct rio_priv *priv = mport->priv; | 614 | struct rio_priv *priv = mport->priv; |
@@ -706,14 +704,14 @@ int rio_open_outb_mbox(struct rio_mport *mport, void *dev_id, int mbox, int entr | |||
706 | } | 704 | } |
707 | 705 | ||
708 | /** | 706 | /** |
709 | * rio_close_outb_mbox - Shut down MPC85xx outbound mailbox | 707 | * fsl_close_outb_mbox - Shut down MPC85xx outbound mailbox |
710 | * @mport: Master port implementing the outbound message unit | 708 | * @mport: Master port implementing the outbound message unit |
711 | * @mbox: Mailbox to close | 709 | * @mbox: Mailbox to close |
712 | * | 710 | * |
713 | * Disables the outbound message unit, free all buffers, and | 711 | * Disables the outbound message unit, free all buffers, and |
714 | * frees the outbound message interrupt. | 712 | * frees the outbound message interrupt. |
715 | */ | 713 | */ |
716 | void rio_close_outb_mbox(struct rio_mport *mport, int mbox) | 714 | static void fsl_close_outb_mbox(struct rio_mport *mport, int mbox) |
717 | { | 715 | { |
718 | struct rio_priv *priv = mport->priv; | 716 | struct rio_priv *priv = mport->priv; |
719 | /* Disable inbound message unit */ | 717 | /* Disable inbound message unit */ |
@@ -770,7 +768,7 @@ fsl_rio_rx_handler(int irq, void *dev_instance) | |||
770 | } | 768 | } |
771 | 769 | ||
772 | /** | 770 | /** |
773 | * rio_open_inb_mbox - Initialize MPC85xx inbound mailbox | 771 | * fsl_open_inb_mbox - Initialize MPC85xx inbound mailbox |
774 | * @mport: Master port implementing the inbound message unit | 772 | * @mport: Master port implementing the inbound message unit |
775 | * @dev_id: Device specific pointer to pass on event | 773 | * @dev_id: Device specific pointer to pass on event |
776 | * @mbox: Mailbox to open | 774 | * @mbox: Mailbox to open |
@@ -780,7 +778,8 @@ fsl_rio_rx_handler(int irq, void *dev_instance) | |||
780 | * and enables the inbound message unit. Returns %0 on success | 778 | * and enables the inbound message unit. Returns %0 on success |
781 | * and %-EINVAL or %-ENOMEM on failure. | 779 | * and %-EINVAL or %-ENOMEM on failure. |
782 | */ | 780 | */ |
783 | int rio_open_inb_mbox(struct rio_mport *mport, void *dev_id, int mbox, int entries) | 781 | static int |
782 | fsl_open_inb_mbox(struct rio_mport *mport, void *dev_id, int mbox, int entries) | ||
784 | { | 783 | { |
785 | int i, rc = 0; | 784 | int i, rc = 0; |
786 | struct rio_priv *priv = mport->priv; | 785 | struct rio_priv *priv = mport->priv; |
@@ -844,14 +843,14 @@ int rio_open_inb_mbox(struct rio_mport *mport, void *dev_id, int mbox, int entri | |||
844 | } | 843 | } |
845 | 844 | ||
846 | /** | 845 | /** |
847 | * rio_close_inb_mbox - Shut down MPC85xx inbound mailbox | 846 | * fsl_close_inb_mbox - Shut down MPC85xx inbound mailbox |
848 | * @mport: Master port implementing the inbound message unit | 847 | * @mport: Master port implementing the inbound message unit |
849 | * @mbox: Mailbox to close | 848 | * @mbox: Mailbox to close |
850 | * | 849 | * |
851 | * Disables the inbound message unit, free all buffers, and | 850 | * Disables the inbound message unit, free all buffers, and |
852 | * frees the inbound message interrupt. | 851 | * frees the inbound message interrupt. |
853 | */ | 852 | */ |
854 | void rio_close_inb_mbox(struct rio_mport *mport, int mbox) | 853 | static void fsl_close_inb_mbox(struct rio_mport *mport, int mbox) |
855 | { | 854 | { |
856 | struct rio_priv *priv = mport->priv; | 855 | struct rio_priv *priv = mport->priv; |
857 | /* Disable inbound message unit */ | 856 | /* Disable inbound message unit */ |
@@ -866,7 +865,7 @@ void rio_close_inb_mbox(struct rio_mport *mport, int mbox) | |||
866 | } | 865 | } |
867 | 866 | ||
868 | /** | 867 | /** |
869 | * rio_hw_add_inb_buffer - Add buffer to the MPC85xx inbound message queue | 868 | * fsl_add_inb_buffer - Add buffer to the MPC85xx inbound message queue |
870 | * @mport: Master port implementing the inbound message unit | 869 | * @mport: Master port implementing the inbound message unit |
871 | * @mbox: Inbound mailbox number | 870 | * @mbox: Inbound mailbox number |
872 | * @buf: Buffer to add to inbound queue | 871 | * @buf: Buffer to add to inbound queue |
@@ -874,12 +873,12 @@ void rio_close_inb_mbox(struct rio_mport *mport, int mbox) | |||
874 | * Adds the @buf buffer to the MPC85xx inbound message queue. Returns | 873 | * Adds the @buf buffer to the MPC85xx inbound message queue. Returns |
875 | * %0 on success or %-EINVAL on failure. | 874 | * %0 on success or %-EINVAL on failure. |
876 | */ | 875 | */ |
877 | int rio_hw_add_inb_buffer(struct rio_mport *mport, int mbox, void *buf) | 876 | static int fsl_add_inb_buffer(struct rio_mport *mport, int mbox, void *buf) |
878 | { | 877 | { |
879 | int rc = 0; | 878 | int rc = 0; |
880 | struct rio_priv *priv = mport->priv; | 879 | struct rio_priv *priv = mport->priv; |
881 | 880 | ||
882 | pr_debug("RIO: rio_hw_add_inb_buffer(), msg_rx_ring.rx_slot %d\n", | 881 | pr_debug("RIO: fsl_add_inb_buffer(), msg_rx_ring.rx_slot %d\n", |
883 | priv->msg_rx_ring.rx_slot); | 882 | priv->msg_rx_ring.rx_slot); |
884 | 883 | ||
885 | if (priv->msg_rx_ring.virt_buffer[priv->msg_rx_ring.rx_slot]) { | 884 | if (priv->msg_rx_ring.virt_buffer[priv->msg_rx_ring.rx_slot]) { |
@@ -898,17 +897,15 @@ int rio_hw_add_inb_buffer(struct rio_mport *mport, int mbox, void *buf) | |||
898 | return rc; | 897 | return rc; |
899 | } | 898 | } |
900 | 899 | ||
901 | EXPORT_SYMBOL_GPL(rio_hw_add_inb_buffer); | ||
902 | |||
903 | /** | 900 | /** |
904 | * rio_hw_get_inb_message - Fetch inbound message from the MPC85xx message unit | 901 | * fsl_get_inb_message - Fetch inbound message from the MPC85xx message unit |
905 | * @mport: Master port implementing the inbound message unit | 902 | * @mport: Master port implementing the inbound message unit |
906 | * @mbox: Inbound mailbox number | 903 | * @mbox: Inbound mailbox number |
907 | * | 904 | * |
908 | * Gets the next available inbound message from the inbound message queue. | 905 | * Gets the next available inbound message from the inbound message queue. |
909 | * A pointer to the message is returned on success or NULL on failure. | 906 | * A pointer to the message is returned on success or NULL on failure. |
910 | */ | 907 | */ |
911 | void *rio_hw_get_inb_message(struct rio_mport *mport, int mbox) | 908 | static void *fsl_get_inb_message(struct rio_mport *mport, int mbox) |
912 | { | 909 | { |
913 | struct rio_priv *priv = mport->priv; | 910 | struct rio_priv *priv = mport->priv; |
914 | u32 phys_buf, virt_buf; | 911 | u32 phys_buf, virt_buf; |
@@ -945,8 +942,6 @@ void *rio_hw_get_inb_message(struct rio_mport *mport, int mbox) | |||
945 | return buf; | 942 | return buf; |
946 | } | 943 | } |
947 | 944 | ||
948 | EXPORT_SYMBOL_GPL(rio_hw_get_inb_message); | ||
949 | |||
950 | /** | 945 | /** |
951 | * fsl_rio_dbell_handler - MPC85xx doorbell interrupt handler | 946 | * fsl_rio_dbell_handler - MPC85xx doorbell interrupt handler |
952 | * @irq: Linux interrupt number | 947 | * @irq: Linux interrupt number |
@@ -1293,28 +1288,6 @@ err_out: | |||
1293 | return rc; | 1288 | return rc; |
1294 | } | 1289 | } |
1295 | 1290 | ||
1296 | static char *cmdline = NULL; | ||
1297 | |||
1298 | static int fsl_rio_get_hdid(int index) | ||
1299 | { | ||
1300 | /* XXX Need to parse multiple entries in some format */ | ||
1301 | if (!cmdline) | ||
1302 | return -1; | ||
1303 | |||
1304 | return simple_strtol(cmdline, NULL, 0); | ||
1305 | } | ||
1306 | |||
1307 | static int fsl_rio_get_cmdline(char *s) | ||
1308 | { | ||
1309 | if (!s) | ||
1310 | return 0; | ||
1311 | |||
1312 | cmdline = s; | ||
1313 | return 1; | ||
1314 | } | ||
1315 | |||
1316 | __setup("riohdid=", fsl_rio_get_cmdline); | ||
1317 | |||
1318 | static inline void fsl_rio_info(struct device *dev, u32 ccsr) | 1291 | static inline void fsl_rio_info(struct device *dev, u32 ccsr) |
1319 | { | 1292 | { |
1320 | const char *str; | 1293 | const char *str; |
@@ -1431,13 +1404,19 @@ int fsl_rio_setup(struct platform_device *dev) | |||
1431 | ops->cwrite = fsl_rio_config_write; | 1404 | ops->cwrite = fsl_rio_config_write; |
1432 | ops->dsend = fsl_rio_doorbell_send; | 1405 | ops->dsend = fsl_rio_doorbell_send; |
1433 | ops->pwenable = fsl_rio_pw_enable; | 1406 | ops->pwenable = fsl_rio_pw_enable; |
1407 | ops->open_outb_mbox = fsl_open_outb_mbox; | ||
1408 | ops->open_inb_mbox = fsl_open_inb_mbox; | ||
1409 | ops->close_outb_mbox = fsl_close_outb_mbox; | ||
1410 | ops->close_inb_mbox = fsl_close_inb_mbox; | ||
1411 | ops->add_outb_message = fsl_add_outb_message; | ||
1412 | ops->add_inb_buffer = fsl_add_inb_buffer; | ||
1413 | ops->get_inb_message = fsl_get_inb_message; | ||
1434 | 1414 | ||
1435 | port = kzalloc(sizeof(struct rio_mport), GFP_KERNEL); | 1415 | port = kzalloc(sizeof(struct rio_mport), GFP_KERNEL); |
1436 | if (!port) { | 1416 | if (!port) { |
1437 | rc = -ENOMEM; | 1417 | rc = -ENOMEM; |
1438 | goto err_port; | 1418 | goto err_port; |
1439 | } | 1419 | } |
1440 | port->id = 0; | ||
1441 | port->index = 0; | 1420 | port->index = 0; |
1442 | 1421 | ||
1443 | priv = kzalloc(sizeof(struct rio_priv), GFP_KERNEL); | 1422 | priv = kzalloc(sizeof(struct rio_priv), GFP_KERNEL); |
@@ -1453,6 +1432,14 @@ int fsl_rio_setup(struct platform_device *dev) | |||
1453 | port->iores.flags = IORESOURCE_MEM; | 1432 | port->iores.flags = IORESOURCE_MEM; |
1454 | port->iores.name = "rio_io_win"; | 1433 | port->iores.name = "rio_io_win"; |
1455 | 1434 | ||
1435 | if (request_resource(&iomem_resource, &port->iores) < 0) { | ||
1436 | dev_err(&dev->dev, "RIO: Error requesting master port region" | ||
1437 | " 0x%016llx-0x%016llx\n", | ||
1438 | (u64)port->iores.start, (u64)port->iores.end); | ||
1439 | rc = -ENOMEM; | ||
1440 | goto err_res; | ||
1441 | } | ||
1442 | |||
1456 | priv->pwirq = irq_of_parse_and_map(dev->dev.of_node, 0); | 1443 | priv->pwirq = irq_of_parse_and_map(dev->dev.of_node, 0); |
1457 | priv->bellirq = irq_of_parse_and_map(dev->dev.of_node, 2); | 1444 | priv->bellirq = irq_of_parse_and_map(dev->dev.of_node, 2); |
1458 | priv->txirq = irq_of_parse_and_map(dev->dev.of_node, 3); | 1445 | priv->txirq = irq_of_parse_and_map(dev->dev.of_node, 3); |
@@ -1468,8 +1455,6 @@ int fsl_rio_setup(struct platform_device *dev) | |||
1468 | priv->dev = &dev->dev; | 1455 | priv->dev = &dev->dev; |
1469 | 1456 | ||
1470 | port->ops = ops; | 1457 | port->ops = ops; |
1471 | port->host_deviceid = fsl_rio_get_hdid(port->id); | ||
1472 | |||
1473 | port->priv = priv; | 1458 | port->priv = priv; |
1474 | port->phys_efptr = 0x100; | 1459 | port->phys_efptr = 0x100; |
1475 | rio_register_mport(port); | 1460 | rio_register_mport(port); |
@@ -1559,6 +1544,7 @@ int fsl_rio_setup(struct platform_device *dev) | |||
1559 | return 0; | 1544 | return 0; |
1560 | err: | 1545 | err: |
1561 | iounmap(priv->regs_win); | 1546 | iounmap(priv->regs_win); |
1547 | err_res: | ||
1562 | kfree(priv); | 1548 | kfree(priv); |
1563 | err_priv: | 1549 | err_priv: |
1564 | kfree(port); | 1550 | kfree(port); |
@@ -1572,18 +1558,10 @@ err_ops: | |||
1572 | */ | 1558 | */ |
1573 | static int __devinit fsl_of_rio_rpn_probe(struct platform_device *dev) | 1559 | static int __devinit fsl_of_rio_rpn_probe(struct platform_device *dev) |
1574 | { | 1560 | { |
1575 | int rc; | ||
1576 | printk(KERN_INFO "Setting up RapidIO peer-to-peer network %s\n", | 1561 | printk(KERN_INFO "Setting up RapidIO peer-to-peer network %s\n", |
1577 | dev->dev.of_node->full_name); | 1562 | dev->dev.of_node->full_name); |
1578 | 1563 | ||
1579 | rc = fsl_rio_setup(dev); | 1564 | return fsl_rio_setup(dev); |
1580 | if (rc) | ||
1581 | goto out; | ||
1582 | |||
1583 | /* Enumerate all registered ports */ | ||
1584 | rc = rio_init_mports(); | ||
1585 | out: | ||
1586 | return rc; | ||
1587 | }; | 1565 | }; |
1588 | 1566 | ||
1589 | static const struct of_device_id fsl_of_rio_rpn_ids[] = { | 1567 | static const struct of_device_id fsl_of_rio_rpn_ids[] = { |
diff --git a/arch/powerpc/sysdev/i8259.c b/arch/powerpc/sysdev/i8259.c index aeda4c8d0a0a..142770cb84b6 100644 --- a/arch/powerpc/sysdev/i8259.c +++ b/arch/powerpc/sysdev/i8259.c | |||
@@ -175,13 +175,13 @@ static int i8259_host_map(struct irq_host *h, unsigned int virq, | |||
175 | 175 | ||
176 | /* We block the internal cascade */ | 176 | /* We block the internal cascade */ |
177 | if (hw == 2) | 177 | if (hw == 2) |
178 | irq_to_desc(virq)->status |= IRQ_NOREQUEST; | 178 | irq_set_status_flags(virq, IRQ_NOREQUEST); |
179 | 179 | ||
180 | /* We use the level handler only for now, we might want to | 180 | /* We use the level handler only for now, we might want to |
181 | * be more cautious here but that works for now | 181 | * be more cautious here but that works for now |
182 | */ | 182 | */ |
183 | irq_to_desc(virq)->status |= IRQ_LEVEL; | 183 | irq_set_status_flags(virq, IRQ_LEVEL); |
184 | set_irq_chip_and_handler(virq, &i8259_pic, handle_level_irq); | 184 | irq_set_chip_and_handler(virq, &i8259_pic, handle_level_irq); |
185 | return 0; | 185 | return 0; |
186 | } | 186 | } |
187 | 187 | ||
@@ -191,7 +191,7 @@ static void i8259_host_unmap(struct irq_host *h, unsigned int virq) | |||
191 | i8259_mask_irq(irq_get_irq_data(virq)); | 191 | i8259_mask_irq(irq_get_irq_data(virq)); |
192 | 192 | ||
193 | /* remove chip and handler */ | 193 | /* remove chip and handler */ |
194 | set_irq_chip_and_handler(virq, NULL, NULL); | 194 | irq_set_chip_and_handler(virq, NULL, NULL); |
195 | 195 | ||
196 | /* Make sure it's completed */ | 196 | /* Make sure it's completed */ |
197 | synchronize_irq(virq); | 197 | synchronize_irq(virq); |
diff --git a/arch/powerpc/sysdev/ipic.c b/arch/powerpc/sysdev/ipic.c index 497047dc986e..fa438be962b7 100644 --- a/arch/powerpc/sysdev/ipic.c +++ b/arch/powerpc/sysdev/ipic.c | |||
@@ -605,7 +605,6 @@ static int ipic_set_irq_type(struct irq_data *d, unsigned int flow_type) | |||
605 | { | 605 | { |
606 | struct ipic *ipic = ipic_from_irq(d->irq); | 606 | struct ipic *ipic = ipic_from_irq(d->irq); |
607 | unsigned int src = ipic_irq_to_hw(d->irq); | 607 | unsigned int src = ipic_irq_to_hw(d->irq); |
608 | struct irq_desc *desc = irq_to_desc(d->irq); | ||
609 | unsigned int vold, vnew, edibit; | 608 | unsigned int vold, vnew, edibit; |
610 | 609 | ||
611 | if (flow_type == IRQ_TYPE_NONE) | 610 | if (flow_type == IRQ_TYPE_NONE) |
@@ -623,17 +622,16 @@ static int ipic_set_irq_type(struct irq_data *d, unsigned int flow_type) | |||
623 | printk(KERN_ERR "ipic: edge sense not supported on internal " | 622 | printk(KERN_ERR "ipic: edge sense not supported on internal " |
624 | "interrupts\n"); | 623 | "interrupts\n"); |
625 | return -EINVAL; | 624 | return -EINVAL; |
625 | |||
626 | } | 626 | } |
627 | 627 | ||
628 | desc->status &= ~(IRQ_TYPE_SENSE_MASK | IRQ_LEVEL); | 628 | irqd_set_trigger_type(d, flow_type); |
629 | desc->status |= flow_type & IRQ_TYPE_SENSE_MASK; | ||
630 | if (flow_type & IRQ_TYPE_LEVEL_LOW) { | 629 | if (flow_type & IRQ_TYPE_LEVEL_LOW) { |
631 | desc->status |= IRQ_LEVEL; | 630 | __irq_set_handler_locked(d->irq, handle_level_irq); |
632 | desc->handle_irq = handle_level_irq; | 631 | d->chip = &ipic_level_irq_chip; |
633 | desc->irq_data.chip = &ipic_level_irq_chip; | ||
634 | } else { | 632 | } else { |
635 | desc->handle_irq = handle_edge_irq; | 633 | __irq_set_handler_locked(d->irq, handle_edge_irq); |
636 | desc->irq_data.chip = &ipic_edge_irq_chip; | 634 | d->chip = &ipic_edge_irq_chip; |
637 | } | 635 | } |
638 | 636 | ||
639 | /* only EXT IRQ senses are programmable on ipic | 637 | /* only EXT IRQ senses are programmable on ipic |
@@ -655,7 +653,7 @@ static int ipic_set_irq_type(struct irq_data *d, unsigned int flow_type) | |||
655 | } | 653 | } |
656 | if (vold != vnew) | 654 | if (vold != vnew) |
657 | ipic_write(ipic->regs, IPIC_SECNR, vnew); | 655 | ipic_write(ipic->regs, IPIC_SECNR, vnew); |
658 | return 0; | 656 | return IRQ_SET_MASK_OK_NOCOPY; |
659 | } | 657 | } |
660 | 658 | ||
661 | /* level interrupts and edge interrupts have different ack operations */ | 659 | /* level interrupts and edge interrupts have different ack operations */ |
@@ -687,11 +685,11 @@ static int ipic_host_map(struct irq_host *h, unsigned int virq, | |||
687 | { | 685 | { |
688 | struct ipic *ipic = h->host_data; | 686 | struct ipic *ipic = h->host_data; |
689 | 687 | ||
690 | set_irq_chip_data(virq, ipic); | 688 | irq_set_chip_data(virq, ipic); |
691 | set_irq_chip_and_handler(virq, &ipic_level_irq_chip, handle_level_irq); | 689 | irq_set_chip_and_handler(virq, &ipic_level_irq_chip, handle_level_irq); |
692 | 690 | ||
693 | /* Set default irq type */ | 691 | /* Set default irq type */ |
694 | set_irq_type(virq, IRQ_TYPE_NONE); | 692 | irq_set_irq_type(virq, IRQ_TYPE_NONE); |
695 | 693 | ||
696 | return 0; | 694 | return 0; |
697 | } | 695 | } |
diff --git a/arch/powerpc/sysdev/mpc8xx_pic.c b/arch/powerpc/sysdev/mpc8xx_pic.c index 1a75a7fb4a99..f550e23632f8 100644 --- a/arch/powerpc/sysdev/mpc8xx_pic.c +++ b/arch/powerpc/sysdev/mpc8xx_pic.c | |||
@@ -72,13 +72,6 @@ static void mpc8xx_end_irq(struct irq_data *d) | |||
72 | 72 | ||
73 | static int mpc8xx_set_irq_type(struct irq_data *d, unsigned int flow_type) | 73 | static int mpc8xx_set_irq_type(struct irq_data *d, unsigned int flow_type) |
74 | { | 74 | { |
75 | struct irq_desc *desc = irq_to_desc(d->irq); | ||
76 | |||
77 | desc->status &= ~(IRQ_TYPE_SENSE_MASK | IRQ_LEVEL); | ||
78 | desc->status |= flow_type & IRQ_TYPE_SENSE_MASK; | ||
79 | if (flow_type & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) | ||
80 | desc->status |= IRQ_LEVEL; | ||
81 | |||
82 | if (flow_type & IRQ_TYPE_EDGE_FALLING) { | 75 | if (flow_type & IRQ_TYPE_EDGE_FALLING) { |
83 | irq_hw_number_t hw = (unsigned int)irq_map[d->irq].hwirq; | 76 | irq_hw_number_t hw = (unsigned int)irq_map[d->irq].hwirq; |
84 | unsigned int siel = in_be32(&siu_reg->sc_siel); | 77 | unsigned int siel = in_be32(&siu_reg->sc_siel); |
@@ -87,7 +80,7 @@ static int mpc8xx_set_irq_type(struct irq_data *d, unsigned int flow_type) | |||
87 | if ((hw & 1) == 0) { | 80 | if ((hw & 1) == 0) { |
88 | siel |= (0x80000000 >> hw); | 81 | siel |= (0x80000000 >> hw); |
89 | out_be32(&siu_reg->sc_siel, siel); | 82 | out_be32(&siu_reg->sc_siel, siel); |
90 | desc->handle_irq = handle_edge_irq; | 83 | __irq_set_handler_locked(irq, handle_edge_irq); |
91 | } | 84 | } |
92 | } | 85 | } |
93 | return 0; | 86 | return 0; |
@@ -124,7 +117,7 @@ static int mpc8xx_pic_host_map(struct irq_host *h, unsigned int virq, | |||
124 | pr_debug("mpc8xx_pic_host_map(%d, 0x%lx)\n", virq, hw); | 117 | pr_debug("mpc8xx_pic_host_map(%d, 0x%lx)\n", virq, hw); |
125 | 118 | ||
126 | /* Set default irq handle */ | 119 | /* Set default irq handle */ |
127 | set_irq_chip_and_handler(virq, &mpc8xx_pic, handle_level_irq); | 120 | irq_set_chip_and_handler(virq, &mpc8xx_pic, handle_level_irq); |
128 | return 0; | 121 | return 0; |
129 | } | 122 | } |
130 | 123 | ||
diff --git a/arch/powerpc/sysdev/mpc8xxx_gpio.c b/arch/powerpc/sysdev/mpc8xxx_gpio.c index 232e701245d7..0892a2841c2b 100644 --- a/arch/powerpc/sysdev/mpc8xxx_gpio.c +++ b/arch/powerpc/sysdev/mpc8xxx_gpio.c | |||
@@ -145,7 +145,7 @@ static int mpc8xxx_gpio_to_irq(struct gpio_chip *gc, unsigned offset) | |||
145 | 145 | ||
146 | static void mpc8xxx_gpio_irq_cascade(unsigned int irq, struct irq_desc *desc) | 146 | static void mpc8xxx_gpio_irq_cascade(unsigned int irq, struct irq_desc *desc) |
147 | { | 147 | { |
148 | struct mpc8xxx_gpio_chip *mpc8xxx_gc = get_irq_desc_data(desc); | 148 | struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_desc_get_handler_data(desc); |
149 | struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc; | 149 | struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc; |
150 | unsigned int mask; | 150 | unsigned int mask; |
151 | 151 | ||
@@ -278,9 +278,9 @@ static int mpc8xxx_gpio_irq_map(struct irq_host *h, unsigned int virq, | |||
278 | if (mpc8xxx_gc->of_dev_id_data) | 278 | if (mpc8xxx_gc->of_dev_id_data) |
279 | mpc8xxx_irq_chip.irq_set_type = mpc8xxx_gc->of_dev_id_data; | 279 | mpc8xxx_irq_chip.irq_set_type = mpc8xxx_gc->of_dev_id_data; |
280 | 280 | ||
281 | set_irq_chip_data(virq, h->host_data); | 281 | irq_set_chip_data(virq, h->host_data); |
282 | set_irq_chip_and_handler(virq, &mpc8xxx_irq_chip, handle_level_irq); | 282 | irq_set_chip_and_handler(virq, &mpc8xxx_irq_chip, handle_level_irq); |
283 | set_irq_type(virq, IRQ_TYPE_NONE); | 283 | irq_set_irq_type(virq, IRQ_TYPE_NONE); |
284 | 284 | ||
285 | return 0; | 285 | return 0; |
286 | } | 286 | } |
@@ -369,8 +369,8 @@ static void __init mpc8xxx_add_controller(struct device_node *np) | |||
369 | out_be32(mm_gc->regs + GPIO_IER, 0xffffffff); | 369 | out_be32(mm_gc->regs + GPIO_IER, 0xffffffff); |
370 | out_be32(mm_gc->regs + GPIO_IMR, 0); | 370 | out_be32(mm_gc->regs + GPIO_IMR, 0); |
371 | 371 | ||
372 | set_irq_data(hwirq, mpc8xxx_gc); | 372 | irq_set_handler_data(hwirq, mpc8xxx_gc); |
373 | set_irq_chained_handler(hwirq, mpc8xxx_gpio_irq_cascade); | 373 | irq_set_chained_handler(hwirq, mpc8xxx_gpio_irq_cascade); |
374 | 374 | ||
375 | skip_irq: | 375 | skip_irq: |
376 | return; | 376 | return; |
diff --git a/arch/powerpc/sysdev/mpic.c b/arch/powerpc/sysdev/mpic.c index eb7021815e2d..f91c065bed5a 100644 --- a/arch/powerpc/sysdev/mpic.c +++ b/arch/powerpc/sysdev/mpic.c | |||
@@ -147,6 +147,16 @@ static u32 mpic_infos[][MPIC_IDX_END] = { | |||
147 | 147 | ||
148 | #endif /* CONFIG_MPIC_WEIRD */ | 148 | #endif /* CONFIG_MPIC_WEIRD */ |
149 | 149 | ||
150 | static inline unsigned int mpic_processor_id(struct mpic *mpic) | ||
151 | { | ||
152 | unsigned int cpu = 0; | ||
153 | |||
154 | if (mpic->flags & MPIC_PRIMARY) | ||
155 | cpu = hard_smp_processor_id(); | ||
156 | |||
157 | return cpu; | ||
158 | } | ||
159 | |||
150 | /* | 160 | /* |
151 | * Register accessor functions | 161 | * Register accessor functions |
152 | */ | 162 | */ |
@@ -210,19 +220,14 @@ static inline void _mpic_ipi_write(struct mpic *mpic, unsigned int ipi, u32 valu | |||
210 | 220 | ||
211 | static inline u32 _mpic_cpu_read(struct mpic *mpic, unsigned int reg) | 221 | static inline u32 _mpic_cpu_read(struct mpic *mpic, unsigned int reg) |
212 | { | 222 | { |
213 | unsigned int cpu = 0; | 223 | unsigned int cpu = mpic_processor_id(mpic); |
214 | 224 | ||
215 | if (mpic->flags & MPIC_PRIMARY) | ||
216 | cpu = hard_smp_processor_id(); | ||
217 | return _mpic_read(mpic->reg_type, &mpic->cpuregs[cpu], reg); | 225 | return _mpic_read(mpic->reg_type, &mpic->cpuregs[cpu], reg); |
218 | } | 226 | } |
219 | 227 | ||
220 | static inline void _mpic_cpu_write(struct mpic *mpic, unsigned int reg, u32 value) | 228 | static inline void _mpic_cpu_write(struct mpic *mpic, unsigned int reg, u32 value) |
221 | { | 229 | { |
222 | unsigned int cpu = 0; | 230 | unsigned int cpu = mpic_processor_id(mpic); |
223 | |||
224 | if (mpic->flags & MPIC_PRIMARY) | ||
225 | cpu = hard_smp_processor_id(); | ||
226 | 231 | ||
227 | _mpic_write(mpic->reg_type, &mpic->cpuregs[cpu], reg, value); | 232 | _mpic_write(mpic->reg_type, &mpic->cpuregs[cpu], reg, value); |
228 | } | 233 | } |
@@ -356,7 +361,7 @@ static inline void mpic_ht_end_irq(struct mpic *mpic, unsigned int source) | |||
356 | } | 361 | } |
357 | 362 | ||
358 | static void mpic_startup_ht_interrupt(struct mpic *mpic, unsigned int source, | 363 | static void mpic_startup_ht_interrupt(struct mpic *mpic, unsigned int source, |
359 | unsigned int irqflags) | 364 | bool level) |
360 | { | 365 | { |
361 | struct mpic_irq_fixup *fixup = &mpic->fixups[source]; | 366 | struct mpic_irq_fixup *fixup = &mpic->fixups[source]; |
362 | unsigned long flags; | 367 | unsigned long flags; |
@@ -365,14 +370,14 @@ static void mpic_startup_ht_interrupt(struct mpic *mpic, unsigned int source, | |||
365 | if (fixup->base == NULL) | 370 | if (fixup->base == NULL) |
366 | return; | 371 | return; |
367 | 372 | ||
368 | DBG("startup_ht_interrupt(0x%x, 0x%x) index: %d\n", | 373 | DBG("startup_ht_interrupt(0x%x) index: %d\n", |
369 | source, irqflags, fixup->index); | 374 | source, fixup->index); |
370 | raw_spin_lock_irqsave(&mpic->fixup_lock, flags); | 375 | raw_spin_lock_irqsave(&mpic->fixup_lock, flags); |
371 | /* Enable and configure */ | 376 | /* Enable and configure */ |
372 | writeb(0x10 + 2 * fixup->index, fixup->base + 2); | 377 | writeb(0x10 + 2 * fixup->index, fixup->base + 2); |
373 | tmp = readl(fixup->base + 4); | 378 | tmp = readl(fixup->base + 4); |
374 | tmp &= ~(0x23U); | 379 | tmp &= ~(0x23U); |
375 | if (irqflags & IRQ_LEVEL) | 380 | if (level) |
376 | tmp |= 0x22; | 381 | tmp |= 0x22; |
377 | writel(tmp, fixup->base + 4); | 382 | writel(tmp, fixup->base + 4); |
378 | raw_spin_unlock_irqrestore(&mpic->fixup_lock, flags); | 383 | raw_spin_unlock_irqrestore(&mpic->fixup_lock, flags); |
@@ -384,8 +389,7 @@ static void mpic_startup_ht_interrupt(struct mpic *mpic, unsigned int source, | |||
384 | #endif | 389 | #endif |
385 | } | 390 | } |
386 | 391 | ||
387 | static void mpic_shutdown_ht_interrupt(struct mpic *mpic, unsigned int source, | 392 | static void mpic_shutdown_ht_interrupt(struct mpic *mpic, unsigned int source) |
388 | unsigned int irqflags) | ||
389 | { | 393 | { |
390 | struct mpic_irq_fixup *fixup = &mpic->fixups[source]; | 394 | struct mpic_irq_fixup *fixup = &mpic->fixups[source]; |
391 | unsigned long flags; | 395 | unsigned long flags; |
@@ -394,7 +398,7 @@ static void mpic_shutdown_ht_interrupt(struct mpic *mpic, unsigned int source, | |||
394 | if (fixup->base == NULL) | 398 | if (fixup->base == NULL) |
395 | return; | 399 | return; |
396 | 400 | ||
397 | DBG("shutdown_ht_interrupt(0x%x, 0x%x)\n", source, irqflags); | 401 | DBG("shutdown_ht_interrupt(0x%x)\n", source); |
398 | 402 | ||
399 | /* Disable */ | 403 | /* Disable */ |
400 | raw_spin_lock_irqsave(&mpic->fixup_lock, flags); | 404 | raw_spin_lock_irqsave(&mpic->fixup_lock, flags); |
@@ -611,7 +615,7 @@ static struct mpic *mpic_find(unsigned int irq) | |||
611 | if (irq < NUM_ISA_INTERRUPTS) | 615 | if (irq < NUM_ISA_INTERRUPTS) |
612 | return NULL; | 616 | return NULL; |
613 | 617 | ||
614 | return get_irq_chip_data(irq); | 618 | return irq_get_chip_data(irq); |
615 | } | 619 | } |
616 | 620 | ||
617 | /* Determine if the linux irq is an IPI */ | 621 | /* Determine if the linux irq is an IPI */ |
@@ -645,7 +649,7 @@ static inline struct mpic * mpic_from_ipi(struct irq_data *d) | |||
645 | /* Get the mpic structure from the irq number */ | 649 | /* Get the mpic structure from the irq number */ |
646 | static inline struct mpic * mpic_from_irq(unsigned int irq) | 650 | static inline struct mpic * mpic_from_irq(unsigned int irq) |
647 | { | 651 | { |
648 | return get_irq_chip_data(irq); | 652 | return irq_get_chip_data(irq); |
649 | } | 653 | } |
650 | 654 | ||
651 | /* Get the mpic structure from the irq data */ | 655 | /* Get the mpic structure from the irq data */ |
@@ -733,7 +737,7 @@ static void mpic_unmask_ht_irq(struct irq_data *d) | |||
733 | 737 | ||
734 | mpic_unmask_irq(d); | 738 | mpic_unmask_irq(d); |
735 | 739 | ||
736 | if (irq_to_desc(d->irq)->status & IRQ_LEVEL) | 740 | if (irqd_is_level_type(d)) |
737 | mpic_ht_end_irq(mpic, src); | 741 | mpic_ht_end_irq(mpic, src); |
738 | } | 742 | } |
739 | 743 | ||
@@ -743,7 +747,7 @@ static unsigned int mpic_startup_ht_irq(struct irq_data *d) | |||
743 | unsigned int src = mpic_irq_to_hw(d->irq); | 747 | unsigned int src = mpic_irq_to_hw(d->irq); |
744 | 748 | ||
745 | mpic_unmask_irq(d); | 749 | mpic_unmask_irq(d); |
746 | mpic_startup_ht_interrupt(mpic, src, irq_to_desc(d->irq)->status); | 750 | mpic_startup_ht_interrupt(mpic, src, irqd_is_level_type(d)); |
747 | 751 | ||
748 | return 0; | 752 | return 0; |
749 | } | 753 | } |
@@ -753,7 +757,7 @@ static void mpic_shutdown_ht_irq(struct irq_data *d) | |||
753 | struct mpic *mpic = mpic_from_irq_data(d); | 757 | struct mpic *mpic = mpic_from_irq_data(d); |
754 | unsigned int src = mpic_irq_to_hw(d->irq); | 758 | unsigned int src = mpic_irq_to_hw(d->irq); |
755 | 759 | ||
756 | mpic_shutdown_ht_interrupt(mpic, src, irq_to_desc(d->irq)->status); | 760 | mpic_shutdown_ht_interrupt(mpic, src); |
757 | mpic_mask_irq(d); | 761 | mpic_mask_irq(d); |
758 | } | 762 | } |
759 | 763 | ||
@@ -770,7 +774,7 @@ static void mpic_end_ht_irq(struct irq_data *d) | |||
770 | * latched another edge interrupt coming in anyway | 774 | * latched another edge interrupt coming in anyway |
771 | */ | 775 | */ |
772 | 776 | ||
773 | if (irq_to_desc(d->irq)->status & IRQ_LEVEL) | 777 | if (irqd_is_level_type(d)) |
774 | mpic_ht_end_irq(mpic, src); | 778 | mpic_ht_end_irq(mpic, src); |
775 | mpic_eoi(mpic); | 779 | mpic_eoi(mpic); |
776 | } | 780 | } |
@@ -859,7 +863,6 @@ int mpic_set_irq_type(struct irq_data *d, unsigned int flow_type) | |||
859 | { | 863 | { |
860 | struct mpic *mpic = mpic_from_irq_data(d); | 864 | struct mpic *mpic = mpic_from_irq_data(d); |
861 | unsigned int src = mpic_irq_to_hw(d->irq); | 865 | unsigned int src = mpic_irq_to_hw(d->irq); |
862 | struct irq_desc *desc = irq_to_desc(d->irq); | ||
863 | unsigned int vecpri, vold, vnew; | 866 | unsigned int vecpri, vold, vnew; |
864 | 867 | ||
865 | DBG("mpic: set_irq_type(mpic:@%p,virq:%d,src:0x%x,type:0x%x)\n", | 868 | DBG("mpic: set_irq_type(mpic:@%p,virq:%d,src:0x%x,type:0x%x)\n", |
@@ -874,10 +877,7 @@ int mpic_set_irq_type(struct irq_data *d, unsigned int flow_type) | |||
874 | if (flow_type == IRQ_TYPE_NONE) | 877 | if (flow_type == IRQ_TYPE_NONE) |
875 | flow_type = IRQ_TYPE_LEVEL_LOW; | 878 | flow_type = IRQ_TYPE_LEVEL_LOW; |
876 | 879 | ||
877 | desc->status &= ~(IRQ_TYPE_SENSE_MASK | IRQ_LEVEL); | 880 | irqd_set_trigger_type(d, flow_type); |
878 | desc->status |= flow_type & IRQ_TYPE_SENSE_MASK; | ||
879 | if (flow_type & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) | ||
880 | desc->status |= IRQ_LEVEL; | ||
881 | 881 | ||
882 | if (mpic_is_ht_interrupt(mpic, src)) | 882 | if (mpic_is_ht_interrupt(mpic, src)) |
883 | vecpri = MPIC_VECPRI_POLARITY_POSITIVE | | 883 | vecpri = MPIC_VECPRI_POLARITY_POSITIVE | |
@@ -892,7 +892,7 @@ int mpic_set_irq_type(struct irq_data *d, unsigned int flow_type) | |||
892 | if (vold != vnew) | 892 | if (vold != vnew) |
893 | mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI), vnew); | 893 | mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI), vnew); |
894 | 894 | ||
895 | return 0; | 895 | return IRQ_SET_MASK_OK_NOCOPY;; |
896 | } | 896 | } |
897 | 897 | ||
898 | void mpic_set_vector(unsigned int virq, unsigned int vector) | 898 | void mpic_set_vector(unsigned int virq, unsigned int vector) |
@@ -913,6 +913,20 @@ void mpic_set_vector(unsigned int virq, unsigned int vector) | |||
913 | mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI), vecpri); | 913 | mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI), vecpri); |
914 | } | 914 | } |
915 | 915 | ||
916 | void mpic_set_destination(unsigned int virq, unsigned int cpuid) | ||
917 | { | ||
918 | struct mpic *mpic = mpic_from_irq(virq); | ||
919 | unsigned int src = mpic_irq_to_hw(virq); | ||
920 | |||
921 | DBG("mpic: set_destination(mpic:@%p,virq:%d,src:%d,cpuid:0x%x)\n", | ||
922 | mpic, virq, src, cpuid); | ||
923 | |||
924 | if (src >= mpic->irq_count) | ||
925 | return; | ||
926 | |||
927 | mpic_irq_write(src, MPIC_INFO(IRQ_DESTINATION), 1 << cpuid); | ||
928 | } | ||
929 | |||
916 | static struct irq_chip mpic_irq_chip = { | 930 | static struct irq_chip mpic_irq_chip = { |
917 | .irq_mask = mpic_mask_irq, | 931 | .irq_mask = mpic_mask_irq, |
918 | .irq_unmask = mpic_unmask_irq, | 932 | .irq_unmask = mpic_unmask_irq, |
@@ -964,8 +978,8 @@ static int mpic_host_map(struct irq_host *h, unsigned int virq, | |||
964 | WARN_ON(!(mpic->flags & MPIC_PRIMARY)); | 978 | WARN_ON(!(mpic->flags & MPIC_PRIMARY)); |
965 | 979 | ||
966 | DBG("mpic: mapping as IPI\n"); | 980 | DBG("mpic: mapping as IPI\n"); |
967 | set_irq_chip_data(virq, mpic); | 981 | irq_set_chip_data(virq, mpic); |
968 | set_irq_chip_and_handler(virq, &mpic->hc_ipi, | 982 | irq_set_chip_and_handler(virq, &mpic->hc_ipi, |
969 | handle_percpu_irq); | 983 | handle_percpu_irq); |
970 | return 0; | 984 | return 0; |
971 | } | 985 | } |
@@ -987,11 +1001,21 @@ static int mpic_host_map(struct irq_host *h, unsigned int virq, | |||
987 | 1001 | ||
988 | DBG("mpic: mapping to irq chip @%p\n", chip); | 1002 | DBG("mpic: mapping to irq chip @%p\n", chip); |
989 | 1003 | ||
990 | set_irq_chip_data(virq, mpic); | 1004 | irq_set_chip_data(virq, mpic); |
991 | set_irq_chip_and_handler(virq, chip, handle_fasteoi_irq); | 1005 | irq_set_chip_and_handler(virq, chip, handle_fasteoi_irq); |
992 | 1006 | ||
993 | /* Set default irq type */ | 1007 | /* Set default irq type */ |
994 | set_irq_type(virq, IRQ_TYPE_NONE); | 1008 | irq_set_irq_type(virq, IRQ_TYPE_NONE); |
1009 | |||
1010 | /* If the MPIC was reset, then all vectors have already been | ||
1011 | * initialized. Otherwise, a per source lazy initialization | ||
1012 | * is done here. | ||
1013 | */ | ||
1014 | if (!mpic_is_ipi(mpic, hw) && (mpic->flags & MPIC_NO_RESET)) { | ||
1015 | mpic_set_vector(virq, hw); | ||
1016 | mpic_set_destination(virq, mpic_processor_id(mpic)); | ||
1017 | mpic_irq_set_priority(virq, 8); | ||
1018 | } | ||
995 | 1019 | ||
996 | return 0; | 1020 | return 0; |
997 | } | 1021 | } |
@@ -1040,6 +1064,11 @@ static struct irq_host_ops mpic_host_ops = { | |||
1040 | .xlate = mpic_host_xlate, | 1064 | .xlate = mpic_host_xlate, |
1041 | }; | 1065 | }; |
1042 | 1066 | ||
1067 | static int mpic_reset_prohibited(struct device_node *node) | ||
1068 | { | ||
1069 | return node && of_get_property(node, "pic-no-reset", NULL); | ||
1070 | } | ||
1071 | |||
1043 | /* | 1072 | /* |
1044 | * Exported functions | 1073 | * Exported functions |
1045 | */ | 1074 | */ |
@@ -1160,7 +1189,15 @@ struct mpic * __init mpic_alloc(struct device_node *node, | |||
1160 | mpic_map(mpic, node, paddr, &mpic->tmregs, MPIC_INFO(TIMER_BASE), 0x1000); | 1189 | mpic_map(mpic, node, paddr, &mpic->tmregs, MPIC_INFO(TIMER_BASE), 0x1000); |
1161 | 1190 | ||
1162 | /* Reset */ | 1191 | /* Reset */ |
1163 | if (flags & MPIC_WANTS_RESET) { | 1192 | |
1193 | /* When using a device-node, reset requests are only honored if the MPIC | ||
1194 | * is allowed to reset. | ||
1195 | */ | ||
1196 | if (mpic_reset_prohibited(node)) | ||
1197 | mpic->flags |= MPIC_NO_RESET; | ||
1198 | |||
1199 | if ((flags & MPIC_WANTS_RESET) && !(mpic->flags & MPIC_NO_RESET)) { | ||
1200 | printk(KERN_DEBUG "mpic: Resetting\n"); | ||
1164 | mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0), | 1201 | mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0), |
1165 | mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0)) | 1202 | mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0)) |
1166 | | MPIC_GREG_GCONF_RESET); | 1203 | | MPIC_GREG_GCONF_RESET); |
@@ -1320,22 +1357,21 @@ void __init mpic_init(struct mpic *mpic) | |||
1320 | 1357 | ||
1321 | mpic_pasemi_msi_init(mpic); | 1358 | mpic_pasemi_msi_init(mpic); |
1322 | 1359 | ||
1323 | if (mpic->flags & MPIC_PRIMARY) | 1360 | cpu = mpic_processor_id(mpic); |
1324 | cpu = hard_smp_processor_id(); | ||
1325 | else | ||
1326 | cpu = 0; | ||
1327 | 1361 | ||
1328 | for (i = 0; i < mpic->num_sources; i++) { | 1362 | if (!(mpic->flags & MPIC_NO_RESET)) { |
1329 | /* start with vector = source number, and masked */ | 1363 | for (i = 0; i < mpic->num_sources; i++) { |
1330 | u32 vecpri = MPIC_VECPRI_MASK | i | | 1364 | /* start with vector = source number, and masked */ |
1331 | (8 << MPIC_VECPRI_PRIORITY_SHIFT); | 1365 | u32 vecpri = MPIC_VECPRI_MASK | i | |
1366 | (8 << MPIC_VECPRI_PRIORITY_SHIFT); | ||
1332 | 1367 | ||
1333 | /* check if protected */ | 1368 | /* check if protected */ |
1334 | if (mpic->protected && test_bit(i, mpic->protected)) | 1369 | if (mpic->protected && test_bit(i, mpic->protected)) |
1335 | continue; | 1370 | continue; |
1336 | /* init hw */ | 1371 | /* init hw */ |
1337 | mpic_irq_write(i, MPIC_INFO(IRQ_VECTOR_PRI), vecpri); | 1372 | mpic_irq_write(i, MPIC_INFO(IRQ_VECTOR_PRI), vecpri); |
1338 | mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION), 1 << cpu); | 1373 | mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION), 1 << cpu); |
1374 | } | ||
1339 | } | 1375 | } |
1340 | 1376 | ||
1341 | /* Init spurious vector */ | 1377 | /* Init spurious vector */ |
diff --git a/arch/powerpc/sysdev/mpic_pasemi_msi.c b/arch/powerpc/sysdev/mpic_pasemi_msi.c index 0b7794acfce1..38e62382070c 100644 --- a/arch/powerpc/sysdev/mpic_pasemi_msi.c +++ b/arch/powerpc/sysdev/mpic_pasemi_msi.c | |||
@@ -81,7 +81,7 @@ static void pasemi_msi_teardown_msi_irqs(struct pci_dev *pdev) | |||
81 | if (entry->irq == NO_IRQ) | 81 | if (entry->irq == NO_IRQ) |
82 | continue; | 82 | continue; |
83 | 83 | ||
84 | set_irq_msi(entry->irq, NULL); | 84 | irq_set_msi_desc(entry->irq, NULL); |
85 | msi_bitmap_free_hwirqs(&msi_mpic->msi_bitmap, | 85 | msi_bitmap_free_hwirqs(&msi_mpic->msi_bitmap, |
86 | virq_to_hw(entry->irq), ALLOC_CHUNK); | 86 | virq_to_hw(entry->irq), ALLOC_CHUNK); |
87 | irq_dispose_mapping(entry->irq); | 87 | irq_dispose_mapping(entry->irq); |
@@ -131,9 +131,9 @@ static int pasemi_msi_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type) | |||
131 | */ | 131 | */ |
132 | mpic_set_vector(virq, 0); | 132 | mpic_set_vector(virq, 0); |
133 | 133 | ||
134 | set_irq_msi(virq, entry); | 134 | irq_set_msi_desc(virq, entry); |
135 | set_irq_chip(virq, &mpic_pasemi_msi_chip); | 135 | irq_set_chip(virq, &mpic_pasemi_msi_chip); |
136 | set_irq_type(virq, IRQ_TYPE_EDGE_RISING); | 136 | irq_set_irq_type(virq, IRQ_TYPE_EDGE_RISING); |
137 | 137 | ||
138 | pr_debug("pasemi_msi: allocated virq 0x%x (hw 0x%x) " \ | 138 | pr_debug("pasemi_msi: allocated virq 0x%x (hw 0x%x) " \ |
139 | "addr 0x%x\n", virq, hwirq, msg.address_lo); | 139 | "addr 0x%x\n", virq, hwirq, msg.address_lo); |
diff --git a/arch/powerpc/sysdev/mpic_u3msi.c b/arch/powerpc/sysdev/mpic_u3msi.c index 71900ac78270..9a7aa0ed9c1c 100644 --- a/arch/powerpc/sysdev/mpic_u3msi.c +++ b/arch/powerpc/sysdev/mpic_u3msi.c | |||
@@ -129,7 +129,7 @@ static void u3msi_teardown_msi_irqs(struct pci_dev *pdev) | |||
129 | if (entry->irq == NO_IRQ) | 129 | if (entry->irq == NO_IRQ) |
130 | continue; | 130 | continue; |
131 | 131 | ||
132 | set_irq_msi(entry->irq, NULL); | 132 | irq_set_msi_desc(entry->irq, NULL); |
133 | msi_bitmap_free_hwirqs(&msi_mpic->msi_bitmap, | 133 | msi_bitmap_free_hwirqs(&msi_mpic->msi_bitmap, |
134 | virq_to_hw(entry->irq), 1); | 134 | virq_to_hw(entry->irq), 1); |
135 | irq_dispose_mapping(entry->irq); | 135 | irq_dispose_mapping(entry->irq); |
@@ -166,9 +166,9 @@ static int u3msi_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type) | |||
166 | return -ENOSPC; | 166 | return -ENOSPC; |
167 | } | 167 | } |
168 | 168 | ||
169 | set_irq_msi(virq, entry); | 169 | irq_set_msi_desc(virq, entry); |
170 | set_irq_chip(virq, &mpic_u3msi_chip); | 170 | irq_set_chip(virq, &mpic_u3msi_chip); |
171 | set_irq_type(virq, IRQ_TYPE_EDGE_RISING); | 171 | irq_set_irq_type(virq, IRQ_TYPE_EDGE_RISING); |
172 | 172 | ||
173 | pr_debug("u3msi: allocated virq 0x%x (hw 0x%x) addr 0x%lx\n", | 173 | pr_debug("u3msi: allocated virq 0x%x (hw 0x%x) addr 0x%lx\n", |
174 | virq, hwirq, (unsigned long)addr); | 174 | virq, hwirq, (unsigned long)addr); |
diff --git a/arch/powerpc/sysdev/mv64x60_pic.c b/arch/powerpc/sysdev/mv64x60_pic.c index bc61ebb8987c..e9c633c7c083 100644 --- a/arch/powerpc/sysdev/mv64x60_pic.c +++ b/arch/powerpc/sysdev/mv64x60_pic.c | |||
@@ -213,11 +213,12 @@ static int mv64x60_host_map(struct irq_host *h, unsigned int virq, | |||
213 | { | 213 | { |
214 | int level1; | 214 | int level1; |
215 | 215 | ||
216 | irq_to_desc(virq)->status |= IRQ_LEVEL; | 216 | irq_set_status_flags(virq, IRQ_LEVEL); |
217 | 217 | ||
218 | level1 = (hwirq & MV64x60_LEVEL1_MASK) >> MV64x60_LEVEL1_OFFSET; | 218 | level1 = (hwirq & MV64x60_LEVEL1_MASK) >> MV64x60_LEVEL1_OFFSET; |
219 | BUG_ON(level1 > MV64x60_LEVEL1_GPP); | 219 | BUG_ON(level1 > MV64x60_LEVEL1_GPP); |
220 | set_irq_chip_and_handler(virq, mv64x60_chips[level1], handle_level_irq); | 220 | irq_set_chip_and_handler(virq, mv64x60_chips[level1], |
221 | handle_level_irq); | ||
221 | 222 | ||
222 | return 0; | 223 | return 0; |
223 | } | 224 | } |
diff --git a/arch/powerpc/sysdev/qe_lib/qe_ic.c b/arch/powerpc/sysdev/qe_lib/qe_ic.c index 8c9ded8ea07c..832d6924ad1c 100644 --- a/arch/powerpc/sysdev/qe_lib/qe_ic.c +++ b/arch/powerpc/sysdev/qe_lib/qe_ic.c | |||
@@ -189,7 +189,7 @@ static inline void qe_ic_write(volatile __be32 __iomem * base, unsigned int reg | |||
189 | 189 | ||
190 | static inline struct qe_ic *qe_ic_from_irq(unsigned int virq) | 190 | static inline struct qe_ic *qe_ic_from_irq(unsigned int virq) |
191 | { | 191 | { |
192 | return get_irq_chip_data(virq); | 192 | return irq_get_chip_data(virq); |
193 | } | 193 | } |
194 | 194 | ||
195 | static inline struct qe_ic *qe_ic_from_irq_data(struct irq_data *d) | 195 | static inline struct qe_ic *qe_ic_from_irq_data(struct irq_data *d) |
@@ -267,10 +267,10 @@ static int qe_ic_host_map(struct irq_host *h, unsigned int virq, | |||
267 | /* Default chip */ | 267 | /* Default chip */ |
268 | chip = &qe_ic->hc_irq; | 268 | chip = &qe_ic->hc_irq; |
269 | 269 | ||
270 | set_irq_chip_data(virq, qe_ic); | 270 | irq_set_chip_data(virq, qe_ic); |
271 | irq_to_desc(virq)->status |= IRQ_LEVEL; | 271 | irq_set_status_flags(virq, IRQ_LEVEL); |
272 | 272 | ||
273 | set_irq_chip_and_handler(virq, chip, handle_level_irq); | 273 | irq_set_chip_and_handler(virq, chip, handle_level_irq); |
274 | 274 | ||
275 | return 0; | 275 | return 0; |
276 | } | 276 | } |
@@ -386,13 +386,13 @@ void __init qe_ic_init(struct device_node *node, unsigned int flags, | |||
386 | 386 | ||
387 | qe_ic_write(qe_ic->regs, QEIC_CICR, temp); | 387 | qe_ic_write(qe_ic->regs, QEIC_CICR, temp); |
388 | 388 | ||
389 | set_irq_data(qe_ic->virq_low, qe_ic); | 389 | irq_set_handler_data(qe_ic->virq_low, qe_ic); |
390 | set_irq_chained_handler(qe_ic->virq_low, low_handler); | 390 | irq_set_chained_handler(qe_ic->virq_low, low_handler); |
391 | 391 | ||
392 | if (qe_ic->virq_high != NO_IRQ && | 392 | if (qe_ic->virq_high != NO_IRQ && |
393 | qe_ic->virq_high != qe_ic->virq_low) { | 393 | qe_ic->virq_high != qe_ic->virq_low) { |
394 | set_irq_data(qe_ic->virq_high, qe_ic); | 394 | irq_set_handler_data(qe_ic->virq_high, qe_ic); |
395 | set_irq_chained_handler(qe_ic->virq_high, high_handler); | 395 | irq_set_chained_handler(qe_ic->virq_high, high_handler); |
396 | } | 396 | } |
397 | } | 397 | } |
398 | 398 | ||
diff --git a/arch/powerpc/sysdev/tsi108_pci.c b/arch/powerpc/sysdev/tsi108_pci.c index 02c91db90037..4d18658116e5 100644 --- a/arch/powerpc/sysdev/tsi108_pci.c +++ b/arch/powerpc/sysdev/tsi108_pci.c | |||
@@ -391,8 +391,8 @@ static int pci_irq_host_map(struct irq_host *h, unsigned int virq, | |||
391 | DBG("%s(%d, 0x%lx)\n", __func__, virq, hw); | 391 | DBG("%s(%d, 0x%lx)\n", __func__, virq, hw); |
392 | if ((virq >= 1) && (virq <= 4)){ | 392 | if ((virq >= 1) && (virq <= 4)){ |
393 | irq = virq + IRQ_PCI_INTAD_BASE - 1; | 393 | irq = virq + IRQ_PCI_INTAD_BASE - 1; |
394 | irq_to_desc(irq)->status |= IRQ_LEVEL; | 394 | irq_set_status_flags(irq, IRQ_LEVEL); |
395 | set_irq_chip(irq, &tsi108_pci_irq); | 395 | irq_set_chip(irq, &tsi108_pci_irq); |
396 | } | 396 | } |
397 | return 0; | 397 | return 0; |
398 | } | 398 | } |
@@ -431,7 +431,7 @@ void __init tsi108_pci_int_init(struct device_node *node) | |||
431 | 431 | ||
432 | void tsi108_irq_cascade(unsigned int irq, struct irq_desc *desc) | 432 | void tsi108_irq_cascade(unsigned int irq, struct irq_desc *desc) |
433 | { | 433 | { |
434 | struct irq_chip *chip = get_irq_desc_chip(desc); | 434 | struct irq_chip *chip = irq_desc_get_chip(desc); |
435 | unsigned int cascade_irq = get_pci_source(); | 435 | unsigned int cascade_irq = get_pci_source(); |
436 | 436 | ||
437 | if (cascade_irq != NO_IRQ) | 437 | if (cascade_irq != NO_IRQ) |
diff --git a/arch/powerpc/sysdev/uic.c b/arch/powerpc/sysdev/uic.c index 835f7958b237..5d9138516628 100644 --- a/arch/powerpc/sysdev/uic.c +++ b/arch/powerpc/sysdev/uic.c | |||
@@ -57,7 +57,6 @@ struct uic { | |||
57 | 57 | ||
58 | static void uic_unmask_irq(struct irq_data *d) | 58 | static void uic_unmask_irq(struct irq_data *d) |
59 | { | 59 | { |
60 | struct irq_desc *desc = irq_to_desc(d->irq); | ||
61 | struct uic *uic = irq_data_get_irq_chip_data(d); | 60 | struct uic *uic = irq_data_get_irq_chip_data(d); |
62 | unsigned int src = uic_irq_to_hw(d->irq); | 61 | unsigned int src = uic_irq_to_hw(d->irq); |
63 | unsigned long flags; | 62 | unsigned long flags; |
@@ -66,7 +65,7 @@ static void uic_unmask_irq(struct irq_data *d) | |||
66 | sr = 1 << (31-src); | 65 | sr = 1 << (31-src); |
67 | spin_lock_irqsave(&uic->lock, flags); | 66 | spin_lock_irqsave(&uic->lock, flags); |
68 | /* ack level-triggered interrupts here */ | 67 | /* ack level-triggered interrupts here */ |
69 | if (desc->status & IRQ_LEVEL) | 68 | if (irqd_is_level_type(d)) |
70 | mtdcr(uic->dcrbase + UIC_SR, sr); | 69 | mtdcr(uic->dcrbase + UIC_SR, sr); |
71 | er = mfdcr(uic->dcrbase + UIC_ER); | 70 | er = mfdcr(uic->dcrbase + UIC_ER); |
72 | er |= sr; | 71 | er |= sr; |
@@ -101,7 +100,6 @@ static void uic_ack_irq(struct irq_data *d) | |||
101 | 100 | ||
102 | static void uic_mask_ack_irq(struct irq_data *d) | 101 | static void uic_mask_ack_irq(struct irq_data *d) |
103 | { | 102 | { |
104 | struct irq_desc *desc = irq_to_desc(d->irq); | ||
105 | struct uic *uic = irq_data_get_irq_chip_data(d); | 103 | struct uic *uic = irq_data_get_irq_chip_data(d); |
106 | unsigned int src = uic_irq_to_hw(d->irq); | 104 | unsigned int src = uic_irq_to_hw(d->irq); |
107 | unsigned long flags; | 105 | unsigned long flags; |
@@ -120,7 +118,7 @@ static void uic_mask_ack_irq(struct irq_data *d) | |||
120 | * level interrupts are ack'ed after the actual | 118 | * level interrupts are ack'ed after the actual |
121 | * isr call in the uic_unmask_irq() | 119 | * isr call in the uic_unmask_irq() |
122 | */ | 120 | */ |
123 | if (!(desc->status & IRQ_LEVEL)) | 121 | if (!irqd_is_level_type(d)) |
124 | mtdcr(uic->dcrbase + UIC_SR, sr); | 122 | mtdcr(uic->dcrbase + UIC_SR, sr); |
125 | spin_unlock_irqrestore(&uic->lock, flags); | 123 | spin_unlock_irqrestore(&uic->lock, flags); |
126 | } | 124 | } |
@@ -129,7 +127,6 @@ static int uic_set_irq_type(struct irq_data *d, unsigned int flow_type) | |||
129 | { | 127 | { |
130 | struct uic *uic = irq_data_get_irq_chip_data(d); | 128 | struct uic *uic = irq_data_get_irq_chip_data(d); |
131 | unsigned int src = uic_irq_to_hw(d->irq); | 129 | unsigned int src = uic_irq_to_hw(d->irq); |
132 | struct irq_desc *desc = irq_to_desc(d->irq); | ||
133 | unsigned long flags; | 130 | unsigned long flags; |
134 | int trigger, polarity; | 131 | int trigger, polarity; |
135 | u32 tr, pr, mask; | 132 | u32 tr, pr, mask; |
@@ -166,11 +163,6 @@ static int uic_set_irq_type(struct irq_data *d, unsigned int flow_type) | |||
166 | mtdcr(uic->dcrbase + UIC_PR, pr); | 163 | mtdcr(uic->dcrbase + UIC_PR, pr); |
167 | mtdcr(uic->dcrbase + UIC_TR, tr); | 164 | mtdcr(uic->dcrbase + UIC_TR, tr); |
168 | 165 | ||
169 | desc->status &= ~(IRQ_TYPE_SENSE_MASK | IRQ_LEVEL); | ||
170 | desc->status |= flow_type & IRQ_TYPE_SENSE_MASK; | ||
171 | if (!trigger) | ||
172 | desc->status |= IRQ_LEVEL; | ||
173 | |||
174 | spin_unlock_irqrestore(&uic->lock, flags); | 166 | spin_unlock_irqrestore(&uic->lock, flags); |
175 | 167 | ||
176 | return 0; | 168 | return 0; |
@@ -190,13 +182,13 @@ static int uic_host_map(struct irq_host *h, unsigned int virq, | |||
190 | { | 182 | { |
191 | struct uic *uic = h->host_data; | 183 | struct uic *uic = h->host_data; |
192 | 184 | ||
193 | set_irq_chip_data(virq, uic); | 185 | irq_set_chip_data(virq, uic); |
194 | /* Despite the name, handle_level_irq() works for both level | 186 | /* Despite the name, handle_level_irq() works for both level |
195 | * and edge irqs on UIC. FIXME: check this is correct */ | 187 | * and edge irqs on UIC. FIXME: check this is correct */ |
196 | set_irq_chip_and_handler(virq, &uic_irq_chip, handle_level_irq); | 188 | irq_set_chip_and_handler(virq, &uic_irq_chip, handle_level_irq); |
197 | 189 | ||
198 | /* Set default irq type */ | 190 | /* Set default irq type */ |
199 | set_irq_type(virq, IRQ_TYPE_NONE); | 191 | irq_set_irq_type(virq, IRQ_TYPE_NONE); |
200 | 192 | ||
201 | return 0; | 193 | return 0; |
202 | } | 194 | } |
@@ -220,17 +212,18 @@ static struct irq_host_ops uic_host_ops = { | |||
220 | 212 | ||
221 | void uic_irq_cascade(unsigned int virq, struct irq_desc *desc) | 213 | void uic_irq_cascade(unsigned int virq, struct irq_desc *desc) |
222 | { | 214 | { |
223 | struct irq_chip *chip = get_irq_desc_chip(desc); | 215 | struct irq_chip *chip = irq_desc_get_chip(desc); |
224 | struct uic *uic = get_irq_data(virq); | 216 | struct irq_data *idata = irq_desc_get_irq_data(desc); |
217 | struct uic *uic = irq_get_handler_data(virq); | ||
225 | u32 msr; | 218 | u32 msr; |
226 | int src; | 219 | int src; |
227 | int subvirq; | 220 | int subvirq; |
228 | 221 | ||
229 | raw_spin_lock(&desc->lock); | 222 | raw_spin_lock(&desc->lock); |
230 | if (desc->status & IRQ_LEVEL) | 223 | if (irqd_is_level_type(idata)) |
231 | chip->irq_mask(&desc->irq_data); | 224 | chip->irq_mask(idata); |
232 | else | 225 | else |
233 | chip->irq_mask_ack(&desc->irq_data); | 226 | chip->irq_mask_ack(idata); |
234 | raw_spin_unlock(&desc->lock); | 227 | raw_spin_unlock(&desc->lock); |
235 | 228 | ||
236 | msr = mfdcr(uic->dcrbase + UIC_MSR); | 229 | msr = mfdcr(uic->dcrbase + UIC_MSR); |
@@ -244,10 +237,10 @@ void uic_irq_cascade(unsigned int virq, struct irq_desc *desc) | |||
244 | 237 | ||
245 | uic_irq_ret: | 238 | uic_irq_ret: |
246 | raw_spin_lock(&desc->lock); | 239 | raw_spin_lock(&desc->lock); |
247 | if (desc->status & IRQ_LEVEL) | 240 | if (irqd_is_level_type(idata)) |
248 | chip->irq_ack(&desc->irq_data); | 241 | chip->irq_ack(idata); |
249 | if (!(desc->status & IRQ_DISABLED) && chip->irq_unmask) | 242 | if (!irqd_irq_disabled(idata) && chip->irq_unmask) |
250 | chip->irq_unmask(&desc->irq_data); | 243 | chip->irq_unmask(idata); |
251 | raw_spin_unlock(&desc->lock); | 244 | raw_spin_unlock(&desc->lock); |
252 | } | 245 | } |
253 | 246 | ||
@@ -336,8 +329,8 @@ void __init uic_init_tree(void) | |||
336 | 329 | ||
337 | cascade_virq = irq_of_parse_and_map(np, 0); | 330 | cascade_virq = irq_of_parse_and_map(np, 0); |
338 | 331 | ||
339 | set_irq_data(cascade_virq, uic); | 332 | irq_set_handler_data(cascade_virq, uic); |
340 | set_irq_chained_handler(cascade_virq, uic_irq_cascade); | 333 | irq_set_chained_handler(cascade_virq, uic_irq_cascade); |
341 | 334 | ||
342 | /* FIXME: setup critical cascade?? */ | 335 | /* FIXME: setup critical cascade?? */ |
343 | } | 336 | } |
diff --git a/arch/powerpc/sysdev/xilinx_intc.c b/arch/powerpc/sysdev/xilinx_intc.c index 7436f3ed4df6..0a13fc19e287 100644 --- a/arch/powerpc/sysdev/xilinx_intc.c +++ b/arch/powerpc/sysdev/xilinx_intc.c | |||
@@ -79,12 +79,6 @@ static void xilinx_intc_mask(struct irq_data *d) | |||
79 | 79 | ||
80 | static int xilinx_intc_set_type(struct irq_data *d, unsigned int flow_type) | 80 | static int xilinx_intc_set_type(struct irq_data *d, unsigned int flow_type) |
81 | { | 81 | { |
82 | struct irq_desc *desc = irq_to_desc(d->irq); | ||
83 | |||
84 | desc->status &= ~(IRQ_TYPE_SENSE_MASK | IRQ_LEVEL); | ||
85 | desc->status |= flow_type & IRQ_TYPE_SENSE_MASK; | ||
86 | if (flow_type & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) | ||
87 | desc->status |= IRQ_LEVEL; | ||
88 | return 0; | 82 | return 0; |
89 | } | 83 | } |
90 | 84 | ||
@@ -170,15 +164,15 @@ static int xilinx_intc_xlate(struct irq_host *h, struct device_node *ct, | |||
170 | static int xilinx_intc_map(struct irq_host *h, unsigned int virq, | 164 | static int xilinx_intc_map(struct irq_host *h, unsigned int virq, |
171 | irq_hw_number_t irq) | 165 | irq_hw_number_t irq) |
172 | { | 166 | { |
173 | set_irq_chip_data(virq, h->host_data); | 167 | irq_set_chip_data(virq, h->host_data); |
174 | 168 | ||
175 | if (xilinx_intc_typetable[irq] == IRQ_TYPE_LEVEL_HIGH || | 169 | if (xilinx_intc_typetable[irq] == IRQ_TYPE_LEVEL_HIGH || |
176 | xilinx_intc_typetable[irq] == IRQ_TYPE_LEVEL_LOW) { | 170 | xilinx_intc_typetable[irq] == IRQ_TYPE_LEVEL_LOW) { |
177 | set_irq_chip_and_handler(virq, &xilinx_intc_level_irqchip, | 171 | irq_set_chip_and_handler(virq, &xilinx_intc_level_irqchip, |
178 | handle_level_irq); | 172 | handle_level_irq); |
179 | } else { | 173 | } else { |
180 | set_irq_chip_and_handler(virq, &xilinx_intc_edge_irqchip, | 174 | irq_set_chip_and_handler(virq, &xilinx_intc_edge_irqchip, |
181 | handle_edge_irq); | 175 | handle_edge_irq); |
182 | } | 176 | } |
183 | return 0; | 177 | return 0; |
184 | } | 178 | } |
@@ -229,7 +223,7 @@ int xilinx_intc_get_irq(void) | |||
229 | */ | 223 | */ |
230 | static void xilinx_i8259_cascade(unsigned int irq, struct irq_desc *desc) | 224 | static void xilinx_i8259_cascade(unsigned int irq, struct irq_desc *desc) |
231 | { | 225 | { |
232 | struct irq_chip *chip = get_irq_desc_chip(desc); | 226 | struct irq_chip *chip = irq_desc_get_chip(desc); |
233 | unsigned int cascade_irq = i8259_irq(); | 227 | unsigned int cascade_irq = i8259_irq(); |
234 | 228 | ||
235 | if (cascade_irq) | 229 | if (cascade_irq) |
@@ -256,7 +250,7 @@ static void __init xilinx_i8259_setup_cascade(void) | |||
256 | } | 250 | } |
257 | 251 | ||
258 | i8259_init(cascade_node, 0); | 252 | i8259_init(cascade_node, 0); |
259 | set_irq_chained_handler(cascade_irq, xilinx_i8259_cascade); | 253 | irq_set_chained_handler(cascade_irq, xilinx_i8259_cascade); |
260 | 254 | ||
261 | /* Program irq 7 (usb/audio), 14/15 (ide) to level sensitive */ | 255 | /* Program irq 7 (usb/audio), 14/15 (ide) to level sensitive */ |
262 | /* This looks like a dirty hack to me --gcl */ | 256 | /* This looks like a dirty hack to me --gcl */ |
diff --git a/arch/powerpc/xmon/xmon.c b/arch/powerpc/xmon/xmon.c index d17d04cfb2cd..33794c1d92c3 100644 --- a/arch/powerpc/xmon/xmon.c +++ b/arch/powerpc/xmon/xmon.c | |||
@@ -821,7 +821,7 @@ cmds(struct pt_regs *excp) | |||
821 | memzcan(); | 821 | memzcan(); |
822 | break; | 822 | break; |
823 | case 'i': | 823 | case 'i': |
824 | show_mem(); | 824 | show_mem(0); |
825 | break; | 825 | break; |
826 | default: | 826 | default: |
827 | termch = cmd; | 827 | termch = cmd; |