aboutsummaryrefslogtreecommitdiffstats
path: root/arch/powerpc
diff options
context:
space:
mode:
Diffstat (limited to 'arch/powerpc')
-rw-r--r--arch/powerpc/Kconfig2
-rw-r--r--arch/powerpc/Kconfig.debug2
-rw-r--r--arch/powerpc/include/asm/hw_irq.h2
-rw-r--r--arch/powerpc/include/asm/pgtable-ppc32.h355
-rw-r--r--arch/powerpc/include/asm/pgtable-ppc64-4k.h (renamed from arch/powerpc/include/asm/pgtable-4k.h)55
-rw-r--r--arch/powerpc/include/asm/pgtable-ppc64-64k.h42
-rw-r--r--arch/powerpc/include/asm/pgtable-ppc64.h91
-rw-r--r--arch/powerpc/include/asm/pte-40x.h64
-rw-r--r--arch/powerpc/include/asm/pte-44x.h102
-rw-r--r--arch/powerpc/include/asm/pte-8xx.h64
-rw-r--r--arch/powerpc/include/asm/pte-fsl-booke.h48
-rw-r--r--arch/powerpc/include/asm/pte-hash32.h49
-rw-r--r--arch/powerpc/include/asm/pte-hash64-4k.h20
-rw-r--r--arch/powerpc/include/asm/pte-hash64-64k.h (renamed from arch/powerpc/include/asm/pgtable-64k.h)132
-rw-r--r--arch/powerpc/include/asm/pte-hash64.h47
-rw-r--r--arch/powerpc/include/asm/udbg.h1
-rw-r--r--arch/powerpc/kernel/Makefile2
-rw-r--r--arch/powerpc/kernel/cputable.c8
-rw-r--r--arch/powerpc/kernel/head_32.S7
-rw-r--r--arch/powerpc/kernel/head_64.S6
-rw-r--r--arch/powerpc/kernel/irq.c4
-rw-r--r--arch/powerpc/kernel/pci-common.c2
-rw-r--r--arch/powerpc/kernel/prom_init.c2
-rw-r--r--arch/powerpc/kernel/prom_init_check.sh2
-rw-r--r--arch/powerpc/kernel/udbg.c7
-rw-r--r--arch/powerpc/kernel/udbg_16550.c60
-rw-r--r--arch/powerpc/mm/Makefile4
-rw-r--r--arch/powerpc/mm/gup.c16
-rw-r--r--arch/powerpc/platforms/512x/Kconfig4
-rw-r--r--arch/powerpc/platforms/52xx/Kconfig2
-rw-r--r--arch/powerpc/platforms/82xx/Kconfig2
-rw-r--r--arch/powerpc/platforms/83xx/Kconfig2
-rw-r--r--arch/powerpc/platforms/86xx/Kconfig2
-rw-r--r--arch/powerpc/platforms/Kconfig27
-rw-r--r--arch/powerpc/platforms/Kconfig.cputype18
-rw-r--r--arch/powerpc/platforms/amigaone/Kconfig2
-rw-r--r--arch/powerpc/platforms/cell/Kconfig11
-rw-r--r--arch/powerpc/platforms/cell/Makefile2
-rw-r--r--arch/powerpc/platforms/cell/spufs/file.c12
-rw-r--r--arch/powerpc/platforms/chrp/Kconfig2
-rw-r--r--arch/powerpc/platforms/embedded6xx/Kconfig2
-rw-r--r--arch/powerpc/platforms/iseries/Kconfig2
-rw-r--r--arch/powerpc/platforms/iseries/irq.c2
-rw-r--r--arch/powerpc/platforms/maple/Kconfig2
-rw-r--r--arch/powerpc/platforms/pasemi/Kconfig2
-rw-r--r--arch/powerpc/platforms/powermac/Kconfig2
-rw-r--r--arch/powerpc/platforms/powermac/pic.h2
-rw-r--r--arch/powerpc/platforms/prep/Kconfig2
-rw-r--r--arch/powerpc/platforms/ps3/Kconfig2
-rw-r--r--arch/powerpc/platforms/pseries/Kconfig7
-rw-r--r--arch/powerpc/platforms/pseries/Makefile2
-rw-r--r--arch/powerpc/platforms/pseries/msi.c24
52 files changed, 785 insertions, 548 deletions
diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
index 5c10af66fb51..ad6b1c084fe3 100644
--- a/arch/powerpc/Kconfig
+++ b/arch/powerpc/Kconfig
@@ -313,7 +313,7 @@ config ARCH_ENABLE_MEMORY_HOTREMOVE
313 313
314config KEXEC 314config KEXEC
315 bool "kexec system call (EXPERIMENTAL)" 315 bool "kexec system call (EXPERIMENTAL)"
316 depends on (PPC_PRPMC2800 || PPC_MULTIPLATFORM) && EXPERIMENTAL 316 depends on BOOK3S && EXPERIMENTAL
317 help 317 help
318 kexec is a system call that implements the ability to shutdown your 318 kexec is a system call that implements the ability to shutdown your
319 current kernel, and to start another kernel. It is like a reboot 319 current kernel, and to start another kernel. It is like a reboot
diff --git a/arch/powerpc/Kconfig.debug b/arch/powerpc/Kconfig.debug
index 08f7cc0a1953..22091bbfdc9b 100644
--- a/arch/powerpc/Kconfig.debug
+++ b/arch/powerpc/Kconfig.debug
@@ -129,7 +129,7 @@ config BDI_SWITCH
129 129
130config BOOTX_TEXT 130config BOOTX_TEXT
131 bool "Support for early boot text console (BootX or OpenFirmware only)" 131 bool "Support for early boot text console (BootX or OpenFirmware only)"
132 depends on PPC_OF && PPC_MULTIPLATFORM 132 depends on PPC_OF && PPC_BOOK3S
133 help 133 help
134 Say Y here to see progress messages from the boot firmware in text 134 Say Y here to see progress messages from the boot firmware in text
135 mode. Requires either BootX or Open Firmware. 135 mode. Requires either BootX or Open Firmware.
diff --git a/arch/powerpc/include/asm/hw_irq.h b/arch/powerpc/include/asm/hw_irq.h
index f75a5fc64d2e..b7e034b0a6dd 100644
--- a/arch/powerpc/include/asm/hw_irq.h
+++ b/arch/powerpc/include/asm/hw_irq.h
@@ -129,7 +129,7 @@ static inline int irqs_disabled_flags(unsigned long flags)
129 * interrupt-retrigger: should we handle this via lost interrupts and IPIs 129 * interrupt-retrigger: should we handle this via lost interrupts and IPIs
130 * or should we not care like we do now ? --BenH. 130 * or should we not care like we do now ? --BenH.
131 */ 131 */
132struct hw_interrupt_type; 132struct irq_chip;
133 133
134#endif /* __KERNEL__ */ 134#endif /* __KERNEL__ */
135#endif /* _ASM_POWERPC_HW_IRQ_H */ 135#endif /* _ASM_POWERPC_HW_IRQ_H */
diff --git a/arch/powerpc/include/asm/pgtable-ppc32.h b/arch/powerpc/include/asm/pgtable-ppc32.h
index 98bd7c5fcd0e..67ceffc01b43 100644
--- a/arch/powerpc/include/asm/pgtable-ppc32.h
+++ b/arch/powerpc/include/asm/pgtable-ppc32.h
@@ -19,55 +19,6 @@ extern int icache_44x_need_flush;
19#endif /* __ASSEMBLY__ */ 19#endif /* __ASSEMBLY__ */
20 20
21/* 21/*
22 * The PowerPC MMU uses a hash table containing PTEs, together with
23 * a set of 16 segment registers (on 32-bit implementations), to define
24 * the virtual to physical address mapping.
25 *
26 * We use the hash table as an extended TLB, i.e. a cache of currently
27 * active mappings. We maintain a two-level page table tree, much
28 * like that used by the i386, for the sake of the Linux memory
29 * management code. Low-level assembler code in hashtable.S
30 * (procedure hash_page) is responsible for extracting ptes from the
31 * tree and putting them into the hash table when necessary, and
32 * updating the accessed and modified bits in the page table tree.
33 */
34
35/*
36 * The PowerPC MPC8xx uses a TLB with hardware assisted, software tablewalk.
37 * We also use the two level tables, but we can put the real bits in them
38 * needed for the TLB and tablewalk. These definitions require Mx_CTR.PPM = 0,
39 * Mx_CTR.PPCS = 0, and MD_CTR.TWAM = 1. The level 2 descriptor has
40 * additional page protection (when Mx_CTR.PPCS = 1) that allows TLB hit
41 * based upon user/super access. The TLB does not have accessed nor write
42 * protect. We assume that if the TLB get loaded with an entry it is
43 * accessed, and overload the changed bit for write protect. We use
44 * two bits in the software pte that are supposed to be set to zero in
45 * the TLB entry (24 and 25) for these indicators. Although the level 1
46 * descriptor contains the guarded and writethrough/copyback bits, we can
47 * set these at the page level since they get copied from the Mx_TWC
48 * register when the TLB entry is loaded. We will use bit 27 for guard, since
49 * that is where it exists in the MD_TWC, and bit 26 for writethrough.
50 * These will get masked from the level 2 descriptor at TLB load time, and
51 * copied to the MD_TWC before it gets loaded.
52 * Large page sizes added. We currently support two sizes, 4K and 8M.
53 * This also allows a TLB hander optimization because we can directly
54 * load the PMD into MD_TWC. The 8M pages are only used for kernel
55 * mapping of well known areas. The PMD (PGD) entries contain control
56 * flags in addition to the address, so care must be taken that the
57 * software no longer assumes these are only pointers.
58 */
59
60/*
61 * At present, all PowerPC 400-class processors share a similar TLB
62 * architecture. The instruction and data sides share a unified,
63 * 64-entry, fully-associative TLB which is maintained totally under
64 * software control. In addition, the instruction side has a
65 * hardware-managed, 4-entry, fully-associative TLB which serves as a
66 * first level to the shared TLB. These two TLBs are known as the UTLB
67 * and ITLB, respectively (see "mmu.h" for definitions).
68 */
69
70/*
71 * The normal case is that PTEs are 32-bits and we have a 1-page 22 * The normal case is that PTEs are 32-bits and we have a 1-page
72 * 1024-entry pgdir pointing to 1-page 1024-entry PTE pages. -- paulus 23 * 1024-entry pgdir pointing to 1-page 1024-entry PTE pages. -- paulus
73 * 24 *
@@ -135,261 +86,25 @@ extern int icache_44x_need_flush;
135 */ 86 */
136 87
137#if defined(CONFIG_40x) 88#if defined(CONFIG_40x)
138 89#include <asm/pte-40x.h>
139/* There are several potential gotchas here. The 40x hardware TLBLO
140 field looks like this:
141
142 0 1 2 3 4 ... 18 19 20 21 22 23 24 25 26 27 28 29 30 31
143 RPN..................... 0 0 EX WR ZSEL....... W I M G
144
145 Where possible we make the Linux PTE bits match up with this
146
147 - bits 20 and 21 must be cleared, because we use 4k pages (40x can
148 support down to 1k pages), this is done in the TLBMiss exception
149 handler.
150 - We use only zones 0 (for kernel pages) and 1 (for user pages)
151 of the 16 available. Bit 24-26 of the TLB are cleared in the TLB
152 miss handler. Bit 27 is PAGE_USER, thus selecting the correct
153 zone.
154 - PRESENT *must* be in the bottom two bits because swap cache
155 entries use the top 30 bits. Because 40x doesn't support SMP
156 anyway, M is irrelevant so we borrow it for PAGE_PRESENT. Bit 30
157 is cleared in the TLB miss handler before the TLB entry is loaded.
158 - All other bits of the PTE are loaded into TLBLO without
159 modification, leaving us only the bits 20, 21, 24, 25, 26, 30 for
160 software PTE bits. We actually use use bits 21, 24, 25, and
161 30 respectively for the software bits: ACCESSED, DIRTY, RW, and
162 PRESENT.
163*/
164
165/* Definitions for 40x embedded chips. */
166#define _PAGE_GUARDED 0x001 /* G: page is guarded from prefetch */
167#define _PAGE_FILE 0x001 /* when !present: nonlinear file mapping */
168#define _PAGE_PRESENT 0x002 /* software: PTE contains a translation */
169#define _PAGE_NO_CACHE 0x004 /* I: caching is inhibited */
170#define _PAGE_WRITETHRU 0x008 /* W: caching is write-through */
171#define _PAGE_USER 0x010 /* matches one of the zone permission bits */
172#define _PAGE_RW 0x040 /* software: Writes permitted */
173#define _PAGE_DIRTY 0x080 /* software: dirty page */
174#define _PAGE_HWWRITE 0x100 /* hardware: Dirty & RW, set in exception */
175#define _PAGE_HWEXEC 0x200 /* hardware: EX permission */
176#define _PAGE_ACCESSED 0x400 /* software: R: page referenced */
177
178#define _PMD_PRESENT 0x400 /* PMD points to page of PTEs */
179#define _PMD_BAD 0x802
180#define _PMD_SIZE 0x0e0 /* size field, != 0 for large-page PMD entry */
181#define _PMD_SIZE_4M 0x0c0
182#define _PMD_SIZE_16M 0x0e0
183#define PMD_PAGE_SIZE(pmdval) (1024 << (((pmdval) & _PMD_SIZE) >> 4))
184
185/* Until my rework is finished, 40x still needs atomic PTE updates */
186#define PTE_ATOMIC_UPDATES 1
187
188#elif defined(CONFIG_44x) 90#elif defined(CONFIG_44x)
189/* 91#include <asm/pte-44x.h>
190 * Definitions for PPC440
191 *
192 * Because of the 3 word TLB entries to support 36-bit addressing,
193 * the attribute are difficult to map in such a fashion that they
194 * are easily loaded during exception processing. I decided to
195 * organize the entry so the ERPN is the only portion in the
196 * upper word of the PTE and the attribute bits below are packed
197 * in as sensibly as they can be in the area below a 4KB page size
198 * oriented RPN. This at least makes it easy to load the RPN and
199 * ERPN fields in the TLB. -Matt
200 *
201 * Note that these bits preclude future use of a page size
202 * less than 4KB.
203 *
204 *
205 * PPC 440 core has following TLB attribute fields;
206 *
207 * TLB1:
208 * 0 1 2 3 4 ... 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
209 * RPN................................. - - - - - - ERPN.......
210 *
211 * TLB2:
212 * 0 1 2 3 4 ... 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
213 * - - - - - - U0 U1 U2 U3 W I M G E - UX UW UR SX SW SR
214 *
215 * Newer 440 cores (440x6 as used on AMCC 460EX/460GT) have additional
216 * TLB2 storage attibute fields. Those are:
217 *
218 * TLB2:
219 * 0...10 11 12 13 14 15 16...31
220 * no change WL1 IL1I IL1D IL2I IL2D no change
221 *
222 * There are some constrains and options, to decide mapping software bits
223 * into TLB entry.
224 *
225 * - PRESENT *must* be in the bottom three bits because swap cache
226 * entries use the top 29 bits for TLB2.
227 *
228 * - FILE *must* be in the bottom three bits because swap cache
229 * entries use the top 29 bits for TLB2.
230 *
231 * - CACHE COHERENT bit (M) has no effect on original PPC440 cores,
232 * because it doesn't support SMP. However, some later 460 variants
233 * have -some- form of SMP support and so I keep the bit there for
234 * future use
235 *
236 * With the PPC 44x Linux implementation, the 0-11th LSBs of the PTE are used
237 * for memory protection related functions (see PTE structure in
238 * include/asm-ppc/mmu.h). The _PAGE_XXX definitions in this file map to the
239 * above bits. Note that the bit values are CPU specific, not architecture
240 * specific.
241 *
242 * The kernel PTE entry holds an arch-dependent swp_entry structure under
243 * certain situations. In other words, in such situations some portion of
244 * the PTE bits are used as a swp_entry. In the PPC implementation, the
245 * 3-24th LSB are shared with swp_entry, however the 0-2nd three LSB still
246 * hold protection values. That means the three protection bits are
247 * reserved for both PTE and SWAP entry at the most significant three
248 * LSBs.
249 *
250 * There are three protection bits available for SWAP entry:
251 * _PAGE_PRESENT
252 * _PAGE_FILE
253 * _PAGE_HASHPTE (if HW has)
254 *
255 * So those three bits have to be inside of 0-2nd LSB of PTE.
256 *
257 */
258
259#define _PAGE_PRESENT 0x00000001 /* S: PTE valid */
260#define _PAGE_RW 0x00000002 /* S: Write permission */
261#define _PAGE_FILE 0x00000004 /* S: nonlinear file mapping */
262#define _PAGE_HWEXEC 0x00000004 /* H: Execute permission */
263#define _PAGE_ACCESSED 0x00000008 /* S: Page referenced */
264#define _PAGE_DIRTY 0x00000010 /* S: Page dirty */
265#define _PAGE_SPECIAL 0x00000020 /* S: Special page */
266#define _PAGE_USER 0x00000040 /* S: User page */
267#define _PAGE_ENDIAN 0x00000080 /* H: E bit */
268#define _PAGE_GUARDED 0x00000100 /* H: G bit */
269#define _PAGE_COHERENT 0x00000200 /* H: M bit */
270#define _PAGE_NO_CACHE 0x00000400 /* H: I bit */
271#define _PAGE_WRITETHRU 0x00000800 /* H: W bit */
272
273/* TODO: Add large page lowmem mapping support */
274#define _PMD_PRESENT 0
275#define _PMD_PRESENT_MASK (PAGE_MASK)
276#define _PMD_BAD (~PAGE_MASK)
277
278/* ERPN in a PTE never gets cleared, ignore it */
279#define _PTE_NONE_MASK 0xffffffff00000000ULL
280
281#define __HAVE_ARCH_PTE_SPECIAL
282
283#elif defined(CONFIG_FSL_BOOKE) 92#elif defined(CONFIG_FSL_BOOKE)
284/* 93#include <asm/pte-fsl-booke.h>
285 MMU Assist Register 3:
286
287 32 33 34 35 36 ... 50 51 52 53 54 55 56 57 58 59 60 61 62 63
288 RPN...................... 0 0 U0 U1 U2 U3 UX SX UW SW UR SR
289
290 - PRESENT *must* be in the bottom three bits because swap cache
291 entries use the top 29 bits.
292
293 - FILE *must* be in the bottom three bits because swap cache
294 entries use the top 29 bits.
295*/
296
297/* Definitions for FSL Book-E Cores */
298#define _PAGE_PRESENT 0x00001 /* S: PTE contains a translation */
299#define _PAGE_USER 0x00002 /* S: User page (maps to UR) */
300#define _PAGE_FILE 0x00002 /* S: when !present: nonlinear file mapping */
301#define _PAGE_RW 0x00004 /* S: Write permission (SW) */
302#define _PAGE_DIRTY 0x00008 /* S: Page dirty */
303#define _PAGE_HWEXEC 0x00010 /* H: SX permission */
304#define _PAGE_ACCESSED 0x00020 /* S: Page referenced */
305
306#define _PAGE_ENDIAN 0x00040 /* H: E bit */
307#define _PAGE_GUARDED 0x00080 /* H: G bit */
308#define _PAGE_COHERENT 0x00100 /* H: M bit */
309#define _PAGE_NO_CACHE 0x00200 /* H: I bit */
310#define _PAGE_WRITETHRU 0x00400 /* H: W bit */
311#define _PAGE_SPECIAL 0x00800 /* S: Special page */
312
313#ifdef CONFIG_PTE_64BIT
314/* ERPN in a PTE never gets cleared, ignore it */
315#define _PTE_NONE_MASK 0xffffffffffff0000ULL
316#endif
317
318#define _PMD_PRESENT 0
319#define _PMD_PRESENT_MASK (PAGE_MASK)
320#define _PMD_BAD (~PAGE_MASK)
321
322#define __HAVE_ARCH_PTE_SPECIAL
323
324#elif defined(CONFIG_8xx) 94#elif defined(CONFIG_8xx)
325/* Definitions for 8xx embedded chips. */ 95#include <asm/pte-8xx.h>
326#define _PAGE_PRESENT 0x0001 /* Page is valid */
327#define _PAGE_FILE 0x0002 /* when !present: nonlinear file mapping */
328#define _PAGE_NO_CACHE 0x0002 /* I: cache inhibit */
329#define _PAGE_SHARED 0x0004 /* No ASID (context) compare */
330
331/* These five software bits must be masked out when the entry is loaded
332 * into the TLB.
333 */
334#define _PAGE_EXEC 0x0008 /* software: i-cache coherency required */
335#define _PAGE_GUARDED 0x0010 /* software: guarded access */
336#define _PAGE_DIRTY 0x0020 /* software: page changed */
337#define _PAGE_RW 0x0040 /* software: user write access allowed */
338#define _PAGE_ACCESSED 0x0080 /* software: page referenced */
339
340/* Setting any bits in the nibble with the follow two controls will
341 * require a TLB exception handler change. It is assumed unused bits
342 * are always zero.
343 */
344#define _PAGE_HWWRITE 0x0100 /* h/w write enable: never set in Linux PTE */
345#define _PAGE_USER 0x0800 /* One of the PP bits, the other is USER&~RW */
346
347#define _PMD_PRESENT 0x0001
348#define _PMD_BAD 0x0ff0
349#define _PMD_PAGE_MASK 0x000c
350#define _PMD_PAGE_8M 0x000c
351
352#define _PTE_NONE_MASK _PAGE_ACCESSED
353
354/* Until my rework is finished, 8xx still needs atomic PTE updates */
355#define PTE_ATOMIC_UPDATES 1
356
357#else /* CONFIG_6xx */ 96#else /* CONFIG_6xx */
358/* Definitions for 60x, 740/750, etc. */ 97#include <asm/pte-hash32.h>
359#define _PAGE_PRESENT 0x001 /* software: pte contains a translation */
360#define _PAGE_HASHPTE 0x002 /* hash_page has made an HPTE for this pte */
361#define _PAGE_FILE 0x004 /* when !present: nonlinear file mapping */
362#define _PAGE_USER 0x004 /* usermode access allowed */
363#define _PAGE_GUARDED 0x008 /* G: prohibit speculative access */
364#define _PAGE_COHERENT 0x010 /* M: enforce memory coherence (SMP systems) */
365#define _PAGE_NO_CACHE 0x020 /* I: cache inhibit */
366#define _PAGE_WRITETHRU 0x040 /* W: cache write-through */
367#define _PAGE_DIRTY 0x080 /* C: page changed */
368#define _PAGE_ACCESSED 0x100 /* R: page referenced */
369#define _PAGE_EXEC 0x200 /* software: i-cache coherency required */
370#define _PAGE_RW 0x400 /* software: user write access allowed */
371#define _PAGE_SPECIAL 0x800 /* software: Special page */
372
373#ifdef CONFIG_PTE_64BIT
374/* We never clear the high word of the pte */
375#define _PTE_NONE_MASK (0xffffffff00000000ULL | _PAGE_HASHPTE)
376#else
377#define _PTE_NONE_MASK _PAGE_HASHPTE
378#endif 98#endif
379 99
380#define _PMD_PRESENT 0 100/* If _PAGE_SPECIAL is defined, then we advertise our support for it */
381#define _PMD_PRESENT_MASK (PAGE_MASK) 101#ifdef _PAGE_SPECIAL
382#define _PMD_BAD (~PAGE_MASK)
383
384/* Hash table based platforms need atomic updates of the linux PTE */
385#define PTE_ATOMIC_UPDATES 1
386
387#define __HAVE_ARCH_PTE_SPECIAL 102#define __HAVE_ARCH_PTE_SPECIAL
388
389#endif 103#endif
390 104
391/* 105/*
392 * Some bits are only used on some cpu families... 106 * Some bits are only used on some cpu families... Make sure that all
107 * the undefined gets defined as 0
393 */ 108 */
394#ifndef _PAGE_HASHPTE 109#ifndef _PAGE_HASHPTE
395#define _PAGE_HASHPTE 0 110#define _PAGE_HASHPTE 0
@@ -431,9 +146,29 @@ extern int icache_44x_need_flush;
431 146
432#define _PAGE_HPTEFLAGS _PAGE_HASHPTE 147#define _PAGE_HPTEFLAGS _PAGE_HASHPTE
433 148
434#define _PAGE_CHG_MASK (PAGE_MASK | _PAGE_ACCESSED | _PAGE_DIRTY | \ 149/* Location of the PFN in the PTE. Most platforms use the same as _PAGE_SHIFT
435 _PAGE_SPECIAL) 150 * here (ie, naturally aligned). Platform who don't just pre-define the
151 * value so we don't override it here
152 */
153#ifndef PTE_RPN_SHIFT
154#define PTE_RPN_SHIFT (PAGE_SHIFT)
155#endif
156
157#ifdef CONFIG_PTE_64BIT
158#define PTE_RPN_MAX (1ULL << (64 - PTE_RPN_SHIFT))
159#define PTE_RPN_MASK (~((1ULL<<PTE_RPN_SHIFT)-1))
160#else
161#define PTE_RPN_MAX (1UL << (32 - PTE_RPN_SHIFT))
162#define PTE_RPN_MASK (~((1UL<<PTE_RPN_SHIFT)-1))
163#endif
164
165/* _PAGE_CHG_MASK masks of bits that are to be preserved accross
166 * pgprot changes
167 */
168#define _PAGE_CHG_MASK (PTE_RPN_MASK | _PAGE_HPTEFLAGS | _PAGE_DIRTY | \
169 _PAGE_ACCESSED | _PAGE_SPECIAL)
436 170
171/* Mask of bits returned by pte_pgprot() */
437#define PAGE_PROT_BITS (_PAGE_GUARDED | _PAGE_COHERENT | _PAGE_NO_CACHE | \ 172#define PAGE_PROT_BITS (_PAGE_GUARDED | _PAGE_COHERENT | _PAGE_NO_CACHE | \
438 _PAGE_WRITETHRU | _PAGE_ENDIAN | \ 173 _PAGE_WRITETHRU | _PAGE_ENDIAN | \
439 _PAGE_USER | _PAGE_ACCESSED | \ 174 _PAGE_USER | _PAGE_ACCESSED | \
@@ -521,18 +256,10 @@ extern unsigned long bad_call_to_PMD_PAGE_SIZE(void);
521 * Conversions between PTE values and page frame numbers. 256 * Conversions between PTE values and page frame numbers.
522 */ 257 */
523 258
524/* in some case we want to additionaly adjust where the pfn is in the pte to 259#define pte_pfn(x) (pte_val(x) >> PTE_RPN_SHIFT)
525 * allow room for more flags */
526#if defined(CONFIG_FSL_BOOKE) && defined(CONFIG_PTE_64BIT)
527#define PFN_SHIFT_OFFSET (PAGE_SHIFT + 8)
528#else
529#define PFN_SHIFT_OFFSET (PAGE_SHIFT)
530#endif
531
532#define pte_pfn(x) (pte_val(x) >> PFN_SHIFT_OFFSET)
533#define pte_page(x) pfn_to_page(pte_pfn(x)) 260#define pte_page(x) pfn_to_page(pte_pfn(x))
534 261
535#define pfn_pte(pfn, prot) __pte(((pte_basic_t)(pfn) << PFN_SHIFT_OFFSET) |\ 262#define pfn_pte(pfn, prot) __pte(((pte_basic_t)(pfn) << PTE_RPN_SHIFT) |\
536 pgprot_val(prot)) 263 pgprot_val(prot))
537#define mk_pte(page, prot) pfn_pte(page_to_pfn(page), prot) 264#define mk_pte(page, prot) pfn_pte(page_to_pfn(page), prot)
538#endif /* __ASSEMBLY__ */ 265#endif /* __ASSEMBLY__ */
@@ -600,11 +327,19 @@ extern void flush_hash_entry(struct mm_struct *mm, pte_t *ptep,
600 unsigned long address); 327 unsigned long address);
601 328
602/* 329/*
603 * Atomic PTE updates. 330 * PTE updates. This function is called whenever an existing
331 * valid PTE is updated. This does -not- include set_pte_at()
332 * which nowadays only sets a new PTE.
333 *
334 * Depending on the type of MMU, we may need to use atomic updates
335 * and the PTE may be either 32 or 64 bit wide. In the later case,
336 * when using atomic updates, only the low part of the PTE is
337 * accessed atomically.
604 * 338 *
605 * pte_update clears and sets bit atomically, and returns 339 * In addition, on 44x, we also maintain a global flag indicating
606 * the old pte value. In the 64-bit PTE case we lock around the 340 * that an executable user mapping was modified, which is needed
607 * low PTE word since we expect ALL flag bits to be there 341 * to properly flush the virtually tagged instruction cache of
342 * those implementations.
608 */ 343 */
609#ifndef CONFIG_PTE_64BIT 344#ifndef CONFIG_PTE_64BIT
610static inline unsigned long pte_update(pte_t *p, 345static inline unsigned long pte_update(pte_t *p,
diff --git a/arch/powerpc/include/asm/pgtable-4k.h b/arch/powerpc/include/asm/pgtable-ppc64-4k.h
index 1dbca4e7de67..6eefdcffa359 100644
--- a/arch/powerpc/include/asm/pgtable-4k.h
+++ b/arch/powerpc/include/asm/pgtable-ppc64-4k.h
@@ -1,5 +1,5 @@
1#ifndef _ASM_POWERPC_PGTABLE_4K_H 1#ifndef _ASM_POWERPC_PGTABLE_PPC64_4K_H
2#define _ASM_POWERPC_PGTABLE_4K_H 2#define _ASM_POWERPC_PGTABLE_PPC64_4K_H
3/* 3/*
4 * Entries per page directory level. The PTE level must use a 64b record 4 * Entries per page directory level. The PTE level must use a 64b record
5 * for each page table entry. The PMD and PGD level use a 32b record for 5 * for each page table entry. The PMD and PGD level use a 32b record for
@@ -40,28 +40,6 @@
40#define PGDIR_SIZE (1UL << PGDIR_SHIFT) 40#define PGDIR_SIZE (1UL << PGDIR_SHIFT)
41#define PGDIR_MASK (~(PGDIR_SIZE-1)) 41#define PGDIR_MASK (~(PGDIR_SIZE-1))
42 42
43/* PTE bits */
44#define _PAGE_HASHPTE 0x0400 /* software: pte has an associated HPTE */
45#define _PAGE_SECONDARY 0x8000 /* software: HPTE is in secondary group */
46#define _PAGE_GROUP_IX 0x7000 /* software: HPTE index within group */
47#define _PAGE_F_SECOND _PAGE_SECONDARY
48#define _PAGE_F_GIX _PAGE_GROUP_IX
49#define _PAGE_SPECIAL 0x10000 /* software: special page */
50#define __HAVE_ARCH_PTE_SPECIAL
51
52/* PTE flags to conserve for HPTE identification */
53#define _PAGE_HPTEFLAGS (_PAGE_BUSY | _PAGE_HASHPTE | \
54 _PAGE_SECONDARY | _PAGE_GROUP_IX)
55
56/* There is no 4K PFN hack on 4K pages */
57#define _PAGE_4K_PFN 0
58
59/* PAGE_MASK gives the right answer below, but only by accident */
60/* It should be preserving the high 48 bits and then specifically */
61/* preserving _PAGE_SECONDARY | _PAGE_GROUP_IX */
62#define _PAGE_CHG_MASK (PAGE_MASK | _PAGE_ACCESSED | _PAGE_DIRTY | \
63 _PAGE_HPTEFLAGS | _PAGE_SPECIAL)
64
65/* Bits to mask out from a PMD to get to the PTE page */ 43/* Bits to mask out from a PMD to get to the PTE page */
66#define PMD_MASKED_BITS 0 44#define PMD_MASKED_BITS 0
67/* Bits to mask out from a PUD to get to the PMD page */ 45/* Bits to mask out from a PUD to get to the PMD page */
@@ -69,30 +47,6 @@
69/* Bits to mask out from a PGD to get to the PUD page */ 47/* Bits to mask out from a PGD to get to the PUD page */
70#define PGD_MASKED_BITS 0 48#define PGD_MASKED_BITS 0
71 49
72/* shift to put page number into pte */
73#define PTE_RPN_SHIFT (17)
74
75#ifdef STRICT_MM_TYPECHECKS
76#define __real_pte(e,p) ((real_pte_t){(e)})
77#define __rpte_to_pte(r) ((r).pte)
78#else
79#define __real_pte(e,p) (e)
80#define __rpte_to_pte(r) (__pte(r))
81#endif
82#define __rpte_to_hidx(r,index) (pte_val(__rpte_to_pte(r)) >> 12)
83
84#define pte_iterate_hashed_subpages(rpte, psize, va, index, shift) \
85 do { \
86 index = 0; \
87 shift = mmu_psize_defs[psize].shift; \
88
89#define pte_iterate_hashed_end() } while(0)
90
91#ifdef CONFIG_PPC_HAS_HASH_64K
92#define pte_pagesize_index(mm, addr, pte) get_slice_psize(mm, addr)
93#else
94#define pte_pagesize_index(mm, addr, pte) MMU_PAGE_4K
95#endif
96 50
97/* 51/*
98 * 4-level page tables related bits 52 * 4-level page tables related bits
@@ -112,6 +66,9 @@
112#define pud_ERROR(e) \ 66#define pud_ERROR(e) \
113 printk("%s:%d: bad pud %08lx.\n", __FILE__, __LINE__, pud_val(e)) 67 printk("%s:%d: bad pud %08lx.\n", __FILE__, __LINE__, pud_val(e))
114 68
69/*
70 * On all 4K setups, remap_4k_pfn() equates to remap_pfn_range() */
115#define remap_4k_pfn(vma, addr, pfn, prot) \ 71#define remap_4k_pfn(vma, addr, pfn, prot) \
116 remap_pfn_range((vma), (addr), (pfn), PAGE_SIZE, (prot)) 72 remap_pfn_range((vma), (addr), (pfn), PAGE_SIZE, (prot))
117#endif /* _ASM_POWERPC_PGTABLE_4K_H */ 73
74#endif /* _ASM_POWERPC_PGTABLE_PPC64_4K_H */
diff --git a/arch/powerpc/include/asm/pgtable-ppc64-64k.h b/arch/powerpc/include/asm/pgtable-ppc64-64k.h
new file mode 100644
index 000000000000..6cc085b945a5
--- /dev/null
+++ b/arch/powerpc/include/asm/pgtable-ppc64-64k.h
@@ -0,0 +1,42 @@
1#ifndef _ASM_POWERPC_PGTABLE_PPC64_64K_H
2#define _ASM_POWERPC_PGTABLE_PPC64_64K_H
3
4#include <asm-generic/pgtable-nopud.h>
5
6
7#define PTE_INDEX_SIZE 12
8#define PMD_INDEX_SIZE 12
9#define PUD_INDEX_SIZE 0
10#define PGD_INDEX_SIZE 4
11
12#ifndef __ASSEMBLY__
13
14#define PTE_TABLE_SIZE (sizeof(real_pte_t) << PTE_INDEX_SIZE)
15#define PMD_TABLE_SIZE (sizeof(pmd_t) << PMD_INDEX_SIZE)
16#define PGD_TABLE_SIZE (sizeof(pgd_t) << PGD_INDEX_SIZE)
17
18#define PTRS_PER_PTE (1 << PTE_INDEX_SIZE)
19#define PTRS_PER_PMD (1 << PMD_INDEX_SIZE)
20#define PTRS_PER_PGD (1 << PGD_INDEX_SIZE)
21
22/* With 4k base page size, hugepage PTEs go at the PMD level */
23#define MIN_HUGEPTE_SHIFT PAGE_SHIFT
24
25/* PMD_SHIFT determines what a second-level page table entry can map */
26#define PMD_SHIFT (PAGE_SHIFT + PTE_INDEX_SIZE)
27#define PMD_SIZE (1UL << PMD_SHIFT)
28#define PMD_MASK (~(PMD_SIZE-1))
29
30/* PGDIR_SHIFT determines what a third-level page table entry can map */
31#define PGDIR_SHIFT (PMD_SHIFT + PMD_INDEX_SIZE)
32#define PGDIR_SIZE (1UL << PGDIR_SHIFT)
33#define PGDIR_MASK (~(PGDIR_SIZE-1))
34
35#endif /* __ASSEMBLY__ */
36
37/* Bits to mask out from a PMD to get to the PTE page */
38#define PMD_MASKED_BITS 0x1ff
39/* Bits to mask out from a PGD/PUD to get to the PMD page */
40#define PUD_MASKED_BITS 0x1ff
41
42#endif /* _ASM_POWERPC_PGTABLE_PPC64_64K_H */
diff --git a/arch/powerpc/include/asm/pgtable-ppc64.h b/arch/powerpc/include/asm/pgtable-ppc64.h
index c627877fcf16..542073836b29 100644
--- a/arch/powerpc/include/asm/pgtable-ppc64.h
+++ b/arch/powerpc/include/asm/pgtable-ppc64.h
@@ -11,9 +11,9 @@
11#endif /* __ASSEMBLY__ */ 11#endif /* __ASSEMBLY__ */
12 12
13#ifdef CONFIG_PPC_64K_PAGES 13#ifdef CONFIG_PPC_64K_PAGES
14#include <asm/pgtable-64k.h> 14#include <asm/pgtable-ppc64-64k.h>
15#else 15#else
16#include <asm/pgtable-4k.h> 16#include <asm/pgtable-ppc64-4k.h>
17#endif 17#endif
18 18
19#define FIRST_USER_ADDRESS 0 19#define FIRST_USER_ADDRESS 0
@@ -25,6 +25,8 @@
25 PUD_INDEX_SIZE + PGD_INDEX_SIZE + PAGE_SHIFT) 25 PUD_INDEX_SIZE + PGD_INDEX_SIZE + PAGE_SHIFT)
26#define PGTABLE_RANGE (ASM_CONST(1) << PGTABLE_EADDR_SIZE) 26#define PGTABLE_RANGE (ASM_CONST(1) << PGTABLE_EADDR_SIZE)
27 27
28
29/* Some sanity checking */
28#if TASK_SIZE_USER64 > PGTABLE_RANGE 30#if TASK_SIZE_USER64 > PGTABLE_RANGE
29#error TASK_SIZE_USER64 exceeds pagetable range 31#error TASK_SIZE_USER64 exceeds pagetable range
30#endif 32#endif
@@ -33,7 +35,6 @@
33#error TASK_SIZE_USER64 exceeds user VSID range 35#error TASK_SIZE_USER64 exceeds user VSID range
34#endif 36#endif
35 37
36
37/* 38/*
38 * Define the address range of the vmalloc VM area. 39 * Define the address range of the vmalloc VM area.
39 */ 40 */
@@ -76,29 +77,26 @@
76 77
77 78
78/* 79/*
79 * Common bits in a linux-style PTE. These match the bits in the 80 * Include the PTE bits definitions
80 * (hardware-defined) PowerPC PTE as closely as possible. Additional
81 * bits may be defined in pgtable-*.h
82 */ 81 */
83#define _PAGE_PRESENT 0x0001 /* software: pte contains a translation */ 82#include <asm/pte-hash64.h>
84#define _PAGE_USER 0x0002 /* matches one of the PP bits */ 83
85#define _PAGE_FILE 0x0002 /* (!present only) software: pte holds file offset */ 84/* To make some generic powerpc code happy */
86#define _PAGE_EXEC 0x0004 /* No execute on POWER4 and newer (we invert) */ 85#ifndef _PAGE_HWEXEC
87#define _PAGE_GUARDED 0x0008 86#define _PAGE_HWEXEC 0
88#define _PAGE_COHERENT 0x0010 /* M: enforce memory coherence (SMP systems) */ 87#endif
89#define _PAGE_NO_CACHE 0x0020 /* I: cache inhibit */ 88
90#define _PAGE_WRITETHRU 0x0040 /* W: cache write-through */ 89/* Some other useful definitions */
91#define _PAGE_DIRTY 0x0080 /* C: page changed */ 90#define PTE_RPN_MAX (1UL << (64 - PTE_RPN_SHIFT))
92#define _PAGE_ACCESSED 0x0100 /* R: page referenced */ 91#define PTE_RPN_MASK (~((1UL<<PTE_RPN_SHIFT)-1))
93#define _PAGE_RW 0x0200 /* software: user write access allowed */ 92
94#define _PAGE_BUSY 0x0800 /* software: PTE & hash are busy */ 93/* _PAGE_CHG_MASK masks of bits that are to be preserved accross
95 94 * pgprot changes
96/* Strong Access Ordering */ 95 */
97#define _PAGE_SAO (_PAGE_WRITETHRU | _PAGE_NO_CACHE | _PAGE_COHERENT) 96#define _PAGE_CHG_MASK (PTE_RPN_MASK | _PAGE_HPTEFLAGS | _PAGE_DIRTY | \
98 97 _PAGE_ACCESSED | _PAGE_SPECIAL)
99#define _PAGE_BASE (_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_COHERENT) 98
100 99
101#define _PAGE_WRENABLE (_PAGE_RW | _PAGE_DIRTY)
102 100
103/* __pgprot defined in arch/powerpc/include/asm/page.h */ 101/* __pgprot defined in arch/powerpc/include/asm/page.h */
104#define PAGE_NONE __pgprot(_PAGE_PRESENT | _PAGE_ACCESSED) 102#define PAGE_NONE __pgprot(_PAGE_PRESENT | _PAGE_ACCESSED)
@@ -117,16 +115,9 @@
117#define PAGE_AGP __pgprot(_PAGE_BASE | _PAGE_WRENABLE | _PAGE_NO_CACHE) 115#define PAGE_AGP __pgprot(_PAGE_BASE | _PAGE_WRENABLE | _PAGE_NO_CACHE)
118#define HAVE_PAGE_AGP 116#define HAVE_PAGE_AGP
119 117
120#define PAGE_PROT_BITS (_PAGE_GUARDED | _PAGE_COHERENT | \ 118/* We always have _PAGE_SPECIAL on 64 bit */
121 _PAGE_NO_CACHE | _PAGE_WRITETHRU | \ 119#define __HAVE_ARCH_PTE_SPECIAL
122 _PAGE_4K_PFN | _PAGE_RW | _PAGE_USER | \
123 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_EXEC)
124/* PTEIDX nibble */
125#define _PTEIDX_SECONDARY 0x8
126#define _PTEIDX_GROUP_IX 0x7
127 120
128/* To make some generic powerpc code happy */
129#define _PAGE_HWEXEC 0
130 121
131/* 122/*
132 * POWER4 and newer have per page execute protection, older chips can only 123 * POWER4 and newer have per page execute protection, older chips can only
@@ -163,6 +154,38 @@
163#ifndef __ASSEMBLY__ 154#ifndef __ASSEMBLY__
164 155
165/* 156/*
157 * This is the default implementation of various PTE accessors, it's
158 * used in all cases except Book3S with 64K pages where we have a
159 * concept of sub-pages
160 */
161#ifndef __real_pte
162
163#ifdef STRICT_MM_TYPECHECKS
164#define __real_pte(e,p) ((real_pte_t){(e)})
165#define __rpte_to_pte(r) ((r).pte)
166#else
167#define __real_pte(e,p) (e)
168#define __rpte_to_pte(r) (__pte(r))
169#endif
170#define __rpte_to_hidx(r,index) (pte_val(__rpte_to_pte(r)) >> 12)
171
172#define pte_iterate_hashed_subpages(rpte, psize, va, index, shift) \
173 do { \
174 index = 0; \
175 shift = mmu_psize_defs[psize].shift; \
176
177#define pte_iterate_hashed_end() } while(0)
178
179#ifdef CONFIG_PPC_HAS_HASH_64K
180#define pte_pagesize_index(mm, addr, pte) get_slice_psize(mm, addr)
181#else
182#define pte_pagesize_index(mm, addr, pte) MMU_PAGE_4K
183#endif
184
185#endif /* __real_pte */
186
187
188/*
166 * Conversion functions: convert a page and protection to a page entry, 189 * Conversion functions: convert a page and protection to a page entry,
167 * and a page entry and page directory to the page they refer to. 190 * and a page entry and page directory to the page they refer to.
168 * 191 *
diff --git a/arch/powerpc/include/asm/pte-40x.h b/arch/powerpc/include/asm/pte-40x.h
new file mode 100644
index 000000000000..07630faae029
--- /dev/null
+++ b/arch/powerpc/include/asm/pte-40x.h
@@ -0,0 +1,64 @@
1#ifndef _ASM_POWERPC_PTE_40x_H
2#define _ASM_POWERPC_PTE_40x_H
3#ifdef __KERNEL__
4
5/*
6 * At present, all PowerPC 400-class processors share a similar TLB
7 * architecture. The instruction and data sides share a unified,
8 * 64-entry, fully-associative TLB which is maintained totally under
9 * software control. In addition, the instruction side has a
10 * hardware-managed, 4-entry, fully-associative TLB which serves as a
11 * first level to the shared TLB. These two TLBs are known as the UTLB
12 * and ITLB, respectively (see "mmu.h" for definitions).
13 *
14 * There are several potential gotchas here. The 40x hardware TLBLO
15 * field looks like this:
16 *
17 * 0 1 2 3 4 ... 18 19 20 21 22 23 24 25 26 27 28 29 30 31
18 * RPN..................... 0 0 EX WR ZSEL....... W I M G
19 *
20 * Where possible we make the Linux PTE bits match up with this
21 *
22 * - bits 20 and 21 must be cleared, because we use 4k pages (40x can
23 * support down to 1k pages), this is done in the TLBMiss exception
24 * handler.
25 * - We use only zones 0 (for kernel pages) and 1 (for user pages)
26 * of the 16 available. Bit 24-26 of the TLB are cleared in the TLB
27 * miss handler. Bit 27 is PAGE_USER, thus selecting the correct
28 * zone.
29 * - PRESENT *must* be in the bottom two bits because swap cache
30 * entries use the top 30 bits. Because 40x doesn't support SMP
31 * anyway, M is irrelevant so we borrow it for PAGE_PRESENT. Bit 30
32 * is cleared in the TLB miss handler before the TLB entry is loaded.
33 * - All other bits of the PTE are loaded into TLBLO without
34 * modification, leaving us only the bits 20, 21, 24, 25, 26, 30 for
35 * software PTE bits. We actually use use bits 21, 24, 25, and
36 * 30 respectively for the software bits: ACCESSED, DIRTY, RW, and
37 * PRESENT.
38 */
39
40#define _PAGE_GUARDED 0x001 /* G: page is guarded from prefetch */
41#define _PAGE_FILE 0x001 /* when !present: nonlinear file mapping */
42#define _PAGE_PRESENT 0x002 /* software: PTE contains a translation */
43#define _PAGE_NO_CACHE 0x004 /* I: caching is inhibited */
44#define _PAGE_WRITETHRU 0x008 /* W: caching is write-through */
45#define _PAGE_USER 0x010 /* matches one of the zone permission bits */
46#define _PAGE_RW 0x040 /* software: Writes permitted */
47#define _PAGE_DIRTY 0x080 /* software: dirty page */
48#define _PAGE_HWWRITE 0x100 /* hardware: Dirty & RW, set in exception */
49#define _PAGE_HWEXEC 0x200 /* hardware: EX permission */
50#define _PAGE_ACCESSED 0x400 /* software: R: page referenced */
51
52#define _PMD_PRESENT 0x400 /* PMD points to page of PTEs */
53#define _PMD_BAD 0x802
54#define _PMD_SIZE 0x0e0 /* size field, != 0 for large-page PMD entry */
55#define _PMD_SIZE_4M 0x0c0
56#define _PMD_SIZE_16M 0x0e0
57
58#define PMD_PAGE_SIZE(pmdval) (1024 << (((pmdval) & _PMD_SIZE) >> 4))
59
60/* Until my rework is finished, 40x still needs atomic PTE updates */
61#define PTE_ATOMIC_UPDATES 1
62
63#endif /* __KERNEL__ */
64#endif /* _ASM_POWERPC_PTE_40x_H */
diff --git a/arch/powerpc/include/asm/pte-44x.h b/arch/powerpc/include/asm/pte-44x.h
new file mode 100644
index 000000000000..37e98bcf83e0
--- /dev/null
+++ b/arch/powerpc/include/asm/pte-44x.h
@@ -0,0 +1,102 @@
1#ifndef _ASM_POWERPC_PTE_44x_H
2#define _ASM_POWERPC_PTE_44x_H
3#ifdef __KERNEL__
4
5/*
6 * Definitions for PPC440
7 *
8 * Because of the 3 word TLB entries to support 36-bit addressing,
9 * the attribute are difficult to map in such a fashion that they
10 * are easily loaded during exception processing. I decided to
11 * organize the entry so the ERPN is the only portion in the
12 * upper word of the PTE and the attribute bits below are packed
13 * in as sensibly as they can be in the area below a 4KB page size
14 * oriented RPN. This at least makes it easy to load the RPN and
15 * ERPN fields in the TLB. -Matt
16 *
17 * This isn't entirely true anymore, at least some bits are now
18 * easier to move into the TLB from the PTE. -BenH.
19 *
20 * Note that these bits preclude future use of a page size
21 * less than 4KB.
22 *
23 *
24 * PPC 440 core has following TLB attribute fields;
25 *
26 * TLB1:
27 * 0 1 2 3 4 ... 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
28 * RPN................................. - - - - - - ERPN.......
29 *
30 * TLB2:
31 * 0 1 2 3 4 ... 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
32 * - - - - - - U0 U1 U2 U3 W I M G E - UX UW UR SX SW SR
33 *
34 * Newer 440 cores (440x6 as used on AMCC 460EX/460GT) have additional
35 * TLB2 storage attibute fields. Those are:
36 *
37 * TLB2:
38 * 0...10 11 12 13 14 15 16...31
39 * no change WL1 IL1I IL1D IL2I IL2D no change
40 *
41 * There are some constrains and options, to decide mapping software bits
42 * into TLB entry.
43 *
44 * - PRESENT *must* be in the bottom three bits because swap cache
45 * entries use the top 29 bits for TLB2.
46 *
47 * - FILE *must* be in the bottom three bits because swap cache
48 * entries use the top 29 bits for TLB2.
49 *
50 * - CACHE COHERENT bit (M) has no effect on original PPC440 cores,
51 * because it doesn't support SMP. However, some later 460 variants
52 * have -some- form of SMP support and so I keep the bit there for
53 * future use
54 *
55 * With the PPC 44x Linux implementation, the 0-11th LSBs of the PTE are used
56 * for memory protection related functions (see PTE structure in
57 * include/asm-ppc/mmu.h). The _PAGE_XXX definitions in this file map to the
58 * above bits. Note that the bit values are CPU specific, not architecture
59 * specific.
60 *
61 * The kernel PTE entry holds an arch-dependent swp_entry structure under
62 * certain situations. In other words, in such situations some portion of
63 * the PTE bits are used as a swp_entry. In the PPC implementation, the
64 * 3-24th LSB are shared with swp_entry, however the 0-2nd three LSB still
65 * hold protection values. That means the three protection bits are
66 * reserved for both PTE and SWAP entry at the most significant three
67 * LSBs.
68 *
69 * There are three protection bits available for SWAP entry:
70 * _PAGE_PRESENT
71 * _PAGE_FILE
72 * _PAGE_HASHPTE (if HW has)
73 *
74 * So those three bits have to be inside of 0-2nd LSB of PTE.
75 *
76 */
77
78#define _PAGE_PRESENT 0x00000001 /* S: PTE valid */
79#define _PAGE_RW 0x00000002 /* S: Write permission */
80#define _PAGE_FILE 0x00000004 /* S: nonlinear file mapping */
81#define _PAGE_HWEXEC 0x00000004 /* H: Execute permission */
82#define _PAGE_ACCESSED 0x00000008 /* S: Page referenced */
83#define _PAGE_DIRTY 0x00000010 /* S: Page dirty */
84#define _PAGE_SPECIAL 0x00000020 /* S: Special page */
85#define _PAGE_USER 0x00000040 /* S: User page */
86#define _PAGE_ENDIAN 0x00000080 /* H: E bit */
87#define _PAGE_GUARDED 0x00000100 /* H: G bit */
88#define _PAGE_COHERENT 0x00000200 /* H: M bit */
89#define _PAGE_NO_CACHE 0x00000400 /* H: I bit */
90#define _PAGE_WRITETHRU 0x00000800 /* H: W bit */
91
92/* TODO: Add large page lowmem mapping support */
93#define _PMD_PRESENT 0
94#define _PMD_PRESENT_MASK (PAGE_MASK)
95#define _PMD_BAD (~PAGE_MASK)
96
97/* ERPN in a PTE never gets cleared, ignore it */
98#define _PTE_NONE_MASK 0xffffffff00000000ULL
99
100
101#endif /* __KERNEL__ */
102#endif /* _ASM_POWERPC_PTE_44x_H */
diff --git a/arch/powerpc/include/asm/pte-8xx.h b/arch/powerpc/include/asm/pte-8xx.h
new file mode 100644
index 000000000000..b07acfd330b0
--- /dev/null
+++ b/arch/powerpc/include/asm/pte-8xx.h
@@ -0,0 +1,64 @@
1#ifndef _ASM_POWERPC_PTE_8xx_H
2#define _ASM_POWERPC_PTE_8xx_H
3#ifdef __KERNEL__
4
5/*
6 * The PowerPC MPC8xx uses a TLB with hardware assisted, software tablewalk.
7 * We also use the two level tables, but we can put the real bits in them
8 * needed for the TLB and tablewalk. These definitions require Mx_CTR.PPM = 0,
9 * Mx_CTR.PPCS = 0, and MD_CTR.TWAM = 1. The level 2 descriptor has
10 * additional page protection (when Mx_CTR.PPCS = 1) that allows TLB hit
11 * based upon user/super access. The TLB does not have accessed nor write
12 * protect. We assume that if the TLB get loaded with an entry it is
13 * accessed, and overload the changed bit for write protect. We use
14 * two bits in the software pte that are supposed to be set to zero in
15 * the TLB entry (24 and 25) for these indicators. Although the level 1
16 * descriptor contains the guarded and writethrough/copyback bits, we can
17 * set these at the page level since they get copied from the Mx_TWC
18 * register when the TLB entry is loaded. We will use bit 27 for guard, since
19 * that is where it exists in the MD_TWC, and bit 26 for writethrough.
20 * These will get masked from the level 2 descriptor at TLB load time, and
21 * copied to the MD_TWC before it gets loaded.
22 * Large page sizes added. We currently support two sizes, 4K and 8M.
23 * This also allows a TLB hander optimization because we can directly
24 * load the PMD into MD_TWC. The 8M pages are only used for kernel
25 * mapping of well known areas. The PMD (PGD) entries contain control
26 * flags in addition to the address, so care must be taken that the
27 * software no longer assumes these are only pointers.
28 */
29
30/* Definitions for 8xx embedded chips. */
31#define _PAGE_PRESENT 0x0001 /* Page is valid */
32#define _PAGE_FILE 0x0002 /* when !present: nonlinear file mapping */
33#define _PAGE_NO_CACHE 0x0002 /* I: cache inhibit */
34#define _PAGE_SHARED 0x0004 /* No ASID (context) compare */
35
36/* These five software bits must be masked out when the entry is loaded
37 * into the TLB.
38 */
39#define _PAGE_EXEC 0x0008 /* software: i-cache coherency required */
40#define _PAGE_GUARDED 0x0010 /* software: guarded access */
41#define _PAGE_DIRTY 0x0020 /* software: page changed */
42#define _PAGE_RW 0x0040 /* software: user write access allowed */
43#define _PAGE_ACCESSED 0x0080 /* software: page referenced */
44
45/* Setting any bits in the nibble with the follow two controls will
46 * require a TLB exception handler change. It is assumed unused bits
47 * are always zero.
48 */
49#define _PAGE_HWWRITE 0x0100 /* h/w write enable: never set in Linux PTE */
50#define _PAGE_USER 0x0800 /* One of the PP bits, the other is USER&~RW */
51
52#define _PMD_PRESENT 0x0001
53#define _PMD_BAD 0x0ff0
54#define _PMD_PAGE_MASK 0x000c
55#define _PMD_PAGE_8M 0x000c
56
57#define _PTE_NONE_MASK _PAGE_ACCESSED
58
59/* Until my rework is finished, 8xx still needs atomic PTE updates */
60#define PTE_ATOMIC_UPDATES 1
61
62
63#endif /* __KERNEL__ */
64#endif /* _ASM_POWERPC_PTE_8xx_H */
diff --git a/arch/powerpc/include/asm/pte-fsl-booke.h b/arch/powerpc/include/asm/pte-fsl-booke.h
new file mode 100644
index 000000000000..10820f58acf5
--- /dev/null
+++ b/arch/powerpc/include/asm/pte-fsl-booke.h
@@ -0,0 +1,48 @@
1#ifndef _ASM_POWERPC_PTE_FSL_BOOKE_H
2#define _ASM_POWERPC_PTE_FSL_BOOKE_H
3#ifdef __KERNEL__
4
5/* PTE bit definitions for Freescale BookE SW loaded TLB MMU based
6 * processors
7 *
8 MMU Assist Register 3:
9
10 32 33 34 35 36 ... 50 51 52 53 54 55 56 57 58 59 60 61 62 63
11 RPN...................... 0 0 U0 U1 U2 U3 UX SX UW SW UR SR
12
13 - PRESENT *must* be in the bottom three bits because swap cache
14 entries use the top 29 bits.
15
16 - FILE *must* be in the bottom three bits because swap cache
17 entries use the top 29 bits.
18*/
19
20/* Definitions for FSL Book-E Cores */
21#define _PAGE_PRESENT 0x00001 /* S: PTE contains a translation */
22#define _PAGE_USER 0x00002 /* S: User page (maps to UR) */
23#define _PAGE_FILE 0x00002 /* S: when !present: nonlinear file mapping */
24#define _PAGE_RW 0x00004 /* S: Write permission (SW) */
25#define _PAGE_DIRTY 0x00008 /* S: Page dirty */
26#define _PAGE_HWEXEC 0x00010 /* H: SX permission */
27#define _PAGE_ACCESSED 0x00020 /* S: Page referenced */
28
29#define _PAGE_ENDIAN 0x00040 /* H: E bit */
30#define _PAGE_GUARDED 0x00080 /* H: G bit */
31#define _PAGE_COHERENT 0x00100 /* H: M bit */
32#define _PAGE_NO_CACHE 0x00200 /* H: I bit */
33#define _PAGE_WRITETHRU 0x00400 /* H: W bit */
34#define _PAGE_SPECIAL 0x00800 /* S: Special page */
35
36#ifdef CONFIG_PTE_64BIT
37/* ERPN in a PTE never gets cleared, ignore it */
38#define _PTE_NONE_MASK 0xffffffffffff0000ULL
39/* We extend the size of the PTE flags area when using 64-bit PTEs */
40#define PTE_RPN_SHIFT (PAGE_SHIFT + 8)
41#endif
42
43#define _PMD_PRESENT 0
44#define _PMD_PRESENT_MASK (PAGE_MASK)
45#define _PMD_BAD (~PAGE_MASK)
46
47#endif /* __KERNEL__ */
48#endif /* _ASM_POWERPC_PTE_FSL_BOOKE_H */
diff --git a/arch/powerpc/include/asm/pte-hash32.h b/arch/powerpc/include/asm/pte-hash32.h
new file mode 100644
index 000000000000..6afe22b02f2f
--- /dev/null
+++ b/arch/powerpc/include/asm/pte-hash32.h
@@ -0,0 +1,49 @@
1#ifndef _ASM_POWERPC_PTE_HASH32_H
2#define _ASM_POWERPC_PTE_HASH32_H
3#ifdef __KERNEL__
4
5/*
6 * The "classic" 32-bit implementation of the PowerPC MMU uses a hash
7 * table containing PTEs, together with a set of 16 segment registers,
8 * to define the virtual to physical address mapping.
9 *
10 * We use the hash table as an extended TLB, i.e. a cache of currently
11 * active mappings. We maintain a two-level page table tree, much
12 * like that used by the i386, for the sake of the Linux memory
13 * management code. Low-level assembler code in hash_low_32.S
14 * (procedure hash_page) is responsible for extracting ptes from the
15 * tree and putting them into the hash table when necessary, and
16 * updating the accessed and modified bits in the page table tree.
17 */
18
19#define _PAGE_PRESENT 0x001 /* software: pte contains a translation */
20#define _PAGE_HASHPTE 0x002 /* hash_page has made an HPTE for this pte */
21#define _PAGE_FILE 0x004 /* when !present: nonlinear file mapping */
22#define _PAGE_USER 0x004 /* usermode access allowed */
23#define _PAGE_GUARDED 0x008 /* G: prohibit speculative access */
24#define _PAGE_COHERENT 0x010 /* M: enforce memory coherence (SMP systems) */
25#define _PAGE_NO_CACHE 0x020 /* I: cache inhibit */
26#define _PAGE_WRITETHRU 0x040 /* W: cache write-through */
27#define _PAGE_DIRTY 0x080 /* C: page changed */
28#define _PAGE_ACCESSED 0x100 /* R: page referenced */
29#define _PAGE_EXEC 0x200 /* software: i-cache coherency required */
30#define _PAGE_RW 0x400 /* software: user write access allowed */
31#define _PAGE_SPECIAL 0x800 /* software: Special page */
32
33#ifdef CONFIG_PTE_64BIT
34/* We never clear the high word of the pte */
35#define _PTE_NONE_MASK (0xffffffff00000000ULL | _PAGE_HASHPTE)
36#else
37#define _PTE_NONE_MASK _PAGE_HASHPTE
38#endif
39
40#define _PMD_PRESENT 0
41#define _PMD_PRESENT_MASK (PAGE_MASK)
42#define _PMD_BAD (~PAGE_MASK)
43
44/* Hash table based platforms need atomic updates of the linux PTE */
45#define PTE_ATOMIC_UPDATES 1
46
47
48#endif /* __KERNEL__ */
49#endif /* _ASM_POWERPC_PTE_HASH32_H */
diff --git a/arch/powerpc/include/asm/pte-hash64-4k.h b/arch/powerpc/include/asm/pte-hash64-4k.h
new file mode 100644
index 000000000000..29fdc158fe3f
--- /dev/null
+++ b/arch/powerpc/include/asm/pte-hash64-4k.h
@@ -0,0 +1,20 @@
1/* To be include by pgtable-hash64.h only */
2
3/* PTE bits */
4#define _PAGE_HASHPTE 0x0400 /* software: pte has an associated HPTE */
5#define _PAGE_SECONDARY 0x8000 /* software: HPTE is in secondary group */
6#define _PAGE_GROUP_IX 0x7000 /* software: HPTE index within group */
7#define _PAGE_F_SECOND _PAGE_SECONDARY
8#define _PAGE_F_GIX _PAGE_GROUP_IX
9#define _PAGE_SPECIAL 0x10000 /* software: special page */
10
11/* There is no 4K PFN hack on 4K pages */
12#define _PAGE_4K_PFN 0
13
14/* PTE flags to conserve for HPTE identification */
15#define _PAGE_HPTEFLAGS (_PAGE_BUSY | _PAGE_HASHPTE | \
16 _PAGE_SECONDARY | _PAGE_GROUP_IX)
17
18/* shift to put page number into pte */
19#define PTE_RPN_SHIFT (17)
20
diff --git a/arch/powerpc/include/asm/pgtable-64k.h b/arch/powerpc/include/asm/pte-hash64-64k.h
index 7389003349a6..e05d26fa372f 100644
--- a/arch/powerpc/include/asm/pgtable-64k.h
+++ b/arch/powerpc/include/asm/pte-hash64-64k.h
@@ -1,76 +1,6 @@
1#ifndef _ASM_POWERPC_PGTABLE_64K_H 1/* To be include by pgtable-hash64.h only */
2#define _ASM_POWERPC_PGTABLE_64K_H
3
4#include <asm-generic/pgtable-nopud.h>
5
6
7#define PTE_INDEX_SIZE 12
8#define PMD_INDEX_SIZE 12
9#define PUD_INDEX_SIZE 0
10#define PGD_INDEX_SIZE 4
11
12#ifndef __ASSEMBLY__
13#define PTE_TABLE_SIZE (sizeof(real_pte_t) << PTE_INDEX_SIZE)
14#define PMD_TABLE_SIZE (sizeof(pmd_t) << PMD_INDEX_SIZE)
15#define PGD_TABLE_SIZE (sizeof(pgd_t) << PGD_INDEX_SIZE)
16
17#define PTRS_PER_PTE (1 << PTE_INDEX_SIZE)
18#define PTRS_PER_PMD (1 << PMD_INDEX_SIZE)
19#define PTRS_PER_PGD (1 << PGD_INDEX_SIZE)
20
21#ifdef CONFIG_PPC_SUBPAGE_PROT
22/*
23 * For the sub-page protection option, we extend the PGD with one of
24 * these. Basically we have a 3-level tree, with the top level being
25 * the protptrs array. To optimize speed and memory consumption when
26 * only addresses < 4GB are being protected, pointers to the first
27 * four pages of sub-page protection words are stored in the low_prot
28 * array.
29 * Each page of sub-page protection words protects 1GB (4 bytes
30 * protects 64k). For the 3-level tree, each page of pointers then
31 * protects 8TB.
32 */
33struct subpage_prot_table {
34 unsigned long maxaddr; /* only addresses < this are protected */
35 unsigned int **protptrs[2];
36 unsigned int *low_prot[4];
37};
38
39#undef PGD_TABLE_SIZE
40#define PGD_TABLE_SIZE ((sizeof(pgd_t) << PGD_INDEX_SIZE) + \
41 sizeof(struct subpage_prot_table))
42
43#define SBP_L1_BITS (PAGE_SHIFT - 2)
44#define SBP_L2_BITS (PAGE_SHIFT - 3)
45#define SBP_L1_COUNT (1 << SBP_L1_BITS)
46#define SBP_L2_COUNT (1 << SBP_L2_BITS)
47#define SBP_L2_SHIFT (PAGE_SHIFT + SBP_L1_BITS)
48#define SBP_L3_SHIFT (SBP_L2_SHIFT + SBP_L2_BITS)
49
50extern void subpage_prot_free(pgd_t *pgd);
51
52static inline struct subpage_prot_table *pgd_subpage_prot(pgd_t *pgd)
53{
54 return (struct subpage_prot_table *)(pgd + PTRS_PER_PGD);
55}
56#endif /* CONFIG_PPC_SUBPAGE_PROT */
57#endif /* __ASSEMBLY__ */
58
59/* With 4k base page size, hugepage PTEs go at the PMD level */
60#define MIN_HUGEPTE_SHIFT PAGE_SHIFT
61
62/* PMD_SHIFT determines what a second-level page table entry can map */
63#define PMD_SHIFT (PAGE_SHIFT + PTE_INDEX_SIZE)
64#define PMD_SIZE (1UL << PMD_SHIFT)
65#define PMD_MASK (~(PMD_SIZE-1))
66
67/* PGDIR_SHIFT determines what a third-level page table entry can map */
68#define PGDIR_SHIFT (PMD_SHIFT + PMD_INDEX_SIZE)
69#define PGDIR_SIZE (1UL << PGDIR_SHIFT)
70#define PGDIR_MASK (~(PGDIR_SIZE-1))
71 2
72/* Additional PTE bits (don't change without checking asm in hash_low.S) */ 3/* Additional PTE bits (don't change without checking asm in hash_low.S) */
73#define __HAVE_ARCH_PTE_SPECIAL
74#define _PAGE_SPECIAL 0x00000400 /* software: special page */ 4#define _PAGE_SPECIAL 0x00000400 /* software: special page */
75#define _PAGE_HPTE_SUB 0x0ffff000 /* combo only: sub pages HPTE bits */ 5#define _PAGE_HPTE_SUB 0x0ffff000 /* combo only: sub pages HPTE bits */
76#define _PAGE_HPTE_SUB0 0x08000000 /* combo only: first sub page */ 6#define _PAGE_HPTE_SUB0 0x08000000 /* combo only: first sub page */
@@ -107,21 +37,15 @@ static inline struct subpage_prot_table *pgd_subpage_prot(pgd_t *pgd)
107 * of addressable physical space, or 46 bits for the special 4k PFNs. 37 * of addressable physical space, or 46 bits for the special 4k PFNs.
108 */ 38 */
109#define PTE_RPN_SHIFT (30) 39#define PTE_RPN_SHIFT (30)
110#define PTE_RPN_MAX (1UL << (64 - PTE_RPN_SHIFT))
111#define PTE_RPN_MASK (~((1UL<<PTE_RPN_SHIFT)-1))
112
113/* _PAGE_CHG_MASK masks of bits that are to be preserved accross
114 * pgprot changes
115 */
116#define _PAGE_CHG_MASK (PTE_RPN_MASK | _PAGE_HPTEFLAGS | _PAGE_DIRTY | \
117 _PAGE_ACCESSED | _PAGE_SPECIAL)
118 40
119/* Bits to mask out from a PMD to get to the PTE page */ 41#ifndef __ASSEMBLY__
120#define PMD_MASKED_BITS 0x1ff
121/* Bits to mask out from a PGD/PUD to get to the PMD page */
122#define PUD_MASKED_BITS 0x1ff
123 42
124/* Manipulate "rpte" values */ 43/*
44 * With 64K pages on hash table, we have a special PTE format that
45 * uses a second "half" of the page table to encode sub-page information
46 * in order to deal with 64K made of 4K HW pages. Thus we override the
47 * generic accessors and iterators here
48 */
125#define __real_pte(e,p) ((real_pte_t) { \ 49#define __real_pte(e,p) ((real_pte_t) { \
126 (e), pte_val(*((p) + PTRS_PER_PTE)) }) 50 (e), pte_val(*((p) + PTRS_PER_PTE)) })
127#define __rpte_to_hidx(r,index) ((pte_val((r).pte) & _PAGE_COMBO) ? \ 51#define __rpte_to_hidx(r,index) ((pte_val((r).pte) & _PAGE_COMBO) ? \
@@ -130,7 +54,6 @@ static inline struct subpage_prot_table *pgd_subpage_prot(pgd_t *pgd)
130#define __rpte_sub_valid(rpte, index) \ 54#define __rpte_sub_valid(rpte, index) \
131 (pte_val(rpte.pte) & (_PAGE_HPTE_SUB0 >> (index))) 55 (pte_val(rpte.pte) & (_PAGE_HPTE_SUB0 >> (index)))
132 56
133
134/* Trick: we set __end to va + 64k, which happens works for 57/* Trick: we set __end to va + 64k, which happens works for
135 * a 16M page as well as we want only one iteration 58 * a 16M page as well as we want only one iteration
136 */ 59 */
@@ -152,4 +75,41 @@ static inline struct subpage_prot_table *pgd_subpage_prot(pgd_t *pgd)
152 remap_pfn_range((vma), (addr), (pfn), PAGE_SIZE, \ 75 remap_pfn_range((vma), (addr), (pfn), PAGE_SIZE, \
153 __pgprot(pgprot_val((prot)) | _PAGE_4K_PFN)) 76 __pgprot(pgprot_val((prot)) | _PAGE_4K_PFN))
154 77
155#endif /* _ASM_POWERPC_PGTABLE_64K_H */ 78
79#ifdef CONFIG_PPC_SUBPAGE_PROT
80/*
81 * For the sub-page protection option, we extend the PGD with one of
82 * these. Basically we have a 3-level tree, with the top level being
83 * the protptrs array. To optimize speed and memory consumption when
84 * only addresses < 4GB are being protected, pointers to the first
85 * four pages of sub-page protection words are stored in the low_prot
86 * array.
87 * Each page of sub-page protection words protects 1GB (4 bytes
88 * protects 64k). For the 3-level tree, each page of pointers then
89 * protects 8TB.
90 */
91struct subpage_prot_table {
92 unsigned long maxaddr; /* only addresses < this are protected */
93 unsigned int **protptrs[2];
94 unsigned int *low_prot[4];
95};
96
97#undef PGD_TABLE_SIZE
98#define PGD_TABLE_SIZE ((sizeof(pgd_t) << PGD_INDEX_SIZE) + \
99 sizeof(struct subpage_prot_table))
100
101#define SBP_L1_BITS (PAGE_SHIFT - 2)
102#define SBP_L2_BITS (PAGE_SHIFT - 3)
103#define SBP_L1_COUNT (1 << SBP_L1_BITS)
104#define SBP_L2_COUNT (1 << SBP_L2_BITS)
105#define SBP_L2_SHIFT (PAGE_SHIFT + SBP_L1_BITS)
106#define SBP_L3_SHIFT (SBP_L2_SHIFT + SBP_L2_BITS)
107
108extern void subpage_prot_free(pgd_t *pgd);
109
110static inline struct subpage_prot_table *pgd_subpage_prot(pgd_t *pgd)
111{
112 return (struct subpage_prot_table *)(pgd + PTRS_PER_PGD);
113}
114#endif /* CONFIG_PPC_SUBPAGE_PROT */
115#endif /* __ASSEMBLY__ */
diff --git a/arch/powerpc/include/asm/pte-hash64.h b/arch/powerpc/include/asm/pte-hash64.h
new file mode 100644
index 000000000000..62766636cc1e
--- /dev/null
+++ b/arch/powerpc/include/asm/pte-hash64.h
@@ -0,0 +1,47 @@
1#ifndef _ASM_POWERPC_PTE_HASH64_H
2#define _ASM_POWERPC_PTE_HASH64_H
3#ifdef __KERNEL__
4
5/*
6 * Common bits between 4K and 64K pages in a linux-style PTE.
7 * These match the bits in the (hardware-defined) PowerPC PTE as closely
8 * as possible. Additional bits may be defined in pgtable-hash64-*.h
9 */
10#define _PAGE_PRESENT 0x0001 /* software: pte contains a translation */
11#define _PAGE_USER 0x0002 /* matches one of the PP bits */
12#define _PAGE_FILE 0x0002 /* (!present only) software: pte holds file offset */
13#define _PAGE_EXEC 0x0004 /* No execute on POWER4 and newer (we invert) */
14#define _PAGE_GUARDED 0x0008
15#define _PAGE_COHERENT 0x0010 /* M: enforce memory coherence (SMP systems) */
16#define _PAGE_NO_CACHE 0x0020 /* I: cache inhibit */
17#define _PAGE_WRITETHRU 0x0040 /* W: cache write-through */
18#define _PAGE_DIRTY 0x0080 /* C: page changed */
19#define _PAGE_ACCESSED 0x0100 /* R: page referenced */
20#define _PAGE_RW 0x0200 /* software: user write access allowed */
21#define _PAGE_BUSY 0x0800 /* software: PTE & hash are busy */
22
23/* Strong Access Ordering */
24#define _PAGE_SAO (_PAGE_WRITETHRU | _PAGE_NO_CACHE | _PAGE_COHERENT)
25
26#define _PAGE_BASE (_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_COHERENT)
27
28#define _PAGE_WRENABLE (_PAGE_RW | _PAGE_DIRTY)
29
30/* PTEIDX nibble */
31#define _PTEIDX_SECONDARY 0x8
32#define _PTEIDX_GROUP_IX 0x7
33
34#define PAGE_PROT_BITS (_PAGE_GUARDED | _PAGE_COHERENT | \
35 _PAGE_NO_CACHE | _PAGE_WRITETHRU | \
36 _PAGE_4K_PFN | _PAGE_RW | _PAGE_USER | \
37 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_EXEC)
38
39
40#ifdef CONFIG_PPC_64K_PAGES
41#include <asm/pte-hash64-64k.h>
42#else
43#include <asm/pte-hash64-4k.h>
44#endif
45
46#endif /* __KERNEL__ */
47#endif /* _ASM_POWERPC_PTE_HASH64_H */
diff --git a/arch/powerpc/include/asm/udbg.h b/arch/powerpc/include/asm/udbg.h
index 6418ceea44b7..cd21e5e6b04f 100644
--- a/arch/powerpc/include/asm/udbg.h
+++ b/arch/powerpc/include/asm/udbg.h
@@ -15,6 +15,7 @@
15#include <linux/init.h> 15#include <linux/init.h>
16 16
17extern void (*udbg_putc)(char c); 17extern void (*udbg_putc)(char c);
18extern void (*udbg_flush)(void);
18extern int (*udbg_getc)(void); 19extern int (*udbg_getc)(void);
19extern int (*udbg_getc_poll)(void); 20extern int (*udbg_getc_poll)(void);
20 21
diff --git a/arch/powerpc/kernel/Makefile b/arch/powerpc/kernel/Makefile
index dfec3d2790b2..71901fbda4a5 100644
--- a/arch/powerpc/kernel/Makefile
+++ b/arch/powerpc/kernel/Makefile
@@ -75,7 +75,7 @@ obj-y += time.o prom.o traps.o setup-common.o \
75obj-$(CONFIG_PPC32) += entry_32.o setup_32.o 75obj-$(CONFIG_PPC32) += entry_32.o setup_32.o
76obj-$(CONFIG_PPC64) += dma-iommu.o iommu.o 76obj-$(CONFIG_PPC64) += dma-iommu.o iommu.o
77obj-$(CONFIG_KGDB) += kgdb.o 77obj-$(CONFIG_KGDB) += kgdb.o
78obj-$(CONFIG_PPC_MULTIPLATFORM) += prom_init.o 78obj-$(CONFIG_PPC_OF_BOOT_TRAMPOLINE) += prom_init.o
79obj-$(CONFIG_MODULES) += ppc_ksyms.o 79obj-$(CONFIG_MODULES) += ppc_ksyms.o
80obj-$(CONFIG_BOOTX_TEXT) += btext.o 80obj-$(CONFIG_BOOTX_TEXT) += btext.o
81obj-$(CONFIG_SMP) += smp.o 81obj-$(CONFIG_SMP) += smp.o
diff --git a/arch/powerpc/kernel/cputable.c b/arch/powerpc/kernel/cputable.c
index 638838691b20..ccea2431ddf8 100644
--- a/arch/powerpc/kernel/cputable.c
+++ b/arch/powerpc/kernel/cputable.c
@@ -731,6 +731,8 @@ static struct cpu_spec __initdata cpu_specs[] = {
731 .cpu_setup = __setup_cpu_750, 731 .cpu_setup = __setup_cpu_750,
732 .machine_check = machine_check_generic, 732 .machine_check = machine_check_generic,
733 .platform = "ppc750", 733 .platform = "ppc750",
734 .oprofile_cpu_type = "ppc/750",
735 .oprofile_type = PPC_OPROFILE_G4,
734 }, 736 },
735 { /* 750FX rev 2.0 must disable HID0[DPM] */ 737 { /* 750FX rev 2.0 must disable HID0[DPM] */
736 .pvr_mask = 0xffffffff, 738 .pvr_mask = 0xffffffff,
@@ -746,6 +748,8 @@ static struct cpu_spec __initdata cpu_specs[] = {
746 .cpu_setup = __setup_cpu_750, 748 .cpu_setup = __setup_cpu_750,
747 .machine_check = machine_check_generic, 749 .machine_check = machine_check_generic,
748 .platform = "ppc750", 750 .platform = "ppc750",
751 .oprofile_cpu_type = "ppc/750",
752 .oprofile_type = PPC_OPROFILE_G4,
749 }, 753 },
750 { /* 750FX (All revs except 2.0) */ 754 { /* 750FX (All revs except 2.0) */
751 .pvr_mask = 0xffff0000, 755 .pvr_mask = 0xffff0000,
@@ -761,6 +765,8 @@ static struct cpu_spec __initdata cpu_specs[] = {
761 .cpu_setup = __setup_cpu_750fx, 765 .cpu_setup = __setup_cpu_750fx,
762 .machine_check = machine_check_generic, 766 .machine_check = machine_check_generic,
763 .platform = "ppc750", 767 .platform = "ppc750",
768 .oprofile_cpu_type = "ppc/750",
769 .oprofile_type = PPC_OPROFILE_G4,
764 }, 770 },
765 { /* 750GX */ 771 { /* 750GX */
766 .pvr_mask = 0xffff0000, 772 .pvr_mask = 0xffff0000,
@@ -776,6 +782,8 @@ static struct cpu_spec __initdata cpu_specs[] = {
776 .cpu_setup = __setup_cpu_750fx, 782 .cpu_setup = __setup_cpu_750fx,
777 .machine_check = machine_check_generic, 783 .machine_check = machine_check_generic,
778 .platform = "ppc750", 784 .platform = "ppc750",
785 .oprofile_cpu_type = "ppc/750",
786 .oprofile_type = PPC_OPROFILE_G4,
779 }, 787 },
780 { /* 740/750 (L2CR bit need fixup for 740) */ 788 { /* 740/750 (L2CR bit need fixup for 740) */
781 .pvr_mask = 0xffff0000, 789 .pvr_mask = 0xffff0000,
diff --git a/arch/powerpc/kernel/head_32.S b/arch/powerpc/kernel/head_32.S
index a1c4cfd25ded..f8c2e6b6f457 100644
--- a/arch/powerpc/kernel/head_32.S
+++ b/arch/powerpc/kernel/head_32.S
@@ -108,18 +108,21 @@ __start:
108 * because OF may have I/O devices mapped into that area 108 * because OF may have I/O devices mapped into that area
109 * (particularly on CHRP). 109 * (particularly on CHRP).
110 */ 110 */
111#ifdef CONFIG_PPC_MULTIPLATFORM
112 cmpwi 0,r5,0 111 cmpwi 0,r5,0
113 beq 1f 112 beq 1f
114 113
114#ifdef CONFIG_PPC_OF_BOOT_TRAMPOLINE
115 /* find out where we are now */ 115 /* find out where we are now */
116 bcl 20,31,$+4 116 bcl 20,31,$+4
1170: mflr r8 /* r8 = runtime addr here */ 1170: mflr r8 /* r8 = runtime addr here */
118 addis r8,r8,(_stext - 0b)@ha 118 addis r8,r8,(_stext - 0b)@ha
119 addi r8,r8,(_stext - 0b)@l /* current runtime base addr */ 119 addi r8,r8,(_stext - 0b)@l /* current runtime base addr */
120 bl prom_init 120 bl prom_init
121#endif /* CONFIG_PPC_OF_BOOT_TRAMPOLINE */
122
123 /* We never return. We also hit that trap if trying to boot
124 * from OF while CONFIG_PPC_OF_BOOT_TRAMPOLINE isn't selected */
121 trap 125 trap
122#endif
123 126
124/* 127/*
125 * Check for BootX signature when supporting PowerMac and branch to 128 * Check for BootX signature when supporting PowerMac and branch to
diff --git a/arch/powerpc/kernel/head_64.S b/arch/powerpc/kernel/head_64.S
index ebaedafc8e67..50ef505b8fb6 100644
--- a/arch/powerpc/kernel/head_64.S
+++ b/arch/powerpc/kernel/head_64.S
@@ -1360,6 +1360,7 @@ _GLOBAL(__start_initialization_multiplatform)
1360 b .__after_prom_start 1360 b .__after_prom_start
1361 1361
1362_INIT_STATIC(__boot_from_prom) 1362_INIT_STATIC(__boot_from_prom)
1363#ifdef CONFIG_PPC_OF_BOOT_TRAMPOLINE
1363 /* Save parameters */ 1364 /* Save parameters */
1364 mr r31,r3 1365 mr r31,r3
1365 mr r30,r4 1366 mr r30,r4
@@ -1390,7 +1391,10 @@ _INIT_STATIC(__boot_from_prom)
1390 /* Do all of the interaction with OF client interface */ 1391 /* Do all of the interaction with OF client interface */
1391 mr r8,r26 1392 mr r8,r26
1392 bl .prom_init 1393 bl .prom_init
1393 /* We never return */ 1394#endif /* #CONFIG_PPC_OF_BOOT_TRAMPOLINE */
1395
1396 /* We never return. We also hit that trap if trying to boot
1397 * from OF while CONFIG_PPC_OF_BOOT_TRAMPOLINE isn't selected */
1394 trap 1398 trap
1395 1399
1396_STATIC(__after_prom_start) 1400_STATIC(__after_prom_start)
diff --git a/arch/powerpc/kernel/irq.c b/arch/powerpc/kernel/irq.c
index 23b8b5e36f98..48ea2008b20d 100644
--- a/arch/powerpc/kernel/irq.c
+++ b/arch/powerpc/kernel/irq.c
@@ -171,7 +171,7 @@ int show_interrupts(struct seq_file *p, void *v)
171{ 171{
172 int i = *(loff_t *)v, j; 172 int i = *(loff_t *)v, j;
173 struct irqaction *action; 173 struct irqaction *action;
174 irq_desc_t *desc; 174 struct irq_desc *desc;
175 unsigned long flags; 175 unsigned long flags;
176 176
177 if (i == 0) { 177 if (i == 0) {
@@ -1038,7 +1038,7 @@ arch_initcall(irq_late_init);
1038static int virq_debug_show(struct seq_file *m, void *private) 1038static int virq_debug_show(struct seq_file *m, void *private)
1039{ 1039{
1040 unsigned long flags; 1040 unsigned long flags;
1041 irq_desc_t *desc; 1041 struct irq_desc *desc;
1042 const char *p; 1042 const char *p;
1043 char none[] = "none"; 1043 char none[] = "none";
1044 int i; 1044 int i;
diff --git a/arch/powerpc/kernel/pci-common.c b/arch/powerpc/kernel/pci-common.c
index 2ad17315fc88..2603f20984c4 100644
--- a/arch/powerpc/kernel/pci-common.c
+++ b/arch/powerpc/kernel/pci-common.c
@@ -1482,7 +1482,7 @@ void __init pcibios_resource_survey(void)
1482 * we proceed to assigning things that were left unassigned 1482 * we proceed to assigning things that were left unassigned
1483 */ 1483 */
1484 if (!(ppc_pci_flags & PPC_PCI_PROBE_ONLY)) { 1484 if (!(ppc_pci_flags & PPC_PCI_PROBE_ONLY)) {
1485 pr_debug("PCI: Assigning unassigned resouces...\n"); 1485 pr_debug("PCI: Assigning unassigned resources...\n");
1486 pci_assign_unassigned_resources(); 1486 pci_assign_unassigned_resources();
1487 } 1487 }
1488 1488
diff --git a/arch/powerpc/kernel/prom_init.c b/arch/powerpc/kernel/prom_init.c
index 7f1b33d5e30d..4d5ebb46b2c4 100644
--- a/arch/powerpc/kernel/prom_init.c
+++ b/arch/powerpc/kernel/prom_init.c
@@ -2283,6 +2283,8 @@ unsigned long __init prom_init(unsigned long r3, unsigned long r4,
2283 */ 2283 */
2284 prom_init_stdout(); 2284 prom_init_stdout();
2285 2285
2286 prom_printf("Preparing to boot %s", PTRRELOC((char *)linux_banner));
2287
2286 /* 2288 /*
2287 * Get default machine type. At this point, we do not differentiate 2289 * Get default machine type. At this point, we do not differentiate
2288 * between pSeries SMP and pSeries LPAR 2290 * between pSeries SMP and pSeries LPAR
diff --git a/arch/powerpc/kernel/prom_init_check.sh b/arch/powerpc/kernel/prom_init_check.sh
index ea3a2ec03ffa..1ac136b128f0 100644
--- a/arch/powerpc/kernel/prom_init_check.sh
+++ b/arch/powerpc/kernel/prom_init_check.sh
@@ -20,7 +20,7 @@ WHITELIST="add_reloc_offset __bss_start __bss_stop copy_and_flush
20_end enter_prom memcpy memset reloc_offset __secondary_hold 20_end enter_prom memcpy memset reloc_offset __secondary_hold
21__secondary_hold_acknowledge __secondary_hold_spinloop __start 21__secondary_hold_acknowledge __secondary_hold_spinloop __start
22strcmp strcpy strlcpy strlen strncmp strstr logo_linux_clut224 22strcmp strcpy strlcpy strlen strncmp strstr logo_linux_clut224
23reloc_got2 kernstart_addr memstart_addr" 23reloc_got2 kernstart_addr memstart_addr linux_banner"
24 24
25NM="$1" 25NM="$1"
26OBJ="$2" 26OBJ="$2"
diff --git a/arch/powerpc/kernel/udbg.c b/arch/powerpc/kernel/udbg.c
index 7d6c9bb8c77f..fc9af47e2128 100644
--- a/arch/powerpc/kernel/udbg.c
+++ b/arch/powerpc/kernel/udbg.c
@@ -18,6 +18,7 @@
18#include <asm/udbg.h> 18#include <asm/udbg.h>
19 19
20void (*udbg_putc)(char c); 20void (*udbg_putc)(char c);
21void (*udbg_flush)(void);
21int (*udbg_getc)(void); 22int (*udbg_getc)(void);
22int (*udbg_getc_poll)(void); 23int (*udbg_getc_poll)(void);
23 24
@@ -76,6 +77,9 @@ void udbg_puts(const char *s)
76 while ((c = *s++) != '\0') 77 while ((c = *s++) != '\0')
77 udbg_putc(c); 78 udbg_putc(c);
78 } 79 }
80
81 if (udbg_flush)
82 udbg_flush();
79 } 83 }
80#if 0 84#if 0
81 else { 85 else {
@@ -98,6 +102,9 @@ int udbg_write(const char *s, int n)
98 } 102 }
99 } 103 }
100 104
105 if (udbg_flush)
106 udbg_flush();
107
101 return n - remain; 108 return n - remain;
102} 109}
103 110
diff --git a/arch/powerpc/kernel/udbg_16550.c b/arch/powerpc/kernel/udbg_16550.c
index 7b7da8cfd5e8..0362a891e54e 100644
--- a/arch/powerpc/kernel/udbg_16550.c
+++ b/arch/powerpc/kernel/udbg_16550.c
@@ -48,14 +48,21 @@ struct NS16550 {
48 48
49static struct NS16550 __iomem *udbg_comport; 49static struct NS16550 __iomem *udbg_comport;
50 50
51static void udbg_550_putc(char c) 51static void udbg_550_flush(void)
52{ 52{
53 if (udbg_comport) { 53 if (udbg_comport) {
54 while ((in_8(&udbg_comport->lsr) & LSR_THRE) == 0) 54 while ((in_8(&udbg_comport->lsr) & LSR_THRE) == 0)
55 /* wait for idle */; 55 /* wait for idle */;
56 out_8(&udbg_comport->thr, c); 56 }
57}
58
59static void udbg_550_putc(char c)
60{
61 if (udbg_comport) {
57 if (c == '\n') 62 if (c == '\n')
58 udbg_550_putc('\r'); 63 udbg_550_putc('\r');
64 udbg_550_flush();
65 out_8(&udbg_comport->thr, c);
59 } 66 }
60} 67}
61 68
@@ -108,6 +115,7 @@ void udbg_init_uart(void __iomem *comport, unsigned int speed,
108 /* Clear & enable FIFOs */ 115 /* Clear & enable FIFOs */
109 out_8(&udbg_comport->fcr ,0x07); 116 out_8(&udbg_comport->fcr ,0x07);
110 udbg_putc = udbg_550_putc; 117 udbg_putc = udbg_550_putc;
118 udbg_flush = udbg_550_flush;
111 udbg_getc = udbg_550_getc; 119 udbg_getc = udbg_550_getc;
112 udbg_getc_poll = udbg_550_getc_poll; 120 udbg_getc_poll = udbg_550_getc_poll;
113 } 121 }
@@ -149,14 +157,21 @@ unsigned int udbg_probe_uart_speed(void __iomem *comport, unsigned int clock)
149} 157}
150 158
151#ifdef CONFIG_PPC_MAPLE 159#ifdef CONFIG_PPC_MAPLE
152void udbg_maple_real_putc(char c) 160void udbg_maple_real_flush(void)
153{ 161{
154 if (udbg_comport) { 162 if (udbg_comport) {
155 while ((real_readb(&udbg_comport->lsr) & LSR_THRE) == 0) 163 while ((real_readb(&udbg_comport->lsr) & LSR_THRE) == 0)
156 /* wait for idle */; 164 /* wait for idle */;
157 real_writeb(c, &udbg_comport->thr); eieio(); 165 }
166}
167
168void udbg_maple_real_putc(char c)
169{
170 if (udbg_comport) {
158 if (c == '\n') 171 if (c == '\n')
159 udbg_maple_real_putc('\r'); 172 udbg_maple_real_putc('\r');
173 udbg_maple_real_flush();
174 real_writeb(c, &udbg_comport->thr); eieio();
160 } 175 }
161} 176}
162 177
@@ -165,20 +180,28 @@ void __init udbg_init_maple_realmode(void)
165 udbg_comport = (struct NS16550 __iomem *)0xf40003f8; 180 udbg_comport = (struct NS16550 __iomem *)0xf40003f8;
166 181
167 udbg_putc = udbg_maple_real_putc; 182 udbg_putc = udbg_maple_real_putc;
183 udbg_flush = udbg_maple_real_flush;
168 udbg_getc = NULL; 184 udbg_getc = NULL;
169 udbg_getc_poll = NULL; 185 udbg_getc_poll = NULL;
170} 186}
171#endif /* CONFIG_PPC_MAPLE */ 187#endif /* CONFIG_PPC_MAPLE */
172 188
173#ifdef CONFIG_PPC_PASEMI 189#ifdef CONFIG_PPC_PASEMI
174void udbg_pas_real_putc(char c) 190void udbg_pas_real_flush(void)
175{ 191{
176 if (udbg_comport) { 192 if (udbg_comport) {
177 while ((real_205_readb(&udbg_comport->lsr) & LSR_THRE) == 0) 193 while ((real_205_readb(&udbg_comport->lsr) & LSR_THRE) == 0)
178 /* wait for idle */; 194 /* wait for idle */;
179 real_205_writeb(c, &udbg_comport->thr); eieio(); 195 }
196}
197
198void udbg_pas_real_putc(char c)
199{
200 if (udbg_comport) {
180 if (c == '\n') 201 if (c == '\n')
181 udbg_pas_real_putc('\r'); 202 udbg_pas_real_putc('\r');
203 udbg_pas_real_flush();
204 real_205_writeb(c, &udbg_comport->thr); eieio();
182 } 205 }
183} 206}
184 207
@@ -187,6 +210,7 @@ void udbg_init_pas_realmode(void)
187 udbg_comport = (struct NS16550 __iomem *)0xfcff03f8UL; 210 udbg_comport = (struct NS16550 __iomem *)0xfcff03f8UL;
188 211
189 udbg_putc = udbg_pas_real_putc; 212 udbg_putc = udbg_pas_real_putc;
213 udbg_flush = udbg_pas_real_flush;
190 udbg_getc = NULL; 214 udbg_getc = NULL;
191 udbg_getc_poll = NULL; 215 udbg_getc_poll = NULL;
192} 216}
@@ -195,14 +219,21 @@ void udbg_init_pas_realmode(void)
195#ifdef CONFIG_PPC_EARLY_DEBUG_44x 219#ifdef CONFIG_PPC_EARLY_DEBUG_44x
196#include <platforms/44x/44x.h> 220#include <platforms/44x/44x.h>
197 221
198static void udbg_44x_as1_putc(char c) 222static int udbg_44x_as1_flush(void)
199{ 223{
200 if (udbg_comport) { 224 if (udbg_comport) {
201 while ((as1_readb(&udbg_comport->lsr) & LSR_THRE) == 0) 225 while ((as1_readb(&udbg_comport->lsr) & LSR_THRE) == 0)
202 /* wait for idle */; 226 /* wait for idle */;
203 as1_writeb(c, &udbg_comport->thr); eieio(); 227 }
228}
229
230static void udbg_44x_as1_putc(char c)
231{
232 if (udbg_comport) {
204 if (c == '\n') 233 if (c == '\n')
205 udbg_44x_as1_putc('\r'); 234 udbg_44x_as1_putc('\r');
235 udbg_44x_as1_flush();
236 as1_writeb(c, &udbg_comport->thr); eieio();
206 } 237 }
207} 238}
208 239
@@ -222,19 +253,27 @@ void __init udbg_init_44x_as1(void)
222 (struct NS16550 __iomem *)PPC44x_EARLY_DEBUG_VIRTADDR; 253 (struct NS16550 __iomem *)PPC44x_EARLY_DEBUG_VIRTADDR;
223 254
224 udbg_putc = udbg_44x_as1_putc; 255 udbg_putc = udbg_44x_as1_putc;
256 udbg_flush = udbg_44x_as1_flush;
225 udbg_getc = udbg_44x_as1_getc; 257 udbg_getc = udbg_44x_as1_getc;
226} 258}
227#endif /* CONFIG_PPC_EARLY_DEBUG_44x */ 259#endif /* CONFIG_PPC_EARLY_DEBUG_44x */
228 260
229#ifdef CONFIG_PPC_EARLY_DEBUG_40x 261#ifdef CONFIG_PPC_EARLY_DEBUG_40x
230static void udbg_40x_real_putc(char c) 262static void udbg_40x_real_flush(void)
231{ 263{
232 if (udbg_comport) { 264 if (udbg_comport) {
233 while ((real_readb(&udbg_comport->lsr) & LSR_THRE) == 0) 265 while ((real_readb(&udbg_comport->lsr) & LSR_THRE) == 0)
234 /* wait for idle */; 266 /* wait for idle */;
235 real_writeb(c, &udbg_comport->thr); eieio(); 267 }
268}
269
270static void udbg_40x_real_putc(char c)
271{
272 if (udbg_comport) {
236 if (c == '\n') 273 if (c == '\n')
237 udbg_40x_real_putc('\r'); 274 udbg_40x_real_putc('\r');
275 udbg_40x_real_flush();
276 real_writeb(c, &udbg_comport->thr); eieio();
238 } 277 }
239} 278}
240 279
@@ -254,6 +293,7 @@ void __init udbg_init_40x_realmode(void)
254 CONFIG_PPC_EARLY_DEBUG_40x_PHYSADDR; 293 CONFIG_PPC_EARLY_DEBUG_40x_PHYSADDR;
255 294
256 udbg_putc = udbg_40x_real_putc; 295 udbg_putc = udbg_40x_real_putc;
296 udbg_flush = udbg_40x_real_flush;
257 udbg_getc = udbg_40x_real_getc; 297 udbg_getc = udbg_40x_real_getc;
258 udbg_getc_poll = NULL; 298 udbg_getc_poll = NULL;
259} 299}
diff --git a/arch/powerpc/mm/Makefile b/arch/powerpc/mm/Makefile
index 953cc4a1cde5..6d2838fc8792 100644
--- a/arch/powerpc/mm/Makefile
+++ b/arch/powerpc/mm/Makefile
@@ -6,7 +6,7 @@ ifeq ($(CONFIG_PPC64),y)
6EXTRA_CFLAGS += -mno-minimal-toc 6EXTRA_CFLAGS += -mno-minimal-toc
7endif 7endif
8 8
9obj-y := fault.o mem.o pgtable.o \ 9obj-y := fault.o mem.o pgtable.o gup.o \
10 init_$(CONFIG_WORD_SIZE).o \ 10 init_$(CONFIG_WORD_SIZE).o \
11 pgtable_$(CONFIG_WORD_SIZE).o 11 pgtable_$(CONFIG_WORD_SIZE).o
12obj-$(CONFIG_PPC_MMU_NOHASH) += mmu_context_nohash.o tlb_nohash.o \ 12obj-$(CONFIG_PPC_MMU_NOHASH) += mmu_context_nohash.o tlb_nohash.o \
@@ -14,7 +14,7 @@ obj-$(CONFIG_PPC_MMU_NOHASH) += mmu_context_nohash.o tlb_nohash.o \
14hash-$(CONFIG_PPC_NATIVE) := hash_native_64.o 14hash-$(CONFIG_PPC_NATIVE) := hash_native_64.o
15obj-$(CONFIG_PPC64) += hash_utils_64.o \ 15obj-$(CONFIG_PPC64) += hash_utils_64.o \
16 slb_low.o slb.o stab.o \ 16 slb_low.o slb.o stab.o \
17 gup.o mmap.o $(hash-y) 17 mmap.o $(hash-y)
18obj-$(CONFIG_PPC_STD_MMU_32) += ppc_mmu_32.o 18obj-$(CONFIG_PPC_STD_MMU_32) += ppc_mmu_32.o
19obj-$(CONFIG_PPC_STD_MMU) += hash_low_$(CONFIG_WORD_SIZE).o \ 19obj-$(CONFIG_PPC_STD_MMU) += hash_low_$(CONFIG_WORD_SIZE).o \
20 tlb_hash$(CONFIG_WORD_SIZE).o \ 20 tlb_hash$(CONFIG_WORD_SIZE).o \
diff --git a/arch/powerpc/mm/gup.c b/arch/powerpc/mm/gup.c
index 28a114db3ba0..bc400c78c97f 100644
--- a/arch/powerpc/mm/gup.c
+++ b/arch/powerpc/mm/gup.c
@@ -14,6 +14,8 @@
14#include <linux/rwsem.h> 14#include <linux/rwsem.h>
15#include <asm/pgtable.h> 15#include <asm/pgtable.h>
16 16
17#ifdef __HAVE_ARCH_PTE_SPECIAL
18
17/* 19/*
18 * The performance critical leaf functions are made noinline otherwise gcc 20 * The performance critical leaf functions are made noinline otherwise gcc
19 * inlines everything into a single function which results in too much 21 * inlines everything into a single function which results in too much
@@ -151,8 +153,11 @@ int get_user_pages_fast(unsigned long start, int nr_pages, int write,
151 unsigned long addr, len, end; 153 unsigned long addr, len, end;
152 unsigned long next; 154 unsigned long next;
153 pgd_t *pgdp; 155 pgd_t *pgdp;
154 int psize, nr = 0; 156 int nr = 0;
157#ifdef CONFIG_PPC64
155 unsigned int shift; 158 unsigned int shift;
159 int psize;
160#endif
156 161
157 pr_debug("%s(%lx,%x,%s)\n", __func__, start, nr_pages, write ? "write" : "read"); 162 pr_debug("%s(%lx,%x,%s)\n", __func__, start, nr_pages, write ? "write" : "read");
158 163
@@ -205,8 +210,13 @@ int get_user_pages_fast(unsigned long start, int nr_pages, int write,
205 */ 210 */
206 local_irq_disable(); 211 local_irq_disable();
207 212
213#ifdef CONFIG_PPC64
214 /* Those bits are related to hugetlbfs implementation and only exist
215 * on 64-bit for now
216 */
208 psize = get_slice_psize(mm, addr); 217 psize = get_slice_psize(mm, addr);
209 shift = mmu_psize_defs[psize].shift; 218 shift = mmu_psize_defs[psize].shift;
219#endif /* CONFIG_PPC64 */
210 220
211#ifdef CONFIG_HUGETLB_PAGE 221#ifdef CONFIG_HUGETLB_PAGE
212 if (unlikely(mmu_huge_psizes[psize])) { 222 if (unlikely(mmu_huge_psizes[psize])) {
@@ -236,7 +246,9 @@ int get_user_pages_fast(unsigned long start, int nr_pages, int write,
236 do { 246 do {
237 pgd_t pgd = *pgdp; 247 pgd_t pgd = *pgdp;
238 248
249#ifdef CONFIG_PPC64
239 VM_BUG_ON(shift != mmu_psize_defs[get_slice_psize(mm, addr)].shift); 250 VM_BUG_ON(shift != mmu_psize_defs[get_slice_psize(mm, addr)].shift);
251#endif
240 pr_debug(" %016lx: normal pgd %p\n", addr, 252 pr_debug(" %016lx: normal pgd %p\n", addr,
241 (void *)pgd_val(pgd)); 253 (void *)pgd_val(pgd));
242 next = pgd_addr_end(addr, end); 254 next = pgd_addr_end(addr, end);
@@ -279,3 +291,5 @@ slow_irqon:
279 return ret; 291 return ret;
280 } 292 }
281} 293}
294
295#endif /* __HAVE_ARCH_PTE_SPECIAL */
diff --git a/arch/powerpc/platforms/512x/Kconfig b/arch/powerpc/platforms/512x/Kconfig
index 326852c78b8f..4dac9b0525a4 100644
--- a/arch/powerpc/platforms/512x/Kconfig
+++ b/arch/powerpc/platforms/512x/Kconfig
@@ -12,7 +12,7 @@ config PPC_MPC5121
12 12
13config MPC5121_ADS 13config MPC5121_ADS
14 bool "Freescale MPC5121E ADS" 14 bool "Freescale MPC5121E ADS"
15 depends on PPC_MULTIPLATFORM && PPC32 15 depends on 6xx
16 select DEFAULT_UIMAGE 16 select DEFAULT_UIMAGE
17 select PPC_MPC5121 17 select PPC_MPC5121
18 select MPC5121_ADS_CPLD 18 select MPC5121_ADS_CPLD
@@ -21,7 +21,7 @@ config MPC5121_ADS
21 21
22config MPC5121_GENERIC 22config MPC5121_GENERIC
23 bool "Generic support for simple MPC5121 based boards" 23 bool "Generic support for simple MPC5121 based boards"
24 depends on PPC_MULTIPLATFORM && PPC32 24 depends on 6xx
25 select DEFAULT_UIMAGE 25 select DEFAULT_UIMAGE
26 select PPC_MPC5121 26 select PPC_MPC5121
27 help 27 help
diff --git a/arch/powerpc/platforms/52xx/Kconfig b/arch/powerpc/platforms/52xx/Kconfig
index 0465e5b36e6a..e0b9454ae691 100644
--- a/arch/powerpc/platforms/52xx/Kconfig
+++ b/arch/powerpc/platforms/52xx/Kconfig
@@ -1,6 +1,6 @@
1config PPC_MPC52xx 1config PPC_MPC52xx
2 bool "52xx-based boards" 2 bool "52xx-based boards"
3 depends on PPC_MULTIPLATFORM && PPC32 3 depends on 6xx
4 select PPC_CLOCK 4 select PPC_CLOCK
5 select PPC_PCI_CHOICE 5 select PPC_PCI_CHOICE
6 6
diff --git a/arch/powerpc/platforms/82xx/Kconfig b/arch/powerpc/platforms/82xx/Kconfig
index 30f008b2f92e..7c7df4003820 100644
--- a/arch/powerpc/platforms/82xx/Kconfig
+++ b/arch/powerpc/platforms/82xx/Kconfig
@@ -1,6 +1,6 @@
1menuconfig PPC_82xx 1menuconfig PPC_82xx
2 bool "82xx-based boards (PQ II)" 2 bool "82xx-based boards (PQ II)"
3 depends on 6xx && PPC_MULTIPLATFORM 3 depends on 6xx
4 4
5if PPC_82xx 5if PPC_82xx
6 6
diff --git a/arch/powerpc/platforms/83xx/Kconfig b/arch/powerpc/platforms/83xx/Kconfig
index 83c664afc897..437d29a59d72 100644
--- a/arch/powerpc/platforms/83xx/Kconfig
+++ b/arch/powerpc/platforms/83xx/Kconfig
@@ -1,6 +1,6 @@
1menuconfig PPC_83xx 1menuconfig PPC_83xx
2 bool "83xx-based boards" 2 bool "83xx-based boards"
3 depends on 6xx && PPC_MULTIPLATFORM 3 depends on 6xx
4 select PPC_UDBG_16550 4 select PPC_UDBG_16550
5 select PPC_PCI_CHOICE 5 select PPC_PCI_CHOICE
6 select FSL_PCI if PCI 6 select FSL_PCI if PCI
diff --git a/arch/powerpc/platforms/86xx/Kconfig b/arch/powerpc/platforms/86xx/Kconfig
index 611d0d19eb5a..fdaf4ddaa955 100644
--- a/arch/powerpc/platforms/86xx/Kconfig
+++ b/arch/powerpc/platforms/86xx/Kconfig
@@ -1,7 +1,7 @@
1config PPC_86xx 1config PPC_86xx
2menuconfig PPC_86xx 2menuconfig PPC_86xx
3 bool "86xx-based boards" 3 bool "86xx-based boards"
4 depends on 6xx && PPC_MULTIPLATFORM 4 depends on 6xx
5 select FSL_SOC 5 select FSL_SOC
6 select ALTIVEC 6 select ALTIVEC
7 help 7 help
diff --git a/arch/powerpc/platforms/Kconfig b/arch/powerpc/platforms/Kconfig
index b4ab3728653e..68b9b8fd9f85 100644
--- a/arch/powerpc/platforms/Kconfig
+++ b/arch/powerpc/platforms/Kconfig
@@ -1,14 +1,5 @@
1menu "Platform support" 1menu "Platform support"
2 2
3config PPC_MULTIPLATFORM
4 bool
5 depends on PPC64 || 6xx
6 default y
7
8config CLASSIC32
9 def_bool y
10 depends on 6xx && PPC_MULTIPLATFORM
11
12source "arch/powerpc/platforms/pseries/Kconfig" 3source "arch/powerpc/platforms/pseries/Kconfig"
13source "arch/powerpc/platforms/iseries/Kconfig" 4source "arch/powerpc/platforms/iseries/Kconfig"
14source "arch/powerpc/platforms/chrp/Kconfig" 5source "arch/powerpc/platforms/chrp/Kconfig"
@@ -32,12 +23,24 @@ source "arch/powerpc/platforms/amigaone/Kconfig"
32 23
33config PPC_NATIVE 24config PPC_NATIVE
34 bool 25 bool
35 depends on PPC_MULTIPLATFORM 26 depends on 6xx || PPC64
36 help 27 help
37 Support for running natively on the hardware, i.e. without 28 Support for running natively on the hardware, i.e. without
38 a hypervisor. This option is not user-selectable but should 29 a hypervisor. This option is not user-selectable but should
39 be selected by all platforms that need it. 30 be selected by all platforms that need it.
40 31
32config PPC_OF_BOOT_TRAMPOLINE
33 bool "Support booting from Open Firmware or yaboot"
34 depends on 6xx || PPC64
35 default y
36 help
37 Support from booting from Open Firmware or yaboot using an
38 Open Firmware client interface. This enables the kernel to
39 communicate with open firmware to retrieve system informations
40 such as the device tree.
41
42 In case of doubt, say Y
43
41config UDBG_RTAS_CONSOLE 44config UDBG_RTAS_CONSOLE
42 bool "RTAS based debug console" 45 bool "RTAS based debug console"
43 depends on PPC_RTAS 46 depends on PPC_RTAS
@@ -71,7 +74,7 @@ config PPC_I8259
71 74
72config U3_DART 75config U3_DART
73 bool 76 bool
74 depends on PPC_MULTIPLATFORM && PPC64 77 depends on PPC64
75 default n 78 default n
76 79
77config PPC_RTAS 80config PPC_RTAS
@@ -188,7 +191,7 @@ config PPC601_SYNC_FIX
188 191
189config TAU 192config TAU
190 bool "On-chip CPU temperature sensor support" 193 bool "On-chip CPU temperature sensor support"
191 depends on CLASSIC32 194 depends on 6xx
192 help 195 help
193 G3 and G4 processors have an on-chip temperature sensor called the 196 G3 and G4 processors have an on-chip temperature sensor called the
194 'Thermal Assist Unit (TAU)', which, in theory, can measure the on-die 197 'Thermal Assist Unit (TAU)', which, in theory, can measure the on-die
diff --git a/arch/powerpc/platforms/Kconfig.cputype b/arch/powerpc/platforms/Kconfig.cputype
index 9428c0e11b20..9da795e49337 100644
--- a/arch/powerpc/platforms/Kconfig.cputype
+++ b/arch/powerpc/platforms/Kconfig.cputype
@@ -57,9 +57,17 @@ config E200
57 57
58endchoice 58endchoice
59 59
60# Until we have a choice of exclusive CPU types on 64-bit, we always
61# use PPC_BOOK3S. On 32-bit, this is equivalent to 6xx which is
62# "classic" MMU
63
64config PPC_BOOK3S
65 def_bool y
66 depends on PPC64 || 6xx
67
60config POWER4_ONLY 68config POWER4_ONLY
61 bool "Optimize for POWER4" 69 bool "Optimize for POWER4"
62 depends on PPC64 70 depends on PPC64 && PPC_BOOK3S
63 default n 71 default n
64 ---help--- 72 ---help---
65 Cause the compiler to optimize for POWER4/POWER5/PPC970 processors. 73 Cause the compiler to optimize for POWER4/POWER5/PPC970 processors.
@@ -68,16 +76,16 @@ config POWER4_ONLY
68 76
69config POWER3 77config POWER3
70 bool 78 bool
71 depends on PPC64 79 depends on PPC64 && PPC_BOOK3S
72 default y if !POWER4_ONLY 80 default y if !POWER4_ONLY
73 81
74config POWER4 82config POWER4
75 depends on PPC64 83 depends on PPC64 && PPC_BOOK3S
76 def_bool y 84 def_bool y
77 85
78config TUNE_CELL 86config TUNE_CELL
79 bool "Optimize for Cell Broadband Engine" 87 bool "Optimize for Cell Broadband Engine"
80 depends on PPC64 88 depends on PPC64 && PPC_BOOK3S
81 help 89 help
82 Cause the compiler to optimize for the PPE of the Cell Broadband 90 Cause the compiler to optimize for the PPE of the Cell Broadband
83 Engine. This will make the code run considerably faster on Cell 91 Engine. This will make the code run considerably faster on Cell
@@ -147,7 +155,7 @@ config PHYS_64BIT
147 155
148config ALTIVEC 156config ALTIVEC
149 bool "AltiVec Support" 157 bool "AltiVec Support"
150 depends on CLASSIC32 || POWER4 158 depends on 6xx || POWER4
151 ---help--- 159 ---help---
152 This option enables kernel support for the Altivec extensions to the 160 This option enables kernel support for the Altivec extensions to the
153 PowerPC processor. The kernel currently supports saving and restoring 161 PowerPC processor. The kernel currently supports saving and restoring
diff --git a/arch/powerpc/platforms/amigaone/Kconfig b/arch/powerpc/platforms/amigaone/Kconfig
index 9276a96cedee..022476717718 100644
--- a/arch/powerpc/platforms/amigaone/Kconfig
+++ b/arch/powerpc/platforms/amigaone/Kconfig
@@ -1,6 +1,6 @@
1config AMIGAONE 1config AMIGAONE
2 bool "Eyetech AmigaOne/MAI Teron" 2 bool "Eyetech AmigaOne/MAI Teron"
3 depends on PPC32 && BROKEN_ON_SMP && PPC_MULTIPLATFORM 3 depends on 6xx && BROKEN_ON_SMP
4 select PPC_I8259 4 select PPC_I8259
5 select PPC_INDIRECT_PCI 5 select PPC_INDIRECT_PCI
6 select PPC_UDBG_16550 6 select PPC_UDBG_16550
diff --git a/arch/powerpc/platforms/cell/Kconfig b/arch/powerpc/platforms/cell/Kconfig
index 037f59a4bfe7..40e24c39ad06 100644
--- a/arch/powerpc/platforms/cell/Kconfig
+++ b/arch/powerpc/platforms/cell/Kconfig
@@ -23,7 +23,7 @@ config PPC_CELL_NATIVE
23 23
24config PPC_IBM_CELL_BLADE 24config PPC_IBM_CELL_BLADE
25 bool "IBM Cell Blade" 25 bool "IBM Cell Blade"
26 depends on PPC_MULTIPLATFORM && PPC64 26 depends on PPC64 && PPC_BOOK3S
27 select PPC_CELL_NATIVE 27 select PPC_CELL_NATIVE
28 select MMIO_NVRAM 28 select MMIO_NVRAM
29 select PPC_UDBG_16550 29 select PPC_UDBG_16550
@@ -31,7 +31,7 @@ config PPC_IBM_CELL_BLADE
31 31
32config PPC_CELLEB 32config PPC_CELLEB
33 bool "Toshiba's Cell Reference Set 'Celleb' Architecture" 33 bool "Toshiba's Cell Reference Set 'Celleb' Architecture"
34 depends on PPC_MULTIPLATFORM && PPC64 34 depends on PPC64 && PPC_BOOK3S
35 select PPC_CELL_NATIVE 35 select PPC_CELL_NATIVE
36 select HAS_TXX9_SERIAL 36 select HAS_TXX9_SERIAL
37 select PPC_UDBG_BEAT 37 select PPC_UDBG_BEAT
@@ -40,9 +40,14 @@ config PPC_CELLEB
40 40
41config PPC_CELL_QPACE 41config PPC_CELL_QPACE
42 bool "IBM Cell - QPACE" 42 bool "IBM Cell - QPACE"
43 depends on PPC_MULTIPLATFORM && PPC64 43 depends on PPC64 && PPC_BOOK3S
44 select PPC_CELL_COMMON 44 select PPC_CELL_COMMON
45 45
46config AXON_MSI
47 bool
48 depends on PPC_IBM_CELL_BLADE && PCI_MSI
49 default y
50
46menu "Cell Broadband Engine options" 51menu "Cell Broadband Engine options"
47 depends on PPC_CELL 52 depends on PPC_CELL
48 53
diff --git a/arch/powerpc/platforms/cell/Makefile b/arch/powerpc/platforms/cell/Makefile
index 43eccb270301..83fafe922641 100644
--- a/arch/powerpc/platforms/cell/Makefile
+++ b/arch/powerpc/platforms/cell/Makefile
@@ -28,7 +28,7 @@ obj-$(CONFIG_SPU_BASE) += spu_callbacks.o spu_base.o \
28 $(spu-manage-y) \ 28 $(spu-manage-y) \
29 spufs/ 29 spufs/
30 30
31obj-$(CONFIG_PCI_MSI) += axon_msi.o 31obj-$(CONFIG_AXON_MSI) += axon_msi.o
32 32
33# qpace setup 33# qpace setup
34obj-$(CONFIG_PPC_CELL_QPACE) += qpace_setup.o 34obj-$(CONFIG_PPC_CELL_QPACE) += qpace_setup.o
diff --git a/arch/powerpc/platforms/cell/spufs/file.c b/arch/powerpc/platforms/cell/spufs/file.c
index 9e4f2739341d..d6a519e6e1c1 100644
--- a/arch/powerpc/platforms/cell/spufs/file.c
+++ b/arch/powerpc/platforms/cell/spufs/file.c
@@ -568,16 +568,17 @@ spufs_regs_write(struct file *file, const char __user *buffer,
568 struct spu_lscsa *lscsa = ctx->csa.lscsa; 568 struct spu_lscsa *lscsa = ctx->csa.lscsa;
569 int ret; 569 int ret;
570 570
571 size = min_t(ssize_t, sizeof lscsa->gprs - *pos, size); 571 if (*pos >= sizeof(lscsa->gprs))
572 if (size <= 0)
573 return -EFBIG; 572 return -EFBIG;
573
574 size = min_t(ssize_t, sizeof(lscsa->gprs) - *pos, size);
574 *pos += size; 575 *pos += size;
575 576
576 ret = spu_acquire_saved(ctx); 577 ret = spu_acquire_saved(ctx);
577 if (ret) 578 if (ret)
578 return ret; 579 return ret;
579 580
580 ret = copy_from_user(lscsa->gprs + *pos - size, 581 ret = copy_from_user((char *)lscsa->gprs + *pos - size,
581 buffer, size) ? -EFAULT : size; 582 buffer, size) ? -EFAULT : size;
582 583
583 spu_release_saved(ctx); 584 spu_release_saved(ctx);
@@ -623,10 +624,11 @@ spufs_fpcr_write(struct file *file, const char __user * buffer,
623 struct spu_lscsa *lscsa = ctx->csa.lscsa; 624 struct spu_lscsa *lscsa = ctx->csa.lscsa;
624 int ret; 625 int ret;
625 626
626 size = min_t(ssize_t, sizeof(lscsa->fpcr) - *pos, size); 627 if (*pos >= sizeof(lscsa->fpcr))
627 if (size <= 0)
628 return -EFBIG; 628 return -EFBIG;
629 629
630 size = min_t(ssize_t, sizeof(lscsa->fpcr) - *pos, size);
631
630 ret = spu_acquire_saved(ctx); 632 ret = spu_acquire_saved(ctx);
631 if (ret) 633 if (ret)
632 return ret; 634 return ret;
diff --git a/arch/powerpc/platforms/chrp/Kconfig b/arch/powerpc/platforms/chrp/Kconfig
index 22b4b4e3b6f0..37d438bd5b7a 100644
--- a/arch/powerpc/platforms/chrp/Kconfig
+++ b/arch/powerpc/platforms/chrp/Kconfig
@@ -1,6 +1,6 @@
1config PPC_CHRP 1config PPC_CHRP
2 bool "Common Hardware Reference Platform (CHRP) based machines" 2 bool "Common Hardware Reference Platform (CHRP) based machines"
3 depends on PPC_MULTIPLATFORM && PPC32 3 depends on 6xx
4 select MPIC 4 select MPIC
5 select PPC_I8259 5 select PPC_I8259
6 select PPC_INDIRECT_PCI 6 select PPC_INDIRECT_PCI
diff --git a/arch/powerpc/platforms/embedded6xx/Kconfig b/arch/powerpc/platforms/embedded6xx/Kconfig
index 4f9f8184d164..291ac9d8cbee 100644
--- a/arch/powerpc/platforms/embedded6xx/Kconfig
+++ b/arch/powerpc/platforms/embedded6xx/Kconfig
@@ -1,6 +1,6 @@
1config EMBEDDED6xx 1config EMBEDDED6xx
2 bool "Embedded 6xx/7xx/7xxx-based boards" 2 bool "Embedded 6xx/7xx/7xxx-based boards"
3 depends on PPC32 && BROKEN_ON_SMP && PPC_MULTIPLATFORM 3 depends on 6xx && BROKEN_ON_SMP
4 4
5config LINKSTATION 5config LINKSTATION
6 bool "Linkstation / Kurobox(HG) from Buffalo" 6 bool "Linkstation / Kurobox(HG) from Buffalo"
diff --git a/arch/powerpc/platforms/iseries/Kconfig b/arch/powerpc/platforms/iseries/Kconfig
index 7ddd0a2c8027..647e87787437 100644
--- a/arch/powerpc/platforms/iseries/Kconfig
+++ b/arch/powerpc/platforms/iseries/Kconfig
@@ -1,6 +1,6 @@
1config PPC_ISERIES 1config PPC_ISERIES
2 bool "IBM Legacy iSeries" 2 bool "IBM Legacy iSeries"
3 depends on PPC_MULTIPLATFORM && PPC64 3 depends on PPC64 && PPC_BOOK3S
4 select PPC_INDIRECT_IO 4 select PPC_INDIRECT_IO
5 select PPC_PCI_CHOICE if EMBEDDED 5 select PPC_PCI_CHOICE if EMBEDDED
6 6
diff --git a/arch/powerpc/platforms/iseries/irq.c b/arch/powerpc/platforms/iseries/irq.c
index 701d9297c207..94f444758836 100644
--- a/arch/powerpc/platforms/iseries/irq.c
+++ b/arch/powerpc/platforms/iseries/irq.c
@@ -214,7 +214,7 @@ void __init iSeries_activate_IRQs()
214 unsigned long flags; 214 unsigned long flags;
215 215
216 for_each_irq (irq) { 216 for_each_irq (irq) {
217 irq_desc_t *desc = get_irq_desc(irq); 217 struct irq_desc *desc = get_irq_desc(irq);
218 218
219 if (desc && desc->chip && desc->chip->startup) { 219 if (desc && desc->chip && desc->chip->startup) {
220 spin_lock_irqsave(&desc->lock, flags); 220 spin_lock_irqsave(&desc->lock, flags);
diff --git a/arch/powerpc/platforms/maple/Kconfig b/arch/powerpc/platforms/maple/Kconfig
index a6467a5591fa..1ea621a94c3b 100644
--- a/arch/powerpc/platforms/maple/Kconfig
+++ b/arch/powerpc/platforms/maple/Kconfig
@@ -1,5 +1,5 @@
1config PPC_MAPLE 1config PPC_MAPLE
2 depends on PPC_MULTIPLATFORM && PPC64 2 depends on PPC64 && PPC_BOOK3S
3 bool "Maple 970FX Evaluation Board" 3 bool "Maple 970FX Evaluation Board"
4 select PCI 4 select PCI
5 select MPIC 5 select MPIC
diff --git a/arch/powerpc/platforms/pasemi/Kconfig b/arch/powerpc/platforms/pasemi/Kconfig
index 348e0619e3e5..a2aeb327d185 100644
--- a/arch/powerpc/platforms/pasemi/Kconfig
+++ b/arch/powerpc/platforms/pasemi/Kconfig
@@ -1,5 +1,5 @@
1config PPC_PASEMI 1config PPC_PASEMI
2 depends on PPC_MULTIPLATFORM && PPC64 2 depends on PPC64 && PPC_BOOK3S
3 bool "PA Semi SoC-based platforms" 3 bool "PA Semi SoC-based platforms"
4 default n 4 default n
5 select MPIC 5 select MPIC
diff --git a/arch/powerpc/platforms/powermac/Kconfig b/arch/powerpc/platforms/powermac/Kconfig
index 055990ca8ce6..1e1a0873e1dd 100644
--- a/arch/powerpc/platforms/powermac/Kconfig
+++ b/arch/powerpc/platforms/powermac/Kconfig
@@ -1,6 +1,6 @@
1config PPC_PMAC 1config PPC_PMAC
2 bool "Apple PowerMac based machines" 2 bool "Apple PowerMac based machines"
3 depends on PPC_MULTIPLATFORM 3 depends on PPC_BOOK3S
4 select MPIC 4 select MPIC
5 select PCI 5 select PCI
6 select PPC_INDIRECT_PCI if PPC32 6 select PPC_INDIRECT_PCI if PPC32
diff --git a/arch/powerpc/platforms/powermac/pic.h b/arch/powerpc/platforms/powermac/pic.h
index c44c89f5e532..d622a8345aaa 100644
--- a/arch/powerpc/platforms/powermac/pic.h
+++ b/arch/powerpc/platforms/powermac/pic.h
@@ -3,7 +3,7 @@
3 3
4#include <linux/irq.h> 4#include <linux/irq.h>
5 5
6extern struct hw_interrupt_type pmac_pic; 6extern struct irq_chip pmac_pic;
7 7
8extern void pmac_pic_init(void); 8extern void pmac_pic_init(void);
9extern int pmac_get_irq(void); 9extern int pmac_get_irq(void);
diff --git a/arch/powerpc/platforms/prep/Kconfig b/arch/powerpc/platforms/prep/Kconfig
index 29d411279b0c..bf8330ef2e76 100644
--- a/arch/powerpc/platforms/prep/Kconfig
+++ b/arch/powerpc/platforms/prep/Kconfig
@@ -1,6 +1,6 @@
1config PPC_PREP 1config PPC_PREP
2 bool "PowerPC Reference Platform (PReP) based machines" 2 bool "PowerPC Reference Platform (PReP) based machines"
3 depends on PPC_MULTIPLATFORM && PPC32 && BROKEN 3 depends on 6xx && BROKEN
4 select MPIC 4 select MPIC
5 select PPC_I8259 5 select PPC_I8259
6 select PPC_INDIRECT_PCI 6 select PPC_INDIRECT_PCI
diff --git a/arch/powerpc/platforms/ps3/Kconfig b/arch/powerpc/platforms/ps3/Kconfig
index 920cf7a454b1..204ae5c402fa 100644
--- a/arch/powerpc/platforms/ps3/Kconfig
+++ b/arch/powerpc/platforms/ps3/Kconfig
@@ -1,6 +1,6 @@
1config PPC_PS3 1config PPC_PS3
2 bool "Sony PS3" 2 bool "Sony PS3"
3 depends on PPC_MULTIPLATFORM && PPC64 3 depends on PPC64 && PPC_BOOK3S
4 select PPC_CELL 4 select PPC_CELL
5 select USB_ARCH_HAS_OHCI 5 select USB_ARCH_HAS_OHCI
6 select USB_OHCI_LITTLE_ENDIAN 6 select USB_OHCI_LITTLE_ENDIAN
diff --git a/arch/powerpc/platforms/pseries/Kconfig b/arch/powerpc/platforms/pseries/Kconfig
index ddc2a307cd50..c0e6ec240f46 100644
--- a/arch/powerpc/platforms/pseries/Kconfig
+++ b/arch/powerpc/platforms/pseries/Kconfig
@@ -1,5 +1,5 @@
1config PPC_PSERIES 1config PPC_PSERIES
2 depends on PPC_MULTIPLATFORM && PPC64 2 depends on PPC64 && PPC_BOOK3S
3 bool "IBM pSeries & new (POWER5-based) iSeries" 3 bool "IBM pSeries & new (POWER5-based) iSeries"
4 select MPIC 4 select MPIC
5 select PPC_I8259 5 select PPC_I8259
@@ -25,6 +25,11 @@ config EEH
25 depends on PPC_PSERIES && PCI 25 depends on PPC_PSERIES && PCI
26 default y if !EMBEDDED 26 default y if !EMBEDDED
27 27
28config PSERIES_MSI
29 bool
30 depends on PCI_MSI && EEH
31 default y
32
28config SCANLOG 33config SCANLOG
29 tristate "Scanlog dump interface" 34 tristate "Scanlog dump interface"
30 depends on RTAS_PROC && PPC_PSERIES 35 depends on RTAS_PROC && PPC_PSERIES
diff --git a/arch/powerpc/platforms/pseries/Makefile b/arch/powerpc/platforms/pseries/Makefile
index dfe574af2dc0..0ce691df595f 100644
--- a/arch/powerpc/platforms/pseries/Makefile
+++ b/arch/powerpc/platforms/pseries/Makefile
@@ -15,7 +15,7 @@ obj-$(CONFIG_SCANLOG) += scanlog.o
15obj-$(CONFIG_EEH) += eeh.o eeh_cache.o eeh_driver.o eeh_event.o eeh_sysfs.o 15obj-$(CONFIG_EEH) += eeh.o eeh_cache.o eeh_driver.o eeh_event.o eeh_sysfs.o
16obj-$(CONFIG_KEXEC) += kexec.o 16obj-$(CONFIG_KEXEC) += kexec.o
17obj-$(CONFIG_PCI) += pci.o pci_dlpar.o 17obj-$(CONFIG_PCI) += pci.o pci_dlpar.o
18obj-$(CONFIG_PCI_MSI) += msi.o 18obj-$(CONFIG_PSERIES_MSI) += msi.o
19 19
20obj-$(CONFIG_HOTPLUG_CPU) += hotplug-cpu.o 20obj-$(CONFIG_HOTPLUG_CPU) += hotplug-cpu.o
21obj-$(CONFIG_MEMORY_HOTPLUG) += hotplug-memory.o 21obj-$(CONFIG_MEMORY_HOTPLUG) += hotplug-memory.o
diff --git a/arch/powerpc/platforms/pseries/msi.c b/arch/powerpc/platforms/pseries/msi.c
index 3e0d6ef3eca9..bf2e1ac41308 100644
--- a/arch/powerpc/platforms/pseries/msi.c
+++ b/arch/powerpc/platforms/pseries/msi.c
@@ -356,6 +356,27 @@ static int rtas_msi_check_device(struct pci_dev *pdev, int nvec, int type)
356 return 0; 356 return 0;
357} 357}
358 358
359static int check_msix_entries(struct pci_dev *pdev)
360{
361 struct msi_desc *entry;
362 int expected;
363
364 /* There's no way for us to express to firmware that we want
365 * a discontiguous, or non-zero based, range of MSI-X entries.
366 * So we must reject such requests. */
367
368 expected = 0;
369 list_for_each_entry(entry, &pdev->msi_list, list) {
370 if (entry->msi_attrib.entry_nr != expected) {
371 pr_debug("rtas_msi: bad MSI-X entries.\n");
372 return -EINVAL;
373 }
374 expected++;
375 }
376
377 return 0;
378}
379
359static int rtas_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type) 380static int rtas_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type)
360{ 381{
361 struct pci_dn *pdn; 382 struct pci_dn *pdn;
@@ -367,6 +388,9 @@ static int rtas_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type)
367 if (!pdn) 388 if (!pdn)
368 return -ENODEV; 389 return -ENODEV;
369 390
391 if (type == PCI_CAP_ID_MSIX && check_msix_entries(pdev))
392 return -EINVAL;
393
370 /* 394 /*
371 * Try the new more explicit firmware interface, if that fails fall 395 * Try the new more explicit firmware interface, if that fails fall
372 * back to the old interface. The old interface is known to never 396 * back to the old interface. The old interface is known to never
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-31 11:11:38 -0500