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-rw-r--r--arch/powerpc/Kconfig27
-rw-r--r--arch/powerpc/boot/dts/mpc7448hpc2.dts190
-rw-r--r--arch/powerpc/boot/dts/mpc8349emds.dts328
-rw-r--r--arch/powerpc/boot/dts/mpc8540ads.dts257
-rw-r--r--arch/powerpc/boot/dts/mpc8541cds.dts244
-rw-r--r--arch/powerpc/boot/dts/mpc8548cds.dts287
-rw-r--r--arch/powerpc/boot/dts/mpc8555cds.dts244
-rw-r--r--arch/powerpc/boot/dts/mpc8641_hpcn.dts339
-rw-r--r--arch/powerpc/configs/g5_defconfig122
-rw-r--r--arch/powerpc/configs/iseries_defconfig78
-rw-r--r--arch/powerpc/configs/mpc834x_mds_defconfig (renamed from arch/powerpc/configs/mpc834x_sys_defconfig)0
-rw-r--r--arch/powerpc/configs/pseries_defconfig78
-rw-r--r--arch/powerpc/kernel/Makefile4
-rw-r--r--arch/powerpc/kernel/cpu_setup_power4.S2
-rw-r--r--arch/powerpc/kernel/crash.c11
-rw-r--r--arch/powerpc/kernel/fpu.S5
-rw-r--r--arch/powerpc/kernel/irq.c86
-rw-r--r--arch/powerpc/kernel/kprobes.c2
-rw-r--r--arch/powerpc/kernel/legacy_serial.c8
-rw-r--r--arch/powerpc/kernel/machine_kexec.c56
-rw-r--r--arch/powerpc/kernel/machine_kexec_64.c57
-rw-r--r--arch/powerpc/kernel/pci_64.c11
-rw-r--r--arch/powerpc/kernel/ppc_ksyms.c4
-rw-r--r--arch/powerpc/kernel/prom_init.c10
-rw-r--r--arch/powerpc/kernel/prom_parse.c30
-rw-r--r--arch/powerpc/kernel/rtas.c21
-rw-r--r--arch/powerpc/kernel/smp-tbsync.c5
-rw-r--r--arch/powerpc/kernel/time.c48
-rw-r--r--arch/powerpc/kernel/traps.c26
-rw-r--r--arch/powerpc/lib/memcpy_64.S11
-rw-r--r--arch/powerpc/mm/44x_mmu.c4
-rw-r--r--arch/powerpc/mm/hugetlbpage.c2
-rw-r--r--arch/powerpc/platforms/83xx/mpc834x_itx.c49
-rw-r--r--arch/powerpc/platforms/83xx/mpc834x_sys.c56
-rw-r--r--arch/powerpc/platforms/83xx/mpc83xx.h1
-rw-r--r--arch/powerpc/platforms/83xx/pci.c9
-rw-r--r--arch/powerpc/platforms/85xx/Kconfig1
-rw-r--r--arch/powerpc/platforms/85xx/mpc85xx_ads.c162
-rw-r--r--arch/powerpc/platforms/85xx/mpc85xx_cds.c210
-rw-r--r--arch/powerpc/platforms/86xx/mpc8641_hpcn.h32
-rw-r--r--arch/powerpc/platforms/86xx/mpc86xx_hpcn.c334
-rw-r--r--arch/powerpc/platforms/86xx/pci.c3
-rw-r--r--arch/powerpc/platforms/embedded6xx/Kconfig1
-rw-r--r--arch/powerpc/platforms/embedded6xx/mpc7448_hpc2.c75
-rw-r--r--arch/powerpc/platforms/powermac/bootx_init.c15
-rw-r--r--arch/powerpc/platforms/powermac/pfunc_base.c2
-rw-r--r--arch/powerpc/platforms/powermac/pic.c6
-rw-r--r--arch/powerpc/platforms/pseries/setup.c2
-rw-r--r--arch/powerpc/platforms/pseries/xics.c6
-rw-r--r--arch/powerpc/sysdev/Makefile4
-rw-r--r--arch/powerpc/sysdev/fsl_soc.c42
-rw-r--r--arch/powerpc/sysdev/ipic.c303
-rw-r--r--arch/powerpc/sysdev/ipic.h23
-rw-r--r--arch/powerpc/sysdev/mpic.c223
-rw-r--r--arch/powerpc/sysdev/tsi108_dev.c10
-rw-r--r--arch/powerpc/sysdev/tsi108_pci.c21
56 files changed, 3226 insertions, 961 deletions
diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
index 13e583f16ede..4d4b6fb156e1 100644
--- a/arch/powerpc/Kconfig
+++ b/arch/powerpc/Kconfig
@@ -354,6 +354,7 @@ endchoice
354config PPC_PSERIES 354config PPC_PSERIES
355 depends on PPC_MULTIPLATFORM && PPC64 355 depends on PPC_MULTIPLATFORM && PPC64
356 bool "IBM pSeries & new (POWER5-based) iSeries" 356 bool "IBM pSeries & new (POWER5-based) iSeries"
357 select MPIC
357 select PPC_I8259 358 select PPC_I8259
358 select PPC_RTAS 359 select PPC_RTAS
359 select RTAS_ERROR_LOGGING 360 select RTAS_ERROR_LOGGING
@@ -363,6 +364,7 @@ config PPC_PSERIES
363config PPC_CHRP 364config PPC_CHRP
364 bool "Common Hardware Reference Platform (CHRP) based machines" 365 bool "Common Hardware Reference Platform (CHRP) based machines"
365 depends on PPC_MULTIPLATFORM && PPC32 366 depends on PPC_MULTIPLATFORM && PPC32
367 select MPIC
366 select PPC_I8259 368 select PPC_I8259
367 select PPC_INDIRECT_PCI 369 select PPC_INDIRECT_PCI
368 select PPC_RTAS 370 select PPC_RTAS
@@ -373,6 +375,7 @@ config PPC_CHRP
373config PPC_PMAC 375config PPC_PMAC
374 bool "Apple PowerMac based machines" 376 bool "Apple PowerMac based machines"
375 depends on PPC_MULTIPLATFORM 377 depends on PPC_MULTIPLATFORM
378 select MPIC
376 select PPC_INDIRECT_PCI if PPC32 379 select PPC_INDIRECT_PCI if PPC32
377 select PPC_MPC106 if PPC32 380 select PPC_MPC106 if PPC32
378 default y 381 default y
@@ -380,6 +383,7 @@ config PPC_PMAC
380config PPC_PMAC64 383config PPC_PMAC64
381 bool 384 bool
382 depends on PPC_PMAC && POWER4 385 depends on PPC_PMAC && POWER4
386 select MPIC
383 select U3_DART 387 select U3_DART
384 select MPIC_BROKEN_U3 388 select MPIC_BROKEN_U3
385 select GENERIC_TBSYNC 389 select GENERIC_TBSYNC
@@ -389,6 +393,7 @@ config PPC_PMAC64
389config PPC_PREP 393config PPC_PREP
390 bool "PowerPC Reference Platform (PReP) based machines" 394 bool "PowerPC Reference Platform (PReP) based machines"
391 depends on PPC_MULTIPLATFORM && PPC32 && BROKEN 395 depends on PPC_MULTIPLATFORM && PPC32 && BROKEN
396 select MPIC
392 select PPC_I8259 397 select PPC_I8259
393 select PPC_INDIRECT_PCI 398 select PPC_INDIRECT_PCI
394 select PPC_UDBG_16550 399 select PPC_UDBG_16550
@@ -397,6 +402,7 @@ config PPC_PREP
397config PPC_MAPLE 402config PPC_MAPLE
398 depends on PPC_MULTIPLATFORM && PPC64 403 depends on PPC_MULTIPLATFORM && PPC64
399 bool "Maple 970FX Evaluation Board" 404 bool "Maple 970FX Evaluation Board"
405 select MPIC
400 select U3_DART 406 select U3_DART
401 select MPIC_BROKEN_U3 407 select MPIC_BROKEN_U3
402 select GENERIC_TBSYNC 408 select GENERIC_TBSYNC
@@ -439,12 +445,6 @@ config U3_DART
439 depends on PPC_MULTIPLATFORM && PPC64 445 depends on PPC_MULTIPLATFORM && PPC64
440 default n 446 default n
441 447
442config MPIC
443 depends on PPC_PSERIES || PPC_PMAC || PPC_MAPLE || PPC_CHRP \
444 || MPC7448HPC2
445 bool
446 default y
447
448config PPC_RTAS 448config PPC_RTAS
449 bool 449 bool
450 default n 450 default n
@@ -812,6 +812,14 @@ config GENERIC_ISA_DMA
812 depends on PPC64 || POWER4 || 6xx && !CPM2 812 depends on PPC64 || POWER4 || 6xx && !CPM2
813 default y 813 default y
814 814
815config MPIC
816 bool
817 default n
818
819config MPIC_WEIRD
820 bool
821 default n
822
815config PPC_I8259 823config PPC_I8259
816 bool 824 bool
817 default n 825 default n
@@ -836,9 +844,10 @@ config MCA
836 bool 844 bool
837 845
838config PCI 846config PCI
839 bool "PCI support" if 40x || CPM2 || PPC_83xx || PPC_85xx || PPC_MPC52xx || (EMBEDDED && PPC_ISERIES) \ 847 bool "PCI support" if 40x || CPM2 || PPC_83xx || PPC_85xx || PPC_86xx \
840 || MPC7448HPC2 848 || PPC_MPC52xx || (EMBEDDED && PPC_ISERIES) || MPC7448HPC2
841 default y if !40x && !CPM2 && !8xx && !APUS && !PPC_83xx && !PPC_85xx && !PPC_86xx 849 default y if !40x && !CPM2 && !8xx && !APUS && !PPC_83xx \
850 && !PPC_85xx && !PPC_86xx
842 default PCI_PERMEDIA if !4xx && !CPM2 && !8xx && APUS 851 default PCI_PERMEDIA if !4xx && !CPM2 && !8xx && APUS
843 default PCI_QSPAN if !4xx && !CPM2 && 8xx 852 default PCI_QSPAN if !4xx && !CPM2 && 8xx
844 help 853 help
diff --git a/arch/powerpc/boot/dts/mpc7448hpc2.dts b/arch/powerpc/boot/dts/mpc7448hpc2.dts
new file mode 100644
index 000000000000..d7b985e6bd2f
--- /dev/null
+++ b/arch/powerpc/boot/dts/mpc7448hpc2.dts
@@ -0,0 +1,190 @@
1/*
2 * MPC7448HPC2 (Taiga) board Device Tree Source
3 *
4 * Copyright 2006 Freescale Semiconductor Inc.
5 * 2006 Roy Zang <Roy Zang at freescale.com>.
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 */
12
13
14/ {
15 model = "mpc7448hpc2";
16 compatible = "mpc74xx";
17 #address-cells = <1>;
18 #size-cells = <1>;
19 linux,phandle = <100>;
20
21 cpus {
22 #cpus = <1>;
23 #address-cells = <1>;
24 #size-cells =<0>;
25 linux,phandle = <200>;
26
27 PowerPC,7448@0 {
28 device_type = "cpu";
29 reg = <0>;
30 d-cache-line-size = <20>; // 32 bytes
31 i-cache-line-size = <20>; // 32 bytes
32 d-cache-size = <8000>; // L1, 32K bytes
33 i-cache-size = <8000>; // L1, 32K bytes
34 timebase-frequency = <0>; // 33 MHz, from uboot
35 clock-frequency = <0>; // From U-Boot
36 bus-frequency = <0>; // From U-Boot
37 32-bit;
38 linux,phandle = <201>;
39 linux,boot-cpu;
40 };
41 };
42
43 memory {
44 device_type = "memory";
45 linux,phandle = <300>;
46 reg = <00000000 20000000 // DDR2 512M at 0
47 >;
48 };
49
50 tsi108@c0000000 {
51 #address-cells = <1>;
52 #size-cells = <1>;
53 #interrupt-cells = <2>;
54 device_type = "tsi-bridge";
55 ranges = <00000000 c0000000 00010000>;
56 reg = <c0000000 00010000>;
57 bus-frequency = <0>;
58
59 i2c@7000 {
60 interrupt-parent = <7400>;
61 interrupts = <E 0>;
62 reg = <7000 400>;
63 device_type = "i2c";
64 compatible = "tsi-i2c";
65 };
66
67 mdio@6000 {
68 device_type = "mdio";
69 compatible = "tsi-ethernet";
70
71 ethernet-phy@6000 {
72 linux,phandle = <6000>;
73 interrupt-parent = <7400>;
74 interrupts = <2 1>;
75 reg = <6000 50>;
76 phy-id = <8>;
77 device_type = "ethernet-phy";
78 };
79
80 ethernet-phy@6400 {
81 linux,phandle = <6400>;
82 interrupt-parent = <7400>;
83 interrupts = <2 1>;
84 reg = <6000 50>;
85 phy-id = <9>;
86 device_type = "ethernet-phy";
87 };
88
89 };
90
91 ethernet@6200 {
92 #size-cells = <0>;
93 device_type = "network";
94 model = "TSI-ETH";
95 compatible = "tsi-ethernet";
96 reg = <6000 200>;
97 address = [ 00 06 D2 00 00 01 ];
98 interrupts = <10 2>;
99 interrupt-parent = <7400>;
100 phy-handle = <6000>;
101 };
102
103 ethernet@6600 {
104 #address-cells = <1>;
105 #size-cells = <0>;
106 device_type = "network";
107 model = "TSI-ETH";
108 compatible = "tsi-ethernet";
109 reg = <6400 200>;
110 address = [ 00 06 D2 00 00 02 ];
111 interrupts = <11 2>;
112 interrupt-parent = <7400>;
113 phy-handle = <6400>;
114 };
115
116 serial@7808 {
117 device_type = "serial";
118 compatible = "ns16550";
119 reg = <7808 200>;
120 clock-frequency = <3f6b5a00>;
121 interrupts = <c 0>;
122 interrupt-parent = <7400>;
123 };
124
125 serial@7c08 {
126 device_type = "serial";
127 compatible = "ns16550";
128 reg = <7c08 200>;
129 clock-frequency = <3f6b5a00>;
130 interrupts = <d 0>;
131 interrupt-parent = <7400>;
132 };
133
134 pic@7400 {
135 linux,phandle = <7400>;
136 clock-frequency = <0>;
137 interrupt-controller;
138 #address-cells = <0>;
139 #interrupt-cells = <2>;
140 reg = <7400 400>;
141 built-in;
142 compatible = "chrp,open-pic";
143 device_type = "open-pic";
144 big-endian;
145 };
146 pci@1000 {
147 compatible = "tsi10x";
148 device_type = "pci";
149 linux,phandle = <1000>;
150 #interrupt-cells = <1>;
151 #size-cells = <2>;
152 #address-cells = <3>;
153 reg = <1000 1000>;
154 bus-range = <0 0>;
155 ranges = <02000000 0 e0000000 e0000000 0 1A000000
156 01000000 0 00000000 fa000000 0 00010000>;
157 clock-frequency = <7f28154>;
158 interrupt-parent = <7400>;
159 interrupts = <17 2>;
160 interrupt-map-mask = <f800 0 0 7>;
161 interrupt-map = <
162
163 /* IDSEL 0x11 */
164 0800 0 0 1 7400 24 0
165 0800 0 0 2 7400 25 0
166 0800 0 0 3 7400 26 0
167 0800 0 0 4 7400 27 0
168
169 /* IDSEL 0x12 */
170 1000 0 0 1 7400 25 0
171 1000 0 0 2 7400 26 0
172 1000 0 0 3 7400 27 0
173 1000 0 0 4 7400 24 0
174
175 /* IDSEL 0x13 */
176 1800 0 0 1 7400 26 0
177 1800 0 0 2 7400 27 0
178 1800 0 0 3 7400 24 0
179 1800 0 0 4 7400 25 0
180
181 /* IDSEL 0x14 */
182 2000 0 0 1 7400 27 0
183 2000 0 0 2 7400 24 0
184 2000 0 0 3 7400 25 0
185 2000 0 0 4 7400 26 0
186 >;
187 };
188 };
189
190};
diff --git a/arch/powerpc/boot/dts/mpc8349emds.dts b/arch/powerpc/boot/dts/mpc8349emds.dts
new file mode 100644
index 000000000000..12f5dbf3055f
--- /dev/null
+++ b/arch/powerpc/boot/dts/mpc8349emds.dts
@@ -0,0 +1,328 @@
1/*
2 * MPC8349E MDS Device Tree Source
3 *
4 * Copyright 2005, 2006 Freescale Semiconductor Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
11
12/ {
13 model = "MPC8349EMDS";
14 compatible = "MPC834xMDS";
15 #address-cells = <1>;
16 #size-cells = <1>;
17
18 cpus {
19 #cpus = <1>;
20 #address-cells = <1>;
21 #size-cells = <0>;
22
23 PowerPC,8349@0 {
24 device_type = "cpu";
25 reg = <0>;
26 d-cache-line-size = <20>; // 32 bytes
27 i-cache-line-size = <20>; // 32 bytes
28 d-cache-size = <8000>; // L1, 32K
29 i-cache-size = <8000>; // L1, 32K
30 timebase-frequency = <0>; // from bootloader
31 bus-frequency = <0>; // from bootloader
32 clock-frequency = <0>; // from bootloader
33 32-bit;
34 };
35 };
36
37 memory {
38 device_type = "memory";
39 reg = <00000000 10000000>; // 256MB at 0
40 };
41
42 soc8349@e0000000 {
43 #address-cells = <1>;
44 #size-cells = <1>;
45 #interrupt-cells = <2>;
46 device_type = "soc";
47 ranges = <0 e0000000 00100000>;
48 reg = <e0000000 00000200>;
49 bus-frequency = <0>;
50
51 wdt@200 {
52 device_type = "watchdog";
53 compatible = "mpc83xx_wdt";
54 reg = <200 100>;
55 };
56
57 i2c@3000 {
58 device_type = "i2c";
59 compatible = "fsl-i2c";
60 reg = <3000 100>;
61 interrupts = <e 8>;
62 interrupt-parent = <700>;
63 dfsrr;
64 };
65
66 i2c@3100 {
67 device_type = "i2c";
68 compatible = "fsl-i2c";
69 reg = <3100 100>;
70 interrupts = <f 8>;
71 interrupt-parent = <700>;
72 dfsrr;
73 };
74
75 spi@7000 {
76 device_type = "spi";
77 compatible = "mpc83xx_spi";
78 reg = <7000 1000>;
79 interrupts = <10 8>;
80 interrupt-parent = <700>;
81 mode = <0>;
82 };
83
84 /* phy type (ULPI or SERIAL) are only types supportted for MPH */
85 /* port = 0 or 1 */
86 usb@22000 {
87 device_type = "usb";
88 compatible = "fsl-usb2-mph";
89 reg = <22000 1000>;
90 #address-cells = <1>;
91 #size-cells = <0>;
92 interrupt-parent = <700>;
93 interrupts = <27 2>;
94 phy_type = "ulpi";
95 port1;
96 };
97 /* phy type (ULPI, UTMI, UTMI_WIDE, SERIAL) */
98 usb@23000 {
99 device_type = "usb";
100 compatible = "fsl-usb2-dr";
101 reg = <23000 1000>;
102 #address-cells = <1>;
103 #size-cells = <0>;
104 interrupt-parent = <700>;
105 interrupts = <26 2>;
106 phy_type = "ulpi";
107 };
108
109 mdio@24520 {
110 device_type = "mdio";
111 compatible = "gianfar";
112 reg = <24520 20>;
113 #address-cells = <1>;
114 #size-cells = <0>;
115 linux,phandle = <24520>;
116 ethernet-phy@0 {
117 linux,phandle = <2452000>;
118 interrupt-parent = <700>;
119 interrupts = <11 2>;
120 reg = <0>;
121 device_type = "ethernet-phy";
122 };
123 ethernet-phy@1 {
124 linux,phandle = <2452001>;
125 interrupt-parent = <700>;
126 interrupts = <12 2>;
127 reg = <1>;
128 device_type = "ethernet-phy";
129 };
130 };
131
132 ethernet@24000 {
133 device_type = "network";
134 model = "TSEC";
135 compatible = "gianfar";
136 reg = <24000 1000>;
137 address = [ 00 00 00 00 00 00 ];
138 local-mac-address = [ 00 00 00 00 00 00 ];
139 interrupts = <20 8 21 8 22 8>;
140 interrupt-parent = <700>;
141 phy-handle = <2452000>;
142 };
143
144 ethernet@25000 {
145 #address-cells = <1>;
146 #size-cells = <0>;
147 device_type = "network";
148 model = "TSEC";
149 compatible = "gianfar";
150 reg = <25000 1000>;
151 address = [ 00 00 00 00 00 00 ];
152 local-mac-address = [ 00 00 00 00 00 00 ];
153 interrupts = <23 8 24 8 25 8>;
154 interrupt-parent = <700>;
155 phy-handle = <2452001>;
156 };
157
158 serial@4500 {
159 device_type = "serial";
160 compatible = "ns16550";
161 reg = <4500 100>;
162 clock-frequency = <0>;
163 interrupts = <9 8>;
164 interrupt-parent = <700>;
165 };
166
167 serial@4600 {
168 device_type = "serial";
169 compatible = "ns16550";
170 reg = <4600 100>;
171 clock-frequency = <0>;
172 interrupts = <a 8>;
173 interrupt-parent = <700>;
174 };
175
176 pci@8500 {
177 interrupt-map-mask = <f800 0 0 7>;
178 interrupt-map = <
179
180 /* IDSEL 0x11 */
181 8800 0 0 1 700 14 8
182 8800 0 0 2 700 15 8
183 8800 0 0 3 700 16 8
184 8800 0 0 4 700 17 8
185
186 /* IDSEL 0x12 */
187 9000 0 0 1 700 16 8
188 9000 0 0 2 700 17 8
189 9000 0 0 3 700 14 8
190 9000 0 0 4 700 15 8
191
192 /* IDSEL 0x13 */
193 9800 0 0 1 700 17 8
194 9800 0 0 2 700 14 8
195 9800 0 0 3 700 15 8
196 9800 0 0 4 700 16 8
197
198 /* IDSEL 0x15 */
199 a800 0 0 1 700 14 8
200 a800 0 0 2 700 15 8
201 a800 0 0 3 700 16 8
202 a800 0 0 4 700 17 8
203
204 /* IDSEL 0x16 */
205 b000 0 0 1 700 17 8
206 b000 0 0 2 700 14 8
207 b000 0 0 3 700 15 8
208 b000 0 0 4 700 16 8
209
210 /* IDSEL 0x17 */
211 b800 0 0 1 700 16 8
212 b800 0 0 2 700 17 8
213 b800 0 0 3 700 14 8
214 b800 0 0 4 700 15 8
215
216 /* IDSEL 0x18 */
217 b000 0 0 1 700 15 8
218 b000 0 0 2 700 16 8
219 b000 0 0 3 700 17 8
220 b000 0 0 4 700 14 8>;
221 interrupt-parent = <700>;
222 interrupts = <42 8>;
223 bus-range = <0 0>;
224 ranges = <02000000 0 a0000000 a0000000 0 10000000
225 42000000 0 80000000 80000000 0 10000000
226 01000000 0 00000000 e2000000 0 00100000>;
227 clock-frequency = <3f940aa>;
228 #interrupt-cells = <1>;
229 #size-cells = <2>;
230 #address-cells = <3>;
231 reg = <8500 100>;
232 compatible = "83xx";
233 device_type = "pci";
234 };
235
236 pci@8600 {
237 interrupt-map-mask = <f800 0 0 7>;
238 interrupt-map = <
239
240 /* IDSEL 0x11 */
241 8800 0 0 1 700 14 8
242 8800 0 0 2 700 15 8
243 8800 0 0 3 700 16 8
244 8800 0 0 4 700 17 8
245
246 /* IDSEL 0x12 */
247 9000 0 0 1 700 16 8
248 9000 0 0 2 700 17 8
249 9000 0 0 3 700 14 8
250 9000 0 0 4 700 15 8
251
252 /* IDSEL 0x13 */
253 9800 0 0 1 700 17 8
254 9800 0 0 2 700 14 8
255 9800 0 0 3 700 15 8
256 9800 0 0 4 700 16 8
257
258 /* IDSEL 0x15 */
259 a800 0 0 1 700 14 8
260 a800 0 0 2 700 15 8
261 a800 0 0 3 700 16 8
262 a800 0 0 4 700 17 8
263
264 /* IDSEL 0x16 */
265 b000 0 0 1 700 17 8
266 b000 0 0 2 700 14 8
267 b000 0 0 3 700 15 8
268 b000 0 0 4 700 16 8
269
270 /* IDSEL 0x17 */
271 b800 0 0 1 700 16 8
272 b800 0 0 2 700 17 8
273 b800 0 0 3 700 14 8
274 b800 0 0 4 700 15 8
275
276 /* IDSEL 0x18 */
277 b000 0 0 1 700 15 8
278 b000 0 0 2 700 16 8
279 b000 0 0 3 700 17 8
280 b000 0 0 4 700 14 8>;
281 interrupt-parent = <700>;
282 interrupts = <42 8>;
283 bus-range = <0 0>;
284 ranges = <02000000 0 b0000000 b0000000 0 10000000
285 42000000 0 90000000 90000000 0 10000000
286 01000000 0 00000000 e2100000 0 00100000>;
287 clock-frequency = <3f940aa>;
288 #interrupt-cells = <1>;
289 #size-cells = <2>;
290 #address-cells = <3>;
291 reg = <8600 100>;
292 compatible = "83xx";
293 device_type = "pci";
294 };
295
296 /* May need to remove if on a part without crypto engine */
297 crypto@30000 {
298 device_type = "crypto";
299 model = "SEC2";
300 compatible = "talitos";
301 reg = <30000 10000>;
302 interrupts = <b 8>;
303 interrupt-parent = <700>;
304 num-channels = <4>;
305 channel-fifo-len = <18>;
306 exec-units-mask = <0000007e>;
307 /* desc mask is for rev2.0,
308 * we need runtime fixup for >2.0 */
309 descriptor-types-mask = <01010ebf>;
310 };
311
312 /* IPIC
313 * interrupts cell = <intr #, sense>
314 * sense values match linux IORESOURCE_IRQ_* defines:
315 * sense == 8: Level, low assertion
316 * sense == 2: Edge, high-to-low change
317 */
318 pic@700 {
319 linux,phandle = <700>;
320 interrupt-controller;
321 #address-cells = <0>;
322 #interrupt-cells = <2>;
323 reg = <700 100>;
324 built-in;
325 device_type = "ipic";
326 };
327 };
328};
diff --git a/arch/powerpc/boot/dts/mpc8540ads.dts b/arch/powerpc/boot/dts/mpc8540ads.dts
new file mode 100644
index 000000000000..5f41c1f7a5f3
--- /dev/null
+++ b/arch/powerpc/boot/dts/mpc8540ads.dts
@@ -0,0 +1,257 @@
1/*
2 * MPC8540 ADS Device Tree Source
3 *
4 * Copyright 2006 Freescale Semiconductor Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
11
12
13/ {
14 model = "MPC8540ADS";
15 compatible = "MPC85xxADS";
16 #address-cells = <1>;
17 #size-cells = <1>;
18 linux,phandle = <100>;
19
20 cpus {
21 #cpus = <1>;
22 #address-cells = <1>;
23 #size-cells = <0>;
24 linux,phandle = <200>;
25
26 PowerPC,8540@0 {
27 device_type = "cpu";
28 reg = <0>;
29 d-cache-line-size = <20>; // 32 bytes
30 i-cache-line-size = <20>; // 32 bytes
31 d-cache-size = <8000>; // L1, 32K
32 i-cache-size = <8000>; // L1, 32K
33 timebase-frequency = <0>; // 33 MHz, from uboot
34 bus-frequency = <0>; // 166 MHz
35 clock-frequency = <0>; // 825 MHz, from uboot
36 32-bit;
37 linux,phandle = <201>;
38 };
39 };
40
41 memory {
42 device_type = "memory";
43 linux,phandle = <300>;
44 reg = <00000000 08000000>; // 128M at 0x0
45 };
46
47 soc8540@e0000000 {
48 #address-cells = <1>;
49 #size-cells = <1>;
50 #interrupt-cells = <2>;
51 device_type = "soc";
52 ranges = <0 e0000000 00100000>;
53 reg = <e0000000 00100000>; // CCSRBAR 1M
54 bus-frequency = <0>;
55
56 i2c@3000 {
57 device_type = "i2c";
58 compatible = "fsl-i2c";
59 reg = <3000 100>;
60 interrupts = <1b 2>;
61 interrupt-parent = <40000>;
62 dfsrr;
63 };
64
65 mdio@24520 {
66 #address-cells = <1>;
67 #size-cells = <0>;
68 device_type = "mdio";
69 compatible = "gianfar";
70 reg = <24520 20>;
71 linux,phandle = <24520>;
72 ethernet-phy@0 {
73 linux,phandle = <2452000>;
74 interrupt-parent = <40000>;
75 interrupts = <35 1>;
76 reg = <0>;
77 device_type = "ethernet-phy";
78 };
79 ethernet-phy@1 {
80 linux,phandle = <2452001>;
81 interrupt-parent = <40000>;
82 interrupts = <35 1>;
83 reg = <1>;
84 device_type = "ethernet-phy";
85 };
86 ethernet-phy@3 {
87 linux,phandle = <2452003>;
88 interrupt-parent = <40000>;
89 interrupts = <37 1>;
90 reg = <3>;
91 device_type = "ethernet-phy";
92 };
93 };
94
95 ethernet@24000 {
96 #address-cells = <1>;
97 #size-cells = <0>;
98 device_type = "network";
99 model = "TSEC";
100 compatible = "gianfar";
101 reg = <24000 1000>;
102 address = [ 00 E0 0C 00 73 00 ];
103 local-mac-address = [ 00 E0 0C 00 73 00 ];
104 interrupts = <d 2 e 2 12 2>;
105 interrupt-parent = <40000>;
106 phy-handle = <2452000>;
107 };
108
109 ethernet@25000 {
110 #address-cells = <1>;
111 #size-cells = <0>;
112 device_type = "network";
113 model = "TSEC";
114 compatible = "gianfar";
115 reg = <25000 1000>;
116 address = [ 00 E0 0C 00 73 01 ];
117 local-mac-address = [ 00 E0 0C 00 73 01 ];
118 interrupts = <13 2 14 2 18 2>;
119 interrupt-parent = <40000>;
120 phy-handle = <2452001>;
121 };
122
123 ethernet@26000 {
124 #address-cells = <1>;
125 #size-cells = <0>;
126 device_type = "network";
127 model = "FEC";
128 compatible = "gianfar";
129 reg = <26000 1000>;
130 address = [ 00 E0 0C 00 73 02 ];
131 local-mac-address = [ 00 E0 0C 00 73 02 ];
132 interrupts = <19 2>;
133 interrupt-parent = <40000>;
134 phy-handle = <2452003>;
135 };
136
137 serial@4500 {
138 device_type = "serial";
139 compatible = "ns16550";
140 reg = <4500 100>; // reg base, size
141 clock-frequency = <0>; // should we fill in in uboot?
142 interrupts = <1a 2>;
143 interrupt-parent = <40000>;
144 };
145
146 serial@4600 {
147 device_type = "serial";
148 compatible = "ns16550";
149 reg = <4600 100>; // reg base, size
150 clock-frequency = <0>; // should we fill in in uboot?
151 interrupts = <1a 2>;
152 interrupt-parent = <40000>;
153 };
154 pci@8000 {
155 linux,phandle = <8000>;
156 interrupt-map-mask = <f800 0 0 7>;
157 interrupt-map = <
158
159 /* IDSEL 0x02 */
160 1000 0 0 1 40000 31 1
161 1000 0 0 2 40000 32 1
162 1000 0 0 3 40000 33 1
163 1000 0 0 4 40000 34 1
164
165 /* IDSEL 0x03 */
166 1800 0 0 1 40000 34 1
167 1800 0 0 2 40000 31 1
168 1800 0 0 3 40000 32 1
169 1800 0 0 4 40000 33 1
170
171 /* IDSEL 0x04 */
172 2000 0 0 1 40000 33 1
173 2000 0 0 2 40000 34 1
174 2000 0 0 3 40000 31 1
175 2000 0 0 4 40000 32 1
176
177 /* IDSEL 0x05 */
178 2800 0 0 1 40000 32 1
179 2800 0 0 2 40000 33 1
180 2800 0 0 3 40000 34 1
181 2800 0 0 4 40000 31 1
182
183 /* IDSEL 0x0c */
184 6000 0 0 1 40000 31 1
185 6000 0 0 2 40000 32 1
186 6000 0 0 3 40000 33 1
187 6000 0 0 4 40000 34 1
188
189 /* IDSEL 0x0d */
190 6800 0 0 1 40000 34 1
191 6800 0 0 2 40000 31 1
192 6800 0 0 3 40000 32 1
193 6800 0 0 4 40000 33 1
194
195 /* IDSEL 0x0e */
196 7000 0 0 1 40000 33 1
197 7000 0 0 2 40000 34 1
198 7000 0 0 3 40000 31 1
199 7000 0 0 4 40000 32 1
200
201 /* IDSEL 0x0f */
202 7800 0 0 1 40000 32 1
203 7800 0 0 2 40000 33 1
204 7800 0 0 3 40000 34 1
205 7800 0 0 4 40000 31 1
206
207 /* IDSEL 0x12 */
208 9000 0 0 1 40000 31 1
209 9000 0 0 2 40000 32 1
210 9000 0 0 3 40000 33 1
211 9000 0 0 4 40000 34 1
212
213 /* IDSEL 0x13 */
214 9800 0 0 1 40000 34 1
215 9800 0 0 2 40000 31 1
216 9800 0 0 3 40000 32 1
217 9800 0 0 4 40000 33 1
218
219 /* IDSEL 0x14 */
220 a000 0 0 1 40000 33 1
221 a000 0 0 2 40000 34 1
222 a000 0 0 3 40000 31 1
223 a000 0 0 4 40000 32 1
224
225 /* IDSEL 0x15 */
226 a800 0 0 1 40000 32 1
227 a800 0 0 2 40000 33 1
228 a800 0 0 3 40000 34 1
229 a800 0 0 4 40000 31 1>;
230 interrupt-parent = <40000>;
231 interrupts = <08 2>;
232 bus-range = <0 0>;
233 ranges = <02000000 0 80000000 80000000 0 20000000
234 01000000 0 00000000 e2000000 0 00100000>;
235 clock-frequency = <3f940aa>;
236 #interrupt-cells = <1>;
237 #size-cells = <2>;
238 #address-cells = <3>;
239 reg = <8000 1000>;
240 compatible = "85xx";
241 device_type = "pci";
242 };
243
244 pic@40000 {
245 linux,phandle = <40000>;
246 clock-frequency = <0>;
247 interrupt-controller;
248 #address-cells = <0>;
249 #interrupt-cells = <2>;
250 reg = <40000 40000>;
251 built-in;
252 compatible = "chrp,open-pic";
253 device_type = "open-pic";
254 big-endian;
255 };
256 };
257};
diff --git a/arch/powerpc/boot/dts/mpc8541cds.dts b/arch/powerpc/boot/dts/mpc8541cds.dts
new file mode 100644
index 000000000000..7be0bc659e1c
--- /dev/null
+++ b/arch/powerpc/boot/dts/mpc8541cds.dts
@@ -0,0 +1,244 @@
1/*
2 * MPC8541 CDS Device Tree Source
3 *
4 * Copyright 2006 Freescale Semiconductor Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
11
12
13/ {
14 model = "MPC8541CDS";
15 compatible = "MPC85xxCDS";
16 #address-cells = <1>;
17 #size-cells = <1>;
18 linux,phandle = <100>;
19
20 cpus {
21 #cpus = <1>;
22 #address-cells = <1>;
23 #size-cells = <0>;
24 linux,phandle = <200>;
25
26 PowerPC,8541@0 {
27 device_type = "cpu";
28 reg = <0>;
29 d-cache-line-size = <20>; // 32 bytes
30 i-cache-line-size = <20>; // 32 bytes
31 d-cache-size = <8000>; // L1, 32K
32 i-cache-size = <8000>; // L1, 32K
33 timebase-frequency = <0>; // 33 MHz, from uboot
34 bus-frequency = <0>; // 166 MHz
35 clock-frequency = <0>; // 825 MHz, from uboot
36 32-bit;
37 linux,phandle = <201>;
38 };
39 };
40
41 memory {
42 device_type = "memory";
43 linux,phandle = <300>;
44 reg = <00000000 08000000>; // 128M at 0x0
45 };
46
47 soc8541@e0000000 {
48 #address-cells = <1>;
49 #size-cells = <1>;
50 #interrupt-cells = <2>;
51 device_type = "soc";
52 ranges = <0 e0000000 00100000>;
53 reg = <e0000000 00100000>; // CCSRBAR 1M
54 bus-frequency = <0>;
55
56 i2c@3000 {
57 device_type = "i2c";
58 compatible = "fsl-i2c";
59 reg = <3000 100>;
60 interrupts = <1b 2>;
61 interrupt-parent = <40000>;
62 dfsrr;
63 };
64
65 mdio@24520 {
66 #address-cells = <1>;
67 #size-cells = <0>;
68 device_type = "mdio";
69 compatible = "gianfar";
70 reg = <24520 20>;
71 linux,phandle = <24520>;
72 ethernet-phy@0 {
73 linux,phandle = <2452000>;
74 interrupt-parent = <40000>;
75 interrupts = <35 0>;
76 reg = <0>;
77 device_type = "ethernet-phy";
78 };
79 ethernet-phy@1 {
80 linux,phandle = <2452001>;
81 interrupt-parent = <40000>;
82 interrupts = <35 0>;
83 reg = <1>;
84 device_type = "ethernet-phy";
85 };
86 };
87
88 ethernet@24000 {
89 #address-cells = <1>;
90 #size-cells = <0>;
91 device_type = "network";
92 model = "TSEC";
93 compatible = "gianfar";
94 reg = <24000 1000>;
95 local-mac-address = [ 00 E0 0C 00 73 00 ];
96 interrupts = <d 2 e 2 12 2>;
97 interrupt-parent = <40000>;
98 phy-handle = <2452000>;
99 };
100
101 ethernet@25000 {
102 #address-cells = <1>;
103 #size-cells = <0>;
104 device_type = "network";
105 model = "TSEC";
106 compatible = "gianfar";
107 reg = <25000 1000>;
108 local-mac-address = [ 00 E0 0C 00 73 01 ];
109 interrupts = <13 2 14 2 18 2>;
110 interrupt-parent = <40000>;
111 phy-handle = <2452001>;
112 };
113
114 serial@4500 {
115 device_type = "serial";
116 compatible = "ns16550";
117 reg = <4500 100>; // reg base, size
118 clock-frequency = <0>; // should we fill in in uboot?
119 interrupts = <1a 2>;
120 interrupt-parent = <40000>;
121 };
122
123 serial@4600 {
124 device_type = "serial";
125 compatible = "ns16550";
126 reg = <4600 100>; // reg base, size
127 clock-frequency = <0>; // should we fill in in uboot?
128 interrupts = <1a 2>;
129 interrupt-parent = <40000>;
130 };
131
132 pci@8000 {
133 linux,phandle = <8000>;
134 interrupt-map-mask = <1f800 0 0 7>;
135 interrupt-map = <
136
137 /* IDSEL 0x10 */
138 08000 0 0 1 40000 30 1
139 08000 0 0 2 40000 31 1
140 08000 0 0 3 40000 32 1
141 08000 0 0 4 40000 33 1
142
143 /* IDSEL 0x11 */
144 08800 0 0 1 40000 30 1
145 08800 0 0 2 40000 31 1
146 08800 0 0 3 40000 32 1
147 08800 0 0 4 40000 33 1
148
149 /* IDSEL 0x12 (Slot 1) */
150 09000 0 0 1 40000 30 1
151 09000 0 0 2 40000 31 1
152 09000 0 0 3 40000 32 1
153 09000 0 0 4 40000 33 1
154
155 /* IDSEL 0x13 (Slot 2) */
156 09800 0 0 1 40000 31 1
157 09800 0 0 2 40000 32 1
158 09800 0 0 3 40000 33 1
159 09800 0 0 4 40000 30 1
160
161 /* IDSEL 0x14 (Slot 3) */
162 0a000 0 0 1 40000 32 1
163 0a000 0 0 2 40000 33 1
164 0a000 0 0 3 40000 30 1
165 0a000 0 0 4 40000 31 1
166
167 /* IDSEL 0x15 (Slot 4) */
168 0a800 0 0 1 40000 33 1
169 0a800 0 0 2 40000 30 1
170 0a800 0 0 3 40000 31 1
171 0a800 0 0 4 40000 32 1
172
173 /* Bus 1 (Tundra Bridge) */
174 /* IDSEL 0x12 (ISA bridge) */
175 19000 0 0 1 40000 30 1
176 19000 0 0 2 40000 31 1
177 19000 0 0 3 40000 32 1
178 19000 0 0 4 40000 33 1>;
179 interrupt-parent = <40000>;
180 interrupts = <08 2>;
181 bus-range = <0 0>;
182 ranges = <02000000 0 80000000 80000000 0 20000000
183 01000000 0 00000000 e2000000 0 00100000>;
184 clock-frequency = <3f940aa>;
185 #interrupt-cells = <1>;
186 #size-cells = <2>;
187 #address-cells = <3>;
188 reg = <8000 1000>;
189 compatible = "85xx";
190 device_type = "pci";
191
192 i8259@19000 {
193 clock-frequency = <0>;
194 interrupt-controller;
195 device_type = "interrupt-controller";
196 reg = <19000 0 0 0 1>;
197 #address-cells = <0>;
198 #interrupt-cells = <2>;
199 built-in;
200 compatible = "chrp,iic";
201 big-endian;
202 interrupts = <1>;
203 interrupt-parent = <8000>;
204 };
205 };
206
207 pci@9000 {
208 linux,phandle = <9000>;
209 interrupt-map-mask = <f800 0 0 7>;
210 interrupt-map = <
211
212 /* IDSEL 0x15 */
213 a800 0 0 1 40000 3b 1
214 a800 0 0 2 40000 3b 1
215 a800 0 0 3 40000 3b 1
216 a800 0 0 4 40000 3b 1>;
217 interrupt-parent = <40000>;
218 interrupts = <09 2>;
219 bus-range = <0 0>;
220 ranges = <02000000 0 a0000000 a0000000 0 20000000
221 01000000 0 00000000 e3000000 0 00100000>;
222 clock-frequency = <3f940aa>;
223 #interrupt-cells = <1>;
224 #size-cells = <2>;
225 #address-cells = <3>;
226 reg = <9000 1000>;
227 compatible = "85xx";
228 device_type = "pci";
229 };
230
231 pic@40000 {
232 linux,phandle = <40000>;
233 clock-frequency = <0>;
234 interrupt-controller;
235 #address-cells = <0>;
236 #interrupt-cells = <2>;
237 reg = <40000 40000>;
238 built-in;
239 compatible = "chrp,open-pic";
240 device_type = "open-pic";
241 big-endian;
242 };
243 };
244};
diff --git a/arch/powerpc/boot/dts/mpc8548cds.dts b/arch/powerpc/boot/dts/mpc8548cds.dts
new file mode 100644
index 000000000000..893d7957c174
--- /dev/null
+++ b/arch/powerpc/boot/dts/mpc8548cds.dts
@@ -0,0 +1,287 @@
1/*
2 * MPC8555 CDS Device Tree Source
3 *
4 * Copyright 2006 Freescale Semiconductor Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
11
12
13/ {
14 model = "MPC8548CDS";
15 compatible = "MPC85xxCDS";
16 #address-cells = <1>;
17 #size-cells = <1>;
18 linux,phandle = <100>;
19
20 cpus {
21 #cpus = <1>;
22 #address-cells = <1>;
23 #size-cells = <0>;
24 linux,phandle = <200>;
25
26 PowerPC,8548@0 {
27 device_type = "cpu";
28 reg = <0>;
29 d-cache-line-size = <20>; // 32 bytes
30 i-cache-line-size = <20>; // 32 bytes
31 d-cache-size = <8000>; // L1, 32K
32 i-cache-size = <8000>; // L1, 32K
33 timebase-frequency = <0>; // 33 MHz, from uboot
34 bus-frequency = <0>; // 166 MHz
35 clock-frequency = <0>; // 825 MHz, from uboot
36 32-bit;
37 linux,phandle = <201>;
38 };
39 };
40
41 memory {
42 device_type = "memory";
43 linux,phandle = <300>;
44 reg = <00000000 08000000>; // 128M at 0x0
45 };
46
47 soc8548@e0000000 {
48 #address-cells = <1>;
49 #size-cells = <1>;
50 #interrupt-cells = <2>;
51 device_type = "soc";
52 ranges = <0 e0000000 00100000>;
53 reg = <e0000000 00100000>; // CCSRBAR 1M
54 bus-frequency = <0>;
55
56 i2c@3000 {
57 device_type = "i2c";
58 compatible = "fsl-i2c";
59 reg = <3000 100>;
60 interrupts = <1b 2>;
61 interrupt-parent = <40000>;
62 dfsrr;
63 };
64
65 mdio@24520 {
66 #address-cells = <1>;
67 #size-cells = <0>;
68 device_type = "mdio";
69 compatible = "gianfar";
70 reg = <24520 20>;
71 linux,phandle = <24520>;
72 ethernet-phy@0 {
73 linux,phandle = <2452000>;
74 interrupt-parent = <40000>;
75 interrupts = <35 0>;
76 reg = <0>;
77 device_type = "ethernet-phy";
78 };
79 ethernet-phy@1 {
80 linux,phandle = <2452001>;
81 interrupt-parent = <40000>;
82 interrupts = <35 0>;
83 reg = <1>;
84 device_type = "ethernet-phy";
85 };
86
87 ethernet-phy@2 {
88 linux,phandle = <2452002>;
89 interrupt-parent = <40000>;
90 interrupts = <35 0>;
91 reg = <2>;
92 device_type = "ethernet-phy";
93 };
94 ethernet-phy@3 {
95 linux,phandle = <2452003>;
96 interrupt-parent = <40000>;
97 interrupts = <35 0>;
98 reg = <3>;
99 device_type = "ethernet-phy";
100 };
101 };
102
103 ethernet@24000 {
104 #address-cells = <1>;
105 #size-cells = <0>;
106 device_type = "network";
107 model = "eTSEC";
108 compatible = "gianfar";
109 reg = <24000 1000>;
110 local-mac-address = [ 00 E0 0C 00 73 00 ];
111 interrupts = <d 2 e 2 12 2>;
112 interrupt-parent = <40000>;
113 phy-handle = <2452000>;
114 };
115
116 ethernet@25000 {
117 #address-cells = <1>;
118 #size-cells = <0>;
119 device_type = "network";
120 model = "eTSEC";
121 compatible = "gianfar";
122 reg = <25000 1000>;
123 local-mac-address = [ 00 E0 0C 00 73 01 ];
124 interrupts = <13 2 14 2 18 2>;
125 interrupt-parent = <40000>;
126 phy-handle = <2452001>;
127 };
128
129 ethernet@26000 {
130 #address-cells = <1>;
131 #size-cells = <0>;
132 device_type = "network";
133 model = "eTSEC";
134 compatible = "gianfar";
135 reg = <26000 1000>;
136 local-mac-address = [ 00 E0 0C 00 73 02 ];
137 interrupts = <f 2 10 2 11 2>;
138 interrupt-parent = <40000>;
139 phy-handle = <2452001>;
140 };
141
142/* eTSEC 4 is currently broken
143 ethernet@27000 {
144 #address-cells = <1>;
145 #size-cells = <0>;
146 device_type = "network";
147 model = "eTSEC";
148 compatible = "gianfar";
149 reg = <27000 1000>;
150 local-mac-address = [ 00 E0 0C 00 73 03 ];
151 interrupts = <15 2 16 2 17 2>;
152 interrupt-parent = <40000>;
153 phy-handle = <2452001>;
154 };
155 */
156
157 serial@4500 {
158 device_type = "serial";
159 compatible = "ns16550";
160 reg = <4500 100>; // reg base, size
161 clock-frequency = <0>; // should we fill in in uboot?
162 interrupts = <1a 2>;
163 interrupt-parent = <40000>;
164 };
165
166 serial@4600 {
167 device_type = "serial";
168 compatible = "ns16550";
169 reg = <4600 100>; // reg base, size
170 clock-frequency = <0>; // should we fill in in uboot?
171 interrupts = <1a 2>;
172 interrupt-parent = <40000>;
173 };
174
175 pci@8000 {
176 linux,phandle = <8000>;
177 interrupt-map-mask = <1f800 0 0 7>;
178 interrupt-map = <
179
180 /* IDSEL 0x10 */
181 08000 0 0 1 40000 30 1
182 08000 0 0 2 40000 31 1
183 08000 0 0 3 40000 32 1
184 08000 0 0 4 40000 33 1
185
186 /* IDSEL 0x11 */
187 08800 0 0 1 40000 30 1
188 08800 0 0 2 40000 31 1
189 08800 0 0 3 40000 32 1
190 08800 0 0 4 40000 33 1
191
192 /* IDSEL 0x12 (Slot 1) */
193 09000 0 0 1 40000 30 1
194 09000 0 0 2 40000 31 1
195 09000 0 0 3 40000 32 1
196 09000 0 0 4 40000 33 1
197
198 /* IDSEL 0x13 (Slot 2) */
199 09800 0 0 1 40000 31 1
200 09800 0 0 2 40000 32 1
201 09800 0 0 3 40000 33 1
202 09800 0 0 4 40000 30 1
203
204 /* IDSEL 0x14 (Slot 3) */
205 0a000 0 0 1 40000 32 1
206 0a000 0 0 2 40000 33 1
207 0a000 0 0 3 40000 30 1
208 0a000 0 0 4 40000 31 1
209
210 /* IDSEL 0x15 (Slot 4) */
211 0a800 0 0 1 40000 33 1
212 0a800 0 0 2 40000 30 1
213 0a800 0 0 3 40000 31 1
214 0a800 0 0 4 40000 32 1
215
216 /* Bus 1 (Tundra Bridge) */
217 /* IDSEL 0x12 (ISA bridge) */
218 19000 0 0 1 40000 30 1
219 19000 0 0 2 40000 31 1
220 19000 0 0 3 40000 32 1
221 19000 0 0 4 40000 33 1>;
222 interrupt-parent = <40000>;
223 interrupts = <08 2>;
224 bus-range = <0 0>;
225 ranges = <02000000 0 80000000 80000000 0 20000000
226 01000000 0 00000000 e2000000 0 00100000>;
227 clock-frequency = <3f940aa>;
228 #interrupt-cells = <1>;
229 #size-cells = <2>;
230 #address-cells = <3>;
231 reg = <8000 1000>;
232 compatible = "85xx";
233 device_type = "pci";
234
235 i8259@19000 {
236 clock-frequency = <0>;
237 interrupt-controller;
238 device_type = "interrupt-controller";
239 reg = <19000 0 0 0 1>;
240 #address-cells = <0>;
241 #interrupt-cells = <2>;
242 built-in;
243 compatible = "chrp,iic";
244 big-endian;
245 interrupts = <1>;
246 interrupt-parent = <8000>;
247 };
248 };
249
250 pci@9000 {
251 linux,phandle = <9000>;
252 interrupt-map-mask = <f800 0 0 7>;
253 interrupt-map = <
254
255 /* IDSEL 0x15 */
256 a800 0 0 1 40000 3b 1
257 a800 0 0 2 40000 3b 1
258 a800 0 0 3 40000 3b 1
259 a800 0 0 4 40000 3b 1>;
260 interrupt-parent = <40000>;
261 interrupts = <09 2>;
262 bus-range = <0 0>;
263 ranges = <02000000 0 a0000000 a0000000 0 20000000
264 01000000 0 00000000 e3000000 0 00100000>;
265 clock-frequency = <3f940aa>;
266 #interrupt-cells = <1>;
267 #size-cells = <2>;
268 #address-cells = <3>;
269 reg = <9000 1000>;
270 compatible = "85xx";
271 device_type = "pci";
272 };
273
274 pic@40000 {
275 linux,phandle = <40000>;
276 clock-frequency = <0>;
277 interrupt-controller;
278 #address-cells = <0>;
279 #interrupt-cells = <2>;
280 reg = <40000 40000>;
281 built-in;
282 compatible = "chrp,open-pic";
283 device_type = "open-pic";
284 big-endian;
285 };
286 };
287};
diff --git a/arch/powerpc/boot/dts/mpc8555cds.dts b/arch/powerpc/boot/dts/mpc8555cds.dts
new file mode 100644
index 000000000000..118f5a887651
--- /dev/null
+++ b/arch/powerpc/boot/dts/mpc8555cds.dts
@@ -0,0 +1,244 @@
1/*
2 * MPC8555 CDS Device Tree Source
3 *
4 * Copyright 2006 Freescale Semiconductor Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
11
12
13/ {
14 model = "MPC8555CDS";
15 compatible = "MPC85xxCDS";
16 #address-cells = <1>;
17 #size-cells = <1>;
18 linux,phandle = <100>;
19
20 cpus {
21 #cpus = <1>;
22 #address-cells = <1>;
23 #size-cells = <0>;
24 linux,phandle = <200>;
25
26 PowerPC,8555@0 {
27 device_type = "cpu";
28 reg = <0>;
29 d-cache-line-size = <20>; // 32 bytes
30 i-cache-line-size = <20>; // 32 bytes
31 d-cache-size = <8000>; // L1, 32K
32 i-cache-size = <8000>; // L1, 32K
33 timebase-frequency = <0>; // 33 MHz, from uboot
34 bus-frequency = <0>; // 166 MHz
35 clock-frequency = <0>; // 825 MHz, from uboot
36 32-bit;
37 linux,phandle = <201>;
38 };
39 };
40
41 memory {
42 device_type = "memory";
43 linux,phandle = <300>;
44 reg = <00000000 08000000>; // 128M at 0x0
45 };
46
47 soc8555@e0000000 {
48 #address-cells = <1>;
49 #size-cells = <1>;
50 #interrupt-cells = <2>;
51 device_type = "soc";
52 ranges = <0 e0000000 00100000>;
53 reg = <e0000000 00100000>; // CCSRBAR 1M
54 bus-frequency = <0>;
55
56 i2c@3000 {
57 device_type = "i2c";
58 compatible = "fsl-i2c";
59 reg = <3000 100>;
60 interrupts = <1b 2>;
61 interrupt-parent = <40000>;
62 dfsrr;
63 };
64
65 mdio@24520 {
66 #address-cells = <1>;
67 #size-cells = <0>;
68 device_type = "mdio";
69 compatible = "gianfar";
70 reg = <24520 20>;
71 linux,phandle = <24520>;
72 ethernet-phy@0 {
73 linux,phandle = <2452000>;
74 interrupt-parent = <40000>;
75 interrupts = <35 0>;
76 reg = <0>;
77 device_type = "ethernet-phy";
78 };
79 ethernet-phy@1 {
80 linux,phandle = <2452001>;
81 interrupt-parent = <40000>;
82 interrupts = <35 0>;
83 reg = <1>;
84 device_type = "ethernet-phy";
85 };
86 };
87
88 ethernet@24000 {
89 #address-cells = <1>;
90 #size-cells = <0>;
91 device_type = "network";
92 model = "TSEC";
93 compatible = "gianfar";
94 reg = <24000 1000>;
95 local-mac-address = [ 00 E0 0C 00 73 00 ];
96 interrupts = <0d 2 0e 2 12 2>;
97 interrupt-parent = <40000>;
98 phy-handle = <2452000>;
99 };
100
101 ethernet@25000 {
102 #address-cells = <1>;
103 #size-cells = <0>;
104 device_type = "network";
105 model = "TSEC";
106 compatible = "gianfar";
107 reg = <25000 1000>;
108 local-mac-address = [ 00 E0 0C 00 73 01 ];
109 interrupts = <13 2 14 2 18 2>;
110 interrupt-parent = <40000>;
111 phy-handle = <2452001>;
112 };
113
114 serial@4500 {
115 device_type = "serial";
116 compatible = "ns16550";
117 reg = <4500 100>; // reg base, size
118 clock-frequency = <0>; // should we fill in in uboot?
119 interrupts = <1a 2>;
120 interrupt-parent = <40000>;
121 };
122
123 serial@4600 {
124 device_type = "serial";
125 compatible = "ns16550";
126 reg = <4600 100>; // reg base, size
127 clock-frequency = <0>; // should we fill in in uboot?
128 interrupts = <1a 2>;
129 interrupt-parent = <40000>;
130 };
131
132 pci@8000 {
133 linux,phandle = <8000>;
134 interrupt-map-mask = <1f800 0 0 7>;
135 interrupt-map = <
136
137 /* IDSEL 0x10 */
138 08000 0 0 1 40000 30 1
139 08000 0 0 2 40000 31 1
140 08000 0 0 3 40000 32 1
141 08000 0 0 4 40000 33 1
142
143 /* IDSEL 0x11 */
144 08800 0 0 1 40000 30 1
145 08800 0 0 2 40000 31 1
146 08800 0 0 3 40000 32 1
147 08800 0 0 4 40000 33 1
148
149 /* IDSEL 0x12 (Slot 1) */
150 09000 0 0 1 40000 30 1
151 09000 0 0 2 40000 31 1
152 09000 0 0 3 40000 32 1
153 09000 0 0 4 40000 33 1
154
155 /* IDSEL 0x13 (Slot 2) */
156 09800 0 0 1 40000 31 1
157 09800 0 0 2 40000 32 1
158 09800 0 0 3 40000 33 1
159 09800 0 0 4 40000 30 1
160
161 /* IDSEL 0x14 (Slot 3) */
162 0a000 0 0 1 40000 32 1
163 0a000 0 0 2 40000 33 1
164 0a000 0 0 3 40000 30 1
165 0a000 0 0 4 40000 31 1
166
167 /* IDSEL 0x15 (Slot 4) */
168 0a800 0 0 1 40000 33 1
169 0a800 0 0 2 40000 30 1
170 0a800 0 0 3 40000 31 1
171 0a800 0 0 4 40000 32 1
172
173 /* Bus 1 (Tundra Bridge) */
174 /* IDSEL 0x12 (ISA bridge) */
175 19000 0 0 1 40000 30 1
176 19000 0 0 2 40000 31 1
177 19000 0 0 3 40000 32 1
178 19000 0 0 4 40000 33 1>;
179 interrupt-parent = <40000>;
180 interrupts = <08 2>;
181 bus-range = <0 0>;
182 ranges = <02000000 0 80000000 80000000 0 20000000
183 01000000 0 00000000 e2000000 0 00100000>;
184 clock-frequency = <3f940aa>;
185 #interrupt-cells = <1>;
186 #size-cells = <2>;
187 #address-cells = <3>;
188 reg = <8000 1000>;
189 compatible = "85xx";
190 device_type = "pci";
191
192 i8259@19000 {
193 clock-frequency = <0>;
194 interrupt-controller;
195 device_type = "interrupt-controller";
196 reg = <19000 0 0 0 1>;
197 #address-cells = <0>;
198 #interrupt-cells = <2>;
199 built-in;
200 compatible = "chrp,iic";
201 big-endian;
202 interrupts = <1>;
203 interrupt-parent = <8000>;
204 };
205 };
206
207 pci@9000 {
208 linux,phandle = <9000>;
209 interrupt-map-mask = <f800 0 0 7>;
210 interrupt-map = <
211
212 /* IDSEL 0x15 */
213 a800 0 0 1 40000 3b 1
214 a800 0 0 2 40000 3b 1
215 a800 0 0 3 40000 3b 1
216 a800 0 0 4 40000 3b 1>;
217 interrupt-parent = <40000>;
218 interrupts = <09 2>;
219 bus-range = <0 0>;
220 ranges = <02000000 0 a0000000 a0000000 0 20000000
221 01000000 0 00000000 e3000000 0 00100000>;
222 clock-frequency = <3f940aa>;
223 #interrupt-cells = <1>;
224 #size-cells = <2>;
225 #address-cells = <3>;
226 reg = <9000 1000>;
227 compatible = "85xx";
228 device_type = "pci";
229 };
230
231 pic@40000 {
232 linux,phandle = <40000>;
233 clock-frequency = <0>;
234 interrupt-controller;
235 #address-cells = <0>;
236 #interrupt-cells = <2>;
237 reg = <40000 40000>;
238 built-in;
239 compatible = "chrp,open-pic";
240 device_type = "open-pic";
241 big-endian;
242 };
243 };
244};
diff --git a/arch/powerpc/boot/dts/mpc8641_hpcn.dts b/arch/powerpc/boot/dts/mpc8641_hpcn.dts
new file mode 100644
index 000000000000..f0c7731743ea
--- /dev/null
+++ b/arch/powerpc/boot/dts/mpc8641_hpcn.dts
@@ -0,0 +1,339 @@
1/*
2 * MPC8641 HPCN Device Tree Source
3 *
4 * Copyright 2006 Freescale Semiconductor Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
11
12
13/ {
14 model = "MPC8641HPCN";
15 compatible = "mpc86xx";
16 #address-cells = <1>;
17 #size-cells = <1>;
18
19 cpus {
20 #cpus = <2>;
21 #address-cells = <1>;
22 #size-cells = <0>;
23
24 PowerPC,8641@0 {
25 device_type = "cpu";
26 reg = <0>;
27 d-cache-line-size = <20>; // 32 bytes
28 i-cache-line-size = <20>; // 32 bytes
29 d-cache-size = <8000>; // L1, 32K
30 i-cache-size = <8000>; // L1, 32K
31 timebase-frequency = <0>; // 33 MHz, from uboot
32 bus-frequency = <0>; // From uboot
33 clock-frequency = <0>; // From uboot
34 32-bit;
35 linux,boot-cpu;
36 };
37 PowerPC,8641@1 {
38 device_type = "cpu";
39 reg = <1>;
40 d-cache-line-size = <20>; // 32 bytes
41 i-cache-line-size = <20>; // 32 bytes
42 d-cache-size = <8000>; // L1, 32K
43 i-cache-size = <8000>; // L1, 32K
44 timebase-frequency = <0>; // 33 MHz, from uboot
45 bus-frequency = <0>; // From uboot
46 clock-frequency = <0>; // From uboot
47 32-bit;
48 };
49 };
50
51 memory {
52 device_type = "memory";
53 reg = <00000000 40000000>; // 1G at 0x0
54 };
55
56 soc8641@f8000000 {
57 #address-cells = <1>;
58 #size-cells = <1>;
59 #interrupt-cells = <2>;
60 device_type = "soc";
61 ranges = <0 f8000000 00100000>;
62 reg = <f8000000 00100000>; // CCSRBAR 1M
63 bus-frequency = <0>;
64
65 i2c@3000 {
66 device_type = "i2c";
67 compatible = "fsl-i2c";
68 reg = <3000 100>;
69 interrupts = <2b 2>;
70 interrupt-parent = <40000>;
71 dfsrr;
72 };
73
74 i2c@3100 {
75 device_type = "i2c";
76 compatible = "fsl-i2c";
77 reg = <3100 100>;
78 interrupts = <2b 2>;
79 interrupt-parent = <40000>;
80 dfsrr;
81 };
82
83 mdio@24520 {
84 #address-cells = <1>;
85 #size-cells = <0>;
86 device_type = "mdio";
87 compatible = "gianfar";
88 reg = <24520 20>;
89 linux,phandle = <24520>;
90 ethernet-phy@0 {
91 linux,phandle = <2452000>;
92 interrupt-parent = <40000>;
93 interrupts = <4a 1>;
94 reg = <0>;
95 device_type = "ethernet-phy";
96 };
97 ethernet-phy@1 {
98 linux,phandle = <2452001>;
99 interrupt-parent = <40000>;
100 interrupts = <4a 1>;
101 reg = <1>;
102 device_type = "ethernet-phy";
103 };
104 ethernet-phy@2 {
105 linux,phandle = <2452002>;
106 interrupt-parent = <40000>;
107 interrupts = <4a 1>;
108 reg = <2>;
109 device_type = "ethernet-phy";
110 };
111 ethernet-phy@3 {
112 linux,phandle = <2452003>;
113 interrupt-parent = <40000>;
114 interrupts = <4a 1>;
115 reg = <3>;
116 device_type = "ethernet-phy";
117 };
118 };
119
120 ethernet@24000 {
121 #address-cells = <1>;
122 #size-cells = <0>;
123 device_type = "network";
124 model = "TSEC";
125 compatible = "gianfar";
126 reg = <24000 1000>;
127 mac-address = [ 00 E0 0C 00 73 00 ];
128 interrupts = <1d 2 1e 2 22 2>;
129 interrupt-parent = <40000>;
130 phy-handle = <2452000>;
131 };
132
133 ethernet@25000 {
134 #address-cells = <1>;
135 #size-cells = <0>;
136 device_type = "network";
137 model = "TSEC";
138 compatible = "gianfar";
139 reg = <25000 1000>;
140 mac-address = [ 00 E0 0C 00 73 01 ];
141 interrupts = <23 2 24 2 28 2>;
142 interrupt-parent = <40000>;
143 phy-handle = <2452001>;
144 };
145
146 ethernet@26000 {
147 #address-cells = <1>;
148 #size-cells = <0>;
149 device_type = "network";
150 model = "TSEC";
151 compatible = "gianfar";
152 reg = <26000 1000>;
153 mac-address = [ 00 E0 0C 00 02 FD ];
154 interrupts = <1F 2 20 2 21 2>;
155 interrupt-parent = <40000>;
156 phy-handle = <2452002>;
157 };
158
159 ethernet@27000 {
160 #address-cells = <1>;
161 #size-cells = <0>;
162 device_type = "network";
163 model = "TSEC";
164 compatible = "gianfar";
165 reg = <27000 1000>;
166 mac-address = [ 00 E0 0C 00 03 FD ];
167 interrupts = <25 2 26 2 27 2>;
168 interrupt-parent = <40000>;
169 phy-handle = <2452003>;
170 };
171 serial@4500 {
172 device_type = "serial";
173 compatible = "ns16550";
174 reg = <4500 100>;
175 clock-frequency = <0>;
176 interrupts = <2a 2>;
177 interrupt-parent = <40000>;
178 };
179
180 serial@4600 {
181 device_type = "serial";
182 compatible = "ns16550";
183 reg = <4600 100>;
184 clock-frequency = <0>;
185 interrupts = <1c 2>;
186 interrupt-parent = <40000>;
187 };
188
189 pci@8000 {
190 compatible = "86xx";
191 device_type = "pci";
192 #interrupt-cells = <1>;
193 #size-cells = <2>;
194 #address-cells = <3>;
195 reg = <8000 1000>;
196 bus-range = <0 fe>;
197 ranges = <02000000 0 80000000 80000000 0 20000000
198 01000000 0 00000000 e2000000 0 00100000>;
199 clock-frequency = <1fca055>;
200 interrupt-parent = <40000>;
201 interrupts = <18 2>;
202 interrupt-map-mask = <f800 0 0 7>;
203 interrupt-map = <
204 /* IDSEL 0x11 */
205 8800 0 0 1 4d0 3 2
206 8800 0 0 2 4d0 4 2
207 8800 0 0 3 4d0 5 2
208 8800 0 0 4 4d0 6 2
209
210 /* IDSEL 0x12 */
211 9000 0 0 1 4d0 4 2
212 9000 0 0 2 4d0 5 2
213 9000 0 0 3 4d0 6 2
214 9000 0 0 4 4d0 3 2
215
216 /* IDSEL 0x13 */
217 9800 0 0 1 4d0 0 0
218 9800 0 0 2 4d0 0 0
219 9800 0 0 3 4d0 0 0
220 9800 0 0 4 4d0 0 0
221
222 /* IDSEL 0x14 */
223 a000 0 0 1 4d0 0 0
224 a000 0 0 2 4d0 0 0
225 a000 0 0 3 4d0 0 0
226 a000 0 0 4 4d0 0 0
227
228 /* IDSEL 0x15 */
229 a800 0 0 1 4d0 0 0
230 a800 0 0 2 4d0 0 0
231 a800 0 0 3 4d0 0 0
232 a800 0 0 4 4d0 0 0
233
234 /* IDSEL 0x16 */
235 b000 0 0 1 4d0 0 0
236 b000 0 0 2 4d0 0 0
237 b000 0 0 3 4d0 0 0
238 b000 0 0 4 4d0 0 0
239
240 /* IDSEL 0x17 */
241 b800 0 0 1 4d0 0 0
242 b800 0 0 2 4d0 0 0
243 b800 0 0 3 4d0 0 0
244 b800 0 0 4 4d0 0 0
245
246 /* IDSEL 0x18 */
247 c000 0 0 1 4d0 0 0
248 c000 0 0 2 4d0 0 0
249 c000 0 0 3 4d0 0 0
250 c000 0 0 4 4d0 0 0
251
252 /* IDSEL 0x19 */
253 c800 0 0 1 4d0 0 0
254 c800 0 0 2 4d0 0 0
255 c800 0 0 3 4d0 0 0
256 c800 0 0 4 4d0 0 0
257
258 /* IDSEL 0x1a */
259 d000 0 0 1 4d0 6 2
260 d000 0 0 2 4d0 3 2
261 d000 0 0 3 4d0 4 2
262 d000 0 0 4 4d0 5 2
263
264
265 /* IDSEL 0x1b */
266 d800 0 0 1 4d0 5 2
267 d800 0 0 2 4d0 0 0
268 d800 0 0 3 4d0 0 0
269 d800 0 0 4 4d0 0 0
270
271 /* IDSEL 0x1c */
272 e000 0 0 1 4d0 9 2
273 e000 0 0 2 4d0 a 2
274 e000 0 0 3 4d0 c 2
275 e000 0 0 4 4d0 7 2
276
277 /* IDSEL 0x1d */
278 e800 0 0 1 4d0 9 2
279 e800 0 0 2 4d0 a 2
280 e800 0 0 3 4d0 b 2
281 e800 0 0 4 4d0 0 0
282
283 /* IDSEL 0x1e */
284 f000 0 0 1 4d0 c 2
285 f000 0 0 2 4d0 0 0
286 f000 0 0 3 4d0 0 0
287 f000 0 0 4 4d0 0 0
288
289 /* IDSEL 0x1f */
290 f800 0 0 1 4d0 6 2
291 f800 0 0 2 4d0 0 0
292 f800 0 0 3 4d0 0 0
293 f800 0 0 4 4d0 0 0
294 >;
295 i8259@4d0 {
296 linux,phandle = <4d0>;
297 clock-frequency = <0>;
298 interrupt-controller;
299 device_type = "interrupt-controller";
300 #address-cells = <0>;
301 #interrupt-cells = <2>;
302 built-in;
303 compatible = "chrp,iic";
304 big-endian;
305 interrupts = <49 2>;
306 interrupt-parent = <40000>;
307 };
308
309 };
310 pic@40000 {
311 linux,phandle = <40000>;
312 clock-frequency = <0>;
313 interrupt-controller;
314 #address-cells = <0>;
315 #interrupt-cells = <2>;
316 reg = <40000 40000>;
317 built-in;
318 compatible = "chrp,open-pic";
319 device_type = "open-pic";
320 big-endian;
321 interrupts = <
322 10 2 11 2 12 2 13 2
323 14 2 15 2 16 2 17 2
324 18 2 19 2 1a 2 1b 2
325 1c 2 1d 2 1e 2 1f 2
326 20 2 21 2 22 2 23 2
327 24 2 25 2 26 2 27 2
328 28 2 29 2 2a 2 2b 2
329 2c 2 2d 2 2e 2 2f 2
330 30 2 31 2 32 2 33 2
331 34 2 35 2 36 2 37 2
332 38 2 39 2 2a 2 3b 2
333 3c 2 3d 2 3e 2 3f 2
334 48 1 49 2 4a 1
335 >;
336 interrupt-parent = <40000>;
337 };
338 };
339};
diff --git a/arch/powerpc/configs/g5_defconfig b/arch/powerpc/configs/g5_defconfig
index a45627547d03..8c6bd17c6929 100644
--- a/arch/powerpc/configs/g5_defconfig
+++ b/arch/powerpc/configs/g5_defconfig
@@ -1,16 +1,18 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.17-rc1 3# Linux kernel version: 2.6.18-rc3
4# Wed Apr 19 13:24:37 2006 4# Tue Aug 8 09:12:29 2006
5# 5#
6CONFIG_PPC64=y 6CONFIG_PPC64=y
7CONFIG_64BIT=y 7CONFIG_64BIT=y
8CONFIG_PPC_MERGE=y 8CONFIG_PPC_MERGE=y
9CONFIG_MMU=y 9CONFIG_MMU=y
10CONFIG_GENERIC_HARDIRQS=y 10CONFIG_GENERIC_HARDIRQS=y
11CONFIG_IRQ_PER_CPU=y
11CONFIG_RWSEM_XCHGADD_ALGORITHM=y 12CONFIG_RWSEM_XCHGADD_ALGORITHM=y
12CONFIG_GENERIC_HWEIGHT=y 13CONFIG_GENERIC_HWEIGHT=y
13CONFIG_GENERIC_CALIBRATE_DELAY=y 14CONFIG_GENERIC_CALIBRATE_DELAY=y
15CONFIG_GENERIC_FIND_NEXT_BIT=y
14CONFIG_PPC=y 16CONFIG_PPC=y
15CONFIG_EARLY_PRINTK=y 17CONFIG_EARLY_PRINTK=y
16CONFIG_COMPAT=y 18CONFIG_COMPAT=y
@@ -33,6 +35,7 @@ CONFIG_PPC_STD_MMU=y
33CONFIG_VIRT_CPU_ACCOUNTING=y 35CONFIG_VIRT_CPU_ACCOUNTING=y
34CONFIG_SMP=y 36CONFIG_SMP=y
35CONFIG_NR_CPUS=4 37CONFIG_NR_CPUS=4
38CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
36 39
37# 40#
38# Code maturity level options 41# Code maturity level options
@@ -50,6 +53,7 @@ CONFIG_SWAP=y
50CONFIG_SYSVIPC=y 53CONFIG_SYSVIPC=y
51CONFIG_POSIX_MQUEUE=y 54CONFIG_POSIX_MQUEUE=y
52# CONFIG_BSD_PROCESS_ACCT is not set 55# CONFIG_BSD_PROCESS_ACCT is not set
56# CONFIG_TASKSTATS is not set
53CONFIG_SYSCTL=y 57CONFIG_SYSCTL=y
54# CONFIG_AUDIT is not set 58# CONFIG_AUDIT is not set
55CONFIG_IKCONFIG=y 59CONFIG_IKCONFIG=y
@@ -67,10 +71,12 @@ CONFIG_PRINTK=y
67CONFIG_BUG=y 71CONFIG_BUG=y
68CONFIG_ELF_CORE=y 72CONFIG_ELF_CORE=y
69CONFIG_BASE_FULL=y 73CONFIG_BASE_FULL=y
74CONFIG_RT_MUTEXES=y
70CONFIG_FUTEX=y 75CONFIG_FUTEX=y
71CONFIG_EPOLL=y 76CONFIG_EPOLL=y
72CONFIG_SHMEM=y 77CONFIG_SHMEM=y
73CONFIG_SLAB=y 78CONFIG_SLAB=y
79CONFIG_VM_EVENT_COUNTERS=y
74# CONFIG_TINY_SHMEM is not set 80# CONFIG_TINY_SHMEM is not set
75CONFIG_BASE_SMALL=0 81CONFIG_BASE_SMALL=0
76# CONFIG_SLOB is not set 82# CONFIG_SLOB is not set
@@ -116,12 +122,16 @@ CONFIG_PPC_PMAC=y
116CONFIG_PPC_PMAC64=y 122CONFIG_PPC_PMAC64=y
117# CONFIG_PPC_MAPLE is not set 123# CONFIG_PPC_MAPLE is not set
118# CONFIG_PPC_CELL is not set 124# CONFIG_PPC_CELL is not set
125# CONFIG_PPC_CELL_NATIVE is not set
126# CONFIG_PPC_IBM_CELL_BLADE is not set
127# CONFIG_UDBG_RTAS_CONSOLE is not set
119CONFIG_U3_DART=y 128CONFIG_U3_DART=y
120CONFIG_MPIC=y 129CONFIG_MPIC=y
121# CONFIG_PPC_RTAS is not set 130# CONFIG_PPC_RTAS is not set
122# CONFIG_MMIO_NVRAM is not set 131# CONFIG_MMIO_NVRAM is not set
123CONFIG_MPIC_BROKEN_U3=y 132CONFIG_MPIC_BROKEN_U3=y
124# CONFIG_PPC_MPC106 is not set 133# CONFIG_PPC_MPC106 is not set
134CONFIG_PPC_970_NAP=y
125CONFIG_CPU_FREQ=y 135CONFIG_CPU_FREQ=y
126CONFIG_CPU_FREQ_TABLE=y 136CONFIG_CPU_FREQ_TABLE=y
127# CONFIG_CPU_FREQ_DEBUG is not set 137# CONFIG_CPU_FREQ_DEBUG is not set
@@ -153,6 +163,7 @@ CONFIG_BINFMT_ELF=y
153CONFIG_FORCE_MAX_ZONEORDER=13 163CONFIG_FORCE_MAX_ZONEORDER=13
154CONFIG_IOMMU_VMERGE=y 164CONFIG_IOMMU_VMERGE=y
155# CONFIG_HOTPLUG_CPU is not set 165# CONFIG_HOTPLUG_CPU is not set
166CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y
156CONFIG_KEXEC=y 167CONFIG_KEXEC=y
157# CONFIG_CRASH_DUMP is not set 168# CONFIG_CRASH_DUMP is not set
158CONFIG_IRQ_ALL_CPUS=y 169CONFIG_IRQ_ALL_CPUS=y
@@ -168,6 +179,7 @@ CONFIG_FLATMEM=y
168CONFIG_FLAT_NODE_MEM_MAP=y 179CONFIG_FLAT_NODE_MEM_MAP=y
169# CONFIG_SPARSEMEM_STATIC is not set 180# CONFIG_SPARSEMEM_STATIC is not set
170CONFIG_SPLIT_PTLOCK_CPUS=4 181CONFIG_SPLIT_PTLOCK_CPUS=4
182CONFIG_RESOURCES_64BIT=y
171# CONFIG_PPC_64K_PAGES is not set 183# CONFIG_PPC_64K_PAGES is not set
172# CONFIG_SCHED_SMT is not set 184# CONFIG_SCHED_SMT is not set
173CONFIG_PROC_DEVICETREE=y 185CONFIG_PROC_DEVICETREE=y
@@ -184,6 +196,7 @@ CONFIG_GENERIC_ISA_DMA=y
184# CONFIG_PPC_INDIRECT_PCI is not set 196# CONFIG_PPC_INDIRECT_PCI is not set
185CONFIG_PCI=y 197CONFIG_PCI=y
186CONFIG_PCI_DOMAINS=y 198CONFIG_PCI_DOMAINS=y
199# CONFIG_PCIEPORTBUS is not set
187# CONFIG_PCI_DEBUG is not set 200# CONFIG_PCI_DEBUG is not set
188 201
189# 202#
@@ -227,6 +240,8 @@ CONFIG_INET_ESP=m
227CONFIG_INET_IPCOMP=m 240CONFIG_INET_IPCOMP=m
228CONFIG_INET_XFRM_TUNNEL=m 241CONFIG_INET_XFRM_TUNNEL=m
229CONFIG_INET_TUNNEL=y 242CONFIG_INET_TUNNEL=y
243CONFIG_INET_XFRM_MODE_TRANSPORT=y
244CONFIG_INET_XFRM_MODE_TUNNEL=y
230CONFIG_INET_DIAG=y 245CONFIG_INET_DIAG=y
231CONFIG_INET_TCP_DIAG=y 246CONFIG_INET_TCP_DIAG=y
232# CONFIG_TCP_CONG_ADVANCED is not set 247# CONFIG_TCP_CONG_ADVANCED is not set
@@ -239,6 +254,7 @@ CONFIG_TCP_CONG_BIC=y
239# CONFIG_IPV6 is not set 254# CONFIG_IPV6 is not set
240# CONFIG_INET6_XFRM_TUNNEL is not set 255# CONFIG_INET6_XFRM_TUNNEL is not set
241# CONFIG_INET6_TUNNEL is not set 256# CONFIG_INET6_TUNNEL is not set
257# CONFIG_NETWORK_SECMARK is not set
242CONFIG_NETFILTER=y 258CONFIG_NETFILTER=y
243# CONFIG_NETFILTER_DEBUG is not set 259# CONFIG_NETFILTER_DEBUG is not set
244 260
@@ -263,6 +279,7 @@ CONFIG_IP_NF_TFTP=m
263CONFIG_IP_NF_AMANDA=m 279CONFIG_IP_NF_AMANDA=m
264# CONFIG_IP_NF_PPTP is not set 280# CONFIG_IP_NF_PPTP is not set
265# CONFIG_IP_NF_H323 is not set 281# CONFIG_IP_NF_H323 is not set
282# CONFIG_IP_NF_SIP is not set
266CONFIG_IP_NF_QUEUE=m 283CONFIG_IP_NF_QUEUE=m
267 284
268# 285#
@@ -318,6 +335,7 @@ CONFIG_STANDALONE=y
318CONFIG_PREVENT_FIRMWARE_BUILD=y 335CONFIG_PREVENT_FIRMWARE_BUILD=y
319CONFIG_FW_LOADER=y 336CONFIG_FW_LOADER=y
320# CONFIG_DEBUG_DRIVER is not set 337# CONFIG_DEBUG_DRIVER is not set
338# CONFIG_SYS_HYPERVISOR is not set
321 339
322# 340#
323# Connector - unified userspace <-> kernelspace linker 341# Connector - unified userspace <-> kernelspace linker
@@ -355,6 +373,7 @@ CONFIG_BLK_DEV_NBD=m
355CONFIG_BLK_DEV_RAM=y 373CONFIG_BLK_DEV_RAM=y
356CONFIG_BLK_DEV_RAM_COUNT=16 374CONFIG_BLK_DEV_RAM_COUNT=16
357CONFIG_BLK_DEV_RAM_SIZE=65536 375CONFIG_BLK_DEV_RAM_SIZE=65536
376CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
358CONFIG_BLK_DEV_INITRD=y 377CONFIG_BLK_DEV_INITRD=y
359CONFIG_CDROM_PKTCDVD=m 378CONFIG_CDROM_PKTCDVD=m
360CONFIG_CDROM_PKTCDVD_BUFFERS=8 379CONFIG_CDROM_PKTCDVD_BUFFERS=8
@@ -417,7 +436,6 @@ CONFIG_IDEDMA_PCI_AUTO=y
417CONFIG_BLK_DEV_IDE_PMAC=y 436CONFIG_BLK_DEV_IDE_PMAC=y
418CONFIG_BLK_DEV_IDE_PMAC_ATA100FIRST=y 437CONFIG_BLK_DEV_IDE_PMAC_ATA100FIRST=y
419CONFIG_BLK_DEV_IDEDMA_PMAC=y 438CONFIG_BLK_DEV_IDEDMA_PMAC=y
420# CONFIG_BLK_DEV_IDE_PMAC_BLINK is not set
421# CONFIG_IDE_ARM is not set 439# CONFIG_IDE_ARM is not set
422CONFIG_BLK_DEV_IDEDMA=y 440CONFIG_BLK_DEV_IDEDMA=y
423# CONFIG_IDEDMA_IVB is not set 441# CONFIG_IDEDMA_IVB is not set
@@ -478,6 +496,7 @@ CONFIG_SCSI_SATA_SVW=y
478# CONFIG_SCSI_SATA_MV is not set 496# CONFIG_SCSI_SATA_MV is not set
479# CONFIG_SCSI_SATA_NV is not set 497# CONFIG_SCSI_SATA_NV is not set
480# CONFIG_SCSI_PDC_ADMA is not set 498# CONFIG_SCSI_PDC_ADMA is not set
499# CONFIG_SCSI_HPTIOP is not set
481# CONFIG_SCSI_SATA_QSTOR is not set 500# CONFIG_SCSI_SATA_QSTOR is not set
482# CONFIG_SCSI_SATA_PROMISE is not set 501# CONFIG_SCSI_SATA_PROMISE is not set
483# CONFIG_SCSI_SATA_SX4 is not set 502# CONFIG_SCSI_SATA_SX4 is not set
@@ -497,7 +516,6 @@ CONFIG_SCSI_SATA_SVW=y
497# CONFIG_SCSI_INIA100 is not set 516# CONFIG_SCSI_INIA100 is not set
498# CONFIG_SCSI_SYM53C8XX_2 is not set 517# CONFIG_SCSI_SYM53C8XX_2 is not set
499# CONFIG_SCSI_IPR is not set 518# CONFIG_SCSI_IPR is not set
500# CONFIG_SCSI_QLOGIC_FC is not set
501# CONFIG_SCSI_QLOGIC_1280 is not set 519# CONFIG_SCSI_QLOGIC_1280 is not set
502# CONFIG_SCSI_QLA_FC is not set 520# CONFIG_SCSI_QLA_FC is not set
503# CONFIG_SCSI_LPFC is not set 521# CONFIG_SCSI_LPFC is not set
@@ -514,9 +532,7 @@ CONFIG_MD_LINEAR=y
514CONFIG_MD_RAID0=y 532CONFIG_MD_RAID0=y
515CONFIG_MD_RAID1=y 533CONFIG_MD_RAID1=y
516CONFIG_MD_RAID10=m 534CONFIG_MD_RAID10=m
517CONFIG_MD_RAID5=y 535# CONFIG_MD_RAID456 is not set
518# CONFIG_MD_RAID5_RESHAPE is not set
519CONFIG_MD_RAID6=m
520CONFIG_MD_MULTIPATH=m 536CONFIG_MD_MULTIPATH=m
521CONFIG_MD_FAULTY=m 537CONFIG_MD_FAULTY=m
522CONFIG_BLK_DEV_DM=y 538CONFIG_BLK_DEV_DM=y
@@ -559,7 +575,6 @@ CONFIG_IEEE1394_OHCI1394=y
559# 575#
560CONFIG_IEEE1394_VIDEO1394=m 576CONFIG_IEEE1394_VIDEO1394=m
561CONFIG_IEEE1394_SBP2=m 577CONFIG_IEEE1394_SBP2=m
562# CONFIG_IEEE1394_SBP2_PHYS_DMA is not set
563CONFIG_IEEE1394_ETH1394=m 578CONFIG_IEEE1394_ETH1394=m
564CONFIG_IEEE1394_DV1394=m 579CONFIG_IEEE1394_DV1394=m
565CONFIG_IEEE1394_RAWIO=y 580CONFIG_IEEE1394_RAWIO=y
@@ -573,6 +588,7 @@ CONFIG_IEEE1394_RAWIO=y
573# Macintosh device drivers 588# Macintosh device drivers
574# 589#
575CONFIG_ADB_PMU=y 590CONFIG_ADB_PMU=y
591# CONFIG_ADB_PMU_LED is not set
576CONFIG_PMAC_SMU=y 592CONFIG_PMAC_SMU=y
577CONFIG_THERM_PM72=y 593CONFIG_THERM_PM72=y
578CONFIG_WINDFARM=y 594CONFIG_WINDFARM=y
@@ -643,6 +659,7 @@ CONFIG_TIGON3=y
643# CONFIG_CHELSIO_T1 is not set 659# CONFIG_CHELSIO_T1 is not set
644# CONFIG_IXGB is not set 660# CONFIG_IXGB is not set
645# CONFIG_S2IO is not set 661# CONFIG_S2IO is not set
662# CONFIG_MYRI10GE is not set
646 663
647# 664#
648# Token Ring devices 665# Token Ring devices
@@ -739,6 +756,7 @@ CONFIG_SERIO=y
739CONFIG_VT=y 756CONFIG_VT=y
740CONFIG_VT_CONSOLE=y 757CONFIG_VT_CONSOLE=y
741CONFIG_HW_CONSOLE=y 758CONFIG_HW_CONSOLE=y
759# CONFIG_VT_HW_CONSOLE_BINDING is not set
742# CONFIG_SERIAL_NONSTANDARD is not set 760# CONFIG_SERIAL_NONSTANDARD is not set
743 761
744# 762#
@@ -754,6 +772,7 @@ CONFIG_HW_CONSOLE=y
754CONFIG_UNIX98_PTYS=y 772CONFIG_UNIX98_PTYS=y
755CONFIG_LEGACY_PTYS=y 773CONFIG_LEGACY_PTYS=y
756CONFIG_LEGACY_PTY_COUNT=256 774CONFIG_LEGACY_PTY_COUNT=256
775# CONFIG_BRIQ_PANEL is not set
757 776
758# 777#
759# IPMI 778# IPMI
@@ -764,6 +783,7 @@ CONFIG_LEGACY_PTY_COUNT=256
764# Watchdog Cards 783# Watchdog Cards
765# 784#
766# CONFIG_WATCHDOG is not set 785# CONFIG_WATCHDOG is not set
786# CONFIG_HW_RANDOM is not set
767CONFIG_GEN_RTC=y 787CONFIG_GEN_RTC=y
768# CONFIG_GEN_RTC_X is not set 788# CONFIG_GEN_RTC_X is not set
769# CONFIG_DTLK is not set 789# CONFIG_DTLK is not set
@@ -774,6 +794,7 @@ CONFIG_GEN_RTC=y
774# Ftape, the floppy tape device driver 794# Ftape, the floppy tape device driver
775# 795#
776CONFIG_AGP=m 796CONFIG_AGP=m
797# CONFIG_AGP_SIS is not set
777# CONFIG_AGP_VIA is not set 798# CONFIG_AGP_VIA is not set
778CONFIG_AGP_UNINORTH=m 799CONFIG_AGP_UNINORTH=m
779# CONFIG_DRM is not set 800# CONFIG_DRM is not set
@@ -813,6 +834,7 @@ CONFIG_I2C_ALGOBIT=y
813# CONFIG_I2C_PIIX4 is not set 834# CONFIG_I2C_PIIX4 is not set
814CONFIG_I2C_POWERMAC=y 835CONFIG_I2C_POWERMAC=y
815# CONFIG_I2C_NFORCE2 is not set 836# CONFIG_I2C_NFORCE2 is not set
837# CONFIG_I2C_OCORES is not set
816# CONFIG_I2C_PARPORT_LIGHT is not set 838# CONFIG_I2C_PARPORT_LIGHT is not set
817# CONFIG_I2C_PROSAVAGE is not set 839# CONFIG_I2C_PROSAVAGE is not set
818# CONFIG_I2C_SAVAGE4 is not set 840# CONFIG_I2C_SAVAGE4 is not set
@@ -849,7 +871,6 @@ CONFIG_I2C_POWERMAC=y
849# 871#
850# Dallas's 1-wire bus 872# Dallas's 1-wire bus
851# 873#
852# CONFIG_W1 is not set
853 874
854# 875#
855# Hardware Monitoring support 876# Hardware Monitoring support
@@ -865,6 +886,7 @@ CONFIG_I2C_POWERMAC=y
865# Multimedia devices 886# Multimedia devices
866# 887#
867# CONFIG_VIDEO_DEV is not set 888# CONFIG_VIDEO_DEV is not set
889CONFIG_VIDEO_V4L2=y
868 890
869# 891#
870# Digital Video Broadcasting Devices 892# Digital Video Broadcasting Devices
@@ -875,22 +897,19 @@ CONFIG_I2C_POWERMAC=y
875# 897#
876# Graphics support 898# Graphics support
877# 899#
900CONFIG_FIRMWARE_EDID=y
878CONFIG_FB=y 901CONFIG_FB=y
879CONFIG_FB_CFB_FILLRECT=y 902CONFIG_FB_CFB_FILLRECT=y
880CONFIG_FB_CFB_COPYAREA=y 903CONFIG_FB_CFB_COPYAREA=y
881CONFIG_FB_CFB_IMAGEBLIT=y 904CONFIG_FB_CFB_IMAGEBLIT=y
882CONFIG_FB_MACMODES=y 905CONFIG_FB_MACMODES=y
883CONFIG_FB_FIRMWARE_EDID=y 906# CONFIG_FB_BACKLIGHT is not set
884CONFIG_FB_MODE_HELPERS=y 907CONFIG_FB_MODE_HELPERS=y
885CONFIG_FB_TILEBLITTING=y 908CONFIG_FB_TILEBLITTING=y
886# CONFIG_FB_CIRRUS is not set 909# CONFIG_FB_CIRRUS is not set
887# CONFIG_FB_PM2 is not set 910# CONFIG_FB_PM2 is not set
888# CONFIG_FB_CYBER2000 is not set 911# CONFIG_FB_CYBER2000 is not set
889CONFIG_FB_OF=y 912CONFIG_FB_OF=y
890# CONFIG_FB_CONTROL is not set
891# CONFIG_FB_PLATINUM is not set
892# CONFIG_FB_VALKYRIE is not set
893# CONFIG_FB_CT65550 is not set
894# CONFIG_FB_ASILIANT is not set 913# CONFIG_FB_ASILIANT is not set
895# CONFIG_FB_IMSTT is not set 914# CONFIG_FB_IMSTT is not set
896# CONFIG_FB_VGA16 is not set 915# CONFIG_FB_VGA16 is not set
@@ -990,6 +1009,18 @@ CONFIG_SND_VERBOSE_PROCFS=y
990# CONFIG_SND_CMIPCI is not set 1009# CONFIG_SND_CMIPCI is not set
991# CONFIG_SND_CS4281 is not set 1010# CONFIG_SND_CS4281 is not set
992# CONFIG_SND_CS46XX is not set 1011# CONFIG_SND_CS46XX is not set
1012# CONFIG_SND_DARLA20 is not set
1013# CONFIG_SND_GINA20 is not set
1014# CONFIG_SND_LAYLA20 is not set
1015# CONFIG_SND_DARLA24 is not set
1016# CONFIG_SND_GINA24 is not set
1017# CONFIG_SND_LAYLA24 is not set
1018# CONFIG_SND_MONA is not set
1019# CONFIG_SND_MIA is not set
1020# CONFIG_SND_ECHO3G is not set
1021# CONFIG_SND_INDIGO is not set
1022# CONFIG_SND_INDIGOIO is not set
1023# CONFIG_SND_INDIGODJ is not set
993# CONFIG_SND_EMU10K1 is not set 1024# CONFIG_SND_EMU10K1 is not set
994# CONFIG_SND_EMU10K1X is not set 1025# CONFIG_SND_EMU10K1X is not set
995# CONFIG_SND_ENS1370 is not set 1026# CONFIG_SND_ENS1370 is not set
@@ -1027,6 +1058,17 @@ CONFIG_SND_POWERMAC=m
1027CONFIG_SND_POWERMAC_AUTO_DRC=y 1058CONFIG_SND_POWERMAC_AUTO_DRC=y
1028 1059
1029# 1060#
1061# Apple Onboard Audio driver
1062#
1063CONFIG_SND_AOA=m
1064CONFIG_SND_AOA_FABRIC_LAYOUT=m
1065CONFIG_SND_AOA_ONYX=m
1066CONFIG_SND_AOA_TAS=m
1067CONFIG_SND_AOA_TOONIE=m
1068CONFIG_SND_AOA_SOUNDBUS=m
1069CONFIG_SND_AOA_SOUNDBUS_I2S=m
1070
1071#
1030# USB devices 1072# USB devices
1031# 1073#
1032CONFIG_SND_USB_AUDIO=m 1074CONFIG_SND_USB_AUDIO=m
@@ -1060,6 +1102,7 @@ CONFIG_USB_DEVICEFS=y
1060CONFIG_USB_EHCI_HCD=y 1102CONFIG_USB_EHCI_HCD=y
1061# CONFIG_USB_EHCI_SPLIT_ISO is not set 1103# CONFIG_USB_EHCI_SPLIT_ISO is not set
1062# CONFIG_USB_EHCI_ROOT_HUB_TT is not set 1104# CONFIG_USB_EHCI_ROOT_HUB_TT is not set
1105# CONFIG_USB_EHCI_TT_NEWSCHED is not set
1063# CONFIG_USB_ISP116X_HCD is not set 1106# CONFIG_USB_ISP116X_HCD is not set
1064CONFIG_USB_OHCI_HCD=y 1107CONFIG_USB_OHCI_HCD=y
1065# CONFIG_USB_OHCI_BIG_ENDIAN is not set 1108# CONFIG_USB_OHCI_BIG_ENDIAN is not set
@@ -1110,9 +1153,7 @@ CONFIG_USB_HIDDEV=y
1110# CONFIG_USB_ACECAD is not set 1153# CONFIG_USB_ACECAD is not set
1111# CONFIG_USB_KBTAB is not set 1154# CONFIG_USB_KBTAB is not set
1112# CONFIG_USB_POWERMATE is not set 1155# CONFIG_USB_POWERMATE is not set
1113# CONFIG_USB_MTOUCH is not set 1156# CONFIG_USB_TOUCHSCREEN is not set
1114# CONFIG_USB_ITMTOUCH is not set
1115# CONFIG_USB_EGALAX is not set
1116# CONFIG_USB_YEALINK is not set 1157# CONFIG_USB_YEALINK is not set
1117# CONFIG_USB_XPAD is not set 1158# CONFIG_USB_XPAD is not set
1118# CONFIG_USB_ATI_REMOTE is not set 1159# CONFIG_USB_ATI_REMOTE is not set
@@ -1155,6 +1196,7 @@ CONFIG_USB_SERIAL=m
1155CONFIG_USB_SERIAL_GENERIC=y 1196CONFIG_USB_SERIAL_GENERIC=y
1156# CONFIG_USB_SERIAL_AIRPRIME is not set 1197# CONFIG_USB_SERIAL_AIRPRIME is not set
1157# CONFIG_USB_SERIAL_ANYDATA is not set 1198# CONFIG_USB_SERIAL_ANYDATA is not set
1199# CONFIG_USB_SERIAL_ARK3116 is not set
1158CONFIG_USB_SERIAL_BELKIN=m 1200CONFIG_USB_SERIAL_BELKIN=m
1159# CONFIG_USB_SERIAL_WHITEHEAT is not set 1201# CONFIG_USB_SERIAL_WHITEHEAT is not set
1160CONFIG_USB_SERIAL_DIGI_ACCELEPORT=m 1202CONFIG_USB_SERIAL_DIGI_ACCELEPORT=m
@@ -1162,6 +1204,7 @@ CONFIG_USB_SERIAL_DIGI_ACCELEPORT=m
1162CONFIG_USB_SERIAL_CYPRESS_M8=m 1204CONFIG_USB_SERIAL_CYPRESS_M8=m
1163CONFIG_USB_SERIAL_EMPEG=m 1205CONFIG_USB_SERIAL_EMPEG=m
1164CONFIG_USB_SERIAL_FTDI_SIO=m 1206CONFIG_USB_SERIAL_FTDI_SIO=m
1207# CONFIG_USB_SERIAL_FUNSOFT is not set
1165CONFIG_USB_SERIAL_VISOR=m 1208CONFIG_USB_SERIAL_VISOR=m
1166CONFIG_USB_SERIAL_IPAQ=m 1209CONFIG_USB_SERIAL_IPAQ=m
1167CONFIG_USB_SERIAL_IR=m 1210CONFIG_USB_SERIAL_IR=m
@@ -1191,9 +1234,11 @@ CONFIG_USB_SERIAL_PL2303=m
1191# CONFIG_USB_SERIAL_HP4X is not set 1234# CONFIG_USB_SERIAL_HP4X is not set
1192CONFIG_USB_SERIAL_SAFE=m 1235CONFIG_USB_SERIAL_SAFE=m
1193CONFIG_USB_SERIAL_SAFE_PADDED=y 1236CONFIG_USB_SERIAL_SAFE_PADDED=y
1237# CONFIG_USB_SERIAL_SIERRAWIRELESS is not set
1194CONFIG_USB_SERIAL_TI=m 1238CONFIG_USB_SERIAL_TI=m
1195CONFIG_USB_SERIAL_CYBERJACK=m 1239CONFIG_USB_SERIAL_CYBERJACK=m
1196CONFIG_USB_SERIAL_XIRCOM=m 1240CONFIG_USB_SERIAL_XIRCOM=m
1241# CONFIG_USB_SERIAL_OPTION is not set
1197CONFIG_USB_SERIAL_OMNINET=m 1242CONFIG_USB_SERIAL_OMNINET=m
1198CONFIG_USB_EZUSB=y 1243CONFIG_USB_EZUSB=y
1199 1244
@@ -1207,10 +1252,12 @@ CONFIG_USB_EZUSB=y
1207# CONFIG_USB_LEGOTOWER is not set 1252# CONFIG_USB_LEGOTOWER is not set
1208# CONFIG_USB_LCD is not set 1253# CONFIG_USB_LCD is not set
1209# CONFIG_USB_LED is not set 1254# CONFIG_USB_LED is not set
1255# CONFIG_USB_CYPRESS_CY7C63 is not set
1210# CONFIG_USB_CYTHERM is not set 1256# CONFIG_USB_CYTHERM is not set
1211# CONFIG_USB_PHIDGETKIT is not set 1257# CONFIG_USB_PHIDGETKIT is not set
1212# CONFIG_USB_PHIDGETSERVO is not set 1258# CONFIG_USB_PHIDGETSERVO is not set
1213# CONFIG_USB_IDMOUSE is not set 1259# CONFIG_USB_IDMOUSE is not set
1260CONFIG_USB_APPLEDISPLAY=m
1214# CONFIG_USB_SISUSBVGA is not set 1261# CONFIG_USB_SISUSBVGA is not set
1215# CONFIG_USB_LD is not set 1262# CONFIG_USB_LD is not set
1216# CONFIG_USB_TEST is not set 1263# CONFIG_USB_TEST is not set
@@ -1235,6 +1282,14 @@ CONFIG_USB_EZUSB=y
1235# CONFIG_NEW_LEDS is not set 1282# CONFIG_NEW_LEDS is not set
1236 1283
1237# 1284#
1285# LED drivers
1286#
1287
1288#
1289# LED Triggers
1290#
1291
1292#
1238# InfiniBand support 1293# InfiniBand support
1239# 1294#
1240# CONFIG_INFINIBAND is not set 1295# CONFIG_INFINIBAND is not set
@@ -1249,6 +1304,19 @@ CONFIG_USB_EZUSB=y
1249# CONFIG_RTC_CLASS is not set 1304# CONFIG_RTC_CLASS is not set
1250 1305
1251# 1306#
1307# DMA Engine support
1308#
1309# CONFIG_DMA_ENGINE is not set
1310
1311#
1312# DMA Clients
1313#
1314
1315#
1316# DMA Devices
1317#
1318
1319#
1252# File systems 1320# File systems
1253# 1321#
1254CONFIG_EXT2_FS=y 1322CONFIG_EXT2_FS=y
@@ -1273,7 +1341,6 @@ CONFIG_REISERFS_FS_SECURITY=y
1273# CONFIG_JFS_FS is not set 1341# CONFIG_JFS_FS is not set
1274CONFIG_FS_POSIX_ACL=y 1342CONFIG_FS_POSIX_ACL=y
1275CONFIG_XFS_FS=m 1343CONFIG_XFS_FS=m
1276CONFIG_XFS_EXPORT=y
1277# CONFIG_XFS_QUOTA is not set 1344# CONFIG_XFS_QUOTA is not set
1278CONFIG_XFS_SECURITY=y 1345CONFIG_XFS_SECURITY=y
1279CONFIG_XFS_POSIX_ACL=y 1346CONFIG_XFS_POSIX_ACL=y
@@ -1282,6 +1349,7 @@ CONFIG_XFS_POSIX_ACL=y
1282# CONFIG_MINIX_FS is not set 1349# CONFIG_MINIX_FS is not set
1283# CONFIG_ROMFS_FS is not set 1350# CONFIG_ROMFS_FS is not set
1284CONFIG_INOTIFY=y 1351CONFIG_INOTIFY=y
1352CONFIG_INOTIFY_USER=y
1285# CONFIG_QUOTA is not set 1353# CONFIG_QUOTA is not set
1286CONFIG_DNOTIFY=y 1354CONFIG_DNOTIFY=y
1287CONFIG_AUTOFS_FS=m 1355CONFIG_AUTOFS_FS=m
@@ -1363,7 +1431,9 @@ CONFIG_RPCSEC_GSS_KRB5=y
1363# CONFIG_SMB_FS is not set 1431# CONFIG_SMB_FS is not set
1364CONFIG_CIFS=m 1432CONFIG_CIFS=m
1365# CONFIG_CIFS_STATS is not set 1433# CONFIG_CIFS_STATS is not set
1434# CONFIG_CIFS_WEAK_PW_HASH is not set
1366# CONFIG_CIFS_XATTR is not set 1435# CONFIG_CIFS_XATTR is not set
1436# CONFIG_CIFS_DEBUG2 is not set
1367# CONFIG_CIFS_EXPERIMENTAL is not set 1437# CONFIG_CIFS_EXPERIMENTAL is not set
1368# CONFIG_NCP_FS is not set 1438# CONFIG_NCP_FS is not set
1369# CONFIG_CODA_FS is not set 1439# CONFIG_CODA_FS is not set
@@ -1444,6 +1514,9 @@ CONFIG_CRC32=y
1444CONFIG_LIBCRC32C=m 1514CONFIG_LIBCRC32C=m
1445CONFIG_ZLIB_INFLATE=y 1515CONFIG_ZLIB_INFLATE=y
1446CONFIG_ZLIB_DEFLATE=m 1516CONFIG_ZLIB_DEFLATE=m
1517CONFIG_TEXTSEARCH=y
1518CONFIG_TEXTSEARCH_KMP=m
1519CONFIG_PLIST=y
1447 1520
1448# 1521#
1449# Instrumentation Support 1522# Instrumentation Support
@@ -1457,14 +1530,19 @@ CONFIG_OPROFILE=y
1457# 1530#
1458# CONFIG_PRINTK_TIME is not set 1531# CONFIG_PRINTK_TIME is not set
1459CONFIG_MAGIC_SYSRQ=y 1532CONFIG_MAGIC_SYSRQ=y
1533# CONFIG_UNUSED_SYMBOLS is not set
1460CONFIG_DEBUG_KERNEL=y 1534CONFIG_DEBUG_KERNEL=y
1461CONFIG_LOG_BUF_SHIFT=17 1535CONFIG_LOG_BUF_SHIFT=17
1462CONFIG_DETECT_SOFTLOCKUP=y 1536CONFIG_DETECT_SOFTLOCKUP=y
1463# CONFIG_SCHEDSTATS is not set 1537# CONFIG_SCHEDSTATS is not set
1464# CONFIG_DEBUG_SLAB is not set 1538# CONFIG_DEBUG_SLAB is not set
1465CONFIG_DEBUG_MUTEXES=y 1539# CONFIG_DEBUG_RT_MUTEXES is not set
1540# CONFIG_RT_MUTEX_TESTER is not set
1466# CONFIG_DEBUG_SPINLOCK is not set 1541# CONFIG_DEBUG_SPINLOCK is not set
1542CONFIG_DEBUG_MUTEXES=y
1543# CONFIG_DEBUG_RWSEMS is not set
1467# CONFIG_DEBUG_SPINLOCK_SLEEP is not set 1544# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
1545# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
1468# CONFIG_DEBUG_KOBJECT is not set 1546# CONFIG_DEBUG_KOBJECT is not set
1469# CONFIG_DEBUG_INFO is not set 1547# CONFIG_DEBUG_INFO is not set
1470CONFIG_DEBUG_FS=y 1548CONFIG_DEBUG_FS=y
@@ -1476,11 +1554,7 @@ CONFIG_FORCED_INLINING=y
1476# CONFIG_DEBUGGER is not set 1554# CONFIG_DEBUGGER is not set
1477CONFIG_IRQSTACKS=y 1555CONFIG_IRQSTACKS=y
1478CONFIG_BOOTX_TEXT=y 1556CONFIG_BOOTX_TEXT=y
1479# CONFIG_PPC_EARLY_DEBUG_LPAR is not set 1557# CONFIG_PPC_EARLY_DEBUG is not set
1480# CONFIG_PPC_EARLY_DEBUG_G5 is not set
1481# CONFIG_PPC_EARLY_DEBUG_RTAS is not set
1482# CONFIG_PPC_EARLY_DEBUG_MAPLE is not set
1483# CONFIG_PPC_EARLY_DEBUG_ISERIES is not set
1484 1558
1485# 1559#
1486# Security options 1560# Security options
diff --git a/arch/powerpc/configs/iseries_defconfig b/arch/powerpc/configs/iseries_defconfig
index a95e455a1944..72ed95b3ead6 100644
--- a/arch/powerpc/configs/iseries_defconfig
+++ b/arch/powerpc/configs/iseries_defconfig
@@ -1,16 +1,18 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.17-rc1 3# Linux kernel version: 2.6.18-rc3
4# Wed Apr 19 11:46:44 2006 4# Tue Aug 8 09:15:46 2006
5# 5#
6CONFIG_PPC64=y 6CONFIG_PPC64=y
7CONFIG_64BIT=y 7CONFIG_64BIT=y
8CONFIG_PPC_MERGE=y 8CONFIG_PPC_MERGE=y
9CONFIG_MMU=y 9CONFIG_MMU=y
10CONFIG_GENERIC_HARDIRQS=y 10CONFIG_GENERIC_HARDIRQS=y
11CONFIG_IRQ_PER_CPU=y
11CONFIG_RWSEM_XCHGADD_ALGORITHM=y 12CONFIG_RWSEM_XCHGADD_ALGORITHM=y
12CONFIG_GENERIC_HWEIGHT=y 13CONFIG_GENERIC_HWEIGHT=y
13CONFIG_GENERIC_CALIBRATE_DELAY=y 14CONFIG_GENERIC_CALIBRATE_DELAY=y
15CONFIG_GENERIC_FIND_NEXT_BIT=y
14CONFIG_PPC=y 16CONFIG_PPC=y
15CONFIG_EARLY_PRINTK=y 17CONFIG_EARLY_PRINTK=y
16CONFIG_COMPAT=y 18CONFIG_COMPAT=y
@@ -34,6 +36,7 @@ CONFIG_PPC_STD_MMU=y
34CONFIG_VIRT_CPU_ACCOUNTING=y 36CONFIG_VIRT_CPU_ACCOUNTING=y
35CONFIG_SMP=y 37CONFIG_SMP=y
36CONFIG_NR_CPUS=32 38CONFIG_NR_CPUS=32
39CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
37 40
38# 41#
39# Code maturity level options 42# Code maturity level options
@@ -51,6 +54,7 @@ CONFIG_SWAP=y
51CONFIG_SYSVIPC=y 54CONFIG_SYSVIPC=y
52CONFIG_POSIX_MQUEUE=y 55CONFIG_POSIX_MQUEUE=y
53# CONFIG_BSD_PROCESS_ACCT is not set 56# CONFIG_BSD_PROCESS_ACCT is not set
57# CONFIG_TASKSTATS is not set
54CONFIG_SYSCTL=y 58CONFIG_SYSCTL=y
55CONFIG_AUDIT=y 59CONFIG_AUDIT=y
56CONFIG_AUDITSYSCALL=y 60CONFIG_AUDITSYSCALL=y
@@ -69,10 +73,12 @@ CONFIG_PRINTK=y
69CONFIG_BUG=y 73CONFIG_BUG=y
70CONFIG_ELF_CORE=y 74CONFIG_ELF_CORE=y
71CONFIG_BASE_FULL=y 75CONFIG_BASE_FULL=y
76CONFIG_RT_MUTEXES=y
72CONFIG_FUTEX=y 77CONFIG_FUTEX=y
73CONFIG_EPOLL=y 78CONFIG_EPOLL=y
74CONFIG_SHMEM=y 79CONFIG_SHMEM=y
75CONFIG_SLAB=y 80CONFIG_SLAB=y
81CONFIG_VM_EVENT_COUNTERS=y
76# CONFIG_TINY_SHMEM is not set 82# CONFIG_TINY_SHMEM is not set
77CONFIG_BASE_SMALL=0 83CONFIG_BASE_SMALL=0
78# CONFIG_SLOB is not set 84# CONFIG_SLOB is not set
@@ -113,10 +119,14 @@ CONFIG_DEFAULT_IOSCHED="anticipatory"
113CONFIG_PPC_ISERIES=y 119CONFIG_PPC_ISERIES=y
114# CONFIG_EMBEDDED6xx is not set 120# CONFIG_EMBEDDED6xx is not set
115# CONFIG_APUS is not set 121# CONFIG_APUS is not set
122# CONFIG_PPC_CELL is not set
123# CONFIG_PPC_CELL_NATIVE is not set
124# CONFIG_UDBG_RTAS_CONSOLE is not set
116# CONFIG_PPC_RTAS is not set 125# CONFIG_PPC_RTAS is not set
117# CONFIG_MMIO_NVRAM is not set 126# CONFIG_MMIO_NVRAM is not set
118CONFIG_IBMVIO=y 127CONFIG_IBMVIO=y
119# CONFIG_PPC_MPC106 is not set 128# CONFIG_PPC_MPC106 is not set
129# CONFIG_PPC_970_NAP is not set
120# CONFIG_CPU_FREQ is not set 130# CONFIG_CPU_FREQ is not set
121# CONFIG_WANT_EARLY_SERIAL is not set 131# CONFIG_WANT_EARLY_SERIAL is not set
122 132
@@ -135,6 +145,7 @@ CONFIG_BINFMT_ELF=y
135# CONFIG_BINFMT_MISC is not set 145# CONFIG_BINFMT_MISC is not set
136CONFIG_FORCE_MAX_ZONEORDER=13 146CONFIG_FORCE_MAX_ZONEORDER=13
137CONFIG_IOMMU_VMERGE=y 147CONFIG_IOMMU_VMERGE=y
148CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y
138CONFIG_IRQ_ALL_CPUS=y 149CONFIG_IRQ_ALL_CPUS=y
139CONFIG_LPARCFG=y 150CONFIG_LPARCFG=y
140# CONFIG_NUMA is not set 151# CONFIG_NUMA is not set
@@ -149,6 +160,7 @@ CONFIG_FLATMEM=y
149CONFIG_FLAT_NODE_MEM_MAP=y 160CONFIG_FLAT_NODE_MEM_MAP=y
150# CONFIG_SPARSEMEM_STATIC is not set 161# CONFIG_SPARSEMEM_STATIC is not set
151CONFIG_SPLIT_PTLOCK_CPUS=4 162CONFIG_SPLIT_PTLOCK_CPUS=4
163CONFIG_RESOURCES_64BIT=y
152# CONFIG_PPC_64K_PAGES is not set 164# CONFIG_PPC_64K_PAGES is not set
153# CONFIG_SCHED_SMT is not set 165# CONFIG_SCHED_SMT is not set
154CONFIG_PROC_DEVICETREE=y 166CONFIG_PROC_DEVICETREE=y
@@ -164,6 +176,7 @@ CONFIG_GENERIC_ISA_DMA=y
164# CONFIG_PPC_INDIRECT_PCI is not set 176# CONFIG_PPC_INDIRECT_PCI is not set
165CONFIG_PCI=y 177CONFIG_PCI=y
166CONFIG_PCI_DOMAINS=y 178CONFIG_PCI_DOMAINS=y
179# CONFIG_PCIEPORTBUS is not set
167# CONFIG_PCI_DEBUG is not set 180# CONFIG_PCI_DEBUG is not set
168 181
169# 182#
@@ -207,6 +220,8 @@ CONFIG_INET_ESP=m
207CONFIG_INET_IPCOMP=m 220CONFIG_INET_IPCOMP=m
208CONFIG_INET_XFRM_TUNNEL=m 221CONFIG_INET_XFRM_TUNNEL=m
209CONFIG_INET_TUNNEL=y 222CONFIG_INET_TUNNEL=y
223CONFIG_INET_XFRM_MODE_TRANSPORT=y
224CONFIG_INET_XFRM_MODE_TUNNEL=y
210CONFIG_INET_DIAG=y 225CONFIG_INET_DIAG=y
211CONFIG_INET_TCP_DIAG=y 226CONFIG_INET_TCP_DIAG=y
212# CONFIG_TCP_CONG_ADVANCED is not set 227# CONFIG_TCP_CONG_ADVANCED is not set
@@ -219,6 +234,7 @@ CONFIG_TCP_CONG_BIC=y
219# CONFIG_IPV6 is not set 234# CONFIG_IPV6 is not set
220# CONFIG_INET6_XFRM_TUNNEL is not set 235# CONFIG_INET6_XFRM_TUNNEL is not set
221# CONFIG_INET6_TUNNEL is not set 236# CONFIG_INET6_TUNNEL is not set
237# CONFIG_NETWORK_SECMARK is not set
222CONFIG_NETFILTER=y 238CONFIG_NETFILTER=y
223# CONFIG_NETFILTER_DEBUG is not set 239# CONFIG_NETFILTER_DEBUG is not set
224 240
@@ -246,9 +262,11 @@ CONFIG_NETFILTER_XT_MATCH_MARK=m
246# CONFIG_NETFILTER_XT_MATCH_POLICY is not set 262# CONFIG_NETFILTER_XT_MATCH_POLICY is not set
247# CONFIG_NETFILTER_XT_MATCH_MULTIPORT is not set 263# CONFIG_NETFILTER_XT_MATCH_MULTIPORT is not set
248CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m 264CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m
265# CONFIG_NETFILTER_XT_MATCH_QUOTA is not set
249CONFIG_NETFILTER_XT_MATCH_REALM=m 266CONFIG_NETFILTER_XT_MATCH_REALM=m
250CONFIG_NETFILTER_XT_MATCH_SCTP=m 267CONFIG_NETFILTER_XT_MATCH_SCTP=m
251CONFIG_NETFILTER_XT_MATCH_STATE=m 268CONFIG_NETFILTER_XT_MATCH_STATE=m
269# CONFIG_NETFILTER_XT_MATCH_STATISTIC is not set
252CONFIG_NETFILTER_XT_MATCH_STRING=m 270CONFIG_NETFILTER_XT_MATCH_STRING=m
253CONFIG_NETFILTER_XT_MATCH_TCPMSS=m 271CONFIG_NETFILTER_XT_MATCH_TCPMSS=m
254 272
@@ -267,6 +285,7 @@ CONFIG_IP_NF_TFTP=m
267CONFIG_IP_NF_AMANDA=m 285CONFIG_IP_NF_AMANDA=m
268# CONFIG_IP_NF_PPTP is not set 286# CONFIG_IP_NF_PPTP is not set
269# CONFIG_IP_NF_H323 is not set 287# CONFIG_IP_NF_H323 is not set
288# CONFIG_IP_NF_SIP is not set
270CONFIG_IP_NF_QUEUE=m 289CONFIG_IP_NF_QUEUE=m
271CONFIG_IP_NF_IPTABLES=m 290CONFIG_IP_NF_IPTABLES=m
272CONFIG_IP_NF_MATCH_IPRANGE=m 291CONFIG_IP_NF_MATCH_IPRANGE=m
@@ -360,6 +379,7 @@ CONFIG_STANDALONE=y
360CONFIG_PREVENT_FIRMWARE_BUILD=y 379CONFIG_PREVENT_FIRMWARE_BUILD=y
361CONFIG_FW_LOADER=m 380CONFIG_FW_LOADER=m
362# CONFIG_DEBUG_DRIVER is not set 381# CONFIG_DEBUG_DRIVER is not set
382# CONFIG_SYS_HYPERVISOR is not set
363 383
364# 384#
365# Connector - unified userspace <-> kernelspace linker 385# Connector - unified userspace <-> kernelspace linker
@@ -396,6 +416,7 @@ CONFIG_BLK_DEV_NBD=m
396CONFIG_BLK_DEV_RAM=y 416CONFIG_BLK_DEV_RAM=y
397CONFIG_BLK_DEV_RAM_COUNT=16 417CONFIG_BLK_DEV_RAM_COUNT=16
398CONFIG_BLK_DEV_RAM_SIZE=65536 418CONFIG_BLK_DEV_RAM_SIZE=65536
419CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
399CONFIG_BLK_DEV_INITRD=y 420CONFIG_BLK_DEV_INITRD=y
400# CONFIG_CDROM_PKTCDVD is not set 421# CONFIG_CDROM_PKTCDVD is not set
401# CONFIG_ATA_OVER_ETH is not set 422# CONFIG_ATA_OVER_ETH is not set
@@ -453,6 +474,7 @@ CONFIG_SCSI_FC_ATTRS=y
453# CONFIG_MEGARAID_LEGACY is not set 474# CONFIG_MEGARAID_LEGACY is not set
454# CONFIG_MEGARAID_SAS is not set 475# CONFIG_MEGARAID_SAS is not set
455# CONFIG_SCSI_SATA is not set 476# CONFIG_SCSI_SATA is not set
477# CONFIG_SCSI_HPTIOP is not set
456# CONFIG_SCSI_BUSLOGIC is not set 478# CONFIG_SCSI_BUSLOGIC is not set
457# CONFIG_SCSI_DMX3191D is not set 479# CONFIG_SCSI_DMX3191D is not set
458# CONFIG_SCSI_EATA is not set 480# CONFIG_SCSI_EATA is not set
@@ -464,7 +486,6 @@ CONFIG_SCSI_IBMVSCSI=m
464# CONFIG_SCSI_INIA100 is not set 486# CONFIG_SCSI_INIA100 is not set
465# CONFIG_SCSI_SYM53C8XX_2 is not set 487# CONFIG_SCSI_SYM53C8XX_2 is not set
466# CONFIG_SCSI_IPR is not set 488# CONFIG_SCSI_IPR is not set
467# CONFIG_SCSI_QLOGIC_FC is not set
468# CONFIG_SCSI_QLOGIC_1280 is not set 489# CONFIG_SCSI_QLOGIC_1280 is not set
469# CONFIG_SCSI_QLA_FC is not set 490# CONFIG_SCSI_QLA_FC is not set
470# CONFIG_SCSI_LPFC is not set 491# CONFIG_SCSI_LPFC is not set
@@ -481,9 +502,7 @@ CONFIG_MD_LINEAR=y
481CONFIG_MD_RAID0=y 502CONFIG_MD_RAID0=y
482CONFIG_MD_RAID1=y 503CONFIG_MD_RAID1=y
483CONFIG_MD_RAID10=m 504CONFIG_MD_RAID10=m
484CONFIG_MD_RAID5=y 505# CONFIG_MD_RAID456 is not set
485# CONFIG_MD_RAID5_RESHAPE is not set
486CONFIG_MD_RAID6=m
487CONFIG_MD_MULTIPATH=m 506CONFIG_MD_MULTIPATH=m
488CONFIG_MD_FAULTY=m 507CONFIG_MD_FAULTY=m
489CONFIG_BLK_DEV_DM=y 508CONFIG_BLK_DEV_DM=y
@@ -596,6 +615,7 @@ CONFIG_E1000=m
596# CONFIG_CHELSIO_T1 is not set 615# CONFIG_CHELSIO_T1 is not set
597# CONFIG_IXGB is not set 616# CONFIG_IXGB is not set
598# CONFIG_S2IO is not set 617# CONFIG_S2IO is not set
618# CONFIG_MYRI10GE is not set
599 619
600# 620#
601# Token Ring devices 621# Token Ring devices
@@ -696,6 +716,7 @@ CONFIG_SERIAL_ICOM=m
696CONFIG_UNIX98_PTYS=y 716CONFIG_UNIX98_PTYS=y
697CONFIG_LEGACY_PTYS=y 717CONFIG_LEGACY_PTYS=y
698CONFIG_LEGACY_PTY_COUNT=256 718CONFIG_LEGACY_PTY_COUNT=256
719# CONFIG_BRIQ_PANEL is not set
699 720
700# 721#
701# IPMI 722# IPMI
@@ -706,6 +727,7 @@ CONFIG_LEGACY_PTY_COUNT=256
706# Watchdog Cards 727# Watchdog Cards
707# 728#
708# CONFIG_WATCHDOG is not set 729# CONFIG_WATCHDOG is not set
730# CONFIG_HW_RANDOM is not set
709CONFIG_GEN_RTC=y 731CONFIG_GEN_RTC=y
710# CONFIG_GEN_RTC_X is not set 732# CONFIG_GEN_RTC_X is not set
711# CONFIG_DTLK is not set 733# CONFIG_DTLK is not set
@@ -741,7 +763,6 @@ CONFIG_MAX_RAW_DEVS=256
741# 763#
742# Dallas's 1-wire bus 764# Dallas's 1-wire bus
743# 765#
744# CONFIG_W1 is not set
745 766
746# 767#
747# Hardware Monitoring support 768# Hardware Monitoring support
@@ -757,6 +778,7 @@ CONFIG_MAX_RAW_DEVS=256
757# Multimedia devices 778# Multimedia devices
758# 779#
759# CONFIG_VIDEO_DEV is not set 780# CONFIG_VIDEO_DEV is not set
781CONFIG_VIDEO_V4L2=y
760 782
761# 783#
762# Digital Video Broadcasting Devices 784# Digital Video Broadcasting Devices
@@ -766,7 +788,9 @@ CONFIG_MAX_RAW_DEVS=256
766# 788#
767# Graphics support 789# Graphics support
768# 790#
791CONFIG_FIRMWARE_EDID=y
769# CONFIG_FB is not set 792# CONFIG_FB is not set
793# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
770 794
771# 795#
772# Sound 796# Sound
@@ -801,6 +825,14 @@ CONFIG_USB_ARCH_HAS_EHCI=y
801# CONFIG_NEW_LEDS is not set 825# CONFIG_NEW_LEDS is not set
802 826
803# 827#
828# LED drivers
829#
830
831#
832# LED Triggers
833#
834
835#
804# InfiniBand support 836# InfiniBand support
805# 837#
806# CONFIG_INFINIBAND is not set 838# CONFIG_INFINIBAND is not set
@@ -815,6 +847,19 @@ CONFIG_USB_ARCH_HAS_EHCI=y
815# CONFIG_RTC_CLASS is not set 847# CONFIG_RTC_CLASS is not set
816 848
817# 849#
850# DMA Engine support
851#
852# CONFIG_DMA_ENGINE is not set
853
854#
855# DMA Clients
856#
857
858#
859# DMA Devices
860#
861
862#
818# File systems 863# File systems
819# 864#
820CONFIG_EXT2_FS=y 865CONFIG_EXT2_FS=y
@@ -843,7 +888,6 @@ CONFIG_JFS_SECURITY=y
843# CONFIG_JFS_STATISTICS is not set 888# CONFIG_JFS_STATISTICS is not set
844CONFIG_FS_POSIX_ACL=y 889CONFIG_FS_POSIX_ACL=y
845CONFIG_XFS_FS=m 890CONFIG_XFS_FS=m
846CONFIG_XFS_EXPORT=y
847# CONFIG_XFS_QUOTA is not set 891# CONFIG_XFS_QUOTA is not set
848CONFIG_XFS_SECURITY=y 892CONFIG_XFS_SECURITY=y
849CONFIG_XFS_POSIX_ACL=y 893CONFIG_XFS_POSIX_ACL=y
@@ -852,6 +896,7 @@ CONFIG_XFS_POSIX_ACL=y
852# CONFIG_MINIX_FS is not set 896# CONFIG_MINIX_FS is not set
853# CONFIG_ROMFS_FS is not set 897# CONFIG_ROMFS_FS is not set
854CONFIG_INOTIFY=y 898CONFIG_INOTIFY=y
899CONFIG_INOTIFY_USER=y
855# CONFIG_QUOTA is not set 900# CONFIG_QUOTA is not set
856CONFIG_DNOTIFY=y 901CONFIG_DNOTIFY=y
857CONFIG_AUTOFS_FS=m 902CONFIG_AUTOFS_FS=m
@@ -933,8 +978,10 @@ CONFIG_RPCSEC_GSS_SPKM3=m
933# CONFIG_SMB_FS is not set 978# CONFIG_SMB_FS is not set
934CONFIG_CIFS=m 979CONFIG_CIFS=m
935# CONFIG_CIFS_STATS is not set 980# CONFIG_CIFS_STATS is not set
981# CONFIG_CIFS_WEAK_PW_HASH is not set
936CONFIG_CIFS_XATTR=y 982CONFIG_CIFS_XATTR=y
937CONFIG_CIFS_POSIX=y 983CONFIG_CIFS_POSIX=y
984# CONFIG_CIFS_DEBUG2 is not set
938# CONFIG_CIFS_EXPERIMENTAL is not set 985# CONFIG_CIFS_EXPERIMENTAL is not set
939# CONFIG_NCP_FS is not set 986# CONFIG_NCP_FS is not set
940# CONFIG_CODA_FS is not set 987# CONFIG_CODA_FS is not set
@@ -1013,10 +1060,12 @@ CONFIG_TEXTSEARCH=y
1013CONFIG_TEXTSEARCH_KMP=m 1060CONFIG_TEXTSEARCH_KMP=m
1014CONFIG_TEXTSEARCH_BM=m 1061CONFIG_TEXTSEARCH_BM=m
1015CONFIG_TEXTSEARCH_FSM=m 1062CONFIG_TEXTSEARCH_FSM=m
1063CONFIG_PLIST=y
1016 1064
1017# 1065#
1018# Instrumentation Support 1066# Instrumentation Support
1019# 1067#
1068# CONFIG_PROFILING is not set
1020# CONFIG_KPROBES is not set 1069# CONFIG_KPROBES is not set
1021 1070
1022# 1071#
@@ -1024,14 +1073,19 @@ CONFIG_TEXTSEARCH_FSM=m
1024# 1073#
1025# CONFIG_PRINTK_TIME is not set 1074# CONFIG_PRINTK_TIME is not set
1026CONFIG_MAGIC_SYSRQ=y 1075CONFIG_MAGIC_SYSRQ=y
1076# CONFIG_UNUSED_SYMBOLS is not set
1027CONFIG_DEBUG_KERNEL=y 1077CONFIG_DEBUG_KERNEL=y
1028CONFIG_LOG_BUF_SHIFT=17 1078CONFIG_LOG_BUF_SHIFT=17
1029CONFIG_DETECT_SOFTLOCKUP=y 1079CONFIG_DETECT_SOFTLOCKUP=y
1030# CONFIG_SCHEDSTATS is not set 1080# CONFIG_SCHEDSTATS is not set
1031# CONFIG_DEBUG_SLAB is not set 1081# CONFIG_DEBUG_SLAB is not set
1032# CONFIG_DEBUG_MUTEXES is not set 1082# CONFIG_DEBUG_RT_MUTEXES is not set
1083# CONFIG_RT_MUTEX_TESTER is not set
1033# CONFIG_DEBUG_SPINLOCK is not set 1084# CONFIG_DEBUG_SPINLOCK is not set
1085# CONFIG_DEBUG_MUTEXES is not set
1086# CONFIG_DEBUG_RWSEMS is not set
1034# CONFIG_DEBUG_SPINLOCK_SLEEP is not set 1087# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
1088# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
1035# CONFIG_DEBUG_KOBJECT is not set 1089# CONFIG_DEBUG_KOBJECT is not set
1036# CONFIG_DEBUG_INFO is not set 1090# CONFIG_DEBUG_INFO is not set
1037CONFIG_DEBUG_FS=y 1091CONFIG_DEBUG_FS=y
@@ -1042,11 +1096,7 @@ CONFIG_DEBUG_STACKOVERFLOW=y
1042CONFIG_DEBUG_STACK_USAGE=y 1096CONFIG_DEBUG_STACK_USAGE=y
1043# CONFIG_DEBUGGER is not set 1097# CONFIG_DEBUGGER is not set
1044CONFIG_IRQSTACKS=y 1098CONFIG_IRQSTACKS=y
1045# CONFIG_PPC_EARLY_DEBUG_LPAR is not set 1099# CONFIG_PPC_EARLY_DEBUG is not set
1046# CONFIG_PPC_EARLY_DEBUG_G5 is not set
1047# CONFIG_PPC_EARLY_DEBUG_RTAS is not set
1048# CONFIG_PPC_EARLY_DEBUG_MAPLE is not set
1049# CONFIG_PPC_EARLY_DEBUG_ISERIES is not set
1050 1100
1051# 1101#
1052# Security options 1102# Security options
diff --git a/arch/powerpc/configs/mpc834x_sys_defconfig b/arch/powerpc/configs/mpc834x_mds_defconfig
index 5078b0441d61..5078b0441d61 100644
--- a/arch/powerpc/configs/mpc834x_sys_defconfig
+++ b/arch/powerpc/configs/mpc834x_mds_defconfig
diff --git a/arch/powerpc/configs/pseries_defconfig b/arch/powerpc/configs/pseries_defconfig
index 31708ad4574e..c18e8600d78f 100644
--- a/arch/powerpc/configs/pseries_defconfig
+++ b/arch/powerpc/configs/pseries_defconfig
@@ -1,13 +1,14 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.17-rc4 3# Linux kernel version: 2.6.18-rc3
4# Sun May 28 07:26:56 2006 4# Tue Aug 8 09:14:48 2006
5# 5#
6CONFIG_PPC64=y 6CONFIG_PPC64=y
7CONFIG_64BIT=y 7CONFIG_64BIT=y
8CONFIG_PPC_MERGE=y 8CONFIG_PPC_MERGE=y
9CONFIG_MMU=y 9CONFIG_MMU=y
10CONFIG_GENERIC_HARDIRQS=y 10CONFIG_GENERIC_HARDIRQS=y
11CONFIG_IRQ_PER_CPU=y
11CONFIG_RWSEM_XCHGADD_ALGORITHM=y 12CONFIG_RWSEM_XCHGADD_ALGORITHM=y
12CONFIG_GENERIC_HWEIGHT=y 13CONFIG_GENERIC_HWEIGHT=y
13CONFIG_GENERIC_CALIBRATE_DELAY=y 14CONFIG_GENERIC_CALIBRATE_DELAY=y
@@ -35,6 +36,7 @@ CONFIG_PPC_STD_MMU=y
35CONFIG_VIRT_CPU_ACCOUNTING=y 36CONFIG_VIRT_CPU_ACCOUNTING=y
36CONFIG_SMP=y 37CONFIG_SMP=y
37CONFIG_NR_CPUS=128 38CONFIG_NR_CPUS=128
39CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
38 40
39# 41#
40# Code maturity level options 42# Code maturity level options
@@ -52,6 +54,7 @@ CONFIG_SWAP=y
52CONFIG_SYSVIPC=y 54CONFIG_SYSVIPC=y
53CONFIG_POSIX_MQUEUE=y 55CONFIG_POSIX_MQUEUE=y
54# CONFIG_BSD_PROCESS_ACCT is not set 56# CONFIG_BSD_PROCESS_ACCT is not set
57# CONFIG_TASKSTATS is not set
55CONFIG_SYSCTL=y 58CONFIG_SYSCTL=y
56CONFIG_AUDIT=y 59CONFIG_AUDIT=y
57CONFIG_AUDITSYSCALL=y 60CONFIG_AUDITSYSCALL=y
@@ -70,10 +73,12 @@ CONFIG_PRINTK=y
70CONFIG_BUG=y 73CONFIG_BUG=y
71CONFIG_ELF_CORE=y 74CONFIG_ELF_CORE=y
72CONFIG_BASE_FULL=y 75CONFIG_BASE_FULL=y
76CONFIG_RT_MUTEXES=y
73CONFIG_FUTEX=y 77CONFIG_FUTEX=y
74CONFIG_EPOLL=y 78CONFIG_EPOLL=y
75CONFIG_SHMEM=y 79CONFIG_SHMEM=y
76CONFIG_SLAB=y 80CONFIG_SLAB=y
81CONFIG_VM_EVENT_COUNTERS=y
77# CONFIG_TINY_SHMEM is not set 82# CONFIG_TINY_SHMEM is not set
78CONFIG_BASE_SMALL=0 83CONFIG_BASE_SMALL=0
79# CONFIG_SLOB is not set 84# CONFIG_SLOB is not set
@@ -118,6 +123,9 @@ CONFIG_PPC_PSERIES=y
118# CONFIG_PPC_PMAC is not set 123# CONFIG_PPC_PMAC is not set
119# CONFIG_PPC_MAPLE is not set 124# CONFIG_PPC_MAPLE is not set
120# CONFIG_PPC_CELL is not set 125# CONFIG_PPC_CELL is not set
126# CONFIG_PPC_CELL_NATIVE is not set
127# CONFIG_PPC_IBM_CELL_BLADE is not set
128# CONFIG_UDBG_RTAS_CONSOLE is not set
121CONFIG_XICS=y 129CONFIG_XICS=y
122# CONFIG_U3_DART is not set 130# CONFIG_U3_DART is not set
123CONFIG_MPIC=y 131CONFIG_MPIC=y
@@ -149,6 +157,7 @@ CONFIG_BINFMT_MISC=m
149CONFIG_FORCE_MAX_ZONEORDER=13 157CONFIG_FORCE_MAX_ZONEORDER=13
150CONFIG_IOMMU_VMERGE=y 158CONFIG_IOMMU_VMERGE=y
151CONFIG_HOTPLUG_CPU=y 159CONFIG_HOTPLUG_CPU=y
160CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y
152CONFIG_KEXEC=y 161CONFIG_KEXEC=y
153# CONFIG_CRASH_DUMP is not set 162# CONFIG_CRASH_DUMP is not set
154CONFIG_IRQ_ALL_CPUS=y 163CONFIG_IRQ_ALL_CPUS=y
@@ -173,6 +182,7 @@ CONFIG_SPARSEMEM_EXTREME=y
173# CONFIG_MEMORY_HOTPLUG is not set 182# CONFIG_MEMORY_HOTPLUG is not set
174CONFIG_SPLIT_PTLOCK_CPUS=4 183CONFIG_SPLIT_PTLOCK_CPUS=4
175CONFIG_MIGRATION=y 184CONFIG_MIGRATION=y
185CONFIG_RESOURCES_64BIT=y
176CONFIG_HAVE_ARCH_EARLY_PFN_TO_NID=y 186CONFIG_HAVE_ARCH_EARLY_PFN_TO_NID=y
177# CONFIG_PPC_64K_PAGES is not set 187# CONFIG_PPC_64K_PAGES is not set
178CONFIG_SCHED_SMT=y 188CONFIG_SCHED_SMT=y
@@ -190,6 +200,7 @@ CONFIG_PPC_I8259=y
190# CONFIG_PPC_INDIRECT_PCI is not set 200# CONFIG_PPC_INDIRECT_PCI is not set
191CONFIG_PCI=y 201CONFIG_PCI=y
192CONFIG_PCI_DOMAINS=y 202CONFIG_PCI_DOMAINS=y
203# CONFIG_PCIEPORTBUS is not set
193# CONFIG_PCI_DEBUG is not set 204# CONFIG_PCI_DEBUG is not set
194 205
195# 206#
@@ -238,6 +249,8 @@ CONFIG_INET_ESP=m
238CONFIG_INET_IPCOMP=m 249CONFIG_INET_IPCOMP=m
239CONFIG_INET_XFRM_TUNNEL=m 250CONFIG_INET_XFRM_TUNNEL=m
240CONFIG_INET_TUNNEL=y 251CONFIG_INET_TUNNEL=y
252CONFIG_INET_XFRM_MODE_TRANSPORT=y
253CONFIG_INET_XFRM_MODE_TUNNEL=y
241CONFIG_INET_DIAG=y 254CONFIG_INET_DIAG=y
242CONFIG_INET_TCP_DIAG=y 255CONFIG_INET_TCP_DIAG=y
243# CONFIG_TCP_CONG_ADVANCED is not set 256# CONFIG_TCP_CONG_ADVANCED is not set
@@ -250,6 +263,7 @@ CONFIG_TCP_CONG_BIC=y
250# CONFIG_IPV6 is not set 263# CONFIG_IPV6 is not set
251# CONFIG_INET6_XFRM_TUNNEL is not set 264# CONFIG_INET6_XFRM_TUNNEL is not set
252# CONFIG_INET6_TUNNEL is not set 265# CONFIG_INET6_TUNNEL is not set
266# CONFIG_NETWORK_SECMARK is not set
253CONFIG_NETFILTER=y 267CONFIG_NETFILTER=y
254# CONFIG_NETFILTER_DEBUG is not set 268# CONFIG_NETFILTER_DEBUG is not set
255 269
@@ -277,6 +291,7 @@ CONFIG_IP_NF_TFTP=m
277CONFIG_IP_NF_AMANDA=m 291CONFIG_IP_NF_AMANDA=m
278# CONFIG_IP_NF_PPTP is not set 292# CONFIG_IP_NF_PPTP is not set
279# CONFIG_IP_NF_H323 is not set 293# CONFIG_IP_NF_H323 is not set
294# CONFIG_IP_NF_SIP is not set
280CONFIG_IP_NF_QUEUE=m 295CONFIG_IP_NF_QUEUE=m
281 296
282# 297#
@@ -316,6 +331,7 @@ CONFIG_LLC=y
316# Network testing 331# Network testing
317# 332#
318# CONFIG_NET_PKTGEN is not set 333# CONFIG_NET_PKTGEN is not set
334# CONFIG_NET_TCPPROBE is not set
319# CONFIG_HAMRADIO is not set 335# CONFIG_HAMRADIO is not set
320# CONFIG_IRDA is not set 336# CONFIG_IRDA is not set
321# CONFIG_BT is not set 337# CONFIG_BT is not set
@@ -332,6 +348,7 @@ CONFIG_STANDALONE=y
332CONFIG_PREVENT_FIRMWARE_BUILD=y 348CONFIG_PREVENT_FIRMWARE_BUILD=y
333CONFIG_FW_LOADER=y 349CONFIG_FW_LOADER=y
334# CONFIG_DEBUG_DRIVER is not set 350# CONFIG_DEBUG_DRIVER is not set
351# CONFIG_SYS_HYPERVISOR is not set
335 352
336# 353#
337# Connector - unified userspace <-> kernelspace linker 354# Connector - unified userspace <-> kernelspace linker
@@ -352,6 +369,7 @@ CONFIG_PARPORT_PC=m
352# CONFIG_PARPORT_PC_FIFO is not set 369# CONFIG_PARPORT_PC_FIFO is not set
353# CONFIG_PARPORT_PC_SUPERIO is not set 370# CONFIG_PARPORT_PC_SUPERIO is not set
354# CONFIG_PARPORT_GSC is not set 371# CONFIG_PARPORT_GSC is not set
372# CONFIG_PARPORT_AX88796 is not set
355# CONFIG_PARPORT_1284 is not set 373# CONFIG_PARPORT_1284 is not set
356 374
357# 375#
@@ -376,6 +394,7 @@ CONFIG_BLK_DEV_NBD=m
376CONFIG_BLK_DEV_RAM=y 394CONFIG_BLK_DEV_RAM=y
377CONFIG_BLK_DEV_RAM_COUNT=16 395CONFIG_BLK_DEV_RAM_COUNT=16
378CONFIG_BLK_DEV_RAM_SIZE=65536 396CONFIG_BLK_DEV_RAM_SIZE=65536
397CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
379CONFIG_BLK_DEV_INITRD=y 398CONFIG_BLK_DEV_INITRD=y
380# CONFIG_CDROM_PKTCDVD is not set 399# CONFIG_CDROM_PKTCDVD is not set
381# CONFIG_ATA_OVER_ETH is not set 400# CONFIG_ATA_OVER_ETH is not set
@@ -487,6 +506,7 @@ CONFIG_SCSI_SAS_ATTRS=m
487# CONFIG_MEGARAID_LEGACY is not set 506# CONFIG_MEGARAID_LEGACY is not set
488# CONFIG_MEGARAID_SAS is not set 507# CONFIG_MEGARAID_SAS is not set
489# CONFIG_SCSI_SATA is not set 508# CONFIG_SCSI_SATA is not set
509# CONFIG_SCSI_HPTIOP is not set
490# CONFIG_SCSI_BUSLOGIC is not set 510# CONFIG_SCSI_BUSLOGIC is not set
491# CONFIG_SCSI_DMX3191D is not set 511# CONFIG_SCSI_DMX3191D is not set
492# CONFIG_SCSI_EATA is not set 512# CONFIG_SCSI_EATA is not set
@@ -508,12 +528,6 @@ CONFIG_SCSI_IPR_TRACE=y
508CONFIG_SCSI_IPR_DUMP=y 528CONFIG_SCSI_IPR_DUMP=y
509# CONFIG_SCSI_QLOGIC_1280 is not set 529# CONFIG_SCSI_QLOGIC_1280 is not set
510CONFIG_SCSI_QLA_FC=m 530CONFIG_SCSI_QLA_FC=m
511CONFIG_SCSI_QLA2XXX_EMBEDDED_FIRMWARE=y
512CONFIG_SCSI_QLA21XX=m
513CONFIG_SCSI_QLA22XX=m
514CONFIG_SCSI_QLA2300=m
515CONFIG_SCSI_QLA2322=m
516CONFIG_SCSI_QLA24XX=m
517CONFIG_SCSI_LPFC=m 531CONFIG_SCSI_LPFC=m
518# CONFIG_SCSI_DC395x is not set 532# CONFIG_SCSI_DC395x is not set
519# CONFIG_SCSI_DC390T is not set 533# CONFIG_SCSI_DC390T is not set
@@ -528,9 +542,7 @@ CONFIG_MD_LINEAR=y
528CONFIG_MD_RAID0=y 542CONFIG_MD_RAID0=y
529CONFIG_MD_RAID1=y 543CONFIG_MD_RAID1=y
530CONFIG_MD_RAID10=m 544CONFIG_MD_RAID10=m
531CONFIG_MD_RAID5=y 545# CONFIG_MD_RAID456 is not set
532CONFIG_MD_RAID5_RESHAPE=y
533CONFIG_MD_RAID6=m
534CONFIG_MD_MULTIPATH=m 546CONFIG_MD_MULTIPATH=m
535CONFIG_MD_FAULTY=m 547CONFIG_MD_FAULTY=m
536CONFIG_BLK_DEV_DM=y 548CONFIG_BLK_DEV_DM=y
@@ -651,6 +663,7 @@ CONFIG_IXGB=m
651# CONFIG_IXGB_NAPI is not set 663# CONFIG_IXGB_NAPI is not set
652CONFIG_S2IO=m 664CONFIG_S2IO=m
653# CONFIG_S2IO_NAPI is not set 665# CONFIG_S2IO_NAPI is not set
666# CONFIG_MYRI10GE is not set
654 667
655# 668#
656# Token Ring devices 669# Token Ring devices
@@ -754,6 +767,7 @@ CONFIG_SERIO_LIBPS2=y
754CONFIG_VT=y 767CONFIG_VT=y
755CONFIG_VT_CONSOLE=y 768CONFIG_VT_CONSOLE=y
756CONFIG_HW_CONSOLE=y 769CONFIG_HW_CONSOLE=y
770# CONFIG_VT_HW_CONSOLE_BINDING is not set
757# CONFIG_SERIAL_NONSTANDARD is not set 771# CONFIG_SERIAL_NONSTANDARD is not set
758 772
759# 773#
@@ -776,6 +790,7 @@ CONFIG_SERIAL_JSM=m
776CONFIG_UNIX98_PTYS=y 790CONFIG_UNIX98_PTYS=y
777CONFIG_LEGACY_PTYS=y 791CONFIG_LEGACY_PTYS=y
778CONFIG_LEGACY_PTY_COUNT=256 792CONFIG_LEGACY_PTY_COUNT=256
793# CONFIG_BRIQ_PANEL is not set
779# CONFIG_PRINTER is not set 794# CONFIG_PRINTER is not set
780# CONFIG_PPDEV is not set 795# CONFIG_PPDEV is not set
781# CONFIG_TIPAR is not set 796# CONFIG_TIPAR is not set
@@ -793,6 +808,7 @@ CONFIG_HVCS=m
793# Watchdog Cards 808# Watchdog Cards
794# 809#
795# CONFIG_WATCHDOG is not set 810# CONFIG_WATCHDOG is not set
811# CONFIG_HW_RANDOM is not set
796CONFIG_GEN_RTC=y 812CONFIG_GEN_RTC=y
797# CONFIG_GEN_RTC_X is not set 813# CONFIG_GEN_RTC_X is not set
798# CONFIG_DTLK is not set 814# CONFIG_DTLK is not set
@@ -839,6 +855,7 @@ CONFIG_I2C_ALGOBIT=y
839# CONFIG_I2C_I810 is not set 855# CONFIG_I2C_I810 is not set
840# CONFIG_I2C_PIIX4 is not set 856# CONFIG_I2C_PIIX4 is not set
841# CONFIG_I2C_NFORCE2 is not set 857# CONFIG_I2C_NFORCE2 is not set
858# CONFIG_I2C_OCORES is not set
842# CONFIG_I2C_PARPORT is not set 859# CONFIG_I2C_PARPORT is not set
843# CONFIG_I2C_PARPORT_LIGHT is not set 860# CONFIG_I2C_PARPORT_LIGHT is not set
844# CONFIG_I2C_PROSAVAGE is not set 861# CONFIG_I2C_PROSAVAGE is not set
@@ -876,7 +893,6 @@ CONFIG_I2C_ALGOBIT=y
876# 893#
877# Dallas's 1-wire bus 894# Dallas's 1-wire bus
878# 895#
879# CONFIG_W1 is not set
880 896
881# 897#
882# Hardware Monitoring support 898# Hardware Monitoring support
@@ -892,6 +908,7 @@ CONFIG_I2C_ALGOBIT=y
892# Multimedia devices 908# Multimedia devices
893# 909#
894# CONFIG_VIDEO_DEV is not set 910# CONFIG_VIDEO_DEV is not set
911CONFIG_VIDEO_V4L2=y
895 912
896# 913#
897# Digital Video Broadcasting Devices 914# Digital Video Broadcasting Devices
@@ -902,19 +919,19 @@ CONFIG_I2C_ALGOBIT=y
902# 919#
903# Graphics support 920# Graphics support
904# 921#
922CONFIG_FIRMWARE_EDID=y
905CONFIG_FB=y 923CONFIG_FB=y
906CONFIG_FB_CFB_FILLRECT=y 924CONFIG_FB_CFB_FILLRECT=y
907CONFIG_FB_CFB_COPYAREA=y 925CONFIG_FB_CFB_COPYAREA=y
908CONFIG_FB_CFB_IMAGEBLIT=y 926CONFIG_FB_CFB_IMAGEBLIT=y
909CONFIG_FB_MACMODES=y 927CONFIG_FB_MACMODES=y
910CONFIG_FB_FIRMWARE_EDID=y 928# CONFIG_FB_BACKLIGHT is not set
911CONFIG_FB_MODE_HELPERS=y 929CONFIG_FB_MODE_HELPERS=y
912CONFIG_FB_TILEBLITTING=y 930CONFIG_FB_TILEBLITTING=y
913# CONFIG_FB_CIRRUS is not set 931# CONFIG_FB_CIRRUS is not set
914# CONFIG_FB_PM2 is not set 932# CONFIG_FB_PM2 is not set
915# CONFIG_FB_CYBER2000 is not set 933# CONFIG_FB_CYBER2000 is not set
916CONFIG_FB_OF=y 934CONFIG_FB_OF=y
917# CONFIG_FB_CT65550 is not set
918# CONFIG_FB_ASILIANT is not set 935# CONFIG_FB_ASILIANT is not set
919# CONFIG_FB_IMSTT is not set 936# CONFIG_FB_IMSTT is not set
920# CONFIG_FB_VGA16 is not set 937# CONFIG_FB_VGA16 is not set
@@ -993,6 +1010,7 @@ CONFIG_USB_DEVICEFS=y
993CONFIG_USB_EHCI_HCD=y 1010CONFIG_USB_EHCI_HCD=y
994# CONFIG_USB_EHCI_SPLIT_ISO is not set 1011# CONFIG_USB_EHCI_SPLIT_ISO is not set
995# CONFIG_USB_EHCI_ROOT_HUB_TT is not set 1012# CONFIG_USB_EHCI_ROOT_HUB_TT is not set
1013# CONFIG_USB_EHCI_TT_NEWSCHED is not set
996# CONFIG_USB_ISP116X_HCD is not set 1014# CONFIG_USB_ISP116X_HCD is not set
997CONFIG_USB_OHCI_HCD=y 1015CONFIG_USB_OHCI_HCD=y
998# CONFIG_USB_OHCI_BIG_ENDIAN is not set 1016# CONFIG_USB_OHCI_BIG_ENDIAN is not set
@@ -1083,10 +1101,12 @@ CONFIG_USB_MON=y
1083# CONFIG_USB_LEGOTOWER is not set 1101# CONFIG_USB_LEGOTOWER is not set
1084# CONFIG_USB_LCD is not set 1102# CONFIG_USB_LCD is not set
1085# CONFIG_USB_LED is not set 1103# CONFIG_USB_LED is not set
1104# CONFIG_USB_CYPRESS_CY7C63 is not set
1086# CONFIG_USB_CYTHERM is not set 1105# CONFIG_USB_CYTHERM is not set
1087# CONFIG_USB_PHIDGETKIT is not set 1106# CONFIG_USB_PHIDGETKIT is not set
1088# CONFIG_USB_PHIDGETSERVO is not set 1107# CONFIG_USB_PHIDGETSERVO is not set
1089# CONFIG_USB_IDMOUSE is not set 1108# CONFIG_USB_IDMOUSE is not set
1109# CONFIG_USB_APPLEDISPLAY is not set
1090# CONFIG_USB_SISUSBVGA is not set 1110# CONFIG_USB_SISUSBVGA is not set
1091# CONFIG_USB_LD is not set 1111# CONFIG_USB_LD is not set
1092# CONFIG_USB_TEST is not set 1112# CONFIG_USB_TEST is not set
@@ -1124,12 +1144,14 @@ CONFIG_USB_MON=y
1124CONFIG_INFINIBAND=m 1144CONFIG_INFINIBAND=m
1125CONFIG_INFINIBAND_USER_MAD=m 1145CONFIG_INFINIBAND_USER_MAD=m
1126CONFIG_INFINIBAND_USER_ACCESS=m 1146CONFIG_INFINIBAND_USER_ACCESS=m
1147CONFIG_INFINIBAND_ADDR_TRANS=y
1127CONFIG_INFINIBAND_MTHCA=m 1148CONFIG_INFINIBAND_MTHCA=m
1128CONFIG_INFINIBAND_MTHCA_DEBUG=y 1149CONFIG_INFINIBAND_MTHCA_DEBUG=y
1129CONFIG_INFINIBAND_IPOIB=m 1150CONFIG_INFINIBAND_IPOIB=m
1130CONFIG_INFINIBAND_IPOIB_DEBUG=y 1151CONFIG_INFINIBAND_IPOIB_DEBUG=y
1131# CONFIG_INFINIBAND_IPOIB_DEBUG_DATA is not set 1152# CONFIG_INFINIBAND_IPOIB_DEBUG_DATA is not set
1132CONFIG_INFINIBAND_SRP=m 1153CONFIG_INFINIBAND_SRP=m
1154# CONFIG_INFINIBAND_ISER is not set
1133 1155
1134# 1156#
1135# EDAC - error detection and reporting (RAS) (EXPERIMENTAL) 1157# EDAC - error detection and reporting (RAS) (EXPERIMENTAL)
@@ -1141,6 +1163,19 @@ CONFIG_INFINIBAND_SRP=m
1141# CONFIG_RTC_CLASS is not set 1163# CONFIG_RTC_CLASS is not set
1142 1164
1143# 1165#
1166# DMA Engine support
1167#
1168# CONFIG_DMA_ENGINE is not set
1169
1170#
1171# DMA Clients
1172#
1173
1174#
1175# DMA Devices
1176#
1177
1178#
1144# File systems 1179# File systems
1145# 1180#
1146CONFIG_EXT2_FS=y 1181CONFIG_EXT2_FS=y
@@ -1169,15 +1204,16 @@ CONFIG_JFS_SECURITY=y
1169# CONFIG_JFS_STATISTICS is not set 1204# CONFIG_JFS_STATISTICS is not set
1170CONFIG_FS_POSIX_ACL=y 1205CONFIG_FS_POSIX_ACL=y
1171CONFIG_XFS_FS=m 1206CONFIG_XFS_FS=m
1172CONFIG_XFS_EXPORT=y
1173# CONFIG_XFS_QUOTA is not set 1207# CONFIG_XFS_QUOTA is not set
1174CONFIG_XFS_SECURITY=y 1208CONFIG_XFS_SECURITY=y
1175CONFIG_XFS_POSIX_ACL=y 1209CONFIG_XFS_POSIX_ACL=y
1176# CONFIG_XFS_RT is not set 1210# CONFIG_XFS_RT is not set
1177CONFIG_OCFS2_FS=m 1211CONFIG_OCFS2_FS=m
1212CONFIG_OCFS2_DEBUG_MASKLOG=y
1178# CONFIG_MINIX_FS is not set 1213# CONFIG_MINIX_FS is not set
1179# CONFIG_ROMFS_FS is not set 1214# CONFIG_ROMFS_FS is not set
1180CONFIG_INOTIFY=y 1215CONFIG_INOTIFY=y
1216CONFIG_INOTIFY_USER=y
1181# CONFIG_QUOTA is not set 1217# CONFIG_QUOTA is not set
1182CONFIG_DNOTIFY=y 1218CONFIG_DNOTIFY=y
1183# CONFIG_AUTOFS_FS is not set 1219# CONFIG_AUTOFS_FS is not set
@@ -1259,8 +1295,10 @@ CONFIG_RPCSEC_GSS_SPKM3=m
1259# CONFIG_SMB_FS is not set 1295# CONFIG_SMB_FS is not set
1260CONFIG_CIFS=m 1296CONFIG_CIFS=m
1261# CONFIG_CIFS_STATS is not set 1297# CONFIG_CIFS_STATS is not set
1298# CONFIG_CIFS_WEAK_PW_HASH is not set
1262CONFIG_CIFS_XATTR=y 1299CONFIG_CIFS_XATTR=y
1263CONFIG_CIFS_POSIX=y 1300CONFIG_CIFS_POSIX=y
1301# CONFIG_CIFS_DEBUG2 is not set
1264# CONFIG_CIFS_EXPERIMENTAL is not set 1302# CONFIG_CIFS_EXPERIMENTAL is not set
1265# CONFIG_NCP_FS is not set 1303# CONFIG_NCP_FS is not set
1266# CONFIG_CODA_FS is not set 1304# CONFIG_CODA_FS is not set
@@ -1326,6 +1364,9 @@ CONFIG_CRC32=y
1326CONFIG_LIBCRC32C=m 1364CONFIG_LIBCRC32C=m
1327CONFIG_ZLIB_INFLATE=y 1365CONFIG_ZLIB_INFLATE=y
1328CONFIG_ZLIB_DEFLATE=m 1366CONFIG_ZLIB_DEFLATE=m
1367CONFIG_TEXTSEARCH=y
1368CONFIG_TEXTSEARCH_KMP=m
1369CONFIG_PLIST=y
1329 1370
1330# 1371#
1331# Instrumentation Support 1372# Instrumentation Support
@@ -1339,14 +1380,19 @@ CONFIG_KPROBES=y
1339# 1380#
1340# CONFIG_PRINTK_TIME is not set 1381# CONFIG_PRINTK_TIME is not set
1341CONFIG_MAGIC_SYSRQ=y 1382CONFIG_MAGIC_SYSRQ=y
1383# CONFIG_UNUSED_SYMBOLS is not set
1342CONFIG_DEBUG_KERNEL=y 1384CONFIG_DEBUG_KERNEL=y
1343CONFIG_LOG_BUF_SHIFT=17 1385CONFIG_LOG_BUF_SHIFT=17
1344CONFIG_DETECT_SOFTLOCKUP=y 1386CONFIG_DETECT_SOFTLOCKUP=y
1345# CONFIG_SCHEDSTATS is not set 1387# CONFIG_SCHEDSTATS is not set
1346# CONFIG_DEBUG_SLAB is not set 1388# CONFIG_DEBUG_SLAB is not set
1347# CONFIG_DEBUG_MUTEXES is not set 1389# CONFIG_DEBUG_RT_MUTEXES is not set
1390# CONFIG_RT_MUTEX_TESTER is not set
1348# CONFIG_DEBUG_SPINLOCK is not set 1391# CONFIG_DEBUG_SPINLOCK is not set
1392# CONFIG_DEBUG_MUTEXES is not set
1393# CONFIG_DEBUG_RWSEMS is not set
1349# CONFIG_DEBUG_SPINLOCK_SLEEP is not set 1394# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
1395# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
1350# CONFIG_DEBUG_KOBJECT is not set 1396# CONFIG_DEBUG_KOBJECT is not set
1351# CONFIG_DEBUG_INFO is not set 1397# CONFIG_DEBUG_INFO is not set
1352CONFIG_DEBUG_FS=y 1398CONFIG_DEBUG_FS=y
diff --git a/arch/powerpc/kernel/Makefile b/arch/powerpc/kernel/Makefile
index 814f242aeb8c..956c2e5564b7 100644
--- a/arch/powerpc/kernel/Makefile
+++ b/arch/powerpc/kernel/Makefile
@@ -67,9 +67,9 @@ pci64-$(CONFIG_PPC64) += pci_64.o pci_dn.o pci_iommu.o \
67 pci_direct_iommu.o iomap.o 67 pci_direct_iommu.o iomap.o
68pci32-$(CONFIG_PPC32) := pci_32.o 68pci32-$(CONFIG_PPC32) := pci_32.o
69obj-$(CONFIG_PCI) += $(pci64-y) $(pci32-y) 69obj-$(CONFIG_PCI) += $(pci64-y) $(pci32-y)
70kexec-$(CONFIG_PPC64) := machine_kexec_64.o crash.o 70kexec-$(CONFIG_PPC64) := machine_kexec_64.o
71kexec-$(CONFIG_PPC32) := machine_kexec_32.o 71kexec-$(CONFIG_PPC32) := machine_kexec_32.o
72obj-$(CONFIG_KEXEC) += machine_kexec.o $(kexec-y) 72obj-$(CONFIG_KEXEC) += machine_kexec.o crash.o $(kexec-y)
73 73
74ifeq ($(CONFIG_PPC_ISERIES),y) 74ifeq ($(CONFIG_PPC_ISERIES),y)
75$(obj)/head_64.o: $(obj)/lparmap.s 75$(obj)/head_64.o: $(obj)/lparmap.s
diff --git a/arch/powerpc/kernel/cpu_setup_power4.S b/arch/powerpc/kernel/cpu_setup_power4.S
index f69af2c5d7b3..76e97aa71c45 100644
--- a/arch/powerpc/kernel/cpu_setup_power4.S
+++ b/arch/powerpc/kernel/cpu_setup_power4.S
@@ -76,6 +76,8 @@ _GLOBAL(__setup_cpu_ppc970)
76 mfspr r0,SPRN_HID0 76 mfspr r0,SPRN_HID0
77 li r11,5 /* clear DOZE and SLEEP */ 77 li r11,5 /* clear DOZE and SLEEP */
78 rldimi r0,r11,52,8 /* set NAP and DPM */ 78 rldimi r0,r11,52,8 /* set NAP and DPM */
79 li r11,0
80 rldimi r0,r11,32,31 /* clear EN_ATTN */
79 mtspr SPRN_HID0,r0 81 mtspr SPRN_HID0,r0
80 mfspr r0,SPRN_HID0 82 mfspr r0,SPRN_HID0
81 mfspr r0,SPRN_HID0 83 mfspr r0,SPRN_HID0
diff --git a/arch/powerpc/kernel/crash.c b/arch/powerpc/kernel/crash.c
index 358cecdc6aef..f04c18e08b8b 100644
--- a/arch/powerpc/kernel/crash.c
+++ b/arch/powerpc/kernel/crash.c
@@ -44,6 +44,7 @@
44/* This keeps a track of which one is crashing cpu. */ 44/* This keeps a track of which one is crashing cpu. */
45int crashing_cpu = -1; 45int crashing_cpu = -1;
46static cpumask_t cpus_in_crash = CPU_MASK_NONE; 46static cpumask_t cpus_in_crash = CPU_MASK_NONE;
47cpumask_t cpus_in_sr = CPU_MASK_NONE;
47 48
48static u32 *append_elf_note(u32 *buf, char *name, unsigned type, void *data, 49static u32 *append_elf_note(u32 *buf, char *name, unsigned type, void *data,
49 size_t data_len) 50 size_t data_len)
@@ -139,7 +140,13 @@ void crash_ipi_callback(struct pt_regs *regs)
139 140
140 if (ppc_md.kexec_cpu_down) 141 if (ppc_md.kexec_cpu_down)
141 ppc_md.kexec_cpu_down(1, 1); 142 ppc_md.kexec_cpu_down(1, 1);
143
144#ifdef CONFIG_PPC64
142 kexec_smp_wait(); 145 kexec_smp_wait();
146#else
147 for (;;); /* FIXME */
148#endif
149
143 /* NOTREACHED */ 150 /* NOTREACHED */
144} 151}
145 152
@@ -255,7 +262,11 @@ static void crash_kexec_prepare_cpus(int cpu)
255 * 262 *
256 * do this if kexec in setup.c ? 263 * do this if kexec in setup.c ?
257 */ 264 */
265#ifdef CONFIG_PPC64
258 smp_release_cpus(); 266 smp_release_cpus();
267#else
268 /* FIXME */
269#endif
259} 270}
260 271
261void crash_kexec_secondary(struct pt_regs *regs) 272void crash_kexec_secondary(struct pt_regs *regs)
diff --git a/arch/powerpc/kernel/fpu.S b/arch/powerpc/kernel/fpu.S
index 7e2c9fe44ac1..821e152e093c 100644
--- a/arch/powerpc/kernel/fpu.S
+++ b/arch/powerpc/kernel/fpu.S
@@ -2,6 +2,11 @@
2 * FPU support code, moved here from head.S so that it can be used 2 * FPU support code, moved here from head.S so that it can be used
3 * by chips which use other head-whatever.S files. 3 * by chips which use other head-whatever.S files.
4 * 4 *
5 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
6 * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu>
7 * Copyright (C) 1996 Paul Mackerras.
8 * Copyright (C) 1997 Dan Malek (dmalek@jlc.net).
9 *
5 * This program is free software; you can redistribute it and/or 10 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License 11 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 12 * as published by the Free Software Foundation; either version
diff --git a/arch/powerpc/kernel/irq.c b/arch/powerpc/kernel/irq.c
index 01bdae35cb55..12c5971d6565 100644
--- a/arch/powerpc/kernel/irq.c
+++ b/arch/powerpc/kernel/irq.c
@@ -322,7 +322,8 @@ EXPORT_SYMBOL(do_softirq);
322 322
323static LIST_HEAD(irq_hosts); 323static LIST_HEAD(irq_hosts);
324static spinlock_t irq_big_lock = SPIN_LOCK_UNLOCKED; 324static spinlock_t irq_big_lock = SPIN_LOCK_UNLOCKED;
325 325static DEFINE_PER_CPU(unsigned int, irq_radix_reader);
326static unsigned int irq_radix_writer;
326struct irq_map_entry irq_map[NR_IRQS]; 327struct irq_map_entry irq_map[NR_IRQS];
327static unsigned int irq_virq_count = NR_IRQS; 328static unsigned int irq_virq_count = NR_IRQS;
328static struct irq_host *irq_default_host; 329static struct irq_host *irq_default_host;
@@ -455,6 +456,58 @@ void irq_set_virq_count(unsigned int count)
455 irq_virq_count = count; 456 irq_virq_count = count;
456} 457}
457 458
459/* radix tree not lockless safe ! we use a brlock-type mecanism
460 * for now, until we can use a lockless radix tree
461 */
462static void irq_radix_wrlock(unsigned long *flags)
463{
464 unsigned int cpu, ok;
465
466 spin_lock_irqsave(&irq_big_lock, *flags);
467 irq_radix_writer = 1;
468 smp_mb();
469 do {
470 barrier();
471 ok = 1;
472 for_each_possible_cpu(cpu) {
473 if (per_cpu(irq_radix_reader, cpu)) {
474 ok = 0;
475 break;
476 }
477 }
478 if (!ok)
479 cpu_relax();
480 } while(!ok);
481}
482
483static void irq_radix_wrunlock(unsigned long flags)
484{
485 smp_wmb();
486 irq_radix_writer = 0;
487 spin_unlock_irqrestore(&irq_big_lock, flags);
488}
489
490static void irq_radix_rdlock(unsigned long *flags)
491{
492 local_irq_save(*flags);
493 __get_cpu_var(irq_radix_reader) = 1;
494 smp_mb();
495 if (likely(irq_radix_writer == 0))
496 return;
497 __get_cpu_var(irq_radix_reader) = 0;
498 smp_wmb();
499 spin_lock(&irq_big_lock);
500 __get_cpu_var(irq_radix_reader) = 1;
501 spin_unlock(&irq_big_lock);
502}
503
504static void irq_radix_rdunlock(unsigned long flags)
505{
506 __get_cpu_var(irq_radix_reader) = 0;
507 local_irq_restore(flags);
508}
509
510
458unsigned int irq_create_mapping(struct irq_host *host, 511unsigned int irq_create_mapping(struct irq_host *host,
459 irq_hw_number_t hwirq) 512 irq_hw_number_t hwirq)
460{ 513{
@@ -604,13 +657,9 @@ void irq_dispose_mapping(unsigned int virq)
604 /* Check if radix tree allocated yet */ 657 /* Check if radix tree allocated yet */
605 if (host->revmap_data.tree.gfp_mask == 0) 658 if (host->revmap_data.tree.gfp_mask == 0)
606 break; 659 break;
607 /* XXX radix tree not safe ! remove lock whem it becomes safe 660 irq_radix_wrlock(&flags);
608 * and use some RCU sync to make sure everything is ok before we
609 * can re-use that map entry
610 */
611 spin_lock_irqsave(&irq_big_lock, flags);
612 radix_tree_delete(&host->revmap_data.tree, hwirq); 661 radix_tree_delete(&host->revmap_data.tree, hwirq);
613 spin_unlock_irqrestore(&irq_big_lock, flags); 662 irq_radix_wrunlock(flags);
614 break; 663 break;
615 } 664 }
616 665
@@ -677,25 +726,24 @@ unsigned int irq_radix_revmap(struct irq_host *host,
677 if (tree->gfp_mask == 0) 726 if (tree->gfp_mask == 0)
678 return irq_find_mapping(host, hwirq); 727 return irq_find_mapping(host, hwirq);
679 728
680 /* XXX Current radix trees are NOT SMP safe !!! Remove that lock
681 * when that is fixed (when Nick's patch gets in
682 */
683 spin_lock_irqsave(&irq_big_lock, flags);
684
685 /* Now try to resolve */ 729 /* Now try to resolve */
730 irq_radix_rdlock(&flags);
686 ptr = radix_tree_lookup(tree, hwirq); 731 ptr = radix_tree_lookup(tree, hwirq);
732 irq_radix_rdunlock(flags);
733
687 /* Found it, return */ 734 /* Found it, return */
688 if (ptr) { 735 if (ptr) {
689 virq = ptr - irq_map; 736 virq = ptr - irq_map;
690 goto bail; 737 return virq;
691 } 738 }
692 739
693 /* If not there, try to insert it */ 740 /* If not there, try to insert it */
694 virq = irq_find_mapping(host, hwirq); 741 virq = irq_find_mapping(host, hwirq);
695 if (virq != NO_IRQ) 742 if (virq != NO_IRQ) {
696 radix_tree_insert(tree, virq, &irq_map[virq]); 743 irq_radix_wrlock(&flags);
697 bail: 744 radix_tree_insert(tree, hwirq, &irq_map[virq]);
698 spin_unlock_irqrestore(&irq_big_lock, flags); 745 irq_radix_wrunlock(flags);
746 }
699 return virq; 747 return virq;
700} 748}
701 749
@@ -806,12 +854,12 @@ static int irq_late_init(void)
806 struct irq_host *h; 854 struct irq_host *h;
807 unsigned long flags; 855 unsigned long flags;
808 856
809 spin_lock_irqsave(&irq_big_lock, flags); 857 irq_radix_wrlock(&flags);
810 list_for_each_entry(h, &irq_hosts, link) { 858 list_for_each_entry(h, &irq_hosts, link) {
811 if (h->revmap_type == IRQ_HOST_MAP_TREE) 859 if (h->revmap_type == IRQ_HOST_MAP_TREE)
812 INIT_RADIX_TREE(&h->revmap_data.tree, GFP_ATOMIC); 860 INIT_RADIX_TREE(&h->revmap_data.tree, GFP_ATOMIC);
813 } 861 }
814 spin_unlock_irqrestore(&irq_big_lock, flags); 862 irq_radix_wrunlock(flags);
815 863
816 return 0; 864 return 0;
817} 865}
diff --git a/arch/powerpc/kernel/kprobes.c b/arch/powerpc/kernel/kprobes.c
index 9f0898c89759..cd65c367b8b6 100644
--- a/arch/powerpc/kernel/kprobes.c
+++ b/arch/powerpc/kernel/kprobes.c
@@ -61,6 +61,8 @@ int __kprobes arch_prepare_kprobe(struct kprobe *p)
61 if (!ret) { 61 if (!ret) {
62 memcpy(p->ainsn.insn, p->addr, MAX_INSN_SIZE * sizeof(kprobe_opcode_t)); 62 memcpy(p->ainsn.insn, p->addr, MAX_INSN_SIZE * sizeof(kprobe_opcode_t));
63 p->opcode = *p->addr; 63 p->opcode = *p->addr;
64 flush_icache_range((unsigned long)p->ainsn.insn,
65 (unsigned long)p->ainsn.insn + sizeof(kprobe_opcode_t));
64 } 66 }
65 67
66 return ret; 68 return ret;
diff --git a/arch/powerpc/kernel/legacy_serial.c b/arch/powerpc/kernel/legacy_serial.c
index 359ab89748e0..40a39291861f 100644
--- a/arch/powerpc/kernel/legacy_serial.c
+++ b/arch/powerpc/kernel/legacy_serial.c
@@ -115,6 +115,7 @@ static int __init add_legacy_soc_port(struct device_node *np,
115 u64 addr; 115 u64 addr;
116 u32 *addrp; 116 u32 *addrp;
117 upf_t flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_SHARE_IRQ; 117 upf_t flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_SHARE_IRQ;
118 struct device_node *tsi = of_get_parent(np);
118 119
119 /* We only support ports that have a clock frequency properly 120 /* We only support ports that have a clock frequency properly
120 * encoded in the device-tree. 121 * encoded in the device-tree.
@@ -134,7 +135,10 @@ static int __init add_legacy_soc_port(struct device_node *np,
134 /* Add port, irq will be dealt with later. We passed a translated 135 /* Add port, irq will be dealt with later. We passed a translated
135 * IO port value. It will be fixed up later along with the irq 136 * IO port value. It will be fixed up later along with the irq
136 */ 137 */
137 return add_legacy_port(np, -1, UPIO_MEM, addr, addr, NO_IRQ, flags, 0); 138 if (tsi && !strcmp(tsi->type, "tsi-bridge"))
139 return add_legacy_port(np, -1, UPIO_TSI, addr, addr, NO_IRQ, flags, 0);
140 else
141 return add_legacy_port(np, -1, UPIO_MEM, addr, addr, NO_IRQ, flags, 0);
138} 142}
139 143
140static int __init add_legacy_isa_port(struct device_node *np, 144static int __init add_legacy_isa_port(struct device_node *np,
@@ -464,7 +468,7 @@ static int __init serial_dev_init(void)
464 fixup_port_irq(i, np, port); 468 fixup_port_irq(i, np, port);
465 if (port->iotype == UPIO_PORT) 469 if (port->iotype == UPIO_PORT)
466 fixup_port_pio(i, np, port); 470 fixup_port_pio(i, np, port);
467 if (port->iotype == UPIO_MEM) 471 if ((port->iotype == UPIO_MEM) || (port->iotype == UPIO_TSI))
468 fixup_port_mmio(i, np, port); 472 fixup_port_mmio(i, np, port);
469 } 473 }
470 474
diff --git a/arch/powerpc/kernel/machine_kexec.c b/arch/powerpc/kernel/machine_kexec.c
index a81ca1b841ec..e60a0c544d63 100644
--- a/arch/powerpc/kernel/machine_kexec.c
+++ b/arch/powerpc/kernel/machine_kexec.c
@@ -13,6 +13,7 @@
13#include <linux/reboot.h> 13#include <linux/reboot.h>
14#include <linux/threads.h> 14#include <linux/threads.h>
15#include <asm/machdep.h> 15#include <asm/machdep.h>
16#include <asm/lmb.h>
16 17
17void machine_crash_shutdown(struct pt_regs *regs) 18void machine_crash_shutdown(struct pt_regs *regs)
18{ 19{
@@ -59,3 +60,58 @@ NORET_TYPE void machine_kexec(struct kimage *image)
59 } 60 }
60 for(;;); 61 for(;;);
61} 62}
63
64static int __init early_parse_crashk(char *p)
65{
66 unsigned long size;
67
68 if (!p)
69 return 1;
70
71 size = memparse(p, &p);
72
73 if (*p == '@')
74 crashk_res.start = memparse(p + 1, &p);
75 else
76 crashk_res.start = KDUMP_KERNELBASE;
77
78 crashk_res.end = crashk_res.start + size - 1;
79
80 return 0;
81}
82early_param("crashkernel", early_parse_crashk);
83
84void __init reserve_crashkernel(void)
85{
86 unsigned long size;
87
88 if (crashk_res.start == 0)
89 return;
90
91 /* We might have got these values via the command line or the
92 * device tree, either way sanitise them now. */
93
94 size = crashk_res.end - crashk_res.start + 1;
95
96 if (crashk_res.start != KDUMP_KERNELBASE)
97 printk("Crash kernel location must be 0x%x\n",
98 KDUMP_KERNELBASE);
99
100 crashk_res.start = KDUMP_KERNELBASE;
101 size = PAGE_ALIGN(size);
102 crashk_res.end = crashk_res.start + size - 1;
103
104 /* Crash kernel trumps memory limit */
105 if (memory_limit && memory_limit <= crashk_res.end) {
106 memory_limit = crashk_res.end + 1;
107 printk("Adjusted memory limit for crashkernel, now 0x%lx\n",
108 memory_limit);
109 }
110
111 lmb_reserve(crashk_res.start, size);
112}
113
114int overlaps_crashkernel(unsigned long start, unsigned long size)
115{
116 return (start + size) > crashk_res.start && start <= crashk_res.end;
117}
diff --git a/arch/powerpc/kernel/machine_kexec_64.c b/arch/powerpc/kernel/machine_kexec_64.c
index b438d45a068c..be58985c7681 100644
--- a/arch/powerpc/kernel/machine_kexec_64.c
+++ b/arch/powerpc/kernel/machine_kexec_64.c
@@ -10,7 +10,6 @@
10 */ 10 */
11 11
12 12
13#include <linux/cpumask.h>
14#include <linux/kexec.h> 13#include <linux/kexec.h>
15#include <linux/smp.h> 14#include <linux/smp.h>
16#include <linux/thread_info.h> 15#include <linux/thread_info.h>
@@ -21,7 +20,6 @@
21#include <asm/machdep.h> 20#include <asm/machdep.h>
22#include <asm/cacheflush.h> 21#include <asm/cacheflush.h>
23#include <asm/paca.h> 22#include <asm/paca.h>
24#include <asm/lmb.h>
25#include <asm/mmu.h> 23#include <asm/mmu.h>
26#include <asm/sections.h> /* _end */ 24#include <asm/sections.h> /* _end */
27#include <asm/prom.h> 25#include <asm/prom.h>
@@ -385,58 +383,3 @@ static int __init kexec_setup(void)
385 return 0; 383 return 0;
386} 384}
387__initcall(kexec_setup); 385__initcall(kexec_setup);
388
389static int __init early_parse_crashk(char *p)
390{
391 unsigned long size;
392
393 if (!p)
394 return 1;
395
396 size = memparse(p, &p);
397
398 if (*p == '@')
399 crashk_res.start = memparse(p + 1, &p);
400 else
401 crashk_res.start = KDUMP_KERNELBASE;
402
403 crashk_res.end = crashk_res.start + size - 1;
404
405 return 0;
406}
407early_param("crashkernel", early_parse_crashk);
408
409void __init reserve_crashkernel(void)
410{
411 unsigned long size;
412
413 if (crashk_res.start == 0)
414 return;
415
416 /* We might have got these values via the command line or the
417 * device tree, either way sanitise them now. */
418
419 size = crashk_res.end - crashk_res.start + 1;
420
421 if (crashk_res.start != KDUMP_KERNELBASE)
422 printk("Crash kernel location must be 0x%x\n",
423 KDUMP_KERNELBASE);
424
425 crashk_res.start = KDUMP_KERNELBASE;
426 size = PAGE_ALIGN(size);
427 crashk_res.end = crashk_res.start + size - 1;
428
429 /* Crash kernel trumps memory limit */
430 if (memory_limit && memory_limit <= crashk_res.end) {
431 memory_limit = crashk_res.end + 1;
432 printk("Adjusted memory limit for crashkernel, now 0x%lx\n",
433 memory_limit);
434 }
435
436 lmb_reserve(crashk_res.start, size);
437}
438
439int overlaps_crashkernel(unsigned long start, unsigned long size)
440{
441 return (start + size) > crashk_res.start && start <= crashk_res.end;
442}
diff --git a/arch/powerpc/kernel/pci_64.c b/arch/powerpc/kernel/pci_64.c
index 2fce7738e9e2..138134c8c17d 100644
--- a/arch/powerpc/kernel/pci_64.c
+++ b/arch/powerpc/kernel/pci_64.c
@@ -1289,6 +1289,9 @@ int pci_read_irq_line(struct pci_dev *pci_dev)
1289 1289
1290 DBG("Try to map irq for %s...\n", pci_name(pci_dev)); 1290 DBG("Try to map irq for %s...\n", pci_name(pci_dev));
1291 1291
1292#ifdef DEBUG
1293 memset(&oirq, 0xff, sizeof(oirq));
1294#endif
1292 /* Try to get a mapping from the device-tree */ 1295 /* Try to get a mapping from the device-tree */
1293 if (of_irq_map_pci(pci_dev, &oirq)) { 1296 if (of_irq_map_pci(pci_dev, &oirq)) {
1294 u8 line, pin; 1297 u8 line, pin;
@@ -1314,8 +1317,9 @@ int pci_read_irq_line(struct pci_dev *pci_dev)
1314 if (virq != NO_IRQ) 1317 if (virq != NO_IRQ)
1315 set_irq_type(virq, IRQ_TYPE_LEVEL_LOW); 1318 set_irq_type(virq, IRQ_TYPE_LEVEL_LOW);
1316 } else { 1319 } else {
1317 DBG(" -> got one, spec %d cells (0x%08x...) on %s\n", 1320 DBG(" -> got one, spec %d cells (0x%08x 0x%08x...) on %s\n",
1318 oirq.size, oirq.specifier[0], oirq.controller->full_name); 1321 oirq.size, oirq.specifier[0], oirq.specifier[1],
1322 oirq.controller->full_name);
1319 1323
1320 virq = irq_create_of_mapping(oirq.controller, oirq.specifier, 1324 virq = irq_create_of_mapping(oirq.controller, oirq.specifier,
1321 oirq.size); 1325 oirq.size);
@@ -1324,6 +1328,9 @@ int pci_read_irq_line(struct pci_dev *pci_dev)
1324 DBG(" -> failed to map !\n"); 1328 DBG(" -> failed to map !\n");
1325 return -1; 1329 return -1;
1326 } 1330 }
1331
1332 DBG(" -> mapped to linux irq %d\n", virq);
1333
1327 pci_dev->irq = virq; 1334 pci_dev->irq = virq;
1328 pci_write_config_byte(pci_dev, PCI_INTERRUPT_LINE, virq); 1335 pci_write_config_byte(pci_dev, PCI_INTERRUPT_LINE, virq);
1329 1336
diff --git a/arch/powerpc/kernel/ppc_ksyms.c b/arch/powerpc/kernel/ppc_ksyms.c
index f6a05f090b25..39d3bfcabcd2 100644
--- a/arch/powerpc/kernel/ppc_ksyms.c
+++ b/arch/powerpc/kernel/ppc_ksyms.c
@@ -126,10 +126,6 @@ EXPORT_SYMBOL(pci_bus_mem_base_phys);
126EXPORT_SYMBOL(pci_bus_to_hose); 126EXPORT_SYMBOL(pci_bus_to_hose);
127#endif /* CONFIG_PCI */ 127#endif /* CONFIG_PCI */
128 128
129#ifdef CONFIG_NOT_COHERENT_CACHE
130EXPORT_SYMBOL(flush_dcache_all);
131#endif
132
133EXPORT_SYMBOL(start_thread); 129EXPORT_SYMBOL(start_thread);
134EXPORT_SYMBOL(kernel_thread); 130EXPORT_SYMBOL(kernel_thread);
135 131
diff --git a/arch/powerpc/kernel/prom_init.c b/arch/powerpc/kernel/prom_init.c
index 462bced40c12..4394e545f9f7 100644
--- a/arch/powerpc/kernel/prom_init.c
+++ b/arch/powerpc/kernel/prom_init.c
@@ -646,13 +646,13 @@ static unsigned char ibm_architecture_vec[] = {
646 5 - 1, /* 5 option vectors */ 646 5 - 1, /* 5 option vectors */
647 647
648 /* option vector 1: processor architectures supported */ 648 /* option vector 1: processor architectures supported */
649 3 - 1, /* length */ 649 3 - 2, /* length */
650 0, /* don't ignore, don't halt */ 650 0, /* don't ignore, don't halt */
651 OV1_PPC_2_00 | OV1_PPC_2_01 | OV1_PPC_2_02 | OV1_PPC_2_03 | 651 OV1_PPC_2_00 | OV1_PPC_2_01 | OV1_PPC_2_02 | OV1_PPC_2_03 |
652 OV1_PPC_2_04 | OV1_PPC_2_05, 652 OV1_PPC_2_04 | OV1_PPC_2_05,
653 653
654 /* option vector 2: Open Firmware options supported */ 654 /* option vector 2: Open Firmware options supported */
655 34 - 1, /* length */ 655 34 - 2, /* length */
656 OV2_REAL_MODE, 656 OV2_REAL_MODE,
657 0, 0, 657 0, 0,
658 W(0xffffffff), /* real_base */ 658 W(0xffffffff), /* real_base */
@@ -666,16 +666,16 @@ static unsigned char ibm_architecture_vec[] = {
666 48, /* max log_2(hash table size) */ 666 48, /* max log_2(hash table size) */
667 667
668 /* option vector 3: processor options supported */ 668 /* option vector 3: processor options supported */
669 3 - 1, /* length */ 669 3 - 2, /* length */
670 0, /* don't ignore, don't halt */ 670 0, /* don't ignore, don't halt */
671 OV3_FP | OV3_VMX, 671 OV3_FP | OV3_VMX,
672 672
673 /* option vector 4: IBM PAPR implementation */ 673 /* option vector 4: IBM PAPR implementation */
674 2 - 1, /* length */ 674 2 - 2, /* length */
675 0, /* don't halt */ 675 0, /* don't halt */
676 676
677 /* option vector 5: PAPR/OF options */ 677 /* option vector 5: PAPR/OF options */
678 3 - 1, /* length */ 678 3 - 2, /* length */
679 0, /* don't ignore, don't halt */ 679 0, /* don't ignore, don't halt */
680 OV5_LPAR | OV5_SPLPAR | OV5_LARGE_PAGES, 680 OV5_LPAR | OV5_SPLPAR | OV5_LARGE_PAGES,
681}; 681};
diff --git a/arch/powerpc/kernel/prom_parse.c b/arch/powerpc/kernel/prom_parse.c
index 6a7e997c401d..a10825a5dfe6 100644
--- a/arch/powerpc/kernel/prom_parse.c
+++ b/arch/powerpc/kernel/prom_parse.c
@@ -598,11 +598,6 @@ static struct device_node *of_irq_find_parent(struct device_node *child)
598 return p; 598 return p;
599} 599}
600 600
601static u8 of_irq_pci_swizzle(u8 slot, u8 pin)
602{
603 return (((pin - 1) + slot) % 4) + 1;
604}
605
606/* This doesn't need to be called if you don't have any special workaround 601/* This doesn't need to be called if you don't have any special workaround
607 * flags to pass 602 * flags to pass
608 */ 603 */
@@ -644,14 +639,17 @@ void of_irq_map_init(unsigned int flags)
644 639
645} 640}
646 641
647int of_irq_map_raw(struct device_node *parent, u32 *intspec, u32 *addr, 642int of_irq_map_raw(struct device_node *parent, u32 *intspec, u32 ointsize,
648 struct of_irq *out_irq) 643 u32 *addr, struct of_irq *out_irq)
649{ 644{
650 struct device_node *ipar, *tnode, *old = NULL, *newpar = NULL; 645 struct device_node *ipar, *tnode, *old = NULL, *newpar = NULL;
651 u32 *tmp, *imap, *imask; 646 u32 *tmp, *imap, *imask;
652 u32 intsize = 1, addrsize, newintsize = 0, newaddrsize = 0; 647 u32 intsize = 1, addrsize, newintsize = 0, newaddrsize = 0;
653 int imaplen, match, i; 648 int imaplen, match, i;
654 649
650 DBG("of_irq_map_raw: par=%s,intspec=[0x%08x 0x%08x...],ointsize=%d\n",
651 parent->full_name, intspec[0], intspec[1], ointsize);
652
655 ipar = of_node_get(parent); 653 ipar = of_node_get(parent);
656 654
657 /* First get the #interrupt-cells property of the current cursor 655 /* First get the #interrupt-cells property of the current cursor
@@ -675,6 +673,9 @@ int of_irq_map_raw(struct device_node *parent, u32 *intspec, u32 *addr,
675 673
676 DBG("of_irq_map_raw: ipar=%s, size=%d\n", ipar->full_name, intsize); 674 DBG("of_irq_map_raw: ipar=%s, size=%d\n", ipar->full_name, intsize);
677 675
676 if (ointsize != intsize)
677 return -EINVAL;
678
678 /* Look for this #address-cells. We have to implement the old linux 679 /* Look for this #address-cells. We have to implement the old linux
679 * trick of looking for the parent here as some device-trees rely on it 680 * trick of looking for the parent here as some device-trees rely on it
680 */ 681 */
@@ -880,17 +881,26 @@ int of_irq_map_one(struct device_node *device, int index, struct of_irq *out_irq
880 } 881 }
881 intsize = *tmp; 882 intsize = *tmp;
882 883
884 DBG(" intsize=%d intlen=%d\n", intsize, intlen);
885
883 /* Check index */ 886 /* Check index */
884 if ((index + 1) * intsize > intlen) 887 if ((index + 1) * intsize > intlen)
885 return -EINVAL; 888 return -EINVAL;
886 889
887 /* Get new specifier and map it */ 890 /* Get new specifier and map it */
888 res = of_irq_map_raw(p, intspec + index * intsize, addr, out_irq); 891 res = of_irq_map_raw(p, intspec + index * intsize, intsize,
892 addr, out_irq);
889 of_node_put(p); 893 of_node_put(p);
890 return res; 894 return res;
891} 895}
892EXPORT_SYMBOL_GPL(of_irq_map_one); 896EXPORT_SYMBOL_GPL(of_irq_map_one);
893 897
898#ifdef CONFIG_PCI
899static u8 of_irq_pci_swizzle(u8 slot, u8 pin)
900{
901 return (((pin - 1) + slot) % 4) + 1;
902}
903
894int of_irq_map_pci(struct pci_dev *pdev, struct of_irq *out_irq) 904int of_irq_map_pci(struct pci_dev *pdev, struct of_irq *out_irq)
895{ 905{
896 struct device_node *dn, *ppnode; 906 struct device_node *dn, *ppnode;
@@ -964,7 +974,7 @@ int of_irq_map_pci(struct pci_dev *pdev, struct of_irq *out_irq)
964 laddr[0] = (pdev->bus->number << 16) 974 laddr[0] = (pdev->bus->number << 16)
965 | (pdev->devfn << 8); 975 | (pdev->devfn << 8);
966 laddr[1] = laddr[2] = 0; 976 laddr[1] = laddr[2] = 0;
967 return of_irq_map_raw(ppnode, &lspec, laddr, out_irq); 977 return of_irq_map_raw(ppnode, &lspec, 1, laddr, out_irq);
968} 978}
969EXPORT_SYMBOL_GPL(of_irq_map_pci); 979EXPORT_SYMBOL_GPL(of_irq_map_pci);
970 980#endif /* CONFIG_PCI */
diff --git a/arch/powerpc/kernel/rtas.c b/arch/powerpc/kernel/rtas.c
index 4a4cb5598402..77f1e06d208d 100644
--- a/arch/powerpc/kernel/rtas.c
+++ b/arch/powerpc/kernel/rtas.c
@@ -569,6 +569,27 @@ int rtas_set_indicator(int indicator, int index, int new_value)
569} 569}
570EXPORT_SYMBOL(rtas_set_indicator); 570EXPORT_SYMBOL(rtas_set_indicator);
571 571
572/*
573 * Ignoring RTAS extended delay
574 */
575int rtas_set_indicator_fast(int indicator, int index, int new_value)
576{
577 int rc;
578 int token = rtas_token("set-indicator");
579
580 if (token == RTAS_UNKNOWN_SERVICE)
581 return -ENOENT;
582
583 rc = rtas_call(token, 3, 1, NULL, indicator, index, new_value);
584
585 WARN_ON(rc == -2 || (rc >= 9900 && rc <= 9905));
586
587 if (rc < 0)
588 return rtas_error_rc(rc);
589
590 return rc;
591}
592
572void rtas_restart(char *cmd) 593void rtas_restart(char *cmd)
573{ 594{
574 if (rtas_flash_term_hook) 595 if (rtas_flash_term_hook)
diff --git a/arch/powerpc/kernel/smp-tbsync.c b/arch/powerpc/kernel/smp-tbsync.c
index f19e2e0e61e7..de59c6c31a5b 100644
--- a/arch/powerpc/kernel/smp-tbsync.c
+++ b/arch/powerpc/kernel/smp-tbsync.c
@@ -45,8 +45,9 @@ void __devinit smp_generic_take_timebase(void)
45{ 45{
46 int cmd; 46 int cmd;
47 u64 tb; 47 u64 tb;
48 unsigned long flags;
48 49
49 local_irq_disable(); 50 local_irq_save(flags);
50 while (!running) 51 while (!running)
51 barrier(); 52 barrier();
52 rmb(); 53 rmb();
@@ -70,7 +71,7 @@ void __devinit smp_generic_take_timebase(void)
70 set_tb(tb >> 32, tb & 0xfffffffful); 71 set_tb(tb >> 32, tb & 0xfffffffful);
71 enter_contest(tbsync->mark, -1); 72 enter_contest(tbsync->mark, -1);
72 } 73 }
73 local_irq_enable(); 74 local_irq_restore(flags);
74} 75}
75 76
76static int __devinit start_contest(int cmd, long offset, int num) 77static int __devinit start_contest(int cmd, long offset, int num)
diff --git a/arch/powerpc/kernel/time.c b/arch/powerpc/kernel/time.c
index 774c0a3c5019..a124499e65d9 100644
--- a/arch/powerpc/kernel/time.c
+++ b/arch/powerpc/kernel/time.c
@@ -125,15 +125,8 @@ static long timezone_offset;
125unsigned long ppc_proc_freq; 125unsigned long ppc_proc_freq;
126unsigned long ppc_tb_freq; 126unsigned long ppc_tb_freq;
127 127
128u64 tb_last_jiffy __cacheline_aligned_in_smp; 128static u64 tb_last_jiffy __cacheline_aligned_in_smp;
129unsigned long tb_last_stamp; 129static DEFINE_PER_CPU(u64, last_jiffy);
130
131/*
132 * Note that on ppc32 this only stores the bottom 32 bits of
133 * the timebase value, but that's enough to tell when a jiffy
134 * has passed.
135 */
136DEFINE_PER_CPU(unsigned long, last_jiffy);
137 130
138#ifdef CONFIG_VIRT_CPU_ACCOUNTING 131#ifdef CONFIG_VIRT_CPU_ACCOUNTING
139/* 132/*
@@ -417,7 +410,7 @@ static __inline__ void timer_check_rtc(void)
417/* 410/*
418 * This version of gettimeofday has microsecond resolution. 411 * This version of gettimeofday has microsecond resolution.
419 */ 412 */
420static inline void __do_gettimeofday(struct timeval *tv, u64 tb_val) 413static inline void __do_gettimeofday(struct timeval *tv)
421{ 414{
422 unsigned long sec, usec; 415 unsigned long sec, usec;
423 u64 tb_ticks, xsec; 416 u64 tb_ticks, xsec;
@@ -431,7 +424,12 @@ static inline void __do_gettimeofday(struct timeval *tv, u64 tb_val)
431 * without a divide (and in fact, without a multiply) 424 * without a divide (and in fact, without a multiply)
432 */ 425 */
433 temp_varp = do_gtod.varp; 426 temp_varp = do_gtod.varp;
434 tb_ticks = tb_val - temp_varp->tb_orig_stamp; 427
428 /* Sampling the time base must be done after loading
429 * do_gtod.varp in order to avoid racing with update_gtod.
430 */
431 data_barrier(temp_varp);
432 tb_ticks = get_tb() - temp_varp->tb_orig_stamp;
435 temp_tb_to_xs = temp_varp->tb_to_xs; 433 temp_tb_to_xs = temp_varp->tb_to_xs;
436 temp_stamp_xsec = temp_varp->stamp_xsec; 434 temp_stamp_xsec = temp_varp->stamp_xsec;
437 xsec = temp_stamp_xsec + mulhdu(tb_ticks, temp_tb_to_xs); 435 xsec = temp_stamp_xsec + mulhdu(tb_ticks, temp_tb_to_xs);
@@ -453,7 +451,7 @@ void do_gettimeofday(struct timeval *tv)
453 do { 451 do {
454 seq = read_seqbegin_irqsave(&xtime_lock, flags); 452 seq = read_seqbegin_irqsave(&xtime_lock, flags);
455 sec = xtime.tv_sec; 453 sec = xtime.tv_sec;
456 nsec = xtime.tv_nsec + tb_ticks_since(tb_last_stamp); 454 nsec = xtime.tv_nsec + tb_ticks_since(tb_last_jiffy);
457 } while (read_seqretry_irqrestore(&xtime_lock, seq, flags)); 455 } while (read_seqretry_irqrestore(&xtime_lock, seq, flags));
458 usec = nsec / 1000; 456 usec = nsec / 1000;
459 while (usec >= 1000000) { 457 while (usec >= 1000000) {
@@ -464,7 +462,7 @@ void do_gettimeofday(struct timeval *tv)
464 tv->tv_usec = usec; 462 tv->tv_usec = usec;
465 return; 463 return;
466 } 464 }
467 __do_gettimeofday(tv, get_tb()); 465 __do_gettimeofday(tv);
468} 466}
469 467
470EXPORT_SYMBOL(do_gettimeofday); 468EXPORT_SYMBOL(do_gettimeofday);
@@ -650,6 +648,7 @@ void timer_interrupt(struct pt_regs * regs)
650 int next_dec; 648 int next_dec;
651 int cpu = smp_processor_id(); 649 int cpu = smp_processor_id();
652 unsigned long ticks; 650 unsigned long ticks;
651 u64 tb_next_jiffy;
653 652
654#ifdef CONFIG_PPC32 653#ifdef CONFIG_PPC32
655 if (atomic_read(&ppc_n_lost_interrupts) != 0) 654 if (atomic_read(&ppc_n_lost_interrupts) != 0)
@@ -691,11 +690,13 @@ void timer_interrupt(struct pt_regs * regs)
691 continue; 690 continue;
692 691
693 write_seqlock(&xtime_lock); 692 write_seqlock(&xtime_lock);
694 tb_last_jiffy += tb_ticks_per_jiffy; 693 tb_next_jiffy = tb_last_jiffy + tb_ticks_per_jiffy;
695 tb_last_stamp = per_cpu(last_jiffy, cpu); 694 if (per_cpu(last_jiffy, cpu) >= tb_next_jiffy) {
696 do_timer(regs); 695 tb_last_jiffy = tb_next_jiffy;
697 timer_recalc_offset(tb_last_jiffy); 696 do_timer(regs);
698 timer_check_rtc(); 697 timer_recalc_offset(tb_last_jiffy);
698 timer_check_rtc();
699 }
699 write_sequnlock(&xtime_lock); 700 write_sequnlock(&xtime_lock);
700 } 701 }
701 702
@@ -740,7 +741,7 @@ void __init smp_space_timers(unsigned int max_cpus)
740 int i; 741 int i;
741 unsigned long half = tb_ticks_per_jiffy / 2; 742 unsigned long half = tb_ticks_per_jiffy / 2;
742 unsigned long offset = tb_ticks_per_jiffy / max_cpus; 743 unsigned long offset = tb_ticks_per_jiffy / max_cpus;
743 unsigned long previous_tb = per_cpu(last_jiffy, boot_cpuid); 744 u64 previous_tb = per_cpu(last_jiffy, boot_cpuid);
744 745
745 /* make sure tb > per_cpu(last_jiffy, cpu) for all cpus always */ 746 /* make sure tb > per_cpu(last_jiffy, cpu) for all cpus always */
746 previous_tb -= tb_ticks_per_jiffy; 747 previous_tb -= tb_ticks_per_jiffy;
@@ -821,7 +822,7 @@ int do_settimeofday(struct timespec *tv)
821 * and therefore the (jiffies - wall_jiffies) computation 822 * and therefore the (jiffies - wall_jiffies) computation
822 * has been removed. 823 * has been removed.
823 */ 824 */
824 tb_delta = tb_ticks_since(tb_last_stamp); 825 tb_delta = tb_ticks_since(tb_last_jiffy);
825 tb_delta = mulhdu(tb_delta, do_gtod.varp->tb_to_xs); /* in xsec */ 826 tb_delta = mulhdu(tb_delta, do_gtod.varp->tb_to_xs); /* in xsec */
826 new_nsec -= SCALE_XSEC(tb_delta, 1000000000); 827 new_nsec -= SCALE_XSEC(tb_delta, 1000000000);
827 828
@@ -941,8 +942,7 @@ void __init time_init(void)
941 if (__USE_RTC()) { 942 if (__USE_RTC()) {
942 /* 601 processor: dec counts down by 128 every 128ns */ 943 /* 601 processor: dec counts down by 128 every 128ns */
943 ppc_tb_freq = 1000000000; 944 ppc_tb_freq = 1000000000;
944 tb_last_stamp = get_rtcl(); 945 tb_last_jiffy = get_rtcl();
945 tb_last_jiffy = tb_last_stamp;
946 } else { 946 } else {
947 /* Normal PowerPC with timebase register */ 947 /* Normal PowerPC with timebase register */
948 ppc_md.calibrate_decr(); 948 ppc_md.calibrate_decr();
@@ -950,7 +950,7 @@ void __init time_init(void)
950 ppc_tb_freq / 1000000, ppc_tb_freq % 1000000); 950 ppc_tb_freq / 1000000, ppc_tb_freq % 1000000);
951 printk(KERN_DEBUG "time_init: processor frequency = %lu.%.6lu MHz\n", 951 printk(KERN_DEBUG "time_init: processor frequency = %lu.%.6lu MHz\n",
952 ppc_proc_freq / 1000000, ppc_proc_freq % 1000000); 952 ppc_proc_freq / 1000000, ppc_proc_freq % 1000000);
953 tb_last_stamp = tb_last_jiffy = get_tb(); 953 tb_last_jiffy = get_tb();
954 } 954 }
955 955
956 tb_ticks_per_jiffy = ppc_tb_freq / HZ; 956 tb_ticks_per_jiffy = ppc_tb_freq / HZ;
@@ -1027,7 +1027,7 @@ void __init time_init(void)
1027 do_gtod.varp = &do_gtod.vars[0]; 1027 do_gtod.varp = &do_gtod.vars[0];
1028 do_gtod.var_idx = 0; 1028 do_gtod.var_idx = 0;
1029 do_gtod.varp->tb_orig_stamp = tb_last_jiffy; 1029 do_gtod.varp->tb_orig_stamp = tb_last_jiffy;
1030 __get_cpu_var(last_jiffy) = tb_last_stamp; 1030 __get_cpu_var(last_jiffy) = tb_last_jiffy;
1031 do_gtod.varp->stamp_xsec = (u64) xtime.tv_sec * XSEC_PER_SEC; 1031 do_gtod.varp->stamp_xsec = (u64) xtime.tv_sec * XSEC_PER_SEC;
1032 do_gtod.tb_ticks_per_sec = tb_ticks_per_sec; 1032 do_gtod.tb_ticks_per_sec = tb_ticks_per_sec;
1033 do_gtod.varp->tb_to_xs = tb_to_xs; 1033 do_gtod.varp->tb_to_xs = tb_to_xs;
diff --git a/arch/powerpc/kernel/traps.c b/arch/powerpc/kernel/traps.c
index 2105767fcc57..9b352bd0a460 100644
--- a/arch/powerpc/kernel/traps.c
+++ b/arch/powerpc/kernel/traps.c
@@ -55,9 +55,6 @@
55 55
56#ifdef CONFIG_PPC64 /* XXX */ 56#ifdef CONFIG_PPC64 /* XXX */
57#define _IO_BASE pci_io_base 57#define _IO_BASE pci_io_base
58#ifdef CONFIG_KEXEC
59cpumask_t cpus_in_sr = CPU_MASK_NONE;
60#endif
61#endif 58#endif
62 59
63#ifdef CONFIG_DEBUGGER 60#ifdef CONFIG_DEBUGGER
@@ -151,7 +148,7 @@ int die(const char *str, struct pt_regs *regs, long err)
151 panic("Fatal exception in interrupt"); 148 panic("Fatal exception in interrupt");
152 149
153 if (panic_on_oops) 150 if (panic_on_oops)
154 panic("Fatal exception: panic_on_oops"); 151 panic("Fatal exception");
155 152
156 do_exit(err); 153 do_exit(err);
157 154
@@ -211,6 +208,19 @@ void system_reset_exception(struct pt_regs *regs)
211 208
212 die("System Reset", regs, SIGABRT); 209 die("System Reset", regs, SIGABRT);
213 210
211 /*
212 * Some CPUs when released from the debugger will execute this path.
213 * These CPUs entered the debugger via a soft-reset. If the CPU was
214 * hung before entering the debugger it will return to the hung
215 * state when exiting this function. This causes a problem in
216 * kdump since the hung CPU(s) will not respond to the IPI sent
217 * from kdump. To prevent the problem we call crash_kexec_secondary()
218 * here. If a kdump had not been initiated or we exit the debugger
219 * with the "exit and recover" command (x) crash_kexec_secondary()
220 * will return after 5ms and the CPU returns to its previous state.
221 */
222 crash_kexec_secondary(regs);
223
214 /* Must die if the interrupt is not recoverable */ 224 /* Must die if the interrupt is not recoverable */
215 if (!(regs->msr & MSR_RI)) 225 if (!(regs->msr & MSR_RI))
216 panic("Unrecoverable System Reset"); 226 panic("Unrecoverable System Reset");
@@ -575,14 +585,14 @@ static void parse_fpe(struct pt_regs *regs)
575#define INST_MFSPR_PVR_MASK 0xfc1fffff 585#define INST_MFSPR_PVR_MASK 0xfc1fffff
576 586
577#define INST_DCBA 0x7c0005ec 587#define INST_DCBA 0x7c0005ec
578#define INST_DCBA_MASK 0x7c0007fe 588#define INST_DCBA_MASK 0xfc0007fe
579 589
580#define INST_MCRXR 0x7c000400 590#define INST_MCRXR 0x7c000400
581#define INST_MCRXR_MASK 0x7c0007fe 591#define INST_MCRXR_MASK 0xfc0007fe
582 592
583#define INST_STRING 0x7c00042a 593#define INST_STRING 0x7c00042a
584#define INST_STRING_MASK 0x7c0007fe 594#define INST_STRING_MASK 0xfc0007fe
585#define INST_STRING_GEN_MASK 0x7c00067e 595#define INST_STRING_GEN_MASK 0xfc00067e
586#define INST_LSWI 0x7c0004aa 596#define INST_LSWI 0x7c0004aa
587#define INST_LSWX 0x7c00042a 597#define INST_LSWX 0x7c00042a
588#define INST_STSWI 0x7c0005aa 598#define INST_STSWI 0x7c0005aa
diff --git a/arch/powerpc/lib/memcpy_64.S b/arch/powerpc/lib/memcpy_64.S
index fd66acfd3e3e..7173ba98f427 100644
--- a/arch/powerpc/lib/memcpy_64.S
+++ b/arch/powerpc/lib/memcpy_64.S
@@ -11,6 +11,7 @@
11 11
12 .align 7 12 .align 7
13_GLOBAL(memcpy) 13_GLOBAL(memcpy)
14 std r3,48(r1) /* save destination pointer for return value */
14 mtcrf 0x01,r5 15 mtcrf 0x01,r5
15 cmpldi cr1,r5,16 16 cmpldi cr1,r5,16
16 neg r6,r3 # LS 3 bits = # bytes to 8-byte dest bdry 17 neg r6,r3 # LS 3 bits = # bytes to 8-byte dest bdry
@@ -38,7 +39,7 @@ _GLOBAL(memcpy)
38 stdu r9,16(r3) 39 stdu r9,16(r3)
39 bdnz 1b 40 bdnz 1b
403: std r8,8(r3) 413: std r8,8(r3)
41 beqlr 42 beq 3f
42 addi r3,r3,16 43 addi r3,r3,16
43 ld r9,8(r4) 44 ld r9,8(r4)
44.Ldo_tail: 45.Ldo_tail:
@@ -53,7 +54,8 @@ _GLOBAL(memcpy)
532: bf cr7*4+3,3f 542: bf cr7*4+3,3f
54 rotldi r9,r9,8 55 rotldi r9,r9,8
55 stb r9,0(r3) 56 stb r9,0(r3)
563: blr 573: ld r3,48(r1) /* return dest pointer */
58 blr
57 59
58.Lsrc_unaligned: 60.Lsrc_unaligned:
59 srdi r6,r5,3 61 srdi r6,r5,3
@@ -115,7 +117,7 @@ _GLOBAL(memcpy)
1155: srd r12,r9,r11 1175: srd r12,r9,r11
116 or r12,r8,r12 118 or r12,r8,r12
117 std r12,24(r3) 119 std r12,24(r3)
118 beqlr 120 beq 4f
119 cmpwi cr1,r5,8 121 cmpwi cr1,r5,8
120 addi r3,r3,32 122 addi r3,r3,32
121 sld r9,r9,r10 123 sld r9,r9,r10
@@ -167,4 +169,5 @@ _GLOBAL(memcpy)
1673: bf cr7*4+3,4f 1693: bf cr7*4+3,4f
168 lbz r0,0(r4) 170 lbz r0,0(r4)
169 stb r0,0(r3) 171 stb r0,0(r3)
1704: blr 1724: ld r3,48(r1) /* return dest pointer */
173 blr
diff --git a/arch/powerpc/mm/44x_mmu.c b/arch/powerpc/mm/44x_mmu.c
index 376829ed2211..0a0a0487b334 100644
--- a/arch/powerpc/mm/44x_mmu.c
+++ b/arch/powerpc/mm/44x_mmu.c
@@ -103,7 +103,7 @@ unsigned long __init mmu_mapin_ram(void)
103 103
104 /* Determine number of entries necessary to cover lowmem */ 104 /* Determine number of entries necessary to cover lowmem */
105 pinned_tlbs = (unsigned int) 105 pinned_tlbs = (unsigned int)
106 (_ALIGN(total_lowmem, PPC44x_PIN_SIZE) >> PPC44x_PIN_SHIFT); 106 (_ALIGN(total_lowmem, PPC_PIN_SIZE) >> PPC44x_PIN_SHIFT);
107 107
108 /* Write upper watermark to save location */ 108 /* Write upper watermark to save location */
109 tlb_44x_hwater = PPC44x_LOW_SLOT - pinned_tlbs; 109 tlb_44x_hwater = PPC44x_LOW_SLOT - pinned_tlbs;
@@ -111,7 +111,7 @@ unsigned long __init mmu_mapin_ram(void)
111 /* If necessary, set additional pinned TLBs */ 111 /* If necessary, set additional pinned TLBs */
112 if (pinned_tlbs > 1) 112 if (pinned_tlbs > 1)
113 for (i = (PPC44x_LOW_SLOT-(pinned_tlbs-1)); i < PPC44x_LOW_SLOT; i++) { 113 for (i = (PPC44x_LOW_SLOT-(pinned_tlbs-1)); i < PPC44x_LOW_SLOT; i++) {
114 unsigned int phys_addr = (PPC44x_LOW_SLOT-i) * PPC44x_PIN_SIZE; 114 unsigned int phys_addr = (PPC44x_LOW_SLOT-i) * PPC_PIN_SIZE;
115 ppc44x_pin_tlb(i, phys_addr+PAGE_OFFSET, phys_addr); 115 ppc44x_pin_tlb(i, phys_addr+PAGE_OFFSET, phys_addr);
116 } 116 }
117 117
diff --git a/arch/powerpc/mm/hugetlbpage.c b/arch/powerpc/mm/hugetlbpage.c
index 266b8b2ceac9..5615acc29527 100644
--- a/arch/powerpc/mm/hugetlbpage.c
+++ b/arch/powerpc/mm/hugetlbpage.c
@@ -153,7 +153,7 @@ static void free_hugepte_range(struct mmu_gather *tlb, hugepd_t *hpdp)
153 hpdp->pd = 0; 153 hpdp->pd = 0;
154 tlb->need_flush = 1; 154 tlb->need_flush = 1;
155 pgtable_free_tlb(tlb, pgtable_free_cache(hugepte, HUGEPTE_CACHE_NUM, 155 pgtable_free_tlb(tlb, pgtable_free_cache(hugepte, HUGEPTE_CACHE_NUM,
156 HUGEPTE_TABLE_SIZE-1)); 156 PGF_CACHENUM_MASK));
157} 157}
158 158
159#ifdef CONFIG_PPC_64K_PAGES 159#ifdef CONFIG_PPC_64K_PAGES
diff --git a/arch/powerpc/platforms/83xx/mpc834x_itx.c b/arch/powerpc/platforms/83xx/mpc834x_itx.c
index b46305645d38..cf3967a66fb5 100644
--- a/arch/powerpc/platforms/83xx/mpc834x_itx.c
+++ b/arch/powerpc/platforms/83xx/mpc834x_itx.c
@@ -46,26 +46,6 @@ unsigned long isa_io_base = 0;
46unsigned long isa_mem_base = 0; 46unsigned long isa_mem_base = 0;
47#endif 47#endif
48 48
49#ifdef CONFIG_PCI
50static int
51mpc83xx_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
52{
53 static char pci_irq_table[][4] =
54 /*
55 * PCI IDSEL/INTPIN->INTLINE
56 * A B C D
57 */
58 {
59 {PIRQB, PIRQC, PIRQD, PIRQA}, /* idsel 0x0e */
60 {PIRQA, PIRQB, PIRQC, PIRQD}, /* idsel 0x0f */
61 {PIRQC, PIRQD, PIRQA, PIRQB}, /* idsel 0x10 */
62 };
63
64 const long min_idsel = 0x0e, max_idsel = 0x10, irqs_per_slot = 4;
65 return PCI_IRQ_TABLE_LOOKUP;
66}
67#endif /* CONFIG_PCI */
68
69/* ************************************************************************ 49/* ************************************************************************
70 * 50 *
71 * Setup the architecture 51 * Setup the architecture
@@ -92,8 +72,6 @@ static void __init mpc834x_itx_setup_arch(void)
92 for (np = NULL; (np = of_find_node_by_type(np, "pci")) != NULL;) 72 for (np = NULL; (np = of_find_node_by_type(np, "pci")) != NULL;)
93 add_bridge(np); 73 add_bridge(np);
94 74
95 ppc_md.pci_swizzle = common_swizzle;
96 ppc_md.pci_map_irq = mpc83xx_map_irq;
97 ppc_md.pci_exclude_device = mpc83xx_exclude_device; 75 ppc_md.pci_exclude_device = mpc83xx_exclude_device;
98#endif 76#endif
99 77
@@ -106,25 +84,13 @@ static void __init mpc834x_itx_setup_arch(void)
106 84
107void __init mpc834x_itx_init_IRQ(void) 85void __init mpc834x_itx_init_IRQ(void)
108{ 86{
109 u8 senses[8] = { 87 struct device_node *np;
110 0, /* EXT 0 */ 88
111 IRQ_SENSE_LEVEL, /* EXT 1 */ 89 np = of_find_node_by_type(NULL, "ipic");
112 IRQ_SENSE_LEVEL, /* EXT 2 */ 90 if (!np)
113 0, /* EXT 3 */ 91 return;
114#ifdef CONFIG_PCI
115 IRQ_SENSE_LEVEL, /* EXT 4 */
116 IRQ_SENSE_LEVEL, /* EXT 5 */
117 IRQ_SENSE_LEVEL, /* EXT 6 */
118 IRQ_SENSE_LEVEL, /* EXT 7 */
119#else
120 0, /* EXT 4 */
121 0, /* EXT 5 */
122 0, /* EXT 6 */
123 0, /* EXT 7 */
124#endif
125 };
126 92
127 ipic_init(get_immrbase() + 0x00700, 0, 0, senses, 8); 93 ipic_init(np, 0);
128 94
129 /* Initialize the default interrupt mapping priorities, 95 /* Initialize the default interrupt mapping priorities,
130 * in case the boot rom changed something on us. 96 * in case the boot rom changed something on us.
@@ -153,4 +119,7 @@ define_machine(mpc834x_itx) {
153 .time_init = mpc83xx_time_init, 119 .time_init = mpc83xx_time_init,
154 .calibrate_decr = generic_calibrate_decr, 120 .calibrate_decr = generic_calibrate_decr,
155 .progress = udbg_progress, 121 .progress = udbg_progress,
122#ifdef CONFIG_PCI
123 .pcibios_fixup = mpc83xx_pcibios_fixup,
124#endif
156}; 125};
diff --git a/arch/powerpc/platforms/83xx/mpc834x_sys.c b/arch/powerpc/platforms/83xx/mpc834x_sys.c
index 3e1c16eb4a63..32df239d1c48 100644
--- a/arch/powerpc/platforms/83xx/mpc834x_sys.c
+++ b/arch/powerpc/platforms/83xx/mpc834x_sys.c
@@ -43,33 +43,6 @@ unsigned long isa_io_base = 0;
43unsigned long isa_mem_base = 0; 43unsigned long isa_mem_base = 0;
44#endif 44#endif
45 45
46#ifdef CONFIG_PCI
47static int
48mpc83xx_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
49{
50 static char pci_irq_table[][4] =
51 /*
52 * PCI IDSEL/INTPIN->INTLINE
53 * A B C D
54 */
55 {
56 {PIRQA, PIRQB, PIRQC, PIRQD}, /* idsel 0x11 */
57 {PIRQC, PIRQD, PIRQA, PIRQB}, /* idsel 0x12 */
58 {PIRQD, PIRQA, PIRQB, PIRQC}, /* idsel 0x13 */
59 {0, 0, 0, 0},
60 {PIRQA, PIRQB, PIRQC, PIRQD}, /* idsel 0x15 */
61 {PIRQD, PIRQA, PIRQB, PIRQC}, /* idsel 0x16 */
62 {PIRQC, PIRQD, PIRQA, PIRQB}, /* idsel 0x17 */
63 {PIRQB, PIRQC, PIRQD, PIRQA}, /* idsel 0x18 */
64 {0, 0, 0, 0}, /* idsel 0x19 */
65 {0, 0, 0, 0}, /* idsel 0x20 */
66 };
67
68 const long min_idsel = 0x11, max_idsel = 0x20, irqs_per_slot = 4;
69 return PCI_IRQ_TABLE_LOOKUP;
70}
71#endif /* CONFIG_PCI */
72
73/* ************************************************************************ 46/* ************************************************************************
74 * 47 *
75 * Setup the architecture 48 * Setup the architecture
@@ -96,8 +69,6 @@ static void __init mpc834x_sys_setup_arch(void)
96 for (np = NULL; (np = of_find_node_by_type(np, "pci")) != NULL;) 69 for (np = NULL; (np = of_find_node_by_type(np, "pci")) != NULL;)
97 add_bridge(np); 70 add_bridge(np);
98 71
99 ppc_md.pci_swizzle = common_swizzle;
100 ppc_md.pci_map_irq = mpc83xx_map_irq;
101 ppc_md.pci_exclude_device = mpc83xx_exclude_device; 72 ppc_md.pci_exclude_device = mpc83xx_exclude_device;
102#endif 73#endif
103 74
@@ -110,25 +81,13 @@ static void __init mpc834x_sys_setup_arch(void)
110 81
111void __init mpc834x_sys_init_IRQ(void) 82void __init mpc834x_sys_init_IRQ(void)
112{ 83{
113 u8 senses[8] = { 84 struct device_node *np;
114 0, /* EXT 0 */ 85
115 IRQ_SENSE_LEVEL, /* EXT 1 */ 86 np = of_find_node_by_type(NULL, "ipic");
116 IRQ_SENSE_LEVEL, /* EXT 2 */ 87 if (!np)
117 0, /* EXT 3 */ 88 return;
118#ifdef CONFIG_PCI
119 IRQ_SENSE_LEVEL, /* EXT 4 */
120 IRQ_SENSE_LEVEL, /* EXT 5 */
121 IRQ_SENSE_LEVEL, /* EXT 6 */
122 IRQ_SENSE_LEVEL, /* EXT 7 */
123#else
124 0, /* EXT 4 */
125 0, /* EXT 5 */
126 0, /* EXT 6 */
127 0, /* EXT 7 */
128#endif
129 };
130 89
131 ipic_init(get_immrbase() + 0x00700, 0, 0, senses, 8); 90 ipic_init(np, 0);
132 91
133 /* Initialize the default interrupt mapping priorities, 92 /* Initialize the default interrupt mapping priorities,
134 * in case the boot rom changed something on us. 93 * in case the boot rom changed something on us.
@@ -178,4 +137,7 @@ define_machine(mpc834x_sys) {
178 .time_init = mpc83xx_time_init, 137 .time_init = mpc83xx_time_init,
179 .calibrate_decr = generic_calibrate_decr, 138 .calibrate_decr = generic_calibrate_decr,
180 .progress = udbg_progress, 139 .progress = udbg_progress,
140#ifdef CONFIG_PCI
141 .pcibios_fixup = mpc83xx_pcibios_fixup,
142#endif
181}; 143};
diff --git a/arch/powerpc/platforms/83xx/mpc83xx.h b/arch/powerpc/platforms/83xx/mpc83xx.h
index 01cae106912b..2c82bca9bfbb 100644
--- a/arch/powerpc/platforms/83xx/mpc83xx.h
+++ b/arch/powerpc/platforms/83xx/mpc83xx.h
@@ -11,6 +11,7 @@
11 11
12extern int add_bridge(struct device_node *dev); 12extern int add_bridge(struct device_node *dev);
13extern int mpc83xx_exclude_device(u_char bus, u_char devfn); 13extern int mpc83xx_exclude_device(u_char bus, u_char devfn);
14extern void mpc83xx_pcibios_fixup(void);
14extern void mpc83xx_restart(char *cmd); 15extern void mpc83xx_restart(char *cmd);
15extern long mpc83xx_time_init(void); 16extern long mpc83xx_time_init(void);
16 17
diff --git a/arch/powerpc/platforms/83xx/pci.c b/arch/powerpc/platforms/83xx/pci.c
index 3b5e563c279f..5d84a9ccd103 100644
--- a/arch/powerpc/platforms/83xx/pci.c
+++ b/arch/powerpc/platforms/83xx/pci.c
@@ -45,6 +45,15 @@ int mpc83xx_exclude_device(u_char bus, u_char devfn)
45 return PCIBIOS_SUCCESSFUL; 45 return PCIBIOS_SUCCESSFUL;
46} 46}
47 47
48void __init mpc83xx_pcibios_fixup(void)
49{
50 struct pci_dev *dev = NULL;
51
52 /* map all the PCI irqs */
53 for_each_pci_dev(dev)
54 pci_read_irq_line(dev);
55}
56
48int __init add_bridge(struct device_node *dev) 57int __init add_bridge(struct device_node *dev)
49{ 58{
50 int len; 59 int len;
diff --git a/arch/powerpc/platforms/85xx/Kconfig b/arch/powerpc/platforms/85xx/Kconfig
index 454fc53289ab..c3268d9877e4 100644
--- a/arch/powerpc/platforms/85xx/Kconfig
+++ b/arch/powerpc/platforms/85xx/Kconfig
@@ -14,7 +14,6 @@ config MPC8540_ADS
14config MPC85xx_CDS 14config MPC85xx_CDS
15 bool "Freescale MPC85xx CDS" 15 bool "Freescale MPC85xx CDS"
16 select DEFAULT_UIMAGE 16 select DEFAULT_UIMAGE
17 select PPC_I8259 if PCI
18 help 17 help
19 This option enables support for the MPC85xx CDS board 18 This option enables support for the MPC85xx CDS board
20 19
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_ads.c b/arch/powerpc/platforms/85xx/mpc85xx_ads.c
index 06a497676c99..9d2acfbbeccd 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_ads.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_ads.c
@@ -37,79 +37,7 @@ unsigned long isa_io_base = 0;
37unsigned long isa_mem_base = 0; 37unsigned long isa_mem_base = 0;
38#endif 38#endif
39 39
40/*
41 * Internal interrupts are all Level Sensitive, and Positive Polarity
42 *
43 * Note: Likely, this table and the following function should be
44 * obtained and derived from the OF Device Tree.
45 */
46static u_char mpc85xx_ads_openpic_initsenses[] __initdata = {
47 MPC85XX_INTERNAL_IRQ_SENSES,
48 0x0, /* External 0: */
49#if defined(CONFIG_PCI)
50 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext 1: PCI slot 0 */
51 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext 2: PCI slot 1 */
52 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext 3: PCI slot 2 */
53 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext 4: PCI slot 3 */
54#else
55 0x0, /* External 1: */
56 0x0, /* External 2: */
57 0x0, /* External 3: */
58 0x0, /* External 4: */
59#endif
60 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 5: PHY */
61 0x0, /* External 6: */
62 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 7: PHY */
63 0x0, /* External 8: */
64 0x0, /* External 9: */
65 0x0, /* External 10: */
66 0x0, /* External 11: */
67};
68
69#ifdef CONFIG_PCI 40#ifdef CONFIG_PCI
70/*
71 * interrupt routing
72 */
73
74int
75mpc85xx_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
76{
77 static char pci_irq_table[][4] =
78 /*
79 * This is little evil, but works around the fact
80 * that revA boards have IDSEL starting at 18
81 * and others boards (older) start at 12
82 *
83 * PCI IDSEL/INTPIN->INTLINE
84 * A B C D
85 */
86 {
87 {PIRQA, PIRQB, PIRQC, PIRQD}, /* IDSEL 2 */
88 {PIRQD, PIRQA, PIRQB, PIRQC},
89 {PIRQC, PIRQD, PIRQA, PIRQB},
90 {PIRQB, PIRQC, PIRQD, PIRQA}, /* IDSEL 5 */
91 {0, 0, 0, 0}, /* -- */
92 {0, 0, 0, 0}, /* -- */
93 {0, 0, 0, 0}, /* -- */
94 {0, 0, 0, 0}, /* -- */
95 {0, 0, 0, 0}, /* -- */
96 {0, 0, 0, 0}, /* -- */
97 {PIRQA, PIRQB, PIRQC, PIRQD}, /* IDSEL 12 */
98 {PIRQD, PIRQA, PIRQB, PIRQC},
99 {PIRQC, PIRQD, PIRQA, PIRQB},
100 {PIRQB, PIRQC, PIRQD, PIRQA}, /* IDSEL 15 */
101 {0, 0, 0, 0}, /* -- */
102 {0, 0, 0, 0}, /* -- */
103 {PIRQA, PIRQB, PIRQC, PIRQD}, /* IDSEL 18 */
104 {PIRQD, PIRQA, PIRQB, PIRQC},
105 {PIRQC, PIRQD, PIRQA, PIRQB},
106 {PIRQB, PIRQC, PIRQD, PIRQA}, /* IDSEL 21 */
107 };
108
109 const long min_idsel = 2, max_idsel = 21, irqs_per_slot = 4;
110 return PCI_IRQ_TABLE_LOOKUP;
111}
112
113int 41int
114mpc85xx_exclude_device(u_char bus, u_char devfn) 42mpc85xx_exclude_device(u_char bus, u_char devfn)
115{ 43{
@@ -119,44 +47,63 @@ mpc85xx_exclude_device(u_char bus, u_char devfn)
119 return PCIBIOS_SUCCESSFUL; 47 return PCIBIOS_SUCCESSFUL;
120} 48}
121 49
50void __init
51mpc85xx_pcibios_fixup(void)
52{
53 struct pci_dev *dev = NULL;
54
55 for_each_pci_dev(dev)
56 pci_read_irq_line(dev);
57}
122#endif /* CONFIG_PCI */ 58#endif /* CONFIG_PCI */
123 59
124 60
125void __init mpc85xx_ads_pic_init(void) 61void __init mpc85xx_ads_pic_init(void)
126{ 62{
127 struct mpic *mpic1; 63 struct mpic *mpic;
128 phys_addr_t OpenPIC_PAddr; 64 struct resource r;
129 65 struct device_node *np = NULL;
130 /* Determine the Physical Address of the OpenPIC regs */ 66
131 OpenPIC_PAddr = get_immrbase() + MPC85xx_OPENPIC_OFFSET; 67 np = of_find_node_by_type(np, "open-pic");
132 68
133 mpic1 = mpic_alloc(OpenPIC_PAddr, 69 if (np == NULL) {
134 MPIC_PRIMARY | MPIC_WANTS_RESET | MPIC_BIG_ENDIAN, 70 printk(KERN_ERR "Could not find open-pic node\n");
135 4, MPC85xx_OPENPIC_IRQ_OFFSET, 0, 250, 71 return;
136 mpc85xx_ads_openpic_initsenses, 72 }
137 sizeof(mpc85xx_ads_openpic_initsenses), 73
138 " OpenPIC "); 74 if(of_address_to_resource(np, 0, &r)) {
139 BUG_ON(mpic1 == NULL); 75 printk(KERN_ERR "Could not map mpic register space\n");
140 mpic_assign_isu(mpic1, 0, OpenPIC_PAddr + 0x10200); 76 of_node_put(np);
141 mpic_assign_isu(mpic1, 1, OpenPIC_PAddr + 0x10280); 77 return;
142 mpic_assign_isu(mpic1, 2, OpenPIC_PAddr + 0x10300); 78 }
143 mpic_assign_isu(mpic1, 3, OpenPIC_PAddr + 0x10380); 79
144 mpic_assign_isu(mpic1, 4, OpenPIC_PAddr + 0x10400); 80 mpic = mpic_alloc(np, r.start,
145 mpic_assign_isu(mpic1, 5, OpenPIC_PAddr + 0x10480); 81 MPIC_PRIMARY | MPIC_WANTS_RESET | MPIC_BIG_ENDIAN,
146 mpic_assign_isu(mpic1, 6, OpenPIC_PAddr + 0x10500); 82 4, 0, " OpenPIC ");
147 mpic_assign_isu(mpic1, 7, OpenPIC_PAddr + 0x10580); 83 BUG_ON(mpic == NULL);
148 84 of_node_put(np);
149 /* dummy mappings to get to 48 */ 85
150 mpic_assign_isu(mpic1, 8, OpenPIC_PAddr + 0x10600); 86 mpic_assign_isu(mpic, 0, r.start + 0x10200);
151 mpic_assign_isu(mpic1, 9, OpenPIC_PAddr + 0x10680); 87 mpic_assign_isu(mpic, 1, r.start + 0x10280);
152 mpic_assign_isu(mpic1, 10, OpenPIC_PAddr + 0x10700); 88 mpic_assign_isu(mpic, 2, r.start + 0x10300);
153 mpic_assign_isu(mpic1, 11, OpenPIC_PAddr + 0x10780); 89 mpic_assign_isu(mpic, 3, r.start + 0x10380);
154 90 mpic_assign_isu(mpic, 4, r.start + 0x10400);
155 /* External ints */ 91 mpic_assign_isu(mpic, 5, r.start + 0x10480);
156 mpic_assign_isu(mpic1, 12, OpenPIC_PAddr + 0x10000); 92 mpic_assign_isu(mpic, 6, r.start + 0x10500);
157 mpic_assign_isu(mpic1, 13, OpenPIC_PAddr + 0x10080); 93 mpic_assign_isu(mpic, 7, r.start + 0x10580);
158 mpic_assign_isu(mpic1, 14, OpenPIC_PAddr + 0x10100); 94
159 mpic_init(mpic1); 95 /* Unused on this platform (leave room for 8548) */
96 mpic_assign_isu(mpic, 8, r.start + 0x10600);
97 mpic_assign_isu(mpic, 9, r.start + 0x10680);
98 mpic_assign_isu(mpic, 10, r.start + 0x10700);
99 mpic_assign_isu(mpic, 11, r.start + 0x10780);
100
101 /* External Interrupts */
102 mpic_assign_isu(mpic, 12, r.start + 0x10000);
103 mpic_assign_isu(mpic, 13, r.start + 0x10080);
104 mpic_assign_isu(mpic, 14, r.start + 0x10100);
105
106 mpic_init(mpic);
160} 107}
161 108
162/* 109/*
@@ -165,7 +112,9 @@ void __init mpc85xx_ads_pic_init(void)
165static void __init mpc85xx_ads_setup_arch(void) 112static void __init mpc85xx_ads_setup_arch(void)
166{ 113{
167 struct device_node *cpu; 114 struct device_node *cpu;
115#ifdef CONFIG_PCI
168 struct device_node *np; 116 struct device_node *np;
117#endif
169 118
170 if (ppc_md.progress) 119 if (ppc_md.progress)
171 ppc_md.progress("mpc85xx_ads_setup_arch()", 0); 120 ppc_md.progress("mpc85xx_ads_setup_arch()", 0);
@@ -186,8 +135,7 @@ static void __init mpc85xx_ads_setup_arch(void)
186 for (np = NULL; (np = of_find_node_by_type(np, "pci")) != NULL;) 135 for (np = NULL; (np = of_find_node_by_type(np, "pci")) != NULL;)
187 add_bridge(np); 136 add_bridge(np);
188 137
189 ppc_md.pci_swizzle = common_swizzle; 138 ppc_md.pcibios_fixup = mpc85xx_pcibios_fixup;
190 ppc_md.pci_map_irq = mpc85xx_map_irq;
191 ppc_md.pci_exclude_device = mpc85xx_exclude_device; 139 ppc_md.pci_exclude_device = mpc85xx_exclude_device;
192#endif 140#endif
193 141
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_cds.c b/arch/powerpc/platforms/85xx/mpc85xx_cds.c
index 18e6e11f7020..1d357d32a29f 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_cds.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_cds.c
@@ -57,94 +57,8 @@ unsigned long isa_mem_base = 0;
57static int cds_pci_slot = 2; 57static int cds_pci_slot = 2;
58static volatile u8 *cadmus; 58static volatile u8 *cadmus;
59 59
60/*
61 * Internal interrupts are all Level Sensitive, and Positive Polarity
62 *
63 * Note: Likely, this table and the following function should be
64 * obtained and derived from the OF Device Tree.
65 */
66static u_char mpc85xx_cds_openpic_initsenses[] __initdata = {
67 MPC85XX_INTERNAL_IRQ_SENSES,
68#if defined(CONFIG_PCI)
69 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Ext 0: PCI slot 0 */
70 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext 1: PCI slot 1 */
71 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext 2: PCI slot 2 */
72 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext 3: PCI slot 3 */
73#else
74 0x0, /* External 0: */
75 0x0, /* External 1: */
76 0x0, /* External 2: */
77 0x0, /* External 3: */
78#endif
79 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 5: PHY */
80 0x0, /* External 6: */
81 0x0, /* External 7: */
82 0x0, /* External 8: */
83 0x0, /* External 9: */
84 0x0, /* External 10: */
85#ifdef CONFIG_PCI
86 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext 11: PCI2 slot 0 */
87#else
88 0x0, /* External 11: */
89#endif
90};
91
92 60
93#ifdef CONFIG_PCI 61#ifdef CONFIG_PCI
94/*
95 * interrupt routing
96 */
97int
98mpc85xx_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
99{
100 struct pci_controller *hose = pci_bus_to_hose(dev->bus->number);
101
102 if (!hose->index)
103 {
104 /* Handle PCI1 interrupts */
105 char pci_irq_table[][4] =
106 /*
107 * PCI IDSEL/INTPIN->INTLINE
108 * A B C D
109 */
110
111 /* Note IRQ assignment for slots is based on which slot the elysium is
112 * in -- in this setup elysium is in slot #2 (this PIRQA as first
113 * interrupt on slot */
114 {
115 { 0, 1, 2, 3 }, /* 16 - PMC */
116 { 0, 1, 2, 3 }, /* 17 P2P (Tsi320) */
117 { 0, 1, 2, 3 }, /* 18 - Slot 1 */
118 { 1, 2, 3, 0 }, /* 19 - Slot 2 */
119 { 2, 3, 0, 1 }, /* 20 - Slot 3 */
120 { 3, 0, 1, 2 }, /* 21 - Slot 4 */
121 };
122
123 const long min_idsel = 16, max_idsel = 21, irqs_per_slot = 4;
124 int i, j;
125
126 for (i = 0; i < 6; i++)
127 for (j = 0; j < 4; j++)
128 pci_irq_table[i][j] =
129 ((pci_irq_table[i][j] + 5 -
130 cds_pci_slot) & 0x3) + PIRQ0A;
131
132 return PCI_IRQ_TABLE_LOOKUP;
133 } else {
134 /* Handle PCI2 interrupts (if we have one) */
135 char pci_irq_table[][4] =
136 {
137 /*
138 * We only have one slot and one interrupt
139 * going to PIRQA - PIRQD */
140 { PIRQ1A, PIRQ1A, PIRQ1A, PIRQ1A }, /* 21 - slot 0 */
141 };
142
143 const long min_idsel = 21, max_idsel = 21, irqs_per_slot = 4;
144
145 return PCI_IRQ_TABLE_LOOKUP;
146 }
147}
148 62
149#define ARCADIA_HOST_BRIDGE_IDSEL 17 63#define ARCADIA_HOST_BRIDGE_IDSEL 17
150#define ARCADIA_2ND_BRIDGE_IDSEL 3 64#define ARCADIA_2ND_BRIDGE_IDSEL 3
@@ -210,50 +124,104 @@ mpc85xx_cds_pcibios_fixup(void)
210 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, 11); 124 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, 11);
211 pci_dev_put(dev); 125 pci_dev_put(dev);
212 } 126 }
127
128 /* Now map all the PCI irqs */
129 dev = NULL;
130 for_each_pci_dev(dev)
131 pci_read_irq_line(dev);
132}
133
134#ifdef CONFIG_PPC_I8259
135#warning The i8259 PIC support is currently broken
136static void mpc85xx_8259_cascade(unsigned int irq, struct
137 irq_desc *desc, struct pt_regs *regs)
138{
139 unsigned int cascade_irq = i8259_irq(regs);
140
141 if (cascade_irq != NO_IRQ)
142 generic_handle_irq(cascade_irq, regs);
143
144 desc->chip->eoi(irq);
213} 145}
146#endif /* PPC_I8259 */
214#endif /* CONFIG_PCI */ 147#endif /* CONFIG_PCI */
215 148
216void __init mpc85xx_cds_pic_init(void) 149void __init mpc85xx_cds_pic_init(void)
217{ 150{
218 struct mpic *mpic1; 151 struct mpic *mpic;
219 phys_addr_t OpenPIC_PAddr; 152 struct resource r;
153 struct device_node *np = NULL;
154 struct device_node *cascade_node = NULL;
155 int cascade_irq;
220 156
221 /* Determine the Physical Address of the OpenPIC regs */ 157 np = of_find_node_by_type(np, "open-pic");
222 OpenPIC_PAddr = get_immrbase() + MPC85xx_OPENPIC_OFFSET; 158
159 if (np == NULL) {
160 printk(KERN_ERR "Could not find open-pic node\n");
161 return;
162 }
223 163
224 mpic1 = mpic_alloc(OpenPIC_PAddr, 164 if (of_address_to_resource(np, 0, &r)) {
165 printk(KERN_ERR "Failed to map mpic register space\n");
166 of_node_put(np);
167 return;
168 }
169
170 mpic = mpic_alloc(np, r.start,
225 MPIC_PRIMARY | MPIC_WANTS_RESET | MPIC_BIG_ENDIAN, 171 MPIC_PRIMARY | MPIC_WANTS_RESET | MPIC_BIG_ENDIAN,
226 4, MPC85xx_OPENPIC_IRQ_OFFSET, 0, 250, 172 4, 0, " OpenPIC ");
227 mpc85xx_cds_openpic_initsenses, 173 BUG_ON(mpic == NULL);
228 sizeof(mpc85xx_cds_openpic_initsenses), " OpenPIC "); 174
229 BUG_ON(mpic1 == NULL); 175 /* Return the mpic node */
230 mpic_assign_isu(mpic1, 0, OpenPIC_PAddr + 0x10200); 176 of_node_put(np);
231 mpic_assign_isu(mpic1, 1, OpenPIC_PAddr + 0x10280); 177
232 mpic_assign_isu(mpic1, 2, OpenPIC_PAddr + 0x10300); 178 mpic_assign_isu(mpic, 0, r.start + 0x10200);
233 mpic_assign_isu(mpic1, 3, OpenPIC_PAddr + 0x10380); 179 mpic_assign_isu(mpic, 1, r.start + 0x10280);
234 mpic_assign_isu(mpic1, 4, OpenPIC_PAddr + 0x10400); 180 mpic_assign_isu(mpic, 2, r.start + 0x10300);
235 mpic_assign_isu(mpic1, 5, OpenPIC_PAddr + 0x10480); 181 mpic_assign_isu(mpic, 3, r.start + 0x10380);
236 mpic_assign_isu(mpic1, 6, OpenPIC_PAddr + 0x10500); 182 mpic_assign_isu(mpic, 4, r.start + 0x10400);
237 mpic_assign_isu(mpic1, 7, OpenPIC_PAddr + 0x10580); 183 mpic_assign_isu(mpic, 5, r.start + 0x10480);
238 184 mpic_assign_isu(mpic, 6, r.start + 0x10500);
239 /* dummy mappings to get to 48 */ 185 mpic_assign_isu(mpic, 7, r.start + 0x10580);
240 mpic_assign_isu(mpic1, 8, OpenPIC_PAddr + 0x10600); 186
241 mpic_assign_isu(mpic1, 9, OpenPIC_PAddr + 0x10680); 187 /* Used only for 8548 so far, but no harm in
242 mpic_assign_isu(mpic1, 10, OpenPIC_PAddr + 0x10700); 188 * allocating them for everyone */
243 mpic_assign_isu(mpic1, 11, OpenPIC_PAddr + 0x10780); 189 mpic_assign_isu(mpic, 8, r.start + 0x10600);
244 190 mpic_assign_isu(mpic, 9, r.start + 0x10680);
245 /* External ints */ 191 mpic_assign_isu(mpic, 10, r.start + 0x10700);
246 mpic_assign_isu(mpic1, 12, OpenPIC_PAddr + 0x10000); 192 mpic_assign_isu(mpic, 11, r.start + 0x10780);
247 mpic_assign_isu(mpic1, 13, OpenPIC_PAddr + 0x10080); 193
248 mpic_assign_isu(mpic1, 14, OpenPIC_PAddr + 0x10100); 194 /* External Interrupts */
249 195 mpic_assign_isu(mpic, 12, r.start + 0x10000);
250 mpic_init(mpic1); 196 mpic_assign_isu(mpic, 13, r.start + 0x10080);
197 mpic_assign_isu(mpic, 14, r.start + 0x10100);
198
199 mpic_init(mpic);
200
201#ifdef CONFIG_PPC_I8259
202 /* Initialize the i8259 controller */
203 for_each_node_by_type(np, "interrupt-controller")
204 if (device_is_compatible(np, "chrp,iic")) {
205 cascade_node = np;
206 break;
207 }
208
209 if (cascade_node == NULL) {
210 printk(KERN_DEBUG "Could not find i8259 PIC\n");
211 return;
212 }
251 213
252#ifdef CONFIG_PCI 214 cascade_irq = irq_of_parse_and_map(cascade_node, 0);
253 mpic_setup_cascade(PIRQ0A, i8259_irq_cascade, NULL); 215 if (cascade_irq == NO_IRQ) {
216 printk(KERN_ERR "Failed to map cascade interrupt\n");
217 return;
218 }
254 219
255 i8259_init(0,0); 220 i8259_init(cascade_node, 0);
256#endif 221 of_node_put(cascade_node);
222
223 set_irq_chained_handler(cascade_irq, mpc85xx_8259_cascade);
224#endif /* CONFIG_PPC_I8259 */
257} 225}
258 226
259 227
@@ -298,8 +266,6 @@ mpc85xx_cds_setup_arch(void)
298 add_bridge(np); 266 add_bridge(np);
299 267
300 ppc_md.pcibios_fixup = mpc85xx_cds_pcibios_fixup; 268 ppc_md.pcibios_fixup = mpc85xx_cds_pcibios_fixup;
301 ppc_md.pci_swizzle = common_swizzle;
302 ppc_md.pci_map_irq = mpc85xx_map_irq;
303 ppc_md.pci_exclude_device = mpc85xx_exclude_device; 269 ppc_md.pci_exclude_device = mpc85xx_exclude_device;
304#endif 270#endif
305 271
diff --git a/arch/powerpc/platforms/86xx/mpc8641_hpcn.h b/arch/powerpc/platforms/86xx/mpc8641_hpcn.h
index 5d2bcf78cef7..41e554c4af94 100644
--- a/arch/powerpc/platforms/86xx/mpc8641_hpcn.h
+++ b/arch/powerpc/platforms/86xx/mpc8641_hpcn.h
@@ -16,38 +16,6 @@
16 16
17#include <linux/init.h> 17#include <linux/init.h>
18 18
19/* PCI interrupt controller */
20#define PIRQA 3
21#define PIRQB 4
22#define PIRQC 5
23#define PIRQD 6
24#define PIRQ7 7
25#define PIRQE 9
26#define PIRQF 10
27#define PIRQG 11
28#define PIRQH 12
29
30/* PCI-Express memory map */
31#define MPC86XX_PCIE_LOWER_IO 0x00000000
32#define MPC86XX_PCIE_UPPER_IO 0x00ffffff
33
34#define MPC86XX_PCIE_LOWER_MEM 0x80000000
35#define MPC86XX_PCIE_UPPER_MEM 0x9fffffff
36
37#define MPC86XX_PCIE_IO_BASE 0xe2000000
38#define MPC86XX_PCIE_MEM_OFFSET 0x00000000
39
40#define MPC86XX_PCIE_IO_SIZE 0x01000000
41
42#define PCIE1_CFG_ADDR_OFFSET (0x8000)
43#define PCIE1_CFG_DATA_OFFSET (0x8004)
44
45#define PCIE2_CFG_ADDR_OFFSET (0x9000)
46#define PCIE2_CFG_DATA_OFFSET (0x9004)
47
48#define MPC86xx_PCIE_OFFSET PCIE1_CFG_ADDR_OFFSET
49#define MPC86xx_PCIE_SIZE (0x1000)
50
51#define MPC86XX_RSTCR_OFFSET (0xe00b0) /* Reset Control Register */ 19#define MPC86XX_RSTCR_OFFSET (0xe00b0) /* Reset Control Register */
52 20
53#endif /* __MPC8641_HPCN_H__ */ 21#endif /* __MPC8641_HPCN_H__ */
diff --git a/arch/powerpc/platforms/86xx/mpc86xx_hpcn.c b/arch/powerpc/platforms/86xx/mpc86xx_hpcn.c
index ebae73eb0063..0b1b52168bb7 100644
--- a/arch/powerpc/platforms/86xx/mpc86xx_hpcn.c
+++ b/arch/powerpc/platforms/86xx/mpc86xx_hpcn.c
@@ -37,6 +37,14 @@
37#include "mpc86xx.h" 37#include "mpc86xx.h"
38#include "mpc8641_hpcn.h" 38#include "mpc8641_hpcn.h"
39 39
40#undef DEBUG
41
42#ifdef DEBUG
43#define DBG(fmt...) do { printk(KERN_ERR fmt); } while(0)
44#else
45#define DBG(fmt...) do { } while(0)
46#endif
47
40#ifndef CONFIG_PCI 48#ifndef CONFIG_PCI
41unsigned long isa_io_base = 0; 49unsigned long isa_io_base = 0;
42unsigned long isa_mem_base = 0; 50unsigned long isa_mem_base = 0;
@@ -44,205 +52,219 @@ unsigned long pci_dram_offset = 0;
44#endif 52#endif
45 53
46 54
47/* 55#ifdef CONFIG_PCI
48 * Internal interrupts are all Level Sensitive, and Positive Polarity 56static void mpc86xx_8259_cascade(unsigned int irq, struct irq_desc *desc,
49 */ 57 struct pt_regs *regs)
50 58{
51static u_char mpc86xx_hpcn_openpic_initsenses[] __initdata = { 59 unsigned int cascade_irq = i8259_irq(regs);
52 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 0: Reserved */ 60 if (cascade_irq != NO_IRQ)
53 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 1: MCM */ 61 generic_handle_irq(cascade_irq, regs);
54 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 2: DDR DRAM */ 62 desc->chip->eoi(irq);
55 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 3: LBIU */ 63}
56 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 4: DMA 0 */ 64#endif /* CONFIG_PCI */
57 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 5: DMA 1 */
58 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 6: DMA 2 */
59 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 7: DMA 3 */
60 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 8: PCIE1 */
61 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 9: PCIE2 */
62 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 10: Reserved */
63 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 11: Reserved */
64 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 12: DUART2 */
65 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 13: TSEC 1 Transmit */
66 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 14: TSEC 1 Receive */
67 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 15: TSEC 3 transmit */
68 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 16: TSEC 3 receive */
69 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 17: TSEC 3 error */
70 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 18: TSEC 1 Receive/Transmit Error */
71 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 19: TSEC 2 Transmit */
72 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 20: TSEC 2 Receive */
73 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 21: TSEC 4 transmit */
74 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 22: TSEC 4 receive */
75 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 23: TSEC 4 error */
76 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 24: TSEC 2 Receive/Transmit Error */
77 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 25: Unused */
78 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 26: DUART1 */
79 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 27: I2C */
80 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 28: Performance Monitor */
81 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 29: Unused */
82 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 30: Unused */
83 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 31: Unused */
84 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 32: SRIO error/write-port unit */
85 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 33: SRIO outbound doorbell */
86 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 34: SRIO inbound doorbell */
87 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 35: Unused */
88 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 36: Unused */
89 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 37: SRIO outbound message unit 1 */
90 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 38: SRIO inbound message unit 1 */
91 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 39: SRIO outbound message unit 2 */
92 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 40: SRIO inbound message unit 2 */
93 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 41: Unused */
94 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 42: Unused */
95 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 43: Unused */
96 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 44: Unused */
97 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 45: Unused */
98 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 46: Unused */
99 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 47: Unused */
100 0x0, /* External 0: */
101 0x0, /* External 1: */
102 0x0, /* External 2: */
103 0x0, /* External 3: */
104 0x0, /* External 4: */
105 0x0, /* External 5: */
106 0x0, /* External 6: */
107 0x0, /* External 7: */
108 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 8: Pixis FPGA */
109 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* External 9: ULI 8259 INTR Cascade */
110 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 10: Quad ETH PHY */
111 0x0, /* External 11: */
112 0x0,
113 0x0,
114 0x0,
115 0x0,
116};
117
118 65
119void __init 66void __init
120mpc86xx_hpcn_init_irq(void) 67mpc86xx_hpcn_init_irq(void)
121{ 68{
122 struct mpic *mpic1; 69 struct mpic *mpic1;
123 phys_addr_t openpic_paddr; 70 struct device_node *np;
71 struct resource res;
72#ifdef CONFIG_PCI
73 struct device_node *cascade_node = NULL;
74 int cascade_irq;
75#endif
124 76
125 /* Determine the Physical Address of the OpenPIC regs */ 77 /* Determine PIC address. */
126 openpic_paddr = get_immrbase() + MPC86xx_OPENPIC_OFFSET; 78 np = of_find_node_by_type(NULL, "open-pic");
79 if (np == NULL)
80 return;
81 of_address_to_resource(np, 0, &res);
127 82
128 /* Alloc mpic structure and per isu has 16 INT entries. */ 83 /* Alloc mpic structure and per isu has 16 INT entries. */
129 mpic1 = mpic_alloc(openpic_paddr, 84 mpic1 = mpic_alloc(np, res.start,
130 MPIC_PRIMARY | MPIC_WANTS_RESET | MPIC_BIG_ENDIAN, 85 MPIC_PRIMARY | MPIC_WANTS_RESET | MPIC_BIG_ENDIAN,
131 16, MPC86xx_OPENPIC_IRQ_OFFSET, 0, 250, 86 16, NR_IRQS - 4,
132 mpc86xx_hpcn_openpic_initsenses,
133 sizeof(mpc86xx_hpcn_openpic_initsenses),
134 " MPIC "); 87 " MPIC ");
135 BUG_ON(mpic1 == NULL); 88 BUG_ON(mpic1 == NULL);
136 89
90 mpic_assign_isu(mpic1, 0, res.start + 0x10000);
91
137 /* 48 Internal Interrupts */ 92 /* 48 Internal Interrupts */
138 mpic_assign_isu(mpic1, 0, openpic_paddr + 0x10200); 93 mpic_assign_isu(mpic1, 1, res.start + 0x10200);
139 mpic_assign_isu(mpic1, 1, openpic_paddr + 0x10400); 94 mpic_assign_isu(mpic1, 2, res.start + 0x10400);
140 mpic_assign_isu(mpic1, 2, openpic_paddr + 0x10600); 95 mpic_assign_isu(mpic1, 3, res.start + 0x10600);
141 96
142 /* 16 External interrupts */ 97 /* 16 External interrupts
143 mpic_assign_isu(mpic1, 3, openpic_paddr + 0x10000); 98 * Moving them from [0 - 15] to [64 - 79]
99 */
100 mpic_assign_isu(mpic1, 4, res.start + 0x10000);
144 101
145 mpic_init(mpic1); 102 mpic_init(mpic1);
146 103
147#ifdef CONFIG_PCI 104#ifdef CONFIG_PCI
148 mpic_setup_cascade(MPC86xx_IRQ_EXT9, i8259_irq_cascade, NULL); 105 /* Initialize i8259 controller */
149 i8259_init(0, I8259_OFFSET); 106 for_each_node_by_type(np, "interrupt-controller")
150#endif 107 if (device_is_compatible(np, "chrp,iic")) {
151} 108 cascade_node = np;
109 break;
110 }
111 if (cascade_node == NULL) {
112 printk(KERN_DEBUG "mpc86xxhpcn: no ISA interrupt controller\n");
113 return;
114 }
152 115
116 cascade_irq = irq_of_parse_and_map(cascade_node, 0);
117 if (cascade_irq == NO_IRQ) {
118 printk(KERN_ERR "mpc86xxhpcn: failed to map cascade interrupt");
119 return;
120 }
121 DBG("mpc86xxhpcn: cascade mapped to irq %d\n", cascade_irq);
153 122
123 i8259_init(cascade_node, 0);
124 set_irq_chained_handler(cascade_irq, mpc86xx_8259_cascade);
125#endif
126}
154 127
155#ifdef CONFIG_PCI 128#ifdef CONFIG_PCI
156/*
157 * interrupt routing
158 */
159 129
160int 130enum pirq{PIRQA = 8, PIRQB, PIRQC, PIRQD, PIRQE, PIRQF, PIRQG, PIRQH};
161mpc86xx_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin) 131const unsigned char uli1575_irq_route_table[16] = {
132 0, /* 0: Reserved */
133 0x8, /* 1: 0b1000 */
134 0, /* 2: Reserved */
135 0x2, /* 3: 0b0010 */
136 0x4, /* 4: 0b0100 */
137 0x5, /* 5: 0b0101 */
138 0x7, /* 6: 0b0111 */
139 0x6, /* 7: 0b0110 */
140 0, /* 8: Reserved */
141 0x1, /* 9: 0b0001 */
142 0x3, /* 10: 0b0011 */
143 0x9, /* 11: 0b1001 */
144 0xb, /* 12: 0b1011 */
145 0, /* 13: Reserved */
146 0xd, /* 14, 0b1101 */
147 0xf, /* 15, 0b1111 */
148};
149
150static int __devinit
151get_pci_irq_from_of(struct pci_controller *hose, int slot, int pin)
162{ 152{
163 static char pci_irq_table[][4] = { 153 struct of_irq oirq;
164 /* 154 u32 laddr[3];
165 * PCI IDSEL/INTPIN->INTLINE 155 struct device_node *hosenode = hose ? hose->arch_data : NULL;
166 * A B C D 156
167 */ 157 if (!hosenode) return -EINVAL;
168 {PIRQA, PIRQB, PIRQC, PIRQD}, /* IDSEL 17 -- PCI Slot 1 */ 158
169 {PIRQB, PIRQC, PIRQD, PIRQA}, /* IDSEL 18 -- PCI Slot 2 */ 159 laddr[0] = (hose->first_busno << 16) | (PCI_DEVFN(slot, 0) << 8);
170 {0, 0, 0, 0}, /* IDSEL 19 */ 160 laddr[1] = laddr[2] = 0;
171 {0, 0, 0, 0}, /* IDSEL 20 */ 161 of_irq_map_raw(hosenode, &pin, laddr, &oirq);
172 {0, 0, 0, 0}, /* IDSEL 21 */ 162 DBG("mpc86xx_hpcn: pci irq addr %x, slot %d, pin %d, irq %d\n",
173 {0, 0, 0, 0}, /* IDSEL 22 */ 163 laddr[0], slot, pin, oirq.specifier[0]);
174 {0, 0, 0, 0}, /* IDSEL 23 */ 164 return oirq.specifier[0];
175 {0, 0, 0, 0}, /* IDSEL 24 */
176 {0, 0, 0, 0}, /* IDSEL 25 */
177 {PIRQD, PIRQA, PIRQB, PIRQC}, /* IDSEL 26 -- PCI Bridge*/
178 {PIRQC, 0, 0, 0}, /* IDSEL 27 -- LAN */
179 {PIRQE, PIRQF, PIRQH, PIRQ7}, /* IDSEL 28 -- USB 1.1 */
180 {PIRQE, PIRQF, PIRQG, 0}, /* IDSEL 29 -- Audio & Modem */
181 {PIRQH, 0, 0, 0}, /* IDSEL 30 -- LPC & PMU*/
182 {PIRQD, 0, 0, 0}, /* IDSEL 31 -- ATA */
183 };
184
185 const long min_idsel = 17, max_idsel = 31, irqs_per_slot = 4;
186 return PCI_IRQ_TABLE_LOOKUP + I8259_OFFSET;
187} 165}
188 166
189static void __devinit quirk_ali1575(struct pci_dev *dev) 167static void __devinit quirk_uli1575(struct pci_dev *dev)
190{ 168{
191 unsigned short temp; 169 unsigned short temp;
170 struct pci_controller *hose = pci_bus_to_host(dev->bus);
171 unsigned char irq2pin[16];
172 unsigned long pirq_map_word = 0;
173 u32 irq;
174 int i;
175
176 /*
177 * ULI1575 interrupts route setup
178 */
179 memset(irq2pin, 0, 16); /* Initialize default value 0 */
180
181 /*
182 * PIRQA -> PIRQD mapping read from OF-tree
183 *
184 * interrupts for PCI slot0 -- PIRQA / PIRQB / PIRQC / PIRQD
185 * PCI slot1 -- PIRQB / PIRQC / PIRQD / PIRQA
186 */
187 for (i = 0; i < 4; i++){
188 irq = get_pci_irq_from_of(hose, 17, i + 1);
189 if (irq > 0 && irq < 16)
190 irq2pin[irq] = PIRQA + i;
191 else
192 printk(KERN_WARNING "ULI1575 device"
193 "(slot %d, pin %d) irq %d is invalid.\n",
194 17, i, irq);
195 }
192 196
193 /* 197 /*
194 * ALI1575 interrupts route table setup: 198 * PIRQE -> PIRQF mapping set manually
195 * 199 *
196 * IRQ pin IRQ# 200 * IRQ pin IRQ#
197 * PIRQA ---- 3
198 * PIRQB ---- 4
199 * PIRQC ---- 5
200 * PIRQD ---- 6
201 * PIRQE ---- 9 201 * PIRQE ---- 9
202 * PIRQF ---- 10 202 * PIRQF ---- 10
203 * PIRQG ---- 11 203 * PIRQG ---- 11
204 * PIRQH ---- 12 204 * PIRQH ---- 12
205 *
206 * interrupts for PCI slot0 -- PIRQA / PIRQB / PIRQC / PIRQD
207 * PCI slot1 -- PIRQB / PIRQC / PIRQD / PIRQA
208 */ 205 */
209 pci_write_config_dword(dev, 0x48, 0xb9317542); 206 for (i = 0; i < 4; i++) irq2pin[i + 9] = PIRQE + i;
207
208 /* Set IRQ-PIRQ Mapping to ULI1575 */
209 for (i = 0; i < 16; i++)
210 if (irq2pin[i])
211 pirq_map_word |= (uli1575_irq_route_table[i] & 0xf)
212 << ((irq2pin[i] - PIRQA) * 4);
213
214 /* ULI1575 IRQ mapping conf register default value is 0xb9317542 */
215 DBG("Setup ULI1575 IRQ mapping configuration register value = 0x%x\n",
216 pirq_map_word);
217 pci_write_config_dword(dev, 0x48, pirq_map_word);
218
219#define ULI1575_SET_DEV_IRQ(slot, pin, reg) \
220 do { \
221 int irq; \
222 irq = get_pci_irq_from_of(hose, slot, pin); \
223 if (irq > 0 && irq < 16) \
224 pci_write_config_byte(dev, reg, irq2pin[irq]); \
225 else \
226 printk(KERN_WARNING "ULI1575 device" \
227 "(slot %d, pin %d) irq %d is invalid.\n", \
228 slot, pin, irq); \
229 } while(0)
210 230
211 /* USB 1.1 OHCI controller 1, interrupt: PIRQE */ 231 /* USB 1.1 OHCI controller 1, slot 28, pin 1 */
212 pci_write_config_byte(dev, 0x86, 0x0c); 232 ULI1575_SET_DEV_IRQ(28, 1, 0x86);
213 233
214 /* USB 1.1 OHCI controller 2, interrupt: PIRQF */ 234 /* USB 1.1 OHCI controller 2, slot 28, pin 2 */
215 pci_write_config_byte(dev, 0x87, 0x0d); 235 ULI1575_SET_DEV_IRQ(28, 2, 0x87);
216 236
217 /* USB 1.1 OHCI controller 3, interrupt: PIRQH */ 237 /* USB 1.1 OHCI controller 3, slot 28, pin 3 */
218 pci_write_config_byte(dev, 0x88, 0x0f); 238 ULI1575_SET_DEV_IRQ(28, 3, 0x88);
219 239
220 /* USB 2.0 controller, interrupt: PIRQ7 */ 240 /* USB 2.0 controller, slot 28, pin 4 */
221 pci_write_config_byte(dev, 0x74, 0x06); 241 irq = get_pci_irq_from_of(hose, 28, 4);
242 if (irq >= 0 && irq <=15)
243 pci_write_config_dword(dev, 0x74, uli1575_irq_route_table[irq]);
222 244
223 /* Audio controller, interrupt: PIRQE */ 245 /* Audio controller, slot 29, pin 1 */
224 pci_write_config_byte(dev, 0x8a, 0x0c); 246 ULI1575_SET_DEV_IRQ(29, 1, 0x8a);
225 247
226 /* Modem controller, interrupt: PIRQF */ 248 /* Modem controller, slot 29, pin 2 */
227 pci_write_config_byte(dev, 0x8b, 0x0d); 249 ULI1575_SET_DEV_IRQ(29, 2, 0x8b);
228 250
229 /* HD audio controller, interrupt: PIRQG */ 251 /* HD audio controller, slot 29, pin 3 */
230 pci_write_config_byte(dev, 0x8c, 0x0e); 252 ULI1575_SET_DEV_IRQ(29, 3, 0x8c);
231 253
232 /* Serial ATA interrupt: PIRQD */ 254 /* SMB interrupt: slot 30, pin 1 */
233 pci_write_config_byte(dev, 0x8d, 0x0b); 255 ULI1575_SET_DEV_IRQ(30, 1, 0x8e);
234 256
235 /* SMB interrupt: PIRQH */ 257 /* PMU ACPI SCI interrupt: slot 30, pin 2 */
236 pci_write_config_byte(dev, 0x8e, 0x0f); 258 ULI1575_SET_DEV_IRQ(30, 2, 0x8f);
237 259
238 /* PMU ACPI SCI interrupt: PIRQH */ 260 /* Serial ATA interrupt: slot 31, pin 1 */
239 pci_write_config_byte(dev, 0x8f, 0x0f); 261 ULI1575_SET_DEV_IRQ(31, 1, 0x8d);
240 262
241 /* Primary PATA IDE IRQ: 14 263 /* Primary PATA IDE IRQ: 14
242 * Secondary PATA IDE IRQ: 15 264 * Secondary PATA IDE IRQ: 15
243 */ 265 */
244 pci_write_config_byte(dev, 0x44, 0x3d); 266 pci_write_config_byte(dev, 0x44, 0x30 | uli1575_irq_route_table[14]);
245 pci_write_config_byte(dev, 0x75, 0x0f); 267 pci_write_config_byte(dev, 0x75, uli1575_irq_route_table[15]);
246 268
247 /* Set IRQ14 and IRQ15 to legacy IRQs */ 269 /* Set IRQ14 and IRQ15 to legacy IRQs */
248 pci_read_config_word(dev, 0x46, &temp); 270 pci_read_config_word(dev, 0x46, &temp);
@@ -264,6 +286,8 @@ static void __devinit quirk_ali1575(struct pci_dev *dev)
264 */ 286 */
265 outb(0xfa, 0x4d0); 287 outb(0xfa, 0x4d0);
266 outb(0x1e, 0x4d1); 288 outb(0x1e, 0x4d1);
289
290#undef ULI1575_SET_DEV_IRQ
267} 291}
268 292
269static void __devinit quirk_uli5288(struct pci_dev *dev) 293static void __devinit quirk_uli5288(struct pci_dev *dev)
@@ -306,7 +330,7 @@ static void __devinit early_uli5249(struct pci_dev *dev)
306 dev->class |= 0x1; 330 dev->class |= 0x1;
307} 331}
308 332
309DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, 0x1575, quirk_ali1575); 333DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, 0x1575, quirk_uli1575);
310DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, 0x5288, quirk_uli5288); 334DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, 0x5288, quirk_uli5288);
311DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, 0x5229, quirk_uli5229); 335DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, 0x5229, quirk_uli5229);
312DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AL, 0x5249, early_uli5249); 336DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AL, 0x5249, early_uli5249);
@@ -337,8 +361,6 @@ mpc86xx_hpcn_setup_arch(void)
337 for (np = NULL; (np = of_find_node_by_type(np, "pci")) != NULL;) 361 for (np = NULL; (np = of_find_node_by_type(np, "pci")) != NULL;)
338 add_bridge(np); 362 add_bridge(np);
339 363
340 ppc_md.pci_swizzle = common_swizzle;
341 ppc_md.pci_map_irq = mpc86xx_map_irq;
342 ppc_md.pci_exclude_device = mpc86xx_exclude_device; 364 ppc_md.pci_exclude_device = mpc86xx_exclude_device;
343#endif 365#endif
344 366
@@ -377,6 +399,15 @@ mpc86xx_hpcn_show_cpuinfo(struct seq_file *m)
377} 399}
378 400
379 401
402void __init mpc86xx_hpcn_pcibios_fixup(void)
403{
404 struct pci_dev *dev = NULL;
405
406 for_each_pci_dev(dev)
407 pci_read_irq_line(dev);
408}
409
410
380/* 411/*
381 * Called very early, device-tree isn't unflattened 412 * Called very early, device-tree isn't unflattened
382 */ 413 */
@@ -431,6 +462,7 @@ define_machine(mpc86xx_hpcn) {
431 .setup_arch = mpc86xx_hpcn_setup_arch, 462 .setup_arch = mpc86xx_hpcn_setup_arch,
432 .init_IRQ = mpc86xx_hpcn_init_irq, 463 .init_IRQ = mpc86xx_hpcn_init_irq,
433 .show_cpuinfo = mpc86xx_hpcn_show_cpuinfo, 464 .show_cpuinfo = mpc86xx_hpcn_show_cpuinfo,
465 .pcibios_fixup = mpc86xx_hpcn_pcibios_fixup,
434 .get_irq = mpic_get_irq, 466 .get_irq = mpic_get_irq,
435 .restart = mpc86xx_restart, 467 .restart = mpc86xx_restart,
436 .time_init = mpc86xx_time_init, 468 .time_init = mpc86xx_time_init,
diff --git a/arch/powerpc/platforms/86xx/pci.c b/arch/powerpc/platforms/86xx/pci.c
index bc5139043112..a8c8f0a44055 100644
--- a/arch/powerpc/platforms/86xx/pci.c
+++ b/arch/powerpc/platforms/86xx/pci.c
@@ -188,7 +188,8 @@ int __init add_bridge(struct device_node *dev)
188 188
189 printk(KERN_INFO "Found MPC86xx PCIE host bridge at 0x%08lx. " 189 printk(KERN_INFO "Found MPC86xx PCIE host bridge at 0x%08lx. "
190 "Firmware bus number: %d->%d\n", 190 "Firmware bus number: %d->%d\n",
191 rsrc.start, hose->first_busno, hose->last_busno); 191 (unsigned long) rsrc.start,
192 hose->first_busno, hose->last_busno);
192 193
193 DBG(" ->Hose at 0x%p, cfg_addr=0x%p,cfg_data=0x%p\n", 194 DBG(" ->Hose at 0x%p, cfg_addr=0x%p,cfg_data=0x%p\n",
194 hose, hose->cfg_addr, hose->cfg_data); 195 hose, hose->cfg_addr, hose->cfg_data);
diff --git a/arch/powerpc/platforms/embedded6xx/Kconfig b/arch/powerpc/platforms/embedded6xx/Kconfig
index ba07a9a7c039..234a861870a8 100644
--- a/arch/powerpc/platforms/embedded6xx/Kconfig
+++ b/arch/powerpc/platforms/embedded6xx/Kconfig
@@ -80,6 +80,7 @@ config MPC7448HPC2
80 select DEFAULT_UIMAGE 80 select DEFAULT_UIMAGE
81 select PPC_UDBG_16550 81 select PPC_UDBG_16550
82 select MPIC 82 select MPIC
83 select MPIC_WEIRD
83 help 84 help
84 Select MPC7448HPC2 if configuring for Freescale MPC7448HPC2 (Taiga) 85 Select MPC7448HPC2 if configuring for Freescale MPC7448HPC2 (Taiga)
85 platform 86 platform
diff --git a/arch/powerpc/platforms/embedded6xx/mpc7448_hpc2.c b/arch/powerpc/platforms/embedded6xx/mpc7448_hpc2.c
index d7a4fc7ca238..5d393eb94935 100644
--- a/arch/powerpc/platforms/embedded6xx/mpc7448_hpc2.c
+++ b/arch/powerpc/platforms/embedded6xx/mpc7448_hpc2.c
@@ -1,7 +1,7 @@
1/* 1/*
2 * mpc7448_hpc2.c 2 * mpc7448_hpc2.c
3 * 3 *
4 * Board setup routines for the Freescale Taiga platform 4 * Board setup routines for the Freescale mpc7448hpc2(taiga) platform
5 * 5 *
6 * Author: Jacob Pan 6 * Author: Jacob Pan
7 * jacob.pan@freescale.com 7 * jacob.pan@freescale.com
@@ -12,10 +12,10 @@
12 * 12 *
13 * Copyright 2004-2006 Freescale Semiconductor, Inc. 13 * Copyright 2004-2006 Freescale Semiconductor, Inc.
14 * 14 *
15 * This file is licensed under 15 * This program is free software; you can redistribute it and/or
16 * the terms of the GNU General Public License version 2. This program 16 * modify it under the terms of the GNU General Public License
17 * is licensed "as is" without any warranty of any kind, whether express 17 * as published by the Free Software Foundation; either version
18 * or implied. 18 * 2 of the License, or (at your option) any later version.
19 */ 19 */
20 20
21#include <linux/config.h> 21#include <linux/config.h>
@@ -62,43 +62,8 @@ pci_dram_offset = MPC7448_HPC2_PCI_MEM_OFFSET;
62extern int tsi108_setup_pci(struct device_node *dev); 62extern int tsi108_setup_pci(struct device_node *dev);
63extern void _nmask_and_or_msr(unsigned long nmask, unsigned long or_val); 63extern void _nmask_and_or_msr(unsigned long nmask, unsigned long or_val);
64extern void tsi108_pci_int_init(void); 64extern void tsi108_pci_int_init(void);
65extern int tsi108_irq_cascade(struct pt_regs *regs, void *unused); 65extern void tsi108_irq_cascade(unsigned int irq, struct irq_desc *desc,
66 66 struct pt_regs *regs);
67/*
68 * Define all of the IRQ senses and polarities. Taken from the
69 * mpc7448hpc manual.
70 * Note: Likely, this table and the following function should be
71 * obtained and derived from the OF Device Tree.
72 */
73
74static u_char mpc7448_hpc2_pic_initsenses[] __initdata = {
75 /* External on-board sources */
76 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* INT[0] XINT0 from FPGA */
77 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* INT[1] XINT1 from FPGA */
78 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* INT[2] PHY_INT from both GIGE */
79 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* INT[3] RESERVED */
80 /* Internal Tsi108/109 interrupt sources */
81 (IRQ_SENSE_EDGE | IRQ_POLARITY_POSITIVE), /* Reserved IRQ */
82 (IRQ_SENSE_EDGE | IRQ_POLARITY_POSITIVE), /* Reserved IRQ */
83 (IRQ_SENSE_EDGE | IRQ_POLARITY_POSITIVE), /* Reserved IRQ */
84 (IRQ_SENSE_EDGE | IRQ_POLARITY_POSITIVE), /* Reserved IRQ */
85 (IRQ_SENSE_EDGE | IRQ_POLARITY_POSITIVE), /* DMA0 */
86 (IRQ_SENSE_EDGE | IRQ_POLARITY_POSITIVE), /* DMA1 */
87 (IRQ_SENSE_EDGE | IRQ_POLARITY_POSITIVE), /* DMA2 */
88 (IRQ_SENSE_EDGE | IRQ_POLARITY_POSITIVE), /* DMA3 */
89 (IRQ_SENSE_EDGE | IRQ_POLARITY_POSITIVE), /* UART0 */
90 (IRQ_SENSE_EDGE | IRQ_POLARITY_POSITIVE), /* UART1 */
91 (IRQ_SENSE_EDGE | IRQ_POLARITY_POSITIVE), /* I2C */
92 (IRQ_SENSE_EDGE | IRQ_POLARITY_POSITIVE), /* GPIO */
93 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* GIGE0 */
94 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* GIGE1 */
95 (IRQ_SENSE_EDGE | IRQ_POLARITY_POSITIVE), /* Reserved IRQ */
96 (IRQ_SENSE_EDGE | IRQ_POLARITY_POSITIVE), /* HLP */
97 (IRQ_SENSE_EDGE | IRQ_POLARITY_POSITIVE), /* SDC */
98 (IRQ_SENSE_EDGE | IRQ_POLARITY_POSITIVE), /* Processor IF */
99 (IRQ_SENSE_EDGE | IRQ_POLARITY_POSITIVE), /* Reserved IRQ */
100 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* PCI/X block */
101};
102 67
103int mpc7448_hpc2_exclude_device(u_char bus, u_char devfn) 68int mpc7448_hpc2_exclude_device(u_char bus, u_char devfn)
104{ 69{
@@ -229,6 +194,8 @@ static void __init mpc7448_hpc2_init_IRQ(void)
229{ 194{
230 struct mpic *mpic; 195 struct mpic *mpic;
231 phys_addr_t mpic_paddr = 0; 196 phys_addr_t mpic_paddr = 0;
197 unsigned int cascade_pci_irq;
198 struct device_node *tsi_pci;
232 struct device_node *tsi_pic; 199 struct device_node *tsi_pic;
233 200
234 tsi_pic = of_find_node_by_type(NULL, "open-pic"); 201 tsi_pic = of_find_node_by_type(NULL, "open-pic");
@@ -246,24 +213,31 @@ static void __init mpc7448_hpc2_init_IRQ(void)
246 DBG("%s: tsi108pic phys_addr = 0x%x\n", __FUNCTION__, 213 DBG("%s: tsi108pic phys_addr = 0x%x\n", __FUNCTION__,
247 (u32) mpic_paddr); 214 (u32) mpic_paddr);
248 215
249 mpic = mpic_alloc(mpic_paddr, 216 mpic = mpic_alloc(tsi_pic, mpic_paddr,
250 MPIC_PRIMARY | MPIC_BIG_ENDIAN | MPIC_WANTS_RESET | 217 MPIC_PRIMARY | MPIC_BIG_ENDIAN | MPIC_WANTS_RESET |
251 MPIC_SPV_EOI | MPIC_MOD_ID(MPIC_ID_TSI108), 218 MPIC_SPV_EOI | MPIC_NO_PTHROU_DIS | MPIC_REGSET_TSI108,
252 0, /* num_sources used */ 219 0, /* num_sources used */
253 TSI108_IRQ_BASE,
254 0, /* num_sources used */ 220 0, /* num_sources used */
255 NR_IRQS - 4 /* XXXX */, 221 "Tsi108_PIC");
256 mpc7448_hpc2_pic_initsenses,
257 sizeof(mpc7448_hpc2_pic_initsenses), "Tsi108_PIC");
258 222
259 BUG_ON(mpic == NULL); /* XXXX */ 223 BUG_ON(mpic == NULL); /* XXXX */
260
261 mpic_init(mpic); 224 mpic_init(mpic);
262 mpic_setup_cascade(IRQ_TSI108_PCI, tsi108_irq_cascade, mpic); 225
226 tsi_pci = of_find_node_by_type(NULL, "pci");
227 if (tsi_pci == 0) {
228 printk("%s: No tsi108 pci node found !\n", __FUNCTION__);
229 return;
230 }
231
232 cascade_pci_irq = irq_of_parse_and_map(tsi_pci, 0);
233 set_irq_data(cascade_pci_irq, mpic);
234 set_irq_chained_handler(cascade_pci_irq, tsi108_irq_cascade);
235
263 tsi108_pci_int_init(); 236 tsi108_pci_int_init();
264 237
265 /* Configure MPIC outputs to CPU0 */ 238 /* Configure MPIC outputs to CPU0 */
266 tsi108_write_reg(TSI108_MPIC_OFFSET + 0x30c, 0); 239 tsi108_write_reg(TSI108_MPIC_OFFSET + 0x30c, 0);
240 of_node_put(tsi_pic);
267} 241}
268 242
269void mpc7448_hpc2_show_cpuinfo(struct seq_file *m) 243void mpc7448_hpc2_show_cpuinfo(struct seq_file *m)
@@ -320,6 +294,7 @@ static int mpc7448_machine_check_exception(struct pt_regs *regs)
320 return 0; 294 return 0;
321 295
322} 296}
297
323define_machine(mpc7448_hpc2){ 298define_machine(mpc7448_hpc2){
324 .name = "MPC7448 HPC2", 299 .name = "MPC7448 HPC2",
325 .probe = mpc7448_hpc2_probe, 300 .probe = mpc7448_hpc2_probe,
diff --git a/arch/powerpc/platforms/powermac/bootx_init.c b/arch/powerpc/platforms/powermac/bootx_init.c
index 6a026c733f6a..9d73d0234c5d 100644
--- a/arch/powerpc/platforms/powermac/bootx_init.c
+++ b/arch/powerpc/platforms/powermac/bootx_init.c
@@ -411,8 +411,15 @@ static unsigned long __init bootx_flatten_dt(unsigned long start)
411 DBG("End of boot params: %x\n", mem_end); 411 DBG("End of boot params: %x\n", mem_end);
412 rsvmap[0] = mem_start; 412 rsvmap[0] = mem_start;
413 rsvmap[1] = mem_end; 413 rsvmap[1] = mem_end;
414 rsvmap[2] = 0; 414 if (bootx_info->ramDisk) {
415 rsvmap[3] = 0; 415 rsvmap[2] = ((unsigned long)bootx_info) + bootx_info->ramDisk;
416 rsvmap[3] = rsvmap[2] + bootx_info->ramDiskSize;
417 rsvmap[4] = 0;
418 rsvmap[5] = 0;
419 } else {
420 rsvmap[2] = 0;
421 rsvmap[3] = 0;
422 }
416 423
417 return (unsigned long)hdr; 424 return (unsigned long)hdr;
418} 425}
@@ -543,12 +550,12 @@ void __init bootx_init(unsigned long r3, unsigned long r4)
543 */ 550 */
544 if (bi->version < 5) { 551 if (bi->version < 5) {
545 space = bi->deviceTreeOffset + bi->deviceTreeSize; 552 space = bi->deviceTreeOffset + bi->deviceTreeSize;
546 if (bi->ramDisk) 553 if (bi->ramDisk >= space)
547 space = bi->ramDisk + bi->ramDiskSize; 554 space = bi->ramDisk + bi->ramDiskSize;
548 } else 555 } else
549 space = bi->totalParamsSize; 556 space = bi->totalParamsSize;
550 557
551 bootx_printf("Total space used by parameters & ramdisk: %x \n", space); 558 bootx_printf("Total space used by parameters & ramdisk: 0x%x \n", space);
552 559
553 /* New BootX will have flushed all TLBs and enters kernel with 560 /* New BootX will have flushed all TLBs and enters kernel with
554 * MMU switched OFF, so this should not be useful anymore. 561 * MMU switched OFF, so this should not be useful anymore.
diff --git a/arch/powerpc/platforms/powermac/pfunc_base.c b/arch/powerpc/platforms/powermac/pfunc_base.c
index 6d66359ec8c8..aacfa59595d1 100644
--- a/arch/powerpc/platforms/powermac/pfunc_base.c
+++ b/arch/powerpc/platforms/powermac/pfunc_base.c
@@ -256,7 +256,7 @@ static struct pmf_handlers macio_mmio_handlers = {
256 .write_reg32 = macio_do_write_reg32, 256 .write_reg32 = macio_do_write_reg32,
257 .read_reg32 = macio_do_read_reg32, 257 .read_reg32 = macio_do_read_reg32,
258 .write_reg8 = macio_do_write_reg8, 258 .write_reg8 = macio_do_write_reg8,
259 .read_reg32 = macio_do_read_reg8, 259 .read_reg8 = macio_do_read_reg8,
260 .read_reg32_msrx = macio_do_read_reg32_msrx, 260 .read_reg32_msrx = macio_do_read_reg32_msrx,
261 .read_reg8_msrx = macio_do_read_reg8_msrx, 261 .read_reg8_msrx = macio_do_read_reg8_msrx,
262 .write_reg32_slm = macio_do_write_reg32_slm, 262 .write_reg32_slm = macio_do_write_reg32_slm,
diff --git a/arch/powerpc/platforms/powermac/pic.c b/arch/powerpc/platforms/powermac/pic.c
index 060789e31c67..39f7ddb554ea 100644
--- a/arch/powerpc/platforms/powermac/pic.c
+++ b/arch/powerpc/platforms/powermac/pic.c
@@ -87,8 +87,8 @@ static void __pmac_retrigger(unsigned int irq_nr)
87static void pmac_mask_and_ack_irq(unsigned int virq) 87static void pmac_mask_and_ack_irq(unsigned int virq)
88{ 88{
89 unsigned int src = irq_map[virq].hwirq; 89 unsigned int src = irq_map[virq].hwirq;
90 unsigned long bit = 1UL << (virq & 0x1f); 90 unsigned long bit = 1UL << (src & 0x1f);
91 int i = virq >> 5; 91 int i = src >> 5;
92 unsigned long flags; 92 unsigned long flags;
93 93
94 spin_lock_irqsave(&pmac_pic_lock, flags); 94 spin_lock_irqsave(&pmac_pic_lock, flags);
@@ -175,7 +175,7 @@ static void pmac_mask_irq(unsigned int virq)
175 175
176 spin_lock_irqsave(&pmac_pic_lock, flags); 176 spin_lock_irqsave(&pmac_pic_lock, flags);
177 __clear_bit(src, ppc_cached_irq_mask); 177 __clear_bit(src, ppc_cached_irq_mask);
178 __pmac_set_irq_mask(src, 0); 178 __pmac_set_irq_mask(src, 1);
179 spin_unlock_irqrestore(&pmac_pic_lock, flags); 179 spin_unlock_irqrestore(&pmac_pic_lock, flags);
180} 180}
181 181
diff --git a/arch/powerpc/platforms/pseries/setup.c b/arch/powerpc/platforms/pseries/setup.c
index 71c634e0b87c..31867a701fcb 100644
--- a/arch/powerpc/platforms/pseries/setup.c
+++ b/arch/powerpc/platforms/pseries/setup.c
@@ -213,8 +213,6 @@ static void pseries_lpar_enable_pmcs(void)
213{ 213{
214 unsigned long set, reset; 214 unsigned long set, reset;
215 215
216 power4_enable_pmcs();
217
218 set = 1UL << 63; 216 set = 1UL << 63;
219 reset = 0; 217 reset = 0;
220 plpar_hcall_norets(H_PERFMON, set, reset); 218 plpar_hcall_norets(H_PERFMON, set, reset);
diff --git a/arch/powerpc/platforms/pseries/xics.c b/arch/powerpc/platforms/pseries/xics.c
index 2d0da6f9e244..e98863025721 100644
--- a/arch/powerpc/platforms/pseries/xics.c
+++ b/arch/powerpc/platforms/pseries/xics.c
@@ -467,7 +467,7 @@ void xics_setup_cpu(void)
467 * 467 *
468 * XXX: undo of teardown on kexec needs this too, as may hotplug 468 * XXX: undo of teardown on kexec needs this too, as may hotplug
469 */ 469 */
470 rtas_set_indicator(GLOBAL_INTERRUPT_QUEUE, 470 rtas_set_indicator_fast(GLOBAL_INTERRUPT_QUEUE,
471 (1UL << interrupt_server_size) - 1 - default_distrib_server, 1); 471 (1UL << interrupt_server_size) - 1 - default_distrib_server, 1);
472} 472}
473 473
@@ -796,7 +796,7 @@ void xics_teardown_cpu(int secondary)
796 * so leave the master cpu in the group. 796 * so leave the master cpu in the group.
797 */ 797 */
798 if (secondary) 798 if (secondary)
799 rtas_set_indicator(GLOBAL_INTERRUPT_QUEUE, 799 rtas_set_indicator_fast(GLOBAL_INTERRUPT_QUEUE,
800 (1UL << interrupt_server_size) - 1 - 800 (1UL << interrupt_server_size) - 1 -
801 default_distrib_server, 0); 801 default_distrib_server, 0);
802} 802}
@@ -813,7 +813,7 @@ void xics_migrate_irqs_away(void)
813 xics_set_cpu_priority(cpu, 0); 813 xics_set_cpu_priority(cpu, 0);
814 814
815 /* remove ourselves from the global interrupt queue */ 815 /* remove ourselves from the global interrupt queue */
816 status = rtas_set_indicator(GLOBAL_INTERRUPT_QUEUE, 816 status = rtas_set_indicator_fast(GLOBAL_INTERRUPT_QUEUE,
817 (1UL << interrupt_server_size) - 1 - default_distrib_server, 0); 817 (1UL << interrupt_server_size) - 1 - default_distrib_server, 0);
818 WARN_ON(status < 0); 818 WARN_ON(status < 0);
819 819
diff --git a/arch/powerpc/sysdev/Makefile b/arch/powerpc/sysdev/Makefile
index cebfae242602..e5e999ea891a 100644
--- a/arch/powerpc/sysdev/Makefile
+++ b/arch/powerpc/sysdev/Makefile
@@ -9,11 +9,11 @@ obj-$(CONFIG_BOOKE) += dcr.o
9obj-$(CONFIG_40x) += dcr.o 9obj-$(CONFIG_40x) += dcr.o
10obj-$(CONFIG_U3_DART) += dart_iommu.o 10obj-$(CONFIG_U3_DART) += dart_iommu.o
11obj-$(CONFIG_MMIO_NVRAM) += mmio_nvram.o 11obj-$(CONFIG_MMIO_NVRAM) += mmio_nvram.o
12obj-$(CONFIG_PPC_83xx) += ipic.o
13obj-$(CONFIG_FSL_SOC) += fsl_soc.o 12obj-$(CONFIG_FSL_SOC) += fsl_soc.o
14obj-$(CONFIG_PPC_TODC) += todc.o 13obj-$(CONFIG_PPC_TODC) += todc.o
15obj-$(CONFIG_TSI108_BRIDGE) += tsi108_pci.o tsi108_dev.o 14obj-$(CONFIG_TSI108_BRIDGE) += tsi108_pci.o tsi108_dev.o
16 15
17ifeq ($(CONFIG_PPC_MERGE),y) 16ifeq ($(CONFIG_PPC_MERGE),y)
18obj-$(CONFIG_PPC_I8259) += i8259.o 17obj-$(CONFIG_PPC_I8259) += i8259.o
19 endif 18obj-$(CONFIG_PPC_83xx) += ipic.o
19endif
diff --git a/arch/powerpc/sysdev/fsl_soc.c b/arch/powerpc/sysdev/fsl_soc.c
index e983972132d8..ef10bcf2d943 100644
--- a/arch/powerpc/sysdev/fsl_soc.c
+++ b/arch/powerpc/sysdev/fsl_soc.c
@@ -85,11 +85,8 @@ static int __init gfar_mdio_of_init(void)
85 mdio_data.irq[k] = -1; 85 mdio_data.irq[k] = -1;
86 86
87 while ((child = of_get_next_child(np, child)) != NULL) { 87 while ((child = of_get_next_child(np, child)) != NULL) {
88 if (child->n_intrs) { 88 u32 *id = get_property(child, "reg", NULL);
89 u32 *id = 89 mdio_data.irq[*id] = irq_of_parse_and_map(child, 0);
90 (u32 *) get_property(child, "reg", NULL);
91 mdio_data.irq[*id] = child->intrs[0].line;
92 }
93 } 90 }
94 91
95 ret = 92 ret =
@@ -131,6 +128,7 @@ static int __init gfar_of_init(void)
131 char *model; 128 char *model;
132 void *mac_addr; 129 void *mac_addr;
133 phandle *ph; 130 phandle *ph;
131 int n_res = 1;
134 132
135 memset(r, 0, sizeof(r)); 133 memset(r, 0, sizeof(r));
136 memset(&gfar_data, 0, sizeof(gfar_data)); 134 memset(&gfar_data, 0, sizeof(gfar_data));
@@ -139,8 +137,7 @@ static int __init gfar_of_init(void)
139 if (ret) 137 if (ret)
140 goto err; 138 goto err;
141 139
142 r[1].start = np->intrs[0].line; 140 r[1].start = r[1].end = irq_of_parse_and_map(np, 0);
143 r[1].end = np->intrs[0].line;
144 r[1].flags = IORESOURCE_IRQ; 141 r[1].flags = IORESOURCE_IRQ;
145 142
146 model = get_property(np, "model", NULL); 143 model = get_property(np, "model", NULL);
@@ -150,27 +147,35 @@ static int __init gfar_of_init(void)
150 r[1].name = gfar_tx_intr; 147 r[1].name = gfar_tx_intr;
151 148
152 r[2].name = gfar_rx_intr; 149 r[2].name = gfar_rx_intr;
153 r[2].start = np->intrs[1].line; 150 r[2].start = r[2].end = irq_of_parse_and_map(np, 1);
154 r[2].end = np->intrs[1].line;
155 r[2].flags = IORESOURCE_IRQ; 151 r[2].flags = IORESOURCE_IRQ;
156 152
157 r[3].name = gfar_err_intr; 153 r[3].name = gfar_err_intr;
158 r[3].start = np->intrs[2].line; 154 r[3].start = r[3].end = irq_of_parse_and_map(np, 2);
159 r[3].end = np->intrs[2].line;
160 r[3].flags = IORESOURCE_IRQ; 155 r[3].flags = IORESOURCE_IRQ;
156
157 n_res += 2;
161 } 158 }
162 159
163 gfar_dev = 160 gfar_dev =
164 platform_device_register_simple("fsl-gianfar", i, &r[0], 161 platform_device_register_simple("fsl-gianfar", i, &r[0],
165 np->n_intrs + 1); 162 n_res + 1);
166 163
167 if (IS_ERR(gfar_dev)) { 164 if (IS_ERR(gfar_dev)) {
168 ret = PTR_ERR(gfar_dev); 165 ret = PTR_ERR(gfar_dev);
169 goto err; 166 goto err;
170 } 167 }
171 168
172 mac_addr = get_property(np, "address", NULL); 169 mac_addr = get_property(np, "local-mac-address", NULL);
173 memcpy(gfar_data.mac_addr, mac_addr, 6); 170 if (mac_addr == NULL)
171 mac_addr = get_property(np, "mac-address", NULL);
172 if (mac_addr == NULL) {
173 /* Obsolete */
174 mac_addr = get_property(np, "address", NULL);
175 }
176
177 if (mac_addr)
178 memcpy(gfar_data.mac_addr, mac_addr, 6);
174 179
175 if (model && !strcasecmp(model, "TSEC")) 180 if (model && !strcasecmp(model, "TSEC"))
176 gfar_data.device_flags = 181 gfar_data.device_flags =
@@ -251,8 +256,7 @@ static int __init fsl_i2c_of_init(void)
251 if (ret) 256 if (ret)
252 goto err; 257 goto err;
253 258
254 r[1].start = np->intrs[0].line; 259 r[1].start = r[1].end = irq_of_parse_and_map(np, 0);
255 r[1].end = np->intrs[0].line;
256 r[1].flags = IORESOURCE_IRQ; 260 r[1].flags = IORESOURCE_IRQ;
257 261
258 i2c_dev = platform_device_register_simple("fsl-i2c", i, r, 2); 262 i2c_dev = platform_device_register_simple("fsl-i2c", i, r, 2);
@@ -388,8 +392,7 @@ static int __init fsl_usb_of_init(void)
388 if (ret) 392 if (ret)
389 goto err; 393 goto err;
390 394
391 r[1].start = np->intrs[0].line; 395 r[1].start = r[1].end = irq_of_parse_and_map(np, 0);
392 r[1].end = np->intrs[0].line;
393 r[1].flags = IORESOURCE_IRQ; 396 r[1].flags = IORESOURCE_IRQ;
394 397
395 usb_dev_mph = 398 usb_dev_mph =
@@ -437,8 +440,7 @@ static int __init fsl_usb_of_init(void)
437 if (ret) 440 if (ret)
438 goto unreg_mph; 441 goto unreg_mph;
439 442
440 r[1].start = np->intrs[0].line; 443 r[1].start = r[1].end = irq_of_parse_and_map(np, 0);
441 r[1].end = np->intrs[0].line;
442 r[1].flags = IORESOURCE_IRQ; 444 r[1].flags = IORESOURCE_IRQ;
443 445
444 usb_dev_dr = 446 usb_dev_dr =
diff --git a/arch/powerpc/sysdev/ipic.c b/arch/powerpc/sysdev/ipic.c
index 46801f5ec03f..70e707785d49 100644
--- a/arch/powerpc/sysdev/ipic.c
+++ b/arch/powerpc/sysdev/ipic.c
@@ -19,15 +19,18 @@
19#include <linux/sched.h> 19#include <linux/sched.h>
20#include <linux/signal.h> 20#include <linux/signal.h>
21#include <linux/sysdev.h> 21#include <linux/sysdev.h>
22#include <linux/device.h>
23#include <linux/bootmem.h>
24#include <linux/spinlock.h>
22#include <asm/irq.h> 25#include <asm/irq.h>
23#include <asm/io.h> 26#include <asm/io.h>
27#include <asm/prom.h>
24#include <asm/ipic.h> 28#include <asm/ipic.h>
25#include <asm/mpc83xx.h>
26 29
27#include "ipic.h" 30#include "ipic.h"
28 31
29static struct ipic p_ipic;
30static struct ipic * primary_ipic; 32static struct ipic * primary_ipic;
33static DEFINE_SPINLOCK(ipic_lock);
31 34
32static struct ipic_info ipic_info[] = { 35static struct ipic_info ipic_info[] = {
33 [9] = { 36 [9] = {
@@ -373,74 +376,220 @@ static inline void ipic_write(volatile u32 __iomem *base, unsigned int reg, u32
373 out_be32(base + (reg >> 2), value); 376 out_be32(base + (reg >> 2), value);
374} 377}
375 378
376static inline struct ipic * ipic_from_irq(unsigned int irq) 379static inline struct ipic * ipic_from_irq(unsigned int virq)
377{ 380{
378 return primary_ipic; 381 return primary_ipic;
379} 382}
380 383
381static void ipic_enable_irq(unsigned int irq) 384#define ipic_irq_to_hw(virq) ((unsigned int)irq_map[virq].hwirq)
385
386static void ipic_unmask_irq(unsigned int virq)
382{ 387{
383 struct ipic *ipic = ipic_from_irq(irq); 388 struct ipic *ipic = ipic_from_irq(virq);
384 unsigned int src = irq - ipic->irq_offset; 389 unsigned int src = ipic_irq_to_hw(virq);
390 unsigned long flags;
385 u32 temp; 391 u32 temp;
386 392
393 spin_lock_irqsave(&ipic_lock, flags);
394
387 temp = ipic_read(ipic->regs, ipic_info[src].mask); 395 temp = ipic_read(ipic->regs, ipic_info[src].mask);
388 temp |= (1 << (31 - ipic_info[src].bit)); 396 temp |= (1 << (31 - ipic_info[src].bit));
389 ipic_write(ipic->regs, ipic_info[src].mask, temp); 397 ipic_write(ipic->regs, ipic_info[src].mask, temp);
398
399 spin_unlock_irqrestore(&ipic_lock, flags);
390} 400}
391 401
392static void ipic_disable_irq(unsigned int irq) 402static void ipic_mask_irq(unsigned int virq)
393{ 403{
394 struct ipic *ipic = ipic_from_irq(irq); 404 struct ipic *ipic = ipic_from_irq(virq);
395 unsigned int src = irq - ipic->irq_offset; 405 unsigned int src = ipic_irq_to_hw(virq);
406 unsigned long flags;
396 u32 temp; 407 u32 temp;
397 408
409 spin_lock_irqsave(&ipic_lock, flags);
410
398 temp = ipic_read(ipic->regs, ipic_info[src].mask); 411 temp = ipic_read(ipic->regs, ipic_info[src].mask);
399 temp &= ~(1 << (31 - ipic_info[src].bit)); 412 temp &= ~(1 << (31 - ipic_info[src].bit));
400 ipic_write(ipic->regs, ipic_info[src].mask, temp); 413 ipic_write(ipic->regs, ipic_info[src].mask, temp);
414
415 spin_unlock_irqrestore(&ipic_lock, flags);
401} 416}
402 417
403static void ipic_disable_irq_and_ack(unsigned int irq) 418static void ipic_ack_irq(unsigned int virq)
404{ 419{
405 struct ipic *ipic = ipic_from_irq(irq); 420 struct ipic *ipic = ipic_from_irq(virq);
406 unsigned int src = irq - ipic->irq_offset; 421 unsigned int src = ipic_irq_to_hw(virq);
422 unsigned long flags;
407 u32 temp; 423 u32 temp;
408 424
409 ipic_disable_irq(irq); 425 spin_lock_irqsave(&ipic_lock, flags);
410 426
411 temp = ipic_read(ipic->regs, ipic_info[src].pend); 427 temp = ipic_read(ipic->regs, ipic_info[src].pend);
412 temp |= (1 << (31 - ipic_info[src].bit)); 428 temp |= (1 << (31 - ipic_info[src].bit));
413 ipic_write(ipic->regs, ipic_info[src].pend, temp); 429 ipic_write(ipic->regs, ipic_info[src].pend, temp);
430
431 spin_unlock_irqrestore(&ipic_lock, flags);
414} 432}
415 433
416static void ipic_end_irq(unsigned int irq) 434static void ipic_mask_irq_and_ack(unsigned int virq)
417{ 435{
418 if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) 436 struct ipic *ipic = ipic_from_irq(virq);
419 ipic_enable_irq(irq); 437 unsigned int src = ipic_irq_to_hw(virq);
438 unsigned long flags;
439 u32 temp;
440
441 spin_lock_irqsave(&ipic_lock, flags);
442
443 temp = ipic_read(ipic->regs, ipic_info[src].mask);
444 temp &= ~(1 << (31 - ipic_info[src].bit));
445 ipic_write(ipic->regs, ipic_info[src].mask, temp);
446
447 temp = ipic_read(ipic->regs, ipic_info[src].pend);
448 temp |= (1 << (31 - ipic_info[src].bit));
449 ipic_write(ipic->regs, ipic_info[src].pend, temp);
450
451 spin_unlock_irqrestore(&ipic_lock, flags);
420} 452}
421 453
422struct hw_interrupt_type ipic = { 454static int ipic_set_irq_type(unsigned int virq, unsigned int flow_type)
423 .typename = " IPIC ", 455{
424 .enable = ipic_enable_irq, 456 struct ipic *ipic = ipic_from_irq(virq);
425 .disable = ipic_disable_irq, 457 unsigned int src = ipic_irq_to_hw(virq);
426 .ack = ipic_disable_irq_and_ack, 458 struct irq_desc *desc = get_irq_desc(virq);
427 .end = ipic_end_irq, 459 unsigned int vold, vnew, edibit;
460
461 if (flow_type == IRQ_TYPE_NONE)
462 flow_type = IRQ_TYPE_LEVEL_LOW;
463
464 /* ipic supports only low assertion and high-to-low change senses
465 */
466 if (!(flow_type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_EDGE_FALLING))) {
467 printk(KERN_ERR "ipic: sense type 0x%x not supported\n",
468 flow_type);
469 return -EINVAL;
470 }
471
472 desc->status &= ~(IRQ_TYPE_SENSE_MASK | IRQ_LEVEL);
473 desc->status |= flow_type & IRQ_TYPE_SENSE_MASK;
474 if (flow_type & IRQ_TYPE_LEVEL_LOW) {
475 desc->status |= IRQ_LEVEL;
476 set_irq_handler(virq, handle_level_irq);
477 } else {
478 set_irq_handler(virq, handle_edge_irq);
479 }
480
481 /* only EXT IRQ senses are programmable on ipic
482 * internal IRQ senses are LEVEL_LOW
483 */
484 if (src == IPIC_IRQ_EXT0)
485 edibit = 15;
486 else
487 if (src >= IPIC_IRQ_EXT1 && src <= IPIC_IRQ_EXT7)
488 edibit = (14 - (src - IPIC_IRQ_EXT1));
489 else
490 return (flow_type & IRQ_TYPE_LEVEL_LOW) ? 0 : -EINVAL;
491
492 vold = ipic_read(ipic->regs, IPIC_SECNR);
493 if ((flow_type & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_FALLING) {
494 vnew = vold | (1 << edibit);
495 } else {
496 vnew = vold & ~(1 << edibit);
497 }
498 if (vold != vnew)
499 ipic_write(ipic->regs, IPIC_SECNR, vnew);
500 return 0;
501}
502
503static struct irq_chip ipic_irq_chip = {
504 .typename = " IPIC ",
505 .unmask = ipic_unmask_irq,
506 .mask = ipic_mask_irq,
507 .mask_ack = ipic_mask_irq_and_ack,
508 .ack = ipic_ack_irq,
509 .set_type = ipic_set_irq_type,
510};
511
512static int ipic_host_match(struct irq_host *h, struct device_node *node)
513{
514 struct ipic *ipic = h->host_data;
515
516 /* Exact match, unless ipic node is NULL */
517 return ipic->of_node == NULL || ipic->of_node == node;
518}
519
520static int ipic_host_map(struct irq_host *h, unsigned int virq,
521 irq_hw_number_t hw)
522{
523 struct ipic *ipic = h->host_data;
524 struct irq_chip *chip;
525
526 /* Default chip */
527 chip = &ipic->hc_irq;
528
529 set_irq_chip_data(virq, ipic);
530 set_irq_chip_and_handler(virq, chip, handle_level_irq);
531
532 /* Set default irq type */
533 set_irq_type(virq, IRQ_TYPE_NONE);
534
535 return 0;
536}
537
538static int ipic_host_xlate(struct irq_host *h, struct device_node *ct,
539 u32 *intspec, unsigned int intsize,
540 irq_hw_number_t *out_hwirq, unsigned int *out_flags)
541
542{
543 /* interrupt sense values coming from the device tree equal either
544 * LEVEL_LOW (low assertion) or EDGE_FALLING (high-to-low change)
545 */
546 *out_hwirq = intspec[0];
547 if (intsize > 1)
548 *out_flags = intspec[1];
549 else
550 *out_flags = IRQ_TYPE_NONE;
551 return 0;
552}
553
554static struct irq_host_ops ipic_host_ops = {
555 .match = ipic_host_match,
556 .map = ipic_host_map,
557 .xlate = ipic_host_xlate,
428}; 558};
429 559
430void __init ipic_init(phys_addr_t phys_addr, 560void __init ipic_init(struct device_node *node,
431 unsigned int flags, 561 unsigned int flags)
432 unsigned int irq_offset,
433 unsigned char *senses,
434 unsigned int senses_count)
435{ 562{
436 u32 i, temp = 0; 563 struct ipic *ipic;
564 struct resource res;
565 u32 temp = 0, ret;
566
567 ipic = alloc_bootmem(sizeof(struct ipic));
568 if (ipic == NULL)
569 return;
570
571 memset(ipic, 0, sizeof(struct ipic));
572 ipic->of_node = node ? of_node_get(node) : NULL;
573
574 ipic->irqhost = irq_alloc_host(IRQ_HOST_MAP_LINEAR,
575 NR_IPIC_INTS,
576 &ipic_host_ops, 0);
577 if (ipic->irqhost == NULL) {
578 of_node_put(node);
579 return;
580 }
581
582 ret = of_address_to_resource(node, 0, &res);
583 if (ret)
584 return;
437 585
438 primary_ipic = &p_ipic; 586 ipic->regs = ioremap(res.start, res.end - res.start + 1);
439 primary_ipic->regs = ioremap(phys_addr, MPC83xx_IPIC_SIZE);
440 587
441 primary_ipic->irq_offset = irq_offset; 588 ipic->irqhost->host_data = ipic;
589 ipic->hc_irq = ipic_irq_chip;
442 590
443 ipic_write(primary_ipic->regs, IPIC_SICNR, 0x0); 591 /* init hw */
592 ipic_write(ipic->regs, IPIC_SICNR, 0x0);
444 593
445 /* default priority scheme is grouped. If spread mode is required 594 /* default priority scheme is grouped. If spread mode is required
446 * configure SICFR accordingly */ 595 * configure SICFR accordingly */
@@ -453,49 +602,35 @@ void __init ipic_init(phys_addr_t phys_addr,
453 if (flags & IPIC_SPREADMODE_MIX_B) 602 if (flags & IPIC_SPREADMODE_MIX_B)
454 temp |= SICFR_MPSB; 603 temp |= SICFR_MPSB;
455 604
456 ipic_write(primary_ipic->regs, IPIC_SICNR, temp); 605 ipic_write(ipic->regs, IPIC_SICNR, temp);
457 606
458 /* handle MCP route */ 607 /* handle MCP route */
459 temp = 0; 608 temp = 0;
460 if (flags & IPIC_DISABLE_MCP_OUT) 609 if (flags & IPIC_DISABLE_MCP_OUT)
461 temp = SERCR_MCPR; 610 temp = SERCR_MCPR;
462 ipic_write(primary_ipic->regs, IPIC_SERCR, temp); 611 ipic_write(ipic->regs, IPIC_SERCR, temp);
463 612
464 /* handle routing of IRQ0 to MCP */ 613 /* handle routing of IRQ0 to MCP */
465 temp = ipic_read(primary_ipic->regs, IPIC_SEMSR); 614 temp = ipic_read(ipic->regs, IPIC_SEMSR);
466 615
467 if (flags & IPIC_IRQ0_MCP) 616 if (flags & IPIC_IRQ0_MCP)
468 temp |= SEMSR_SIRQ0; 617 temp |= SEMSR_SIRQ0;
469 else 618 else
470 temp &= ~SEMSR_SIRQ0; 619 temp &= ~SEMSR_SIRQ0;
471 620
472 ipic_write(primary_ipic->regs, IPIC_SEMSR, temp); 621 ipic_write(ipic->regs, IPIC_SEMSR, temp);
473 622
474 for (i = 0 ; i < NR_IPIC_INTS ; i++) { 623 primary_ipic = ipic;
475 irq_desc[i+irq_offset].chip = &ipic; 624 irq_set_default_host(primary_ipic->irqhost);
476 irq_desc[i+irq_offset].status = IRQ_LEVEL;
477 }
478 625
479 temp = 0; 626 printk ("IPIC (%d IRQ sources) at %p\n", NR_IPIC_INTS,
480 for (i = 0 ; i < senses_count ; i++) { 627 primary_ipic->regs);
481 if ((senses[i] & IRQ_SENSE_MASK) == IRQ_SENSE_EDGE) {
482 temp |= 1 << (15 - i);
483 if (i != 0)
484 irq_desc[i + irq_offset + MPC83xx_IRQ_EXT1 - 1].status = 0;
485 else
486 irq_desc[irq_offset + MPC83xx_IRQ_EXT0].status = 0;
487 }
488 }
489 ipic_write(primary_ipic->regs, IPIC_SECNR, temp);
490
491 printk ("IPIC (%d IRQ sources, %d External IRQs) at %p\n", NR_IPIC_INTS,
492 senses_count, primary_ipic->regs);
493} 628}
494 629
495int ipic_set_priority(unsigned int irq, unsigned int priority) 630int ipic_set_priority(unsigned int virq, unsigned int priority)
496{ 631{
497 struct ipic *ipic = ipic_from_irq(irq); 632 struct ipic *ipic = ipic_from_irq(virq);
498 unsigned int src = irq - ipic->irq_offset; 633 unsigned int src = ipic_irq_to_hw(virq);
499 u32 temp; 634 u32 temp;
500 635
501 if (priority > 7) 636 if (priority > 7)
@@ -520,10 +655,10 @@ int ipic_set_priority(unsigned int irq, unsigned int priority)
520 return 0; 655 return 0;
521} 656}
522 657
523void ipic_set_highest_priority(unsigned int irq) 658void ipic_set_highest_priority(unsigned int virq)
524{ 659{
525 struct ipic *ipic = ipic_from_irq(irq); 660 struct ipic *ipic = ipic_from_irq(virq);
526 unsigned int src = irq - ipic->irq_offset; 661 unsigned int src = ipic_irq_to_hw(virq);
527 u32 temp; 662 u32 temp;
528 663
529 temp = ipic_read(ipic->regs, IPIC_SICFR); 664 temp = ipic_read(ipic->regs, IPIC_SICFR);
@@ -537,37 +672,10 @@ void ipic_set_highest_priority(unsigned int irq)
537 672
538void ipic_set_default_priority(void) 673void ipic_set_default_priority(void)
539{ 674{
540 ipic_set_priority(MPC83xx_IRQ_TSEC1_TX, 0); 675 ipic_write(primary_ipic->regs, IPIC_SIPRR_A, IPIC_SIPRR_A_DEFAULT);
541 ipic_set_priority(MPC83xx_IRQ_TSEC1_RX, 1); 676 ipic_write(primary_ipic->regs, IPIC_SIPRR_D, IPIC_SIPRR_D_DEFAULT);
542 ipic_set_priority(MPC83xx_IRQ_TSEC1_ERROR, 2); 677 ipic_write(primary_ipic->regs, IPIC_SMPRR_A, IPIC_SMPRR_A_DEFAULT);
543 ipic_set_priority(MPC83xx_IRQ_TSEC2_TX, 3); 678 ipic_write(primary_ipic->regs, IPIC_SMPRR_B, IPIC_SMPRR_B_DEFAULT);
544 ipic_set_priority(MPC83xx_IRQ_TSEC2_RX, 4);
545 ipic_set_priority(MPC83xx_IRQ_TSEC2_ERROR, 5);
546 ipic_set_priority(MPC83xx_IRQ_USB2_DR, 6);
547 ipic_set_priority(MPC83xx_IRQ_USB2_MPH, 7);
548
549 ipic_set_priority(MPC83xx_IRQ_UART1, 0);
550 ipic_set_priority(MPC83xx_IRQ_UART2, 1);
551 ipic_set_priority(MPC83xx_IRQ_SEC2, 2);
552 ipic_set_priority(MPC83xx_IRQ_IIC1, 5);
553 ipic_set_priority(MPC83xx_IRQ_IIC2, 6);
554 ipic_set_priority(MPC83xx_IRQ_SPI, 7);
555 ipic_set_priority(MPC83xx_IRQ_RTC_SEC, 0);
556 ipic_set_priority(MPC83xx_IRQ_PIT, 1);
557 ipic_set_priority(MPC83xx_IRQ_PCI1, 2);
558 ipic_set_priority(MPC83xx_IRQ_PCI2, 3);
559 ipic_set_priority(MPC83xx_IRQ_EXT0, 4);
560 ipic_set_priority(MPC83xx_IRQ_EXT1, 5);
561 ipic_set_priority(MPC83xx_IRQ_EXT2, 6);
562 ipic_set_priority(MPC83xx_IRQ_EXT3, 7);
563 ipic_set_priority(MPC83xx_IRQ_RTC_ALR, 0);
564 ipic_set_priority(MPC83xx_IRQ_MU, 1);
565 ipic_set_priority(MPC83xx_IRQ_SBA, 2);
566 ipic_set_priority(MPC83xx_IRQ_DMA, 3);
567 ipic_set_priority(MPC83xx_IRQ_EXT4, 4);
568 ipic_set_priority(MPC83xx_IRQ_EXT5, 5);
569 ipic_set_priority(MPC83xx_IRQ_EXT6, 6);
570 ipic_set_priority(MPC83xx_IRQ_EXT7, 7);
571} 679}
572 680
573void ipic_enable_mcp(enum ipic_mcp_irq mcp_irq) 681void ipic_enable_mcp(enum ipic_mcp_irq mcp_irq)
@@ -600,17 +708,20 @@ void ipic_clear_mcp_status(u32 mask)
600 ipic_write(primary_ipic->regs, IPIC_SERMR, mask); 708 ipic_write(primary_ipic->regs, IPIC_SERMR, mask);
601} 709}
602 710
603/* Return an interrupt vector or -1 if no interrupt is pending. */ 711/* Return an interrupt vector or NO_IRQ if no interrupt is pending. */
604int ipic_get_irq(struct pt_regs *regs) 712unsigned int ipic_get_irq(struct pt_regs *regs)
605{ 713{
606 int irq; 714 int irq;
607 715
608 irq = ipic_read(primary_ipic->regs, IPIC_SIVCR) & 0x7f; 716 BUG_ON(primary_ipic == NULL);
717
718#define IPIC_SIVCR_VECTOR_MASK 0x7f
719 irq = ipic_read(primary_ipic->regs, IPIC_SIVCR) & IPIC_SIVCR_VECTOR_MASK;
609 720
610 if (irq == 0) /* 0 --> no irq is pending */ 721 if (irq == 0) /* 0 --> no irq is pending */
611 irq = -1; 722 return NO_IRQ;
612 723
613 return irq; 724 return irq_linear_revmap(primary_ipic->irqhost, irq);
614} 725}
615 726
616static struct sysdev_class ipic_sysclass = { 727static struct sysdev_class ipic_sysclass = {
diff --git a/arch/powerpc/sysdev/ipic.h b/arch/powerpc/sysdev/ipic.h
index a60c9d18bb7f..c28e589877eb 100644
--- a/arch/powerpc/sysdev/ipic.h
+++ b/arch/powerpc/sysdev/ipic.h
@@ -15,7 +15,18 @@
15 15
16#include <asm/ipic.h> 16#include <asm/ipic.h>
17 17
18#define MPC83xx_IPIC_SIZE (0x00100) 18#define NR_IPIC_INTS 128
19
20/* External IRQS */
21#define IPIC_IRQ_EXT0 48
22#define IPIC_IRQ_EXT1 17
23#define IPIC_IRQ_EXT7 23
24
25/* Default Priority Registers */
26#define IPIC_SIPRR_A_DEFAULT 0x05309770
27#define IPIC_SIPRR_D_DEFAULT 0x05309770
28#define IPIC_SMPRR_A_DEFAULT 0x05309770
29#define IPIC_SMPRR_B_DEFAULT 0x05309770
19 30
20/* System Global Interrupt Configuration Register */ 31/* System Global Interrupt Configuration Register */
21#define SICFR_IPSA 0x00010000 32#define SICFR_IPSA 0x00010000
@@ -31,7 +42,15 @@
31 42
32struct ipic { 43struct ipic {
33 volatile u32 __iomem *regs; 44 volatile u32 __iomem *regs;
34 unsigned int irq_offset; 45
46 /* The remapper for this IPIC */
47 struct irq_host *irqhost;
48
49 /* The "linux" controller struct */
50 struct irq_chip hc_irq;
51
52 /* The device node of the interrupt controller */
53 struct device_node *of_node;
35}; 54};
36 55
37struct ipic_info { 56struct ipic_info {
diff --git a/arch/powerpc/sysdev/mpic.c b/arch/powerpc/sysdev/mpic.c
index 6e0281afa6c3..b604926401f5 100644
--- a/arch/powerpc/sysdev/mpic.c
+++ b/arch/powerpc/sysdev/mpic.c
@@ -54,6 +54,94 @@ static DEFINE_SPINLOCK(mpic_lock);
54#endif 54#endif
55#endif 55#endif
56 56
57#ifdef CONFIG_MPIC_WEIRD
58static u32 mpic_infos[][MPIC_IDX_END] = {
59 [0] = { /* Original OpenPIC compatible MPIC */
60 MPIC_GREG_BASE,
61 MPIC_GREG_FEATURE_0,
62 MPIC_GREG_GLOBAL_CONF_0,
63 MPIC_GREG_VENDOR_ID,
64 MPIC_GREG_IPI_VECTOR_PRI_0,
65 MPIC_GREG_IPI_STRIDE,
66 MPIC_GREG_SPURIOUS,
67 MPIC_GREG_TIMER_FREQ,
68
69 MPIC_TIMER_BASE,
70 MPIC_TIMER_STRIDE,
71 MPIC_TIMER_CURRENT_CNT,
72 MPIC_TIMER_BASE_CNT,
73 MPIC_TIMER_VECTOR_PRI,
74 MPIC_TIMER_DESTINATION,
75
76 MPIC_CPU_BASE,
77 MPIC_CPU_STRIDE,
78 MPIC_CPU_IPI_DISPATCH_0,
79 MPIC_CPU_IPI_DISPATCH_STRIDE,
80 MPIC_CPU_CURRENT_TASK_PRI,
81 MPIC_CPU_WHOAMI,
82 MPIC_CPU_INTACK,
83 MPIC_CPU_EOI,
84
85 MPIC_IRQ_BASE,
86 MPIC_IRQ_STRIDE,
87 MPIC_IRQ_VECTOR_PRI,
88 MPIC_VECPRI_VECTOR_MASK,
89 MPIC_VECPRI_POLARITY_POSITIVE,
90 MPIC_VECPRI_POLARITY_NEGATIVE,
91 MPIC_VECPRI_SENSE_LEVEL,
92 MPIC_VECPRI_SENSE_EDGE,
93 MPIC_VECPRI_POLARITY_MASK,
94 MPIC_VECPRI_SENSE_MASK,
95 MPIC_IRQ_DESTINATION
96 },
97 [1] = { /* Tsi108/109 PIC */
98 TSI108_GREG_BASE,
99 TSI108_GREG_FEATURE_0,
100 TSI108_GREG_GLOBAL_CONF_0,
101 TSI108_GREG_VENDOR_ID,
102 TSI108_GREG_IPI_VECTOR_PRI_0,
103 TSI108_GREG_IPI_STRIDE,
104 TSI108_GREG_SPURIOUS,
105 TSI108_GREG_TIMER_FREQ,
106
107 TSI108_TIMER_BASE,
108 TSI108_TIMER_STRIDE,
109 TSI108_TIMER_CURRENT_CNT,
110 TSI108_TIMER_BASE_CNT,
111 TSI108_TIMER_VECTOR_PRI,
112 TSI108_TIMER_DESTINATION,
113
114 TSI108_CPU_BASE,
115 TSI108_CPU_STRIDE,
116 TSI108_CPU_IPI_DISPATCH_0,
117 TSI108_CPU_IPI_DISPATCH_STRIDE,
118 TSI108_CPU_CURRENT_TASK_PRI,
119 TSI108_CPU_WHOAMI,
120 TSI108_CPU_INTACK,
121 TSI108_CPU_EOI,
122
123 TSI108_IRQ_BASE,
124 TSI108_IRQ_STRIDE,
125 TSI108_IRQ_VECTOR_PRI,
126 TSI108_VECPRI_VECTOR_MASK,
127 TSI108_VECPRI_POLARITY_POSITIVE,
128 TSI108_VECPRI_POLARITY_NEGATIVE,
129 TSI108_VECPRI_SENSE_LEVEL,
130 TSI108_VECPRI_SENSE_EDGE,
131 TSI108_VECPRI_POLARITY_MASK,
132 TSI108_VECPRI_SENSE_MASK,
133 TSI108_IRQ_DESTINATION
134 },
135};
136
137#define MPIC_INFO(name) mpic->hw_set[MPIC_IDX_##name]
138
139#else /* CONFIG_MPIC_WEIRD */
140
141#define MPIC_INFO(name) MPIC_##name
142
143#endif /* CONFIG_MPIC_WEIRD */
144
57/* 145/*
58 * Register accessor functions 146 * Register accessor functions
59 */ 147 */
@@ -80,7 +168,8 @@ static inline void _mpic_write(unsigned int be, volatile u32 __iomem *base,
80static inline u32 _mpic_ipi_read(struct mpic *mpic, unsigned int ipi) 168static inline u32 _mpic_ipi_read(struct mpic *mpic, unsigned int ipi)
81{ 169{
82 unsigned int be = (mpic->flags & MPIC_BIG_ENDIAN) != 0; 170 unsigned int be = (mpic->flags & MPIC_BIG_ENDIAN) != 0;
83 unsigned int offset = MPIC_GREG_IPI_VECTOR_PRI_0 + (ipi * 0x10); 171 unsigned int offset = MPIC_INFO(GREG_IPI_VECTOR_PRI_0) +
172 (ipi * MPIC_INFO(GREG_IPI_STRIDE));
84 173
85 if (mpic->flags & MPIC_BROKEN_IPI) 174 if (mpic->flags & MPIC_BROKEN_IPI)
86 be = !be; 175 be = !be;
@@ -89,7 +178,8 @@ static inline u32 _mpic_ipi_read(struct mpic *mpic, unsigned int ipi)
89 178
90static inline void _mpic_ipi_write(struct mpic *mpic, unsigned int ipi, u32 value) 179static inline void _mpic_ipi_write(struct mpic *mpic, unsigned int ipi, u32 value)
91{ 180{
92 unsigned int offset = MPIC_GREG_IPI_VECTOR_PRI_0 + (ipi * 0x10); 181 unsigned int offset = MPIC_INFO(GREG_IPI_VECTOR_PRI_0) +
182 (ipi * MPIC_INFO(GREG_IPI_STRIDE));
93 183
94 _mpic_write(mpic->flags & MPIC_BIG_ENDIAN, mpic->gregs, offset, value); 184 _mpic_write(mpic->flags & MPIC_BIG_ENDIAN, mpic->gregs, offset, value);
95} 185}
@@ -120,7 +210,7 @@ static inline u32 _mpic_irq_read(struct mpic *mpic, unsigned int src_no, unsigne
120 unsigned int idx = src_no & mpic->isu_mask; 210 unsigned int idx = src_no & mpic->isu_mask;
121 211
122 return _mpic_read(mpic->flags & MPIC_BIG_ENDIAN, mpic->isus[isu], 212 return _mpic_read(mpic->flags & MPIC_BIG_ENDIAN, mpic->isus[isu],
123 reg + (idx * MPIC_IRQ_STRIDE)); 213 reg + (idx * MPIC_INFO(IRQ_STRIDE)));
124} 214}
125 215
126static inline void _mpic_irq_write(struct mpic *mpic, unsigned int src_no, 216static inline void _mpic_irq_write(struct mpic *mpic, unsigned int src_no,
@@ -130,7 +220,7 @@ static inline void _mpic_irq_write(struct mpic *mpic, unsigned int src_no,
130 unsigned int idx = src_no & mpic->isu_mask; 220 unsigned int idx = src_no & mpic->isu_mask;
131 221
132 _mpic_write(mpic->flags & MPIC_BIG_ENDIAN, mpic->isus[isu], 222 _mpic_write(mpic->flags & MPIC_BIG_ENDIAN, mpic->isus[isu],
133 reg + (idx * MPIC_IRQ_STRIDE), value); 223 reg + (idx * MPIC_INFO(IRQ_STRIDE)), value);
134} 224}
135 225
136#define mpic_read(b,r) _mpic_read(mpic->flags & MPIC_BIG_ENDIAN,(b),(r)) 226#define mpic_read(b,r) _mpic_read(mpic->flags & MPIC_BIG_ENDIAN,(b),(r))
@@ -156,8 +246,8 @@ static void __init mpic_test_broken_ipi(struct mpic *mpic)
156{ 246{
157 u32 r; 247 u32 r;
158 248
159 mpic_write(mpic->gregs, MPIC_GREG_IPI_VECTOR_PRI_0, MPIC_VECPRI_MASK); 249 mpic_write(mpic->gregs, MPIC_INFO(GREG_IPI_VECTOR_PRI_0), MPIC_VECPRI_MASK);
160 r = mpic_read(mpic->gregs, MPIC_GREG_IPI_VECTOR_PRI_0); 250 r = mpic_read(mpic->gregs, MPIC_INFO(GREG_IPI_VECTOR_PRI_0));
161 251
162 if (r == le32_to_cpu(MPIC_VECPRI_MASK)) { 252 if (r == le32_to_cpu(MPIC_VECPRI_MASK)) {
163 printk(KERN_INFO "mpic: Detected reversed IPI registers\n"); 253 printk(KERN_INFO "mpic: Detected reversed IPI registers\n");
@@ -394,8 +484,8 @@ static inline struct mpic * mpic_from_irq(unsigned int irq)
394/* Send an EOI */ 484/* Send an EOI */
395static inline void mpic_eoi(struct mpic *mpic) 485static inline void mpic_eoi(struct mpic *mpic)
396{ 486{
397 mpic_cpu_write(MPIC_CPU_EOI, 0); 487 mpic_cpu_write(MPIC_INFO(CPU_EOI), 0);
398 (void)mpic_cpu_read(MPIC_CPU_WHOAMI); 488 (void)mpic_cpu_read(MPIC_INFO(CPU_WHOAMI));
399} 489}
400 490
401#ifdef CONFIG_SMP 491#ifdef CONFIG_SMP
@@ -419,8 +509,8 @@ static void mpic_unmask_irq(unsigned int irq)
419 509
420 DBG("%p: %s: enable_irq: %d (src %d)\n", mpic, mpic->name, irq, src); 510 DBG("%p: %s: enable_irq: %d (src %d)\n", mpic, mpic->name, irq, src);
421 511
422 mpic_irq_write(src, MPIC_IRQ_VECTOR_PRI, 512 mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI),
423 mpic_irq_read(src, MPIC_IRQ_VECTOR_PRI) & 513 mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) &
424 ~MPIC_VECPRI_MASK); 514 ~MPIC_VECPRI_MASK);
425 /* make sure mask gets to controller before we return to user */ 515 /* make sure mask gets to controller before we return to user */
426 do { 516 do {
@@ -428,7 +518,7 @@ static void mpic_unmask_irq(unsigned int irq)
428 printk(KERN_ERR "mpic_enable_irq timeout\n"); 518 printk(KERN_ERR "mpic_enable_irq timeout\n");
429 break; 519 break;
430 } 520 }
431 } while(mpic_irq_read(src, MPIC_IRQ_VECTOR_PRI) & MPIC_VECPRI_MASK); 521 } while(mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) & MPIC_VECPRI_MASK);
432} 522}
433 523
434static void mpic_mask_irq(unsigned int irq) 524static void mpic_mask_irq(unsigned int irq)
@@ -439,8 +529,8 @@ static void mpic_mask_irq(unsigned int irq)
439 529
440 DBG("%s: disable_irq: %d (src %d)\n", mpic->name, irq, src); 530 DBG("%s: disable_irq: %d (src %d)\n", mpic->name, irq, src);
441 531
442 mpic_irq_write(src, MPIC_IRQ_VECTOR_PRI, 532 mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI),
443 mpic_irq_read(src, MPIC_IRQ_VECTOR_PRI) | 533 mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) |
444 MPIC_VECPRI_MASK); 534 MPIC_VECPRI_MASK);
445 535
446 /* make sure mask gets to controller before we return to user */ 536 /* make sure mask gets to controller before we return to user */
@@ -449,7 +539,7 @@ static void mpic_mask_irq(unsigned int irq)
449 printk(KERN_ERR "mpic_enable_irq timeout\n"); 539 printk(KERN_ERR "mpic_enable_irq timeout\n");
450 break; 540 break;
451 } 541 }
452 } while(!(mpic_irq_read(src, MPIC_IRQ_VECTOR_PRI) & MPIC_VECPRI_MASK)); 542 } while(!(mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) & MPIC_VECPRI_MASK));
453} 543}
454 544
455static void mpic_end_irq(unsigned int irq) 545static void mpic_end_irq(unsigned int irq)
@@ -560,24 +650,28 @@ static void mpic_set_affinity(unsigned int irq, cpumask_t cpumask)
560 650
561 cpus_and(tmp, cpumask, cpu_online_map); 651 cpus_and(tmp, cpumask, cpu_online_map);
562 652
563 mpic_irq_write(src, MPIC_IRQ_DESTINATION, 653 mpic_irq_write(src, MPIC_INFO(IRQ_DESTINATION),
564 mpic_physmask(cpus_addr(tmp)[0])); 654 mpic_physmask(cpus_addr(tmp)[0]));
565} 655}
566 656
567static unsigned int mpic_type_to_vecpri(unsigned int type) 657static unsigned int mpic_type_to_vecpri(struct mpic *mpic, unsigned int type)
568{ 658{
569 /* Now convert sense value */ 659 /* Now convert sense value */
570 switch(type & IRQ_TYPE_SENSE_MASK) { 660 switch(type & IRQ_TYPE_SENSE_MASK) {
571 case IRQ_TYPE_EDGE_RISING: 661 case IRQ_TYPE_EDGE_RISING:
572 return MPIC_VECPRI_SENSE_EDGE | MPIC_VECPRI_POLARITY_POSITIVE; 662 return MPIC_INFO(VECPRI_SENSE_EDGE) |
663 MPIC_INFO(VECPRI_POLARITY_POSITIVE);
573 case IRQ_TYPE_EDGE_FALLING: 664 case IRQ_TYPE_EDGE_FALLING:
574 case IRQ_TYPE_EDGE_BOTH: 665 case IRQ_TYPE_EDGE_BOTH:
575 return MPIC_VECPRI_SENSE_EDGE | MPIC_VECPRI_POLARITY_NEGATIVE; 666 return MPIC_INFO(VECPRI_SENSE_EDGE) |
667 MPIC_INFO(VECPRI_POLARITY_NEGATIVE);
576 case IRQ_TYPE_LEVEL_HIGH: 668 case IRQ_TYPE_LEVEL_HIGH:
577 return MPIC_VECPRI_SENSE_LEVEL | MPIC_VECPRI_POLARITY_POSITIVE; 669 return MPIC_INFO(VECPRI_SENSE_LEVEL) |
670 MPIC_INFO(VECPRI_POLARITY_POSITIVE);
578 case IRQ_TYPE_LEVEL_LOW: 671 case IRQ_TYPE_LEVEL_LOW:
579 default: 672 default:
580 return MPIC_VECPRI_SENSE_LEVEL | MPIC_VECPRI_POLARITY_NEGATIVE; 673 return MPIC_INFO(VECPRI_SENSE_LEVEL) |
674 MPIC_INFO(VECPRI_POLARITY_NEGATIVE);
581 } 675 }
582} 676}
583 677
@@ -609,13 +703,14 @@ static int mpic_set_irq_type(unsigned int virq, unsigned int flow_type)
609 vecpri = MPIC_VECPRI_POLARITY_POSITIVE | 703 vecpri = MPIC_VECPRI_POLARITY_POSITIVE |
610 MPIC_VECPRI_SENSE_EDGE; 704 MPIC_VECPRI_SENSE_EDGE;
611 else 705 else
612 vecpri = mpic_type_to_vecpri(flow_type); 706 vecpri = mpic_type_to_vecpri(mpic, flow_type);
613 707
614 vold = mpic_irq_read(src, MPIC_IRQ_VECTOR_PRI); 708 vold = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI));
615 vnew = vold & ~(MPIC_VECPRI_POLARITY_MASK | MPIC_VECPRI_SENSE_MASK); 709 vnew = vold & ~(MPIC_INFO(VECPRI_POLARITY_MASK) |
710 MPIC_INFO(VECPRI_SENSE_MASK));
616 vnew |= vecpri; 711 vnew |= vecpri;
617 if (vold != vnew) 712 if (vold != vnew)
618 mpic_irq_write(src, MPIC_IRQ_VECTOR_PRI, vnew); 713 mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI), vnew);
619 714
620 return 0; 715 return 0;
621} 716}
@@ -798,17 +893,22 @@ struct mpic * __init mpic_alloc(struct device_node *node,
798 mpic->irq_count = irq_count; 893 mpic->irq_count = irq_count;
799 mpic->num_sources = 0; /* so far */ 894 mpic->num_sources = 0; /* so far */
800 895
896#ifdef CONFIG_MPIC_WEIRD
897 mpic->hw_set = mpic_infos[MPIC_GET_REGSET(flags)];
898#endif
899
801 /* Map the global registers */ 900 /* Map the global registers */
802 mpic->gregs = ioremap(phys_addr + MPIC_GREG_BASE, 0x1000); 901 mpic->gregs = ioremap(phys_addr + MPIC_INFO(GREG_BASE), 0x1000);
803 mpic->tmregs = mpic->gregs + ((MPIC_TIMER_BASE - MPIC_GREG_BASE) >> 2); 902 mpic->tmregs = mpic->gregs +
903 ((MPIC_INFO(TIMER_BASE) - MPIC_INFO(GREG_BASE)) >> 2);
804 BUG_ON(mpic->gregs == NULL); 904 BUG_ON(mpic->gregs == NULL);
805 905
806 /* Reset */ 906 /* Reset */
807 if (flags & MPIC_WANTS_RESET) { 907 if (flags & MPIC_WANTS_RESET) {
808 mpic_write(mpic->gregs, MPIC_GREG_GLOBAL_CONF_0, 908 mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
809 mpic_read(mpic->gregs, MPIC_GREG_GLOBAL_CONF_0) 909 mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
810 | MPIC_GREG_GCONF_RESET); 910 | MPIC_GREG_GCONF_RESET);
811 while( mpic_read(mpic->gregs, MPIC_GREG_GLOBAL_CONF_0) 911 while( mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
812 & MPIC_GREG_GCONF_RESET) 912 & MPIC_GREG_GCONF_RESET)
813 mb(); 913 mb();
814 } 914 }
@@ -817,7 +917,7 @@ struct mpic * __init mpic_alloc(struct device_node *node,
817 * MPICs, num sources as well. On ISU MPICs, sources are counted 917 * MPICs, num sources as well. On ISU MPICs, sources are counted
818 * as ISUs are added 918 * as ISUs are added
819 */ 919 */
820 reg = mpic_read(mpic->gregs, MPIC_GREG_FEATURE_0); 920 reg = mpic_read(mpic->gregs, MPIC_INFO(GREG_FEATURE_0));
821 mpic->num_cpus = ((reg & MPIC_GREG_FEATURE_LAST_CPU_MASK) 921 mpic->num_cpus = ((reg & MPIC_GREG_FEATURE_LAST_CPU_MASK)
822 >> MPIC_GREG_FEATURE_LAST_CPU_SHIFT) + 1; 922 >> MPIC_GREG_FEATURE_LAST_CPU_SHIFT) + 1;
823 if (isu_size == 0) 923 if (isu_size == 0)
@@ -826,16 +926,16 @@ struct mpic * __init mpic_alloc(struct device_node *node,
826 926
827 /* Map the per-CPU registers */ 927 /* Map the per-CPU registers */
828 for (i = 0; i < mpic->num_cpus; i++) { 928 for (i = 0; i < mpic->num_cpus; i++) {
829 mpic->cpuregs[i] = ioremap(phys_addr + MPIC_CPU_BASE + 929 mpic->cpuregs[i] = ioremap(phys_addr + MPIC_INFO(CPU_BASE) +
830 i * MPIC_CPU_STRIDE, 0x1000); 930 i * MPIC_INFO(CPU_STRIDE), 0x1000);
831 BUG_ON(mpic->cpuregs[i] == NULL); 931 BUG_ON(mpic->cpuregs[i] == NULL);
832 } 932 }
833 933
834 /* Initialize main ISU if none provided */ 934 /* Initialize main ISU if none provided */
835 if (mpic->isu_size == 0) { 935 if (mpic->isu_size == 0) {
836 mpic->isu_size = mpic->num_sources; 936 mpic->isu_size = mpic->num_sources;
837 mpic->isus[0] = ioremap(phys_addr + MPIC_IRQ_BASE, 937 mpic->isus[0] = ioremap(phys_addr + MPIC_INFO(IRQ_BASE),
838 MPIC_IRQ_STRIDE * mpic->isu_size); 938 MPIC_INFO(IRQ_STRIDE) * mpic->isu_size);
839 BUG_ON(mpic->isus[0] == NULL); 939 BUG_ON(mpic->isus[0] == NULL);
840 } 940 }
841 mpic->isu_shift = 1 + __ilog2(mpic->isu_size - 1); 941 mpic->isu_shift = 1 + __ilog2(mpic->isu_size - 1);
@@ -879,7 +979,8 @@ void __init mpic_assign_isu(struct mpic *mpic, unsigned int isu_num,
879 979
880 BUG_ON(isu_num >= MPIC_MAX_ISU); 980 BUG_ON(isu_num >= MPIC_MAX_ISU);
881 981
882 mpic->isus[isu_num] = ioremap(phys_addr, MPIC_IRQ_STRIDE * mpic->isu_size); 982 mpic->isus[isu_num] = ioremap(phys_addr,
983 MPIC_INFO(IRQ_STRIDE) * mpic->isu_size);
883 if ((isu_first + mpic->isu_size) > mpic->num_sources) 984 if ((isu_first + mpic->isu_size) > mpic->num_sources)
884 mpic->num_sources = isu_first + mpic->isu_size; 985 mpic->num_sources = isu_first + mpic->isu_size;
885} 986}
@@ -904,14 +1005,16 @@ void __init mpic_init(struct mpic *mpic)
904 printk(KERN_INFO "mpic: Initializing for %d sources\n", mpic->num_sources); 1005 printk(KERN_INFO "mpic: Initializing for %d sources\n", mpic->num_sources);
905 1006
906 /* Set current processor priority to max */ 1007 /* Set current processor priority to max */
907 mpic_cpu_write(MPIC_CPU_CURRENT_TASK_PRI, 0xf); 1008 mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0xf);
908 1009
909 /* Initialize timers: just disable them all */ 1010 /* Initialize timers: just disable them all */
910 for (i = 0; i < 4; i++) { 1011 for (i = 0; i < 4; i++) {
911 mpic_write(mpic->tmregs, 1012 mpic_write(mpic->tmregs,
912 i * MPIC_TIMER_STRIDE + MPIC_TIMER_DESTINATION, 0); 1013 i * MPIC_INFO(TIMER_STRIDE) +
1014 MPIC_INFO(TIMER_DESTINATION), 0);
913 mpic_write(mpic->tmregs, 1015 mpic_write(mpic->tmregs,
914 i * MPIC_TIMER_STRIDE + MPIC_TIMER_VECTOR_PRI, 1016 i * MPIC_INFO(TIMER_STRIDE) +
1017 MPIC_INFO(TIMER_VECTOR_PRI),
915 MPIC_VECPRI_MASK | 1018 MPIC_VECPRI_MASK |
916 (MPIC_VEC_TIMER_0 + i)); 1019 (MPIC_VEC_TIMER_0 + i));
917 } 1020 }
@@ -940,21 +1043,22 @@ void __init mpic_init(struct mpic *mpic)
940 (8 << MPIC_VECPRI_PRIORITY_SHIFT); 1043 (8 << MPIC_VECPRI_PRIORITY_SHIFT);
941 1044
942 /* init hw */ 1045 /* init hw */
943 mpic_irq_write(i, MPIC_IRQ_VECTOR_PRI, vecpri); 1046 mpic_irq_write(i, MPIC_INFO(IRQ_VECTOR_PRI), vecpri);
944 mpic_irq_write(i, MPIC_IRQ_DESTINATION, 1047 mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION),
945 1 << hard_smp_processor_id()); 1048 1 << hard_smp_processor_id());
946 } 1049 }
947 1050
948 /* Init spurrious vector */ 1051 /* Init spurrious vector */
949 mpic_write(mpic->gregs, MPIC_GREG_SPURIOUS, MPIC_VEC_SPURRIOUS); 1052 mpic_write(mpic->gregs, MPIC_INFO(GREG_SPURIOUS), MPIC_VEC_SPURRIOUS);
950 1053
951 /* Disable 8259 passthrough */ 1054 /* Disable 8259 passthrough, if supported */
952 mpic_write(mpic->gregs, MPIC_GREG_GLOBAL_CONF_0, 1055 if (!(mpic->flags & MPIC_NO_PTHROU_DIS))
953 mpic_read(mpic->gregs, MPIC_GREG_GLOBAL_CONF_0) 1056 mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
954 | MPIC_GREG_GCONF_8259_PTHROU_DIS); 1057 mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
1058 | MPIC_GREG_GCONF_8259_PTHROU_DIS);
955 1059
956 /* Set current processor priority to 0 */ 1060 /* Set current processor priority to 0 */
957 mpic_cpu_write(MPIC_CPU_CURRENT_TASK_PRI, 0); 1061 mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0);
958} 1062}
959 1063
960void __init mpic_set_clk_ratio(struct mpic *mpic, u32 clock_ratio) 1064void __init mpic_set_clk_ratio(struct mpic *mpic, u32 clock_ratio)
@@ -997,9 +1101,9 @@ void mpic_irq_set_priority(unsigned int irq, unsigned int pri)
997 mpic_ipi_write(src - MPIC_VEC_IPI_0, 1101 mpic_ipi_write(src - MPIC_VEC_IPI_0,
998 reg | (pri << MPIC_VECPRI_PRIORITY_SHIFT)); 1102 reg | (pri << MPIC_VECPRI_PRIORITY_SHIFT));
999 } else { 1103 } else {
1000 reg = mpic_irq_read(src, MPIC_IRQ_VECTOR_PRI) 1104 reg = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI))
1001 & ~MPIC_VECPRI_PRIORITY_MASK; 1105 & ~MPIC_VECPRI_PRIORITY_MASK;
1002 mpic_irq_write(src, MPIC_IRQ_VECTOR_PRI, 1106 mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI),
1003 reg | (pri << MPIC_VECPRI_PRIORITY_SHIFT)); 1107 reg | (pri << MPIC_VECPRI_PRIORITY_SHIFT));
1004 } 1108 }
1005 spin_unlock_irqrestore(&mpic_lock, flags); 1109 spin_unlock_irqrestore(&mpic_lock, flags);
@@ -1017,7 +1121,7 @@ unsigned int mpic_irq_get_priority(unsigned int irq)
1017 if (is_ipi) 1121 if (is_ipi)
1018 reg = mpic_ipi_read(src = MPIC_VEC_IPI_0); 1122 reg = mpic_ipi_read(src = MPIC_VEC_IPI_0);
1019 else 1123 else
1020 reg = mpic_irq_read(src, MPIC_IRQ_VECTOR_PRI); 1124 reg = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI));
1021 spin_unlock_irqrestore(&mpic_lock, flags); 1125 spin_unlock_irqrestore(&mpic_lock, flags);
1022 return (reg & MPIC_VECPRI_PRIORITY_MASK) >> MPIC_VECPRI_PRIORITY_SHIFT; 1126 return (reg & MPIC_VECPRI_PRIORITY_MASK) >> MPIC_VECPRI_PRIORITY_SHIFT;
1023} 1127}
@@ -1043,12 +1147,12 @@ void mpic_setup_this_cpu(void)
1043 */ 1147 */
1044 if (distribute_irqs) { 1148 if (distribute_irqs) {
1045 for (i = 0; i < mpic->num_sources ; i++) 1149 for (i = 0; i < mpic->num_sources ; i++)
1046 mpic_irq_write(i, MPIC_IRQ_DESTINATION, 1150 mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION),
1047 mpic_irq_read(i, MPIC_IRQ_DESTINATION) | msk); 1151 mpic_irq_read(i, MPIC_INFO(IRQ_DESTINATION)) | msk);
1048 } 1152 }
1049 1153
1050 /* Set current processor priority to 0 */ 1154 /* Set current processor priority to 0 */
1051 mpic_cpu_write(MPIC_CPU_CURRENT_TASK_PRI, 0); 1155 mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0);
1052 1156
1053 spin_unlock_irqrestore(&mpic_lock, flags); 1157 spin_unlock_irqrestore(&mpic_lock, flags);
1054#endif /* CONFIG_SMP */ 1158#endif /* CONFIG_SMP */
@@ -1058,7 +1162,7 @@ int mpic_cpu_get_priority(void)
1058{ 1162{
1059 struct mpic *mpic = mpic_primary; 1163 struct mpic *mpic = mpic_primary;
1060 1164
1061 return mpic_cpu_read(MPIC_CPU_CURRENT_TASK_PRI); 1165 return mpic_cpu_read(MPIC_INFO(CPU_CURRENT_TASK_PRI));
1062} 1166}
1063 1167
1064void mpic_cpu_set_priority(int prio) 1168void mpic_cpu_set_priority(int prio)
@@ -1066,7 +1170,7 @@ void mpic_cpu_set_priority(int prio)
1066 struct mpic *mpic = mpic_primary; 1170 struct mpic *mpic = mpic_primary;
1067 1171
1068 prio &= MPIC_CPU_TASKPRI_MASK; 1172 prio &= MPIC_CPU_TASKPRI_MASK;
1069 mpic_cpu_write(MPIC_CPU_CURRENT_TASK_PRI, prio); 1173 mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), prio);
1070} 1174}
1071 1175
1072/* 1176/*
@@ -1088,11 +1192,11 @@ void mpic_teardown_this_cpu(int secondary)
1088 1192
1089 /* let the mpic know we don't want intrs. */ 1193 /* let the mpic know we don't want intrs. */
1090 for (i = 0; i < mpic->num_sources ; i++) 1194 for (i = 0; i < mpic->num_sources ; i++)
1091 mpic_irq_write(i, MPIC_IRQ_DESTINATION, 1195 mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION),
1092 mpic_irq_read(i, MPIC_IRQ_DESTINATION) & ~msk); 1196 mpic_irq_read(i, MPIC_INFO(IRQ_DESTINATION)) & ~msk);
1093 1197
1094 /* Set current processor priority to max */ 1198 /* Set current processor priority to max */
1095 mpic_cpu_write(MPIC_CPU_CURRENT_TASK_PRI, 0xf); 1199 mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0xf);
1096 1200
1097 spin_unlock_irqrestore(&mpic_lock, flags); 1201 spin_unlock_irqrestore(&mpic_lock, flags);
1098} 1202}
@@ -1108,7 +1212,8 @@ void mpic_send_ipi(unsigned int ipi_no, unsigned int cpu_mask)
1108 DBG("%s: send_ipi(ipi_no: %d)\n", mpic->name, ipi_no); 1212 DBG("%s: send_ipi(ipi_no: %d)\n", mpic->name, ipi_no);
1109#endif 1213#endif
1110 1214
1111 mpic_cpu_write(MPIC_CPU_IPI_DISPATCH_0 + ipi_no * 0x10, 1215 mpic_cpu_write(MPIC_INFO(CPU_IPI_DISPATCH_0) +
1216 ipi_no * MPIC_INFO(CPU_IPI_DISPATCH_STRIDE),
1112 mpic_physmask(cpu_mask & cpus_addr(cpu_online_map)[0])); 1217 mpic_physmask(cpu_mask & cpus_addr(cpu_online_map)[0]));
1113} 1218}
1114 1219
@@ -1116,7 +1221,7 @@ unsigned int mpic_get_one_irq(struct mpic *mpic, struct pt_regs *regs)
1116{ 1221{
1117 u32 src; 1222 u32 src;
1118 1223
1119 src = mpic_cpu_read(MPIC_CPU_INTACK) & MPIC_VECPRI_VECTOR_MASK; 1224 src = mpic_cpu_read(MPIC_INFO(CPU_INTACK)) & MPIC_INFO(VECPRI_VECTOR_MASK);
1120#ifdef DEBUG_LOW 1225#ifdef DEBUG_LOW
1121 DBG("%s: get_one_irq(): %d\n", mpic->name, src); 1226 DBG("%s: get_one_irq(): %d\n", mpic->name, src);
1122#endif 1227#endif
diff --git a/arch/powerpc/sysdev/tsi108_dev.c b/arch/powerpc/sysdev/tsi108_dev.c
index 26a0cc820cde..f3038461d4c0 100644
--- a/arch/powerpc/sysdev/tsi108_dev.c
+++ b/arch/powerpc/sysdev/tsi108_dev.c
@@ -93,13 +93,15 @@ static int __init tsi108_eth_of_init(void)
93 goto err; 93 goto err;
94 94
95 r[1].name = "tx"; 95 r[1].name = "tx";
96 r[1].start = np->intrs[0].line; 96 r[1].start = irq_of_parse_and_map(np, 0);
97 r[1].end = np->intrs[0].line; 97 r[1].end = irq_of_parse_and_map(np, 0);
98 r[1].flags = IORESOURCE_IRQ; 98 r[1].flags = IORESOURCE_IRQ;
99 DBG("%s: name:start->end = %s:0x%lx-> 0x%lx\n",
100 __FUNCTION__,r[1].name, r[1].start, r[1].end);
99 101
100 tsi_eth_dev = 102 tsi_eth_dev =
101 platform_device_register_simple("tsi-ethernet", i, &r[0], 103 platform_device_register_simple("tsi-ethernet", i, &r[0],
102 np->n_intrs + 1); 104 1);
103 105
104 if (IS_ERR(tsi_eth_dev)) { 106 if (IS_ERR(tsi_eth_dev)) {
105 ret = PTR_ERR(tsi_eth_dev); 107 ret = PTR_ERR(tsi_eth_dev);
@@ -127,7 +129,7 @@ static int __init tsi108_eth_of_init(void)
127 tsi_eth_data.regs = r[0].start; 129 tsi_eth_data.regs = r[0].start;
128 tsi_eth_data.phyregs = res.start; 130 tsi_eth_data.phyregs = res.start;
129 tsi_eth_data.phy = *phy_id; 131 tsi_eth_data.phy = *phy_id;
130 tsi_eth_data.irq_num = np->intrs[0].line; 132 tsi_eth_data.irq_num = irq_of_parse_and_map(np, 0);
131 of_node_put(phy); 133 of_node_put(phy);
132 ret = 134 ret =
133 platform_device_add_data(tsi_eth_dev, &tsi_eth_data, 135 platform_device_add_data(tsi_eth_dev, &tsi_eth_data,
diff --git a/arch/powerpc/sysdev/tsi108_pci.c b/arch/powerpc/sysdev/tsi108_pci.c
index 3265d54c82ed..2ab06ed3ae73 100644
--- a/arch/powerpc/sysdev/tsi108_pci.c
+++ b/arch/powerpc/sysdev/tsi108_pci.c
@@ -26,7 +26,6 @@
26#include <linux/irq.h> 26#include <linux/irq.h>
27#include <linux/interrupt.h> 27#include <linux/interrupt.h>
28 28
29
30#include <asm/byteorder.h> 29#include <asm/byteorder.h>
31#include <asm/io.h> 30#include <asm/io.h>
32#include <asm/irq.h> 31#include <asm/irq.h>
@@ -228,7 +227,7 @@ int __init tsi108_setup_pci(struct device_node *dev)
228 227
229 (hose)->ops = &tsi108_direct_pci_ops; 228 (hose)->ops = &tsi108_direct_pci_ops;
230 229
231 printk(KERN_INFO "Found tsi108 PCI host bridge at 0x%08lx. " 230 printk(KERN_INFO "Found tsi108 PCI host bridge at 0x%08x. "
232 "Firmware bus number: %d->%d\n", 231 "Firmware bus number: %d->%d\n",
233 rsrc.start, hose->first_busno, hose->last_busno); 232 rsrc.start, hose->first_busno, hose->last_busno);
234 233
@@ -278,7 +277,7 @@ static void init_pci_source(void)
278 mb(); 277 mb();
279} 278}
280 279
281static inline int get_pci_source(void) 280static inline unsigned int get_pci_source(void)
282{ 281{
283 u_int temp = 0; 282 u_int temp = 0;
284 int irq = -1; 283 int irq = -1;
@@ -371,12 +370,12 @@ static void tsi108_pci_irq_end(u_int irq)
371 * Interrupt controller descriptor for cascaded PCI interrupt controller. 370 * Interrupt controller descriptor for cascaded PCI interrupt controller.
372 */ 371 */
373 372
374struct hw_interrupt_type tsi108_pci_irq = { 373static struct irq_chip tsi108_pci_irq = {
375 .typename = "tsi108_PCI_int", 374 .typename = "tsi108_PCI_int",
376 .enable = tsi108_pci_irq_enable, 375 .mask = tsi108_pci_irq_disable,
377 .disable = tsi108_pci_irq_disable,
378 .ack = tsi108_pci_irq_ack, 376 .ack = tsi108_pci_irq_ack,
379 .end = tsi108_pci_irq_end, 377 .end = tsi108_pci_irq_end,
378 .unmask = tsi108_pci_irq_enable,
380}; 379};
381 380
382/* 381/*
@@ -399,14 +398,18 @@ void __init tsi108_pci_int_init(void)
399 DBG("Tsi108_pci_int_init: initializing PCI interrupts\n"); 398 DBG("Tsi108_pci_int_init: initializing PCI interrupts\n");
400 399
401 for (i = 0; i < NUM_PCI_IRQS; i++) { 400 for (i = 0; i < NUM_PCI_IRQS; i++) {
402 irq_desc[i + IRQ_PCI_INTAD_BASE].handler = &tsi108_pci_irq; 401 irq_desc[i + IRQ_PCI_INTAD_BASE].chip = &tsi108_pci_irq;
403 irq_desc[i + IRQ_PCI_INTAD_BASE].status |= IRQ_LEVEL; 402 irq_desc[i + IRQ_PCI_INTAD_BASE].status |= IRQ_LEVEL;
404 } 403 }
405 404
406 init_pci_source(); 405 init_pci_source();
407} 406}
408 407
409int tsi108_irq_cascade(struct pt_regs *regs, void *unused) 408void tsi108_irq_cascade(unsigned int irq, struct irq_desc *desc,
409 struct pt_regs *regs)
410{ 410{
411 return get_pci_source(); 411 unsigned int cascade_irq = get_pci_source();
412 if (cascade_irq != NO_IRQ)
413 generic_handle_irq(cascade_irq, regs);
414 desc->chip->eoi(irq);
412} 415}
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-15 11:17:44 -0500