11 files changed, 117 insertions, 55 deletions

diff --git a/arch/powerpc/boot/dts/mpc8544ds.dts b/arch/powerpc/boot/dts/mpc8544ds.dts
index b9da42105066..0668d1048779 100644
--- a/arch/powerpc/boot/dts/mpc8544ds.dts
+++ b/arch/powerpc/boot/dts/mpc8544ds.dts
@@ -313,7 +313,7 @@
                           0x1000000 0x0 0x0 0xe1010000 0x0 0x10000>;
                 clock-frequency = <33333333>;
                 interrupt-parent = <&mpic>;
-                interrupts = <26 2>;
+                interrupts = <25 2>;
                 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
                 interrupt-map = <
                         /* IDSEL 0x0 */
@@ -350,7 +350,7 @@
                           0x1000000 0x0 0x0 0xe1020000 0x0 0x10000>;
                 clock-frequency = <33333333>;
                 interrupt-parent = <&mpic>;
-                interrupts = <25 2>;
+                interrupts = <26 2>;
                 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
                 interrupt-map = <
                         /* IDSEL 0x0 */
diff --git a/arch/powerpc/boot/dts/mpc8572ds.dts b/arch/powerpc/boot/dts/mpc8572ds.dts
index 21459e161d02..3dcc001b8ed3 100644
--- a/arch/powerpc/boot/dts/mpc8572ds.dts
+++ b/arch/powerpc/boot/dts/mpc8572ds.dts
@@ -724,7 +724,7 @@
                           0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x00010000>;
                 clock-frequency = <33333333>;
                 interrupt-parent = <&mpic>;
-                interrupts = <26 2>;
+                interrupts = <25 2>;
                 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
                 interrupt-map = <
                         /* IDSEL 0x0 */
@@ -761,7 +761,7 @@
                           0x1000000 0x0 0x00000000 0 0xffc20000 0x0 0x00010000>;
                 clock-frequency = <33333333>;
                 interrupt-parent = <&mpic>;
-                interrupts = <27 2>;
+                interrupts = <26 2>;
                 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
                 interrupt-map = <
                         /* IDSEL 0x0 */
diff --git a/arch/powerpc/boot/dts/mpc8572ds_camp_core0.dts b/arch/powerpc/boot/dts/mpc8572ds_camp_core0.dts
index c114c4ee9931..fd462efa9e61 100644
--- a/arch/powerpc/boot/dts/mpc8572ds_camp_core0.dts
+++ b/arch/powerpc/boot/dts/mpc8572ds_camp_core0.dts
@@ -457,7 +457,7 @@
                           0x1000000 0x0 0x0 0xffc10000 0x0 0x10000>;
                 clock-frequency = <33333333>;
                 interrupt-parent = <&mpic>;
-                interrupts = <26 2>;
+                interrupts = <25 2>;
                 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
                 interrupt-map = <
                         /* IDSEL 0x0 */
diff --git a/arch/powerpc/boot/dts/mpc8572ds_camp_core1.dts b/arch/powerpc/boot/dts/mpc8572ds_camp_core1.dts
index 04ecda18d206..e35230f2ac93 100644
--- a/arch/powerpc/boot/dts/mpc8572ds_camp_core1.dts
+++ b/arch/powerpc/boot/dts/mpc8572ds_camp_core1.dts
@@ -208,7 +208,7 @@
                           0x1000000 0x0 0x0 0xffc20000 0x0 0x10000>;
                 clock-frequency = <33333333>;
                 interrupt-parent = <&mpic>;
-                interrupts = <27 2>;
+                interrupts = <26 2>;
                 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
                 interrupt-map = <
                         /* IDSEL 0x0 */
diff --git a/arch/powerpc/include/asm/qe.h b/arch/powerpc/include/asm/qe.h
index a0a15311d0d8..2701753d9937 100644
--- a/arch/powerpc/include/asm/qe.h
+++ b/arch/powerpc/include/asm/qe.h
@@ -624,7 +624,7 @@ struct ucc_slow_pram {
 #define UCC_GETH_UCCE_RXF1      0x00000002
 #define UCC_GETH_UCCE_RXF0      0x00000001
 
-/* UPSMR, when used as a UART */
+/* UCC Protocol Specific Mode Register (UPSMR), when used for UART */
 #define UCC_UART_UPSMR_FLC              0x8000
 #define UCC_UART_UPSMR_SL               0x4000
 #define UCC_UART_UPSMR_CL_MASK          0x3000
@@ -652,6 +652,23 @@ struct ucc_slow_pram {
 #define UCC_UART_UPSMR_TPM_EVEN         0x0002
 #define UCC_UART_UPSMR_TPM_HIGH         0x0003
 
+/* UCC Protocol Specific Mode Register (UPSMR), when used for Ethernet */
+#define UCC_GETH_UPSMR_FTFE     0x80000000
+#define UCC_GETH_UPSMR_PTPE     0x40000000
+#define UCC_GETH_UPSMR_ECM      0x04000000
+#define UCC_GETH_UPSMR_HSE      0x02000000
+#define UCC_GETH_UPSMR_PRO      0x00400000
+#define UCC_GETH_UPSMR_CAP      0x00200000
+#define UCC_GETH_UPSMR_RSH      0x00100000
+#define UCC_GETH_UPSMR_RPM      0x00080000
+#define UCC_GETH_UPSMR_R10M     0x00040000
+#define UCC_GETH_UPSMR_RLPB     0x00020000
+#define UCC_GETH_UPSMR_TBIM     0x00010000
+#define UCC_GETH_UPSMR_RES1     0x00002000
+#define UCC_GETH_UPSMR_RMM      0x00001000
+#define UCC_GETH_UPSMR_CAM      0x00000400
+#define UCC_GETH_UPSMR_BRO      0x00000200
+
 /* UCC Transmit On Demand Register (UTODR) */
 #define UCC_SLOW_TOD    0x8000
 #define UCC_FAST_TOD    0x8000
diff --git a/arch/powerpc/kernel/asm-offsets.c b/arch/powerpc/kernel/asm-offsets.c
index 9937fe44555f..19ee491e9e23 100644
--- a/arch/powerpc/kernel/asm-offsets.c
+++ b/arch/powerpc/kernel/asm-offsets.c
@@ -56,6 +56,10 @@
 #include "head_booke.h"
 #endif
 
+#if defined(CONFIG_FSL_BOOKE)
+#include "../mm/mmu_decl.h"
+#endif
+
 int main(void)
 {
         DEFINE(THREAD, offsetof(struct task_struct, thread));
@@ -382,6 +386,9 @@ int main(void)
         DEFINE(PGD_T_LOG2, PGD_T_LOG2);
         DEFINE(PTE_T_LOG2, PTE_T_LOG2);
 #endif
+#ifdef CONFIG_FSL_BOOKE
+        DEFINE(TLBCAM_SIZE, sizeof(struct tlbcam));
+#endif
 
 #ifdef CONFIG_KVM_EXIT_TIMING
         DEFINE(VCPU_TIMING_EXIT_TBU, offsetof(struct kvm_vcpu,
diff --git a/arch/powerpc/kernel/head_fsl_booke.S b/arch/powerpc/kernel/head_fsl_booke.S
index 11b549acc034..2f32720a44ae 100644
--- a/arch/powerpc/kernel/head_fsl_booke.S
+++ b/arch/powerpc/kernel/head_fsl_booke.S
@@ -389,10 +389,6 @@ skpinv:	addi	r6,r6,1				/* Increment */
 #endif
 #endif
 
-        mfspr   r3,SPRN_TLB1CFG
-        andi.   r3,r3,0xfff
-        lis     r4,num_tlbcam_entries@ha
-        stw     r3,num_tlbcam_entries@l(r4)
 /*
  * Decide what sort of machine this is and initialize the MMU.
  */
@@ -909,7 +905,7 @@ KernelSPE:
 _GLOBAL(loadcam_entry)
         lis     r4,TLBCAM@ha
         addi    r4,r4,TLBCAM@l
-        mulli   r5,r3,20
+        mulli   r5,r3,TLBCAM_SIZE
         add     r3,r5,r4
         lwz     r4,0(r3)
         mtspr   SPRN_MAS0,r4
diff --git a/arch/powerpc/mm/fsl_booke_mmu.c b/arch/powerpc/mm/fsl_booke_mmu.c
index 23cee39534fd..1971e4ee3d6e 100644
--- a/arch/powerpc/mm/fsl_booke_mmu.c
+++ b/arch/powerpc/mm/fsl_booke_mmu.c
@@ -56,18 +56,11 @@
 
 extern void loadcam_entry(unsigned int index);
 unsigned int tlbcam_index;
-unsigned int num_tlbcam_entries;
 static unsigned long __cam0, __cam1, __cam2;
 
 #define NUM_TLBCAMS     (16)
 
-struct tlbcam {
-        u32     MAS0;
-        u32     MAS1;
-        u32     MAS2;
-        u32     MAS3;
-        u32     MAS7;
-} TLBCAM[NUM_TLBCAMS];
+struct tlbcam TLBCAM[NUM_TLBCAMS];
 
 struct tlbcamrange {
         unsigned long start;
diff --git a/arch/powerpc/mm/mmu_decl.h b/arch/powerpc/mm/mmu_decl.h
index ad123bced404..d1f9c62dc177 100644
--- a/arch/powerpc/mm/mmu_decl.h
+++ b/arch/powerpc/mm/mmu_decl.h
@@ -75,6 +75,15 @@ extern void _tlbia(void);
 #endif /* CONFIG_PPC_MMU_NOHASH */
 
 #ifdef CONFIG_PPC32
+
+struct tlbcam {
+        u32     MAS0;
+        u32     MAS1;
+        u32     MAS2;
+        u32     MAS3;
+        u32     MAS7;
+};
+
 extern void mapin_ram(void);
 extern int map_page(unsigned long va, phys_addr_t pa, int flags);
 extern void setbat(int index, unsigned long virt, phys_addr_t phys,
@@ -90,8 +99,6 @@ extern unsigned int rtas_data, rtas_size;
 struct hash_pte;
 extern struct hash_pte *Hash, *Hash_end;
 extern unsigned long Hash_size, Hash_mask;
-
-extern unsigned int num_tlbcam_entries;
 #endif
 
 extern unsigned long ioremap_bot;
diff --git a/arch/powerpc/platforms/fsl_uli1575.c b/arch/powerpc/platforms/fsl_uli1575.c
index 8c619963becc..1db6b9e037fc 100644
--- a/arch/powerpc/platforms/fsl_uli1575.c
+++ b/arch/powerpc/platforms/fsl_uli1575.c
@@ -249,6 +249,7 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, 0x5288, quirk_uli5288);
 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, 0x5229, quirk_uli5229);
 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, 0x5249, quirk_final_uli5249);
 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, 0x1575, quirk_final_uli1575);
+DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AL, 0x5229, quirk_uli5229);
 
 static void __devinit hpcd_quirk_uli1575(struct pci_dev *dev)
 {
diff --git a/arch/powerpc/sysdev/fsl_pci.c b/arch/powerpc/sysdev/fsl_pci.c
index f611d0369cc8..9817f63723dd 100644
--- a/arch/powerpc/sysdev/fsl_pci.c
+++ b/arch/powerpc/sysdev/fsl_pci.c
@@ -28,63 +28,104 @@
 #include <sysdev/fsl_pci.h>
 
 #if defined(CONFIG_PPC_85xx) || defined(CONFIG_PPC_86xx)
+static int __init setup_one_atmu(struct ccsr_pci __iomem *pci,
+        unsigned int index, const struct resource *res,
+        resource_size_t offset)
+{
+        resource_size_t pci_addr = res->start - offset;
+        resource_size_t phys_addr = res->start;
+        resource_size_t size = res->end - res->start + 1;
+        u32 flags = 0x80044000; /* enable & mem R/W */
+        unsigned int i;
+
+        pr_debug("PCI MEM resource start 0x%016llx, size 0x%016llx.\n",
+                (u64)res->start, (u64)size);
+
+        if (res->flags & IORESOURCE_PREFETCH)
+                flags |= 0x10000000; /* enable relaxed ordering */
+
+        for (i = 0; size > 0; i++) {
+                unsigned int bits = min(__ilog2(size),
+                                        __ffs(pci_addr | phys_addr));
+
+                if (index + i >= 5)
+                        return -1;
+
+                out_be32(&pci->pow[index + i].potar, pci_addr >> 12);
+                out_be32(&pci->pow[index + i].potear, (u64)pci_addr >> 44);
+                out_be32(&pci->pow[index + i].powbar, phys_addr >> 12);
+                out_be32(&pci->pow[index + i].powar, flags | (bits - 1));
+
+                pci_addr += (resource_size_t)1U << bits;
+                phys_addr += (resource_size_t)1U << bits;
+                size -= (resource_size_t)1U << bits;
+        }
+
+        return i;
+}
+
 /* atmu setup for fsl pci/pcie controller */
 static void __init setup_pci_atmu(struct pci_controller *hose,
                                   struct resource *rsrc)
 {
         struct ccsr_pci __iomem *pci;
-        int i;
+        int i, j, n;
 
         pr_debug("PCI memory map start 0x%016llx, size 0x%016llx\n",
                     (u64)rsrc->start, (u64)rsrc->end - (u64)rsrc->start + 1);
         pci = ioremap(rsrc->start, rsrc->end - rsrc->start + 1);
+        if (!pci) {
+            dev_err(hose->parent, "Unable to map ATMU registers\n");
+            return;
+        }
 
-        /* Disable all windows (except powar0 since its ignored) */
+        /* Disable all windows (except powar0 since it's ignored) */
         for(i = 1; i < 5; i++)
                 out_be32(&pci->pow[i].powar, 0);
         for(i = 0; i < 3; i++)
                 out_be32(&pci->piw[i].piwar, 0);
 
         /* Setup outbound MEM window */
-        for(i = 0; i < 3; i++)
-                if (hose->mem_resources[i].flags & IORESOURCE_MEM){
-                        resource_size_t pci_addr_start =
-                                 hose->mem_resources[i].start -
-                                 hose->pci_mem_offset;
-                        pr_debug("PCI MEM resource start 0x%016llx, size 0x%016llx.\n",
-                                (u64)hose->mem_resources[i].start,
-                                (u64)hose->mem_resources[i].end
-                                  - (u64)hose->mem_resources[i].start + 1);
-                        out_be32(&pci->pow[i+1].potar, (pci_addr_start >> 12));
-                        out_be32(&pci->pow[i+1].potear, 0);
-                        out_be32(&pci->pow[i+1].powbar,
-                                (hose->mem_resources[i].start >> 12));
-                        /* Enable, Mem R/W */
-                        out_be32(&pci->pow[i+1].powar, 0x80044000
-                                | (__ilog2(hose->mem_resources[i].end
-                                - hose->mem_resources[i].start + 1) - 1));
-                }
+        for(i = 0, j = 1; i < 3; i++) {
+                if (!(hose->mem_resources[i].flags & IORESOURCE_MEM))
+                        continue;
+
+                n = setup_one_atmu(pci, j, &hose->mem_resources[i],
+                                   hose->pci_mem_offset);
+
+                if (n < 0 || j >= 5) {
+                        pr_err("Ran out of outbound PCI ATMUs for resource %d!\n", i);
+                        hose->mem_resources[i].flags |= IORESOURCE_DISABLED;
+                } else
+                        j += n;
+        }
 
         /* Setup outbound IO window */
-        if (hose->io_resource.flags & IORESOURCE_IO){
-                pr_debug("PCI IO resource start 0x%016llx, size 0x%016llx, "
-                         "phy base 0x%016llx.\n",
-                        (u64)hose->io_resource.start,
-                        (u64)hose->io_resource.end - (u64)hose->io_resource.start + 1,
-                        (u64)hose->io_base_phys);
-                out_be32(&pci->pow[i+1].potar, (hose->io_resource.start >> 12));
-                out_be32(&pci->pow[i+1].potear, 0);
-                out_be32(&pci->pow[i+1].powbar, (hose->io_base_phys >> 12));
-                /* Enable, IO R/W */
-                out_be32(&pci->pow[i+1].powar, 0x80088000
-                        | (__ilog2(hose->io_resource.end
-                        - hose->io_resource.start + 1) - 1));
+        if (hose->io_resource.flags & IORESOURCE_IO) {
+                if (j >= 5) {
+                        pr_err("Ran out of outbound PCI ATMUs for IO resource\n");
+                } else {
+                        pr_debug("PCI IO resource start 0x%016llx, size 0x%016llx, "
+                                 "phy base 0x%016llx.\n",
+                                (u64)hose->io_resource.start,
+                                (u64)hose->io_resource.end - (u64)hose->io_resource.start + 1,
+                                (u64)hose->io_base_phys);
+                        out_be32(&pci->pow[j].potar, (hose->io_resource.start >> 12));
+                        out_be32(&pci->pow[j].potear, 0);
+                        out_be32(&pci->pow[j].powbar, (hose->io_base_phys >> 12));
+                        /* Enable, IO R/W */
+                        out_be32(&pci->pow[j].powar, 0x80088000
+                                | (__ilog2(hose->io_resource.end
+                                - hose->io_resource.start + 1) - 1));
+                }
         }
 
         /* Setup 2G inbound Memory Window @ 1 */
         out_be32(&pci->piw[2].pitar, 0x00000000);
         out_be32(&pci->piw[2].piwbar,0x00000000);
         out_be32(&pci->piw[2].piwar, PIWAR_2G);
+
+        iounmap(pci);
 }
 
 static void __init setup_pci_cmd(struct pci_controller *hose)