7 files changed, 269 insertions, 29 deletions

diff --git a/arch/powerpc/boot/dts/mpc8610_hpcd.dts b/arch/powerpc/boot/dts/mpc8610_hpcd.dts
index 16c947b8a721..1f2f1e0a5571 100644
--- a/arch/powerpc/boot/dts/mpc8610_hpcd.dts
+++ b/arch/powerpc/boot/dts/mpc8610_hpcd.dts
@@ -45,6 +45,11 @@
                 reg = <0x00000000 0x20000000>;  // 512M at 0x0
         };
 
+        board-control@e8000000 {
+                compatible = "fsl,fpga-pixis";
+                reg = <0xe8000000 32>;          // pixis at 0xe8000000
+        };
+
         soc@e0000000 {
                 #address-cells = <1>;
                 #size-cells = <1>;
@@ -104,6 +109,13 @@
                         interrupt-parent = <&mpic>;
                 };
 
+                display@2c000 {
+                        compatible = "fsl,diu";
+                        reg = <0x2c000 100>;
+                        interrupts = <72 2>;
+                        interrupt-parent = <&mpic>;
+                };
+
                 mpic: interrupt-controller@40000 {
                         clock-frequency = <0>;
                         interrupt-controller;
diff --git a/arch/powerpc/mm/mem.c b/arch/powerpc/mm/mem.c
index 5ccb579b81e4..d9e37f365b54 100644
--- a/arch/powerpc/mm/mem.c
+++ b/arch/powerpc/mm/mem.c
@@ -110,15 +110,6 @@ EXPORT_SYMBOL(phys_mem_access_prot);
 
 #ifdef CONFIG_MEMORY_HOTPLUG
 
-void online_page(struct page *page)
-{
-        ClearPageReserved(page);
-        init_page_count(page);
-        __free_page(page);
-        totalram_pages++;
-        num_physpages++;
-}
-
 #ifdef CONFIG_NUMA
 int memory_add_physaddr_to_nid(u64 start)
 {
diff --git a/arch/powerpc/platforms/86xx/mpc8610_hpcd.c b/arch/powerpc/platforms/86xx/mpc8610_hpcd.c
index 18b8ebe930d5..5e1e8cf14e75 100644
--- a/arch/powerpc/platforms/86xx/mpc8610_hpcd.c
+++ b/arch/powerpc/platforms/86xx/mpc8610_hpcd.c
@@ -3,11 +3,12 @@
  *
  * Initial author: Xianghua Xiao <x.xiao@freescale.com>
  * Recode: Jason Jin <jason.jin@freescale.com>
+ *         York Sun <yorksun@freescale.com>
  *
  * Rewrite the interrupt routing. remove the 8259PIC support,
  * All the integrated device in ULI use sideband interrupt.
  *
- * Copyright 2007 Freescale Semiconductor Inc.
+ * Copyright 2008 Freescale Semiconductor Inc.
  *
  * This program is free software; you can redistribute  it and/or modify it
  * under  the terms of  the GNU General  Public License as published by the
@@ -38,6 +39,8 @@
 #include <sysdev/fsl_pci.h>
 #include <sysdev/fsl_soc.h>
 
+static unsigned char *pixis_bdcfg0, *pixis_arch;
+
 static struct of_device_id __initdata mpc8610_ids[] = {
         { .compatible = "fsl,mpc8610-immr", },
         {}
@@ -52,8 +55,7 @@ static int __init mpc8610_declare_of_platform_devices(void)
 }
 machine_device_initcall(mpc86xx_hpcd, mpc8610_declare_of_platform_devices);
 
-static void __init
-mpc86xx_hpcd_init_irq(void)
+static void __init mpc86xx_hpcd_init_irq(void)
 {
         struct mpic *mpic1;
         struct device_node *np;
@@ -161,12 +163,159 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, 0x5229, quirk_uli5229);
 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, 0x5288, final_uli5288);
 #endif /* CONFIG_PCI */
 
-static void __init
-mpc86xx_hpcd_setup_arch(void)
+#if defined(CONFIG_FB_FSL_DIU) || defined(CONFIG_FB_FSL_DIU_MODULE)
+
+static u32 get_busfreq(void)
 {
-#ifdef CONFIG_PCI
-        struct device_node *np;
+        struct device_node *node;
+
+        u32 fs_busfreq = 0;
+        node = of_find_node_by_type(NULL, "cpu");
+        if (node) {
+                unsigned int size;
+                const unsigned int *prop =
+                        of_get_property(node, "bus-frequency", &size);
+                if (prop)
+                        fs_busfreq = *prop;
+                of_node_put(node);
+        };
+        return fs_busfreq;
+}
+
+unsigned int mpc8610hpcd_get_pixel_format(unsigned int bits_per_pixel,
+                                                int monitor_port)
+{
+        static const unsigned long pixelformat[][3] = {
+                {0x88882317, 0x88083218, 0x65052119},
+                {0x88883316, 0x88082219, 0x65053118},
+        };
+        unsigned int pix_fmt, arch_monitor;
+
+        arch_monitor = ((*pixis_arch == 0x01) && (monitor_port == 0))? 0 : 1;
+                /* DVI port for board version 0x01 */
+
+        if (bits_per_pixel == 32)
+                pix_fmt = pixelformat[arch_monitor][0];
+        else if (bits_per_pixel == 24)
+                pix_fmt = pixelformat[arch_monitor][1];
+        else if (bits_per_pixel == 16)
+                pix_fmt = pixelformat[arch_monitor][2];
+        else
+                pix_fmt = pixelformat[1][0];
+
+        return pix_fmt;
+}
+
+void mpc8610hpcd_set_gamma_table(int monitor_port, char *gamma_table_base)
+{
+        int i;
+        if (monitor_port == 2) {                /* dual link LVDS */
+                for (i = 0; i < 256*3; i++)
+                        gamma_table_base[i] = (gamma_table_base[i] << 2) |
+                                         ((gamma_table_base[i] >> 6) & 0x03);
+        }
+}
+
+void mpc8610hpcd_set_monitor_port(int monitor_port)
+{
+        static const u8 bdcfg[] = {0xBD, 0xB5, 0xA5};
+        if (monitor_port < 3)
+                *pixis_bdcfg0 = bdcfg[monitor_port];
+}
+
+void mpc8610hpcd_set_pixel_clock(unsigned int pixclock)
+{
+        u32 __iomem *clkdvdr;
+        u32 temp;
+        /* variables for pixel clock calcs */
+        ulong  bestval, bestfreq, speed_ccb, minpixclock, maxpixclock;
+        ulong pixval;
+        long err;
+        int i;
+
+        clkdvdr = ioremap(get_immrbase() + 0xe0800, sizeof(u32));
+        if (!clkdvdr) {
+                printk(KERN_ERR "Err: can't map clock divider register!\n");
+                return;
+        }
+
+        /* Pixel Clock configuration */
+        pr_debug("DIU: Bus Frequency = %d\n", get_busfreq());
+        speed_ccb = get_busfreq();
+
+        /* Calculate the pixel clock with the smallest error */
+        /* calculate the following in steps to avoid overflow */
+        pr_debug("DIU pixclock in ps - %d\n", pixclock);
+        temp = 1000000000/pixclock;
+        temp *= 1000;
+        pixclock = temp;
+        pr_debug("DIU pixclock freq - %u\n", pixclock);
+
+        temp = pixclock * 5 / 100;
+        pr_debug("deviation = %d\n", temp);
+        minpixclock = pixclock - temp;
+        maxpixclock = pixclock + temp;
+        pr_debug("DIU minpixclock - %lu\n", minpixclock);
+        pr_debug("DIU maxpixclock - %lu\n", maxpixclock);
+        pixval = speed_ccb/pixclock;
+        pr_debug("DIU pixval = %lu\n", pixval);
+
+        err = 100000000;
+        bestval = pixval;
+        pr_debug("DIU bestval = %lu\n", bestval);
+
+        bestfreq = 0;
+        for (i = -1; i <= 1; i++) {
+                temp = speed_ccb / ((pixval+i) + 1);
+                pr_debug("DIU test pixval i= %d, pixval=%lu, temp freq. = %u\n",
+                                                        i, pixval, temp);
+                if ((temp < minpixclock) || (temp > maxpixclock))
+                        pr_debug("DIU exceeds monitor range (%lu to %lu)\n",
+                                minpixclock, maxpixclock);
+                else if (abs(temp - pixclock) < err) {
+                  pr_debug("Entered the else if block %d\n", i);
+                        err = abs(temp - pixclock);
+                        bestval = pixval+i;
+                        bestfreq = temp;
+                }
+        }
+
+        pr_debug("DIU chose = %lx\n", bestval);
+        pr_debug("DIU error = %ld\n NomPixClk ", err);
+        pr_debug("DIU: Best Freq = %lx\n", bestfreq);
+        /* Modify PXCLK in GUTS CLKDVDR */
+        pr_debug("DIU: Current value of CLKDVDR = 0x%08x\n", (*clkdvdr));
+        temp = (*clkdvdr) & 0x2000FFFF;
+        *clkdvdr = temp;                /* turn off clock */
+        *clkdvdr = temp | 0x80000000 | (((bestval) & 0x1F) << 16);
+        pr_debug("DIU: Modified value of CLKDVDR = 0x%08x\n", (*clkdvdr));
+        iounmap(clkdvdr);
+}
+
+ssize_t mpc8610hpcd_show_monitor_port(int monitor_port, char *buf)
+{
+        return snprintf(buf, PAGE_SIZE,
+                        "%c0 - DVI\n"
+                        "%c1 - Single link LVDS\n"
+                        "%c2 - Dual link LVDS\n",
+                        monitor_port == 0 ? '*' : ' ',
+                        monitor_port == 1 ? '*' : ' ',
+                        monitor_port == 2 ? '*' : ' ');
+}
+
+int mpc8610hpcd_set_sysfs_monitor_port(int val)
+{
+        return val < 3 ? val : 0;
+}
+
 #endif
+
+static void __init mpc86xx_hpcd_setup_arch(void)
+{
+        struct resource r;
+        struct device_node *np;
+        unsigned char *pixis;
+
         if (ppc_md.progress)
                 ppc_md.progress("mpc86xx_hpcd_setup_arch()", 0);
 
@@ -183,6 +332,30 @@ mpc86xx_hpcd_setup_arch(void)
                 }
         }
 #endif
+#if defined(CONFIG_FB_FSL_DIU) || defined(CONFIG_FB_FSL_DIU_MODULE)
+        preallocate_diu_videomemory();
+        diu_ops.get_pixel_format        = mpc8610hpcd_get_pixel_format;
+        diu_ops.set_gamma_table         = mpc8610hpcd_set_gamma_table;
+        diu_ops.set_monitor_port        = mpc8610hpcd_set_monitor_port;
+        diu_ops.set_pixel_clock         = mpc8610hpcd_set_pixel_clock;
+        diu_ops.show_monitor_port       = mpc8610hpcd_show_monitor_port;
+        diu_ops.set_sysfs_monitor_port  = mpc8610hpcd_set_sysfs_monitor_port;
+#endif
+
+        np = of_find_compatible_node(NULL, NULL, "fsl,fpga-pixis");
+        if (np) {
+                of_address_to_resource(np, 0, &r);
+                of_node_put(np);
+                pixis = ioremap(r.start, 32);
+                if (!pixis) {
+                        printk(KERN_ERR "Err: can't map FPGA cfg register!\n");
+                        return;
+                }
+                pixis_bdcfg0 = pixis + 8;
+                pixis_arch = pixis + 1;
+        } else
+                printk(KERN_ERR "Err: "
+                                "can't find device node 'fsl,fpga-pixis'\n");
 
         printk("MPC86xx HPCD board from Freescale Semiconductor\n");
 }
@@ -200,8 +373,7 @@ static int __init mpc86xx_hpcd_probe(void)
         return 0;
 }
 
-static long __init
-mpc86xx_time_init(void)
+static long __init mpc86xx_time_init(void)
 {
         unsigned int temp;
 
diff --git a/arch/powerpc/platforms/cell/celleb_scc_pciex.c b/arch/powerpc/platforms/cell/celleb_scc_pciex.c
index ab24d94baab6..31da84c458d2 100644
--- a/arch/powerpc/platforms/cell/celleb_scc_pciex.c
+++ b/arch/powerpc/platforms/cell/celleb_scc_pciex.c
@@ -36,8 +36,8 @@
 #include "celleb_scc.h"
 #include "celleb_pci.h"
 
-#define PEX_IN(base, off)       in_be32((void *)(base) + (off))
-#define PEX_OUT(base, off, data) out_be32((void *)(base) + (off), (data))
+#define PEX_IN(base, off)       in_be32((void __iomem *)(base) + (off))
+#define PEX_OUT(base, off, data) out_be32((void __iomem *)(base) + (off), (data))
 
 static void scc_pciex_io_flush(struct iowa_bus *bus)
 {
@@ -304,7 +304,7 @@ static int __init scc_pciex_iowa_init(struct iowa_bus *bus, void *data)
         ((((0x1 << (size))-1) << ((addr) & 0x3)) << PEXDCMND_BYTE_EN_SHIFT)
 #define MK_PEXDCMND(cmd, addr, size) ((cmd) | MK_PEXDCMND_BYTE_EN(addr, size))
 
-static uint32_t config_read_pciex_dev(unsigned int *base,
+static uint32_t config_read_pciex_dev(unsigned int __iomem *base,
                 uint64_t bus_no, uint64_t dev_no, uint64_t func_no,
                 uint64_t off, uint64_t size)
 {
@@ -320,7 +320,7 @@ static uint32_t config_read_pciex_dev(unsigned int *base,
         return ret;
 }
 
-static void config_write_pciex_dev(unsigned int *base, uint64_t bus_no,
+static void config_write_pciex_dev(unsigned int __iomem *base, uint64_t bus_no,
         uint64_t dev_no, uint64_t func_no, uint64_t off, uint64_t size,
         uint32_t data)
 {
@@ -338,7 +338,7 @@ static void config_write_pciex_dev(unsigned int *base, uint64_t bus_no,
         ((((0x1 << (len)) - 1) << ((off) & 0x3)) << PEXCADRS_BYTE_EN_SHIFT)
 #define MK_PEXCADRS(cmd, addr, size) \
         ((cmd) | MK_PEXCADRS_BYTE_EN(addr, size) | ((addr) & ~0x3))
-static uint32_t config_read_pciex_rc(unsigned int *base,
+static uint32_t config_read_pciex_rc(unsigned int __iomem *base,
                                      uint32_t where, uint32_t size)
 {
         PEX_OUT(base, PEXCADRS, MK_PEXCADRS(PEXCADRS_CMD_READ, where, size));
@@ -346,7 +346,7 @@ static uint32_t config_read_pciex_rc(unsigned int *base,
                 >> ((where & (4 - size)) * 8)) & ((0x1 << (size * 8)) - 1);
 }
 
-static void config_write_pciex_rc(unsigned int *base, uint32_t where,
+static void config_write_pciex_rc(unsigned int __iomem *base, uint32_t where,
                                   uint32_t size, uint32_t val)
 {
         uint32_t data;
@@ -410,7 +410,7 @@ static struct pci_ops scc_pciex_pci_ops = {
         scc_pciex_write_config,
 };
 
-static void pciex_clear_intr_all(unsigned int *base)
+static void pciex_clear_intr_all(unsigned int __iomem *base)
 {
         PEX_OUT(base, PEXAERRSTS, 0xffffffff);
         PEX_OUT(base, PEXPRERRSTS, 0xffffffff);
@@ -427,7 +427,7 @@ static void pciex_disable_intr_all(unsigned int *base)
 }
 #endif
 
-static void pciex_enable_intr_all(unsigned int *base)
+static void pciex_enable_intr_all(unsigned int __iomem *base)
 {
         PEX_OUT(base, PEXINTMASK, 0x0000e7f1);
         PEX_OUT(base, PEXAERRMASK, 0x03ff01ff);
@@ -435,7 +435,7 @@ static void pciex_enable_intr_all(unsigned int *base)
         PEX_OUT(base, PEXVDMASK, 0x00000001);
 }
 
-static void pciex_check_status(unsigned int *base)
+static void pciex_check_status(unsigned int __iomem *base)
 {
         uint32_t err = 0;
         uint32_t intsts, aerr, prerr, rcvcp, lenerr;
diff --git a/arch/powerpc/sysdev/axonram.c b/arch/powerpc/sysdev/axonram.c
index d359d6e92975..7f59188cd9a1 100644
--- a/arch/powerpc/sysdev/axonram.c
+++ b/arch/powerpc/sysdev/axonram.c
@@ -143,7 +143,7 @@ axon_ram_make_request(struct request_queue *queue, struct bio *bio)
  */
 static int
 axon_ram_direct_access(struct block_device *device, sector_t sector,
-                       unsigned long *data)
+                       void **kaddr, unsigned long *pfn)
 {
         struct axon_ram_bank *bank = device->bd_disk->private_data;
         loff_t offset;
@@ -154,7 +154,8 @@ axon_ram_direct_access(struct block_device *device, sector_t sector,
                 return -ERANGE;
         }
 
-        *data = bank->ph_addr + offset;
+        *kaddr = (void *)(bank->ph_addr + offset);
+        *pfn = virt_to_phys(kaddr) >> PAGE_SHIFT;
 
         return 0;
 }
diff --git a/arch/powerpc/sysdev/fsl_soc.c b/arch/powerpc/sysdev/fsl_soc.c
index 5c1b246aaccc..7b45670c7af3 100644
--- a/arch/powerpc/sysdev/fsl_soc.c
+++ b/arch/powerpc/sysdev/fsl_soc.c
@@ -892,3 +892,44 @@ void fsl_rstcr_restart(char *cmd)
         while (1) ;
 }
 #endif
+
+#if defined(CONFIG_FB_FSL_DIU) || defined(CONFIG_FB_FSL_DIU_MODULE)
+struct platform_diu_data_ops diu_ops = {
+        .diu_size = 1280 * 1024 * 4,    /* default one 1280x1024 buffer */
+};
+EXPORT_SYMBOL(diu_ops);
+
+int __init preallocate_diu_videomemory(void)
+{
+        pr_debug("diu_size=%lu\n", diu_ops.diu_size);
+
+        diu_ops.diu_mem = __alloc_bootmem(diu_ops.diu_size, 8, 0);
+        if (!diu_ops.diu_mem) {
+                printk(KERN_ERR "fsl-diu: cannot allocate %lu bytes\n",
+                        diu_ops.diu_size);
+                return -ENOMEM;
+        }
+
+        pr_debug("diu_mem=%p\n", diu_ops.diu_mem);
+
+        rh_init(&diu_ops.diu_rh_info, 4096, ARRAY_SIZE(diu_ops.diu_rh_block),
+                diu_ops.diu_rh_block);
+        return rh_attach_region(&diu_ops.diu_rh_info,
+                                (unsigned long) diu_ops.diu_mem,
+                                diu_ops.diu_size);
+}
+
+static int __init early_parse_diufb(char *p)
+{
+        if (!p)
+                return 1;
+
+        diu_ops.diu_size = _ALIGN_UP(memparse(p, &p), 8);
+
+        pr_debug("diu_size=%lu\n", diu_ops.diu_size);
+
+        return 0;
+}
+early_param("diufb", early_parse_diufb);
+
+#endif
diff --git a/arch/powerpc/sysdev/fsl_soc.h b/arch/powerpc/sysdev/fsl_soc.h
index 74c4a9657b33..52c831fa1886 100644
--- a/arch/powerpc/sysdev/fsl_soc.h
+++ b/arch/powerpc/sysdev/fsl_soc.h
@@ -17,5 +17,28 @@ extern int fsl_spi_init(struct spi_board_info *board_infos,
                         void (*deactivate_cs)(u8 cs, u8 polarity));
 
 extern void fsl_rstcr_restart(char *cmd);
+
+#if defined(CONFIG_FB_FSL_DIU) || defined(CONFIG_FB_FSL_DIU_MODULE)
+#include <linux/bootmem.h>
+#include <asm/rheap.h>
+struct platform_diu_data_ops {
+        rh_block_t diu_rh_block[16];
+        rh_info_t diu_rh_info;
+        unsigned long diu_size;
+        void *diu_mem;
+
+        unsigned int (*get_pixel_format) (unsigned int bits_per_pixel,
+                int monitor_port);
+        void (*set_gamma_table) (int monitor_port, char *gamma_table_base);
+        void (*set_monitor_port) (int monitor_port);
+        void (*set_pixel_clock) (unsigned int pixclock);
+        ssize_t (*show_monitor_port) (int monitor_port, char *buf);
+        int (*set_sysfs_monitor_port) (int val);
+};
+
+extern struct platform_diu_data_ops diu_ops;
+int __init preallocate_diu_videomemory(void);
+#endif
+
 #endif
 #endif