diff options
Diffstat (limited to 'arch/powerpc')
| -rw-r--r-- | arch/powerpc/include/asm/pte-8xx.h | 5 | ||||
| -rw-r--r-- | arch/powerpc/kernel/head_8xx.S | 8 |
2 files changed, 11 insertions, 2 deletions
diff --git a/arch/powerpc/include/asm/pte-8xx.h b/arch/powerpc/include/asm/pte-8xx.h index 68ba861331ee..d44826e4ff97 100644 --- a/arch/powerpc/include/asm/pte-8xx.h +++ b/arch/powerpc/include/asm/pte-8xx.h | |||
| @@ -35,11 +35,12 @@ | |||
| 35 | #define _PAGE_SPECIAL 0x0008 /* SW entry, forced to 0 by the TLB miss */ | 35 | #define _PAGE_SPECIAL 0x0008 /* SW entry, forced to 0 by the TLB miss */ |
| 36 | #define _PAGE_DIRTY 0x0100 /* C: page changed */ | 36 | #define _PAGE_DIRTY 0x0100 /* C: page changed */ |
| 37 | 37 | ||
| 38 | /* These 3 software bits must be masked out when the entry is loaded | 38 | /* These 4 software bits must be masked out when the entry is loaded |
| 39 | * into the TLB, 2 SW bits left. | 39 | * into the TLB, 1 SW bit left(0x0080). |
| 40 | */ | 40 | */ |
| 41 | #define _PAGE_GUARDED 0x0010 /* software: guarded access */ | 41 | #define _PAGE_GUARDED 0x0010 /* software: guarded access */ |
| 42 | #define _PAGE_ACCESSED 0x0020 /* software: page referenced */ | 42 | #define _PAGE_ACCESSED 0x0020 /* software: page referenced */ |
| 43 | #define _PAGE_WRITETHRU 0x0040 /* software: caching is write through */ | ||
| 43 | 44 | ||
| 44 | /* Setting any bits in the nibble with the follow two controls will | 45 | /* Setting any bits in the nibble with the follow two controls will |
| 45 | * require a TLB exception handler change. It is assumed unused bits | 46 | * require a TLB exception handler change. It is assumed unused bits |
diff --git a/arch/powerpc/kernel/head_8xx.S b/arch/powerpc/kernel/head_8xx.S index 1a28ee8ca318..c4ae85b8f8c0 100644 --- a/arch/powerpc/kernel/head_8xx.S +++ b/arch/powerpc/kernel/head_8xx.S | |||
| @@ -422,6 +422,10 @@ DataStoreTLBMiss: | |||
| 422 | * above. | 422 | * above. |
| 423 | */ | 423 | */ |
| 424 | rlwimi r11, r10, 0, 27, 27 | 424 | rlwimi r11, r10, 0, 27, 27 |
| 425 | /* Insert the WriteThru flag into the TWC from the Linux PTE. | ||
| 426 | * It is bit 25 in the Linux PTE and bit 30 in the TWC | ||
| 427 | */ | ||
| 428 | rlwimi r11, r10, 32-5, 30, 30 | ||
| 425 | DO_8xx_CPU6(0x3b80, r3) | 429 | DO_8xx_CPU6(0x3b80, r3) |
| 426 | mtspr SPRN_MD_TWC, r11 | 430 | mtspr SPRN_MD_TWC, r11 |
| 427 | 431 | ||
| @@ -559,6 +563,10 @@ DARFixed:/* Return from dcbx instruction bug workaround, r10 holds value of DAR | |||
| 559 | * It is bit 27 of both the Linux PTE and the TWC | 563 | * It is bit 27 of both the Linux PTE and the TWC |
| 560 | */ | 564 | */ |
| 561 | rlwimi r11, r10, 0, 27, 27 | 565 | rlwimi r11, r10, 0, 27, 27 |
| 566 | /* Insert the WriteThru flag into the TWC from the Linux PTE. | ||
| 567 | * It is bit 25 in the Linux PTE and bit 30 in the TWC | ||
| 568 | */ | ||
| 569 | rlwimi r11, r10, 32-5, 30, 30 | ||
| 562 | DO_8xx_CPU6(0x3b80, r3) | 570 | DO_8xx_CPU6(0x3b80, r3) |
| 563 | mtspr SPRN_MD_TWC, r11 | 571 | mtspr SPRN_MD_TWC, r11 |
| 564 | mfspr r11, SPRN_MD_TWC /* get the pte address again */ | 572 | mfspr r11, SPRN_MD_TWC /* get the pte address again */ |