aboutsummaryrefslogtreecommitdiffstats
path: root/arch/powerpc
diff options
context:
space:
mode:
Diffstat (limited to 'arch/powerpc')
-rw-r--r--arch/powerpc/boot/dts/ksi8560.dts4
-rw-r--r--arch/powerpc/boot/dts/sbc8548.dts4
-rw-r--r--arch/powerpc/boot/dts/sbc8560.dts4
-rw-r--r--arch/powerpc/boot/dts/stx_gp3_8560.dts4
-rw-r--r--arch/powerpc/boot/dts/tqm8540.dts4
-rw-r--r--arch/powerpc/boot/dts/tqm8541.dts4
-rw-r--r--arch/powerpc/boot/dts/tqm8555.dts4
-rw-r--r--arch/powerpc/boot/dts/tqm8560.dts4
8 files changed, 16 insertions, 16 deletions
diff --git a/arch/powerpc/boot/dts/ksi8560.dts b/arch/powerpc/boot/dts/ksi8560.dts
index 308fe7c29dea..c9cfd374bffb 100644
--- a/arch/powerpc/boot/dts/ksi8560.dts
+++ b/arch/powerpc/boot/dts/ksi8560.dts
@@ -57,14 +57,14 @@
57 bus-frequency = <0>; /* Fixed by bootwrapper */ 57 bus-frequency = <0>; /* Fixed by bootwrapper */
58 58
59 memory-controller@2000 { 59 memory-controller@2000 {
60 compatible = "fsl,8540-memory-controller"; 60 compatible = "fsl,mpc8540-memory-controller";
61 reg = <0x2000 0x1000>; 61 reg = <0x2000 0x1000>;
62 interrupt-parent = <&mpic>; 62 interrupt-parent = <&mpic>;
63 interrupts = <0x12 0x2>; 63 interrupts = <0x12 0x2>;
64 }; 64 };
65 65
66 L2: l2-cache-controller@20000 { 66 L2: l2-cache-controller@20000 {
67 compatible = "fsl,8540-l2-cache-controller"; 67 compatible = "fsl,mpc8540-l2-cache-controller";
68 reg = <0x20000 0x1000>; 68 reg = <0x20000 0x1000>;
69 cache-line-size = <0x20>; /* 32 bytes */ 69 cache-line-size = <0x20>; /* 32 bytes */
70 cache-size = <0x40000>; /* L2, 256K */ 70 cache-size = <0x40000>; /* L2, 256K */
diff --git a/arch/powerpc/boot/dts/sbc8548.dts b/arch/powerpc/boot/dts/sbc8548.dts
index 9c5079fec4f2..b1f1416ac998 100644
--- a/arch/powerpc/boot/dts/sbc8548.dts
+++ b/arch/powerpc/boot/dts/sbc8548.dts
@@ -156,14 +156,14 @@
156 compatible = "simple-bus"; 156 compatible = "simple-bus";
157 157
158 memory-controller@2000 { 158 memory-controller@2000 {
159 compatible = "fsl,8548-memory-controller"; 159 compatible = "fsl,mpc8548-memory-controller";
160 reg = <0x2000 0x1000>; 160 reg = <0x2000 0x1000>;
161 interrupt-parent = <&mpic>; 161 interrupt-parent = <&mpic>;
162 interrupts = <0x12 0x2>; 162 interrupts = <0x12 0x2>;
163 }; 163 };
164 164
165 L2: l2-cache-controller@20000 { 165 L2: l2-cache-controller@20000 {
166 compatible = "fsl,8548-l2-cache-controller"; 166 compatible = "fsl,mpc8548-l2-cache-controller";
167 reg = <0x20000 0x1000>; 167 reg = <0x20000 0x1000>;
168 cache-line-size = <0x20>; // 32 bytes 168 cache-line-size = <0x20>; // 32 bytes
169 cache-size = <0x80000>; // L2, 512K 169 cache-size = <0x80000>; // L2, 512K
diff --git a/arch/powerpc/boot/dts/sbc8560.dts b/arch/powerpc/boot/dts/sbc8560.dts
index b772405a9a0a..c4564b81e473 100644
--- a/arch/powerpc/boot/dts/sbc8560.dts
+++ b/arch/powerpc/boot/dts/sbc8560.dts
@@ -61,14 +61,14 @@
61 clock-frequency = <0>; 61 clock-frequency = <0>;
62 62
63 memory-controller@2000 { 63 memory-controller@2000 {
64 compatible = "fsl,8560-memory-controller"; 64 compatible = "fsl,mpc8560-memory-controller";
65 reg = <0x2000 0x1000>; 65 reg = <0x2000 0x1000>;
66 interrupt-parent = <&mpic>; 66 interrupt-parent = <&mpic>;
67 interrupts = <0x12 0x2>; 67 interrupts = <0x12 0x2>;
68 }; 68 };
69 69
70 L2: l2-cache-controller@20000 { 70 L2: l2-cache-controller@20000 {
71 compatible = "fsl,8560-l2-cache-controller"; 71 compatible = "fsl,mpc8560-l2-cache-controller";
72 reg = <0x20000 0x1000>; 72 reg = <0x20000 0x1000>;
73 cache-line-size = <0x20>; // 32 bytes 73 cache-line-size = <0x20>; // 32 bytes
74 cache-size = <0x40000>; // L2, 256K 74 cache-size = <0x40000>; // L2, 256K
diff --git a/arch/powerpc/boot/dts/stx_gp3_8560.dts b/arch/powerpc/boot/dts/stx_gp3_8560.dts
index 8b173957fb5f..ea6b15152de3 100644
--- a/arch/powerpc/boot/dts/stx_gp3_8560.dts
+++ b/arch/powerpc/boot/dts/stx_gp3_8560.dts
@@ -57,14 +57,14 @@
57 compatible = "fsl,mpc8560-immr", "simple-bus"; 57 compatible = "fsl,mpc8560-immr", "simple-bus";
58 58
59 memory-controller@2000 { 59 memory-controller@2000 {
60 compatible = "fsl,8540-memory-controller"; 60 compatible = "fsl,mpc8540-memory-controller";
61 reg = <0x2000 0x1000>; 61 reg = <0x2000 0x1000>;
62 interrupt-parent = <&mpic>; 62 interrupt-parent = <&mpic>;
63 interrupts = <18 2>; 63 interrupts = <18 2>;
64 }; 64 };
65 65
66 L2: l2-cache-controller@20000 { 66 L2: l2-cache-controller@20000 {
67 compatible = "fsl,8540-l2-cache-controller"; 67 compatible = "fsl,mpc8540-l2-cache-controller";
68 reg = <0x20000 0x1000>; 68 reg = <0x20000 0x1000>;
69 cache-line-size = <32>; 69 cache-line-size = <32>;
70 cache-size = <0x40000>; // L2, 256K 70 cache-size = <0x40000>; // L2, 256K
diff --git a/arch/powerpc/boot/dts/tqm8540.dts b/arch/powerpc/boot/dts/tqm8540.dts
index ac9413a29f9f..231bae756637 100644
--- a/arch/powerpc/boot/dts/tqm8540.dts
+++ b/arch/powerpc/boot/dts/tqm8540.dts
@@ -59,14 +59,14 @@
59 compatible = "fsl,mpc8540-immr", "simple-bus"; 59 compatible = "fsl,mpc8540-immr", "simple-bus";
60 60
61 memory-controller@2000 { 61 memory-controller@2000 {
62 compatible = "fsl,8540-memory-controller"; 62 compatible = "fsl,mpc8540-memory-controller";
63 reg = <0x2000 0x1000>; 63 reg = <0x2000 0x1000>;
64 interrupt-parent = <&mpic>; 64 interrupt-parent = <&mpic>;
65 interrupts = <18 2>; 65 interrupts = <18 2>;
66 }; 66 };
67 67
68 L2: l2-cache-controller@20000 { 68 L2: l2-cache-controller@20000 {
69 compatible = "fsl,8540-l2-cache-controller"; 69 compatible = "fsl,mpc8540-l2-cache-controller";
70 reg = <0x20000 0x1000>; 70 reg = <0x20000 0x1000>;
71 cache-line-size = <32>; 71 cache-line-size = <32>;
72 cache-size = <0x40000>; // L2, 256K 72 cache-size = <0x40000>; // L2, 256K
diff --git a/arch/powerpc/boot/dts/tqm8541.dts b/arch/powerpc/boot/dts/tqm8541.dts
index c71bb5dd5e5e..4356a1f08295 100644
--- a/arch/powerpc/boot/dts/tqm8541.dts
+++ b/arch/powerpc/boot/dts/tqm8541.dts
@@ -58,14 +58,14 @@
58 compatible = "fsl,mpc8541-immr", "simple-bus"; 58 compatible = "fsl,mpc8541-immr", "simple-bus";
59 59
60 memory-controller@2000 { 60 memory-controller@2000 {
61 compatible = "fsl,8540-memory-controller"; 61 compatible = "fsl,mpc8540-memory-controller";
62 reg = <0x2000 0x1000>; 62 reg = <0x2000 0x1000>;
63 interrupt-parent = <&mpic>; 63 interrupt-parent = <&mpic>;
64 interrupts = <18 2>; 64 interrupts = <18 2>;
65 }; 65 };
66 66
67 L2: l2-cache-controller@20000 { 67 L2: l2-cache-controller@20000 {
68 compatible = "fsl,8540-l2-cache-controller"; 68 compatible = "fsl,mpc8540-l2-cache-controller";
69 reg = <0x20000 0x1000>; 69 reg = <0x20000 0x1000>;
70 cache-line-size = <32>; 70 cache-line-size = <32>;
71 cache-size = <0x40000>; // L2, 256K 71 cache-size = <0x40000>; // L2, 256K
diff --git a/arch/powerpc/boot/dts/tqm8555.dts b/arch/powerpc/boot/dts/tqm8555.dts
index a133ded6dddb..06d366ebbda3 100644
--- a/arch/powerpc/boot/dts/tqm8555.dts
+++ b/arch/powerpc/boot/dts/tqm8555.dts
@@ -58,14 +58,14 @@
58 compatible = "fsl,mpc8555-immr", "simple-bus"; 58 compatible = "fsl,mpc8555-immr", "simple-bus";
59 59
60 memory-controller@2000 { 60 memory-controller@2000 {
61 compatible = "fsl,8540-memory-controller"; 61 compatible = "fsl,mpc8540-memory-controller";
62 reg = <0x2000 0x1000>; 62 reg = <0x2000 0x1000>;
63 interrupt-parent = <&mpic>; 63 interrupt-parent = <&mpic>;
64 interrupts = <18 2>; 64 interrupts = <18 2>;
65 }; 65 };
66 66
67 L2: l2-cache-controller@20000 { 67 L2: l2-cache-controller@20000 {
68 compatible = "fsl,8540-l2-cache-controller"; 68 compatible = "fsl,mpc8540-l2-cache-controller";
69 reg = <0x20000 0x1000>; 69 reg = <0x20000 0x1000>;
70 cache-line-size = <32>; 70 cache-line-size = <32>;
71 cache-size = <0x40000>; // L2, 256K 71 cache-size = <0x40000>; // L2, 256K
diff --git a/arch/powerpc/boot/dts/tqm8560.dts b/arch/powerpc/boot/dts/tqm8560.dts
index 649e2e576267..feff915e0492 100644
--- a/arch/powerpc/boot/dts/tqm8560.dts
+++ b/arch/powerpc/boot/dts/tqm8560.dts
@@ -60,14 +60,14 @@
60 compatible = "fsl,mpc8560-immr", "simple-bus"; 60 compatible = "fsl,mpc8560-immr", "simple-bus";
61 61
62 memory-controller@2000 { 62 memory-controller@2000 {
63 compatible = "fsl,8540-memory-controller"; 63 compatible = "fsl,mpc8540-memory-controller";
64 reg = <0x2000 0x1000>; 64 reg = <0x2000 0x1000>;
65 interrupt-parent = <&mpic>; 65 interrupt-parent = <&mpic>;
66 interrupts = <18 2>; 66 interrupts = <18 2>;
67 }; 67 };
68 68
69 L2: l2-cache-controller@20000 { 69 L2: l2-cache-controller@20000 {
70 compatible = "fsl,8540-l2-cache-controller"; 70 compatible = "fsl,mpc8540-l2-cache-controller";
71 reg = <0x20000 0x1000>; 71 reg = <0x20000 0x1000>;
72 cache-line-size = <32>; 72 cache-line-size = <32>;
73 cache-size = <0x40000>; // L2, 256K 73 cache-size = <0x40000>; // L2, 256K
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-10 01:04:03 -0500