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-rw-r--r--arch/powerpc/boot/dts/p1010rdb.dts280
-rw-r--r--arch/powerpc/boot/dts/p1010si.dtsi376
-rw-r--r--arch/powerpc/configs/mpc85xx_defconfig1
-rw-r--r--arch/powerpc/platforms/85xx/Kconfig10
-rw-r--r--arch/powerpc/platforms/85xx/Makefile1
-rw-r--r--arch/powerpc/platforms/85xx/p1010rdb.c122
6 files changed, 790 insertions, 0 deletions
diff --git a/arch/powerpc/boot/dts/p1010rdb.dts b/arch/powerpc/boot/dts/p1010rdb.dts
new file mode 100644
index 000000000000..6b33b73a5ba0
--- /dev/null
+++ b/arch/powerpc/boot/dts/p1010rdb.dts
@@ -0,0 +1,280 @@
1/*
2 * P1010 RDB Device Tree Source
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
11
12/include/ "p1010si.dtsi"
13
14/ {
15 model = "fsl,P1010RDB";
16 compatible = "fsl,P1010RDB";
17
18 aliases {
19 serial0 = &serial0;
20 serial1 = &serial1;
21 ethernet0 = &enet0;
22 ethernet1 = &enet1;
23 ethernet2 = &enet2;
24 pci0 = &pci0;
25 pci1 = &pci1;
26 };
27
28 memory {
29 device_type = "memory";
30 };
31
32 ifc@ffe1e000 {
33 /* NOR, NAND Flashes and CPLD on board */
34 ranges = <0x0 0x0 0x0 0xee000000 0x02000000
35 0x1 0x0 0x0 0xff800000 0x00010000
36 0x3 0x0 0x0 0xffb00000 0x00000020>;
37
38 nor@0,0 {
39 #address-cells = <1>;
40 #size-cells = <1>;
41 compatible = "cfi-flash";
42 reg = <0x0 0x0 0x2000000>;
43 bank-width = <2>;
44 device-width = <1>;
45
46 partition@40000 {
47 /* 256KB for DTB Image */
48 reg = <0x00040000 0x00040000>;
49 label = "NOR DTB Image";
50 };
51
52 partition@80000 {
53 /* 7 MB for Linux Kernel Image */
54 reg = <0x00080000 0x00700000>;
55 label = "NOR Linux Kernel Image";
56 };
57
58 partition@800000 {
59 /* 20MB for JFFS2 based Root file System */
60 reg = <0x00800000 0x01400000>;
61 label = "NOR JFFS2 Root File System";
62 };
63
64 partition@1f00000 {
65 /* This location must not be altered */
66 /* 512KB for u-boot Bootloader Image */
67 /* 512KB for u-boot Environment Variables */
68 reg = <0x01f00000 0x00100000>;
69 label = "NOR U-Boot Image";
70 read-only;
71 };
72 };
73
74 nand@1,0 {
75 #address-cells = <1>;
76 #size-cells = <1>;
77 compatible = "fsl,ifc-nand";
78 reg = <0x1 0x0 0x10000>;
79
80 partition@0 {
81 /* This location must not be altered */
82 /* 1MB for u-boot Bootloader Image */
83 reg = <0x0 0x00100000>;
84 label = "NAND U-Boot Image";
85 read-only;
86 };
87
88 partition@100000 {
89 /* 1MB for DTB Image */
90 reg = <0x00100000 0x00100000>;
91 label = "NAND DTB Image";
92 };
93
94 partition@200000 {
95 /* 4MB for Linux Kernel Image */
96 reg = <0x00200000 0x00400000>;
97 label = "NAND Linux Kernel Image";
98 };
99
100 partition@600000 {
101 /* 4MB for Compressed Root file System Image */
102 reg = <0x00600000 0x00400000>;
103 label = "NAND Compressed RFS Image";
104 };
105
106 partition@a00000 {
107 /* 15MB for JFFS2 based Root file System */
108 reg = <0x00a00000 0x00f00000>;
109 label = "NAND JFFS2 Root File System";
110 };
111
112 partition@1900000 {
113 /* 7MB for User Area */
114 reg = <0x01900000 0x00700000>;
115 label = "NAND User area";
116 };
117 };
118
119 cpld@3,0 {
120 #address-cells = <1>;
121 #size-cells = <1>;
122 compatible = "fsl,p1010rdb-cpld";
123 reg = <0x3 0x0 0x0000020>;
124 bank-width = <1>;
125 device-width = <1>;
126 };
127 };
128
129 soc@ffe00000 {
130 spi@7000 {
131 flash@0 {
132 #address-cells = <1>;
133 #size-cells = <1>;
134 compatible = "spansion,s25sl12801";
135 reg = <0>;
136 spi-max-frequency = <50000000>;
137
138 partition@0 {
139 /* 1MB for u-boot Bootloader Image */
140 /* 1MB for Environment */
141 reg = <0x0 0x00100000>;
142 label = "SPI Flash U-Boot Image";
143 read-only;
144 };
145
146 partition@100000 {
147 /* 512KB for DTB Image */
148 reg = <0x00100000 0x00080000>;
149 label = "SPI Flash DTB Image";
150 };
151
152 partition@180000 {
153 /* 4MB for Linux Kernel Image */
154 reg = <0x00180000 0x00400000>;
155 label = "SPI Flash Linux Kernel Image";
156 };
157
158 partition@580000 {
159 /* 4MB for Compressed RFS Image */
160 reg = <0x00580000 0x00400000>;
161 label = "SPI Flash Compressed RFSImage";
162 };
163
164 partition@980000 {
165 /* 6.5MB for JFFS2 based RFS */
166 reg = <0x00980000 0x00680000>;
167 label = "SPI Flash JFFS2 RFS";
168 };
169 };
170 };
171
172 can0@1c000 {
173 fsl,flexcan-clock-source = "platform";
174 };
175
176 can1@1d000 {
177 fsl,flexcan-clock-source = "platform";
178 };
179
180 usb@22000 {
181 phy_type = "utmi";
182 };
183
184 mdio@24000 {
185 phy0: ethernet-phy@0 {
186 interrupt-parent = <&mpic>;
187 interrupts = <3 1>;
188 reg = <0x1>;
189 };
190
191 phy1: ethernet-phy@1 {
192 interrupt-parent = <&mpic>;
193 interrupts = <2 1>;
194 reg = <0x0>;
195 };
196
197 phy2: ethernet-phy@2 {
198 interrupt-parent = <&mpic>;
199 interrupts = <2 1>;
200 reg = <0x2>;
201 };
202 };
203
204 enet0: ethernet@b0000 {
205 phy-handle = <&phy0>;
206 phy-connection-type = "rgmii-id";
207 };
208
209 enet1: ethernet@b1000 {
210 phy-handle = <&phy1>;
211 tbi-handle = <&tbi0>;
212 phy-connection-type = "sgmii";
213 };
214
215 enet2: ethernet@b2000 {
216 phy-handle = <&phy2>;
217 tbi-handle = <&tbi1>;
218 phy-connection-type = "sgmii";
219 };
220 };
221
222 pci0: pcie@ffe09000 {
223 ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
224 0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
225 pcie@0 {
226 reg = <0x0 0x0 0x0 0x0 0x0>;
227 #interrupt-cells = <1>;
228 #size-cells = <2>;
229 #address-cells = <3>;
230 device_type = "pci";
231 interrupt-parent = <&mpic>;
232 interrupts = <16 2>;
233 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
234 interrupt-map = <
235 /* IDSEL 0x0 */
236 0000 0x0 0x0 0x1 &mpic 0x4 0x1
237 0000 0x0 0x0 0x2 &mpic 0x5 0x1
238 0000 0x0 0x0 0x3 &mpic 0x6 0x1
239 0000 0x0 0x0 0x4 &mpic 0x7 0x1
240 >;
241
242 ranges = <0x2000000 0x0 0xa0000000
243 0x2000000 0x0 0xa0000000
244 0x0 0x20000000
245
246 0x1000000 0x0 0x0
247 0x1000000 0x0 0x0
248 0x0 0x100000>;
249 };
250 };
251
252 pci1: pcie@ffe0a000 {
253 ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000
254 0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>;
255 pcie@0 {
256 reg = <0x0 0x0 0x0 0x0 0x0>;
257 #interrupt-cells = <1>;
258 #size-cells = <2>;
259 #address-cells = <3>;
260 device_type = "pci";
261 interrupt-parent = <&mpic>;
262 interrupts = <16 2>;
263 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
264 interrupt-map = <
265 /* IDSEL 0x0 */
266 0000 0x0 0x0 0x1 &mpic 0x4 0x1
267 0000 0x0 0x0 0x2 &mpic 0x5 0x1
268 0000 0x0 0x0 0x3 &mpic 0x6 0x1
269 0000 0x0 0x0 0x4 &mpic 0x7 0x1
270 >;
271 ranges = <0x2000000 0x0 0x80000000
272 0x2000000 0x0 0x80000000
273 0x0 0x20000000
274
275 0x1000000 0x0 0x0
276 0x1000000 0x0 0x0
277 0x0 0x100000>;
278 };
279 };
280};
diff --git a/arch/powerpc/boot/dts/p1010si.dtsi b/arch/powerpc/boot/dts/p1010si.dtsi
new file mode 100644
index 000000000000..7f51104f2e36
--- /dev/null
+++ b/arch/powerpc/boot/dts/p1010si.dtsi
@@ -0,0 +1,376 @@
1/*
2 * P1010si Device Tree Source
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
11
12/dts-v1/;
13/ {
14 compatible = "fsl,P1010";
15 #address-cells = <2>;
16 #size-cells = <2>;
17
18 cpus {
19 #address-cells = <1>;
20 #size-cells = <0>;
21
22 PowerPC,P1010@0 {
23 device_type = "cpu";
24 reg = <0x0>;
25 next-level-cache = <&L2>;
26 };
27 };
28
29 ifc@ffe1e000 {
30 #address-cells = <2>;
31 #size-cells = <1>;
32 compatible = "fsl,ifc", "simple-bus";
33 reg = <0x0 0xffe1e000 0 0x2000>;
34 interrupts = <16 2 19 2>;
35 interrupt-parent = <&mpic>;
36 };
37
38 soc@ffe00000 {
39 #address-cells = <1>;
40 #size-cells = <1>;
41 device_type = "soc";
42 compatible = "fsl,p1010-immr", "simple-bus";
43 ranges = <0x0 0x0 0xffe00000 0x100000>;
44 bus-frequency = <0>; // Filled out by uboot.
45
46 ecm-law@0 {
47 compatible = "fsl,ecm-law";
48 reg = <0x0 0x1000>;
49 fsl,num-laws = <12>;
50 };
51
52 ecm@1000 {
53 compatible = "fsl,p1010-ecm", "fsl,ecm";
54 reg = <0x1000 0x1000>;
55 interrupts = <16 2>;
56 interrupt-parent = <&mpic>;
57 };
58
59 memory-controller@2000 {
60 compatible = "fsl,p1010-memory-controller";
61 reg = <0x2000 0x1000>;
62 interrupt-parent = <&mpic>;
63 interrupts = <16 2>;
64 };
65
66 i2c@3000 {
67 #address-cells = <1>;
68 #size-cells = <0>;
69 cell-index = <0>;
70 compatible = "fsl-i2c";
71 reg = <0x3000 0x100>;
72 interrupts = <43 2>;
73 interrupt-parent = <&mpic>;
74 dfsrr;
75 };
76
77 i2c@3100 {
78 #address-cells = <1>;
79 #size-cells = <0>;
80 cell-index = <1>;
81 compatible = "fsl-i2c";
82 reg = <0x3100 0x100>;
83 interrupts = <43 2>;
84 interrupt-parent = <&mpic>;
85 dfsrr;
86 };
87
88 serial0: serial@4500 {
89 cell-index = <0>;
90 device_type = "serial";
91 compatible = "ns16550";
92 reg = <0x4500 0x100>;
93 clock-frequency = <0>;
94 interrupts = <42 2>;
95 interrupt-parent = <&mpic>;
96 };
97
98 serial1: serial@4600 {
99 cell-index = <1>;
100 device_type = "serial";
101 compatible = "ns16550";
102 reg = <0x4600 0x100>;
103 clock-frequency = <0>;
104 interrupts = <42 2>;
105 interrupt-parent = <&mpic>;
106 };
107
108 spi@7000 {
109 #address-cells = <1>;
110 #size-cells = <0>;
111 compatible = "fsl,mpc8536-espi";
112 reg = <0x7000 0x1000>;
113 interrupts = <59 0x2>;
114 interrupt-parent = <&mpic>;
115 fsl,espi-num-chipselects = <1>;
116 };
117
118 gpio: gpio-controller@f000 {
119 #gpio-cells = <2>;
120 compatible = "fsl,mpc8572-gpio";
121 reg = <0xf000 0x100>;
122 interrupts = <47 0x2>;
123 interrupt-parent = <&mpic>;
124 gpio-controller;
125 };
126
127 sata@18000 {
128 compatible = "fsl,pq-sata-v2";
129 reg = <0x18000 0x1000>;
130 cell-index = <1>;
131 interrupts = <74 0x2>;
132 interrupt-parent = <&mpic>;
133 };
134
135 sata@19000 {
136 compatible = "fsl,pq-sata-v2";
137 reg = <0x19000 0x1000>;
138 cell-index = <2>;
139 interrupts = <41 0x2>;
140 interrupt-parent = <&mpic>;
141 };
142
143 can0@1c000 {
144 compatible = "fsl,flexcan-v1.0";
145 reg = <0x1c000 0x1000>;
146 interrupts = <48 0x2>;
147 interrupt-parent = <&mpic>;
148 fsl,flexcan-clock-divider = <2>;
149 };
150
151 can1@1d000 {
152 compatible = "fsl,flexcan-v1.0";
153 reg = <0x1d000 0x1000>;
154 interrupts = <61 0x2>;
155 interrupt-parent = <&mpic>;
156 fsl,flexcan-clock-divider = <2>;
157 };
158
159 L2: l2-cache-controller@20000 {
160 compatible = "fsl,p1010-l2-cache-controller",
161 "fsl,p1014-l2-cache-controller";
162 reg = <0x20000 0x1000>;
163 cache-line-size = <32>; // 32 bytes
164 cache-size = <0x40000>; // L2,256K
165 interrupt-parent = <&mpic>;
166 interrupts = <16 2>;
167 };
168
169 dma@21300 {
170 #address-cells = <1>;
171 #size-cells = <1>;
172 compatible = "fsl,p1010-dma", "fsl,eloplus-dma";
173 reg = <0x21300 0x4>;
174 ranges = <0x0 0x21100 0x200>;
175 cell-index = <0>;
176 dma-channel@0 {
177 compatible = "fsl,p1010-dma-channel", "fsl,eloplus-dma-channel";
178 reg = <0x0 0x80>;
179 cell-index = <0>;
180 interrupt-parent = <&mpic>;
181 interrupts = <20 2>;
182 };
183 dma-channel@80 {
184 compatible = "fsl,p1010-dma-channel", "fsl,eloplus-dma-channel";
185 reg = <0x80 0x80>;
186 cell-index = <1>;
187 interrupt-parent = <&mpic>;
188 interrupts = <21 2>;
189 };
190 dma-channel@100 {
191 compatible = "fsl,p1010-dma-channel", "fsl,eloplus-dma-channel";
192 reg = <0x100 0x80>;
193 cell-index = <2>;
194 interrupt-parent = <&mpic>;
195 interrupts = <22 2>;
196 };
197 dma-channel@180 {
198 compatible = "fsl,p1010-dma-channel", "fsl,eloplus-dma-channel";
199 reg = <0x180 0x80>;
200 cell-index = <3>;
201 interrupt-parent = <&mpic>;
202 interrupts = <23 2>;
203 };
204 };
205
206 usb@22000 {
207 compatible = "fsl-usb2-dr";
208 reg = <0x22000 0x1000>;
209 #address-cells = <1>;
210 #size-cells = <0>;
211 interrupt-parent = <&mpic>;
212 interrupts = <28 0x2>;
213 dr_mode = "host";
214 };
215
216 mdio@24000 {
217 #address-cells = <1>;
218 #size-cells = <0>;
219 compatible = "fsl,etsec2-mdio";
220 reg = <0x24000 0x1000 0xb0030 0x4>;
221 };
222
223 mdio@25000 {
224 #address-cells = <1>;
225 #size-cells = <0>;
226 compatible = "fsl,etsec2-tbi";
227 reg = <0x25000 0x1000 0xb1030 0x4>;
228 tbi0: tbi-phy@11 {
229 reg = <0x11>;
230 device_type = "tbi-phy";
231 };
232 };
233
234 mdio@26000 {
235 #address-cells = <1>;
236 #size-cells = <0>;
237 compatible = "fsl,etsec2-tbi";
238 reg = <0x26000 0x1000 0xb1030 0x4>;
239 tbi1: tbi-phy@11 {
240 reg = <0x11>;
241 device_type = "tbi-phy";
242 };
243 };
244
245 sdhci@2e000 {
246 compatible = "fsl,esdhc";
247 reg = <0x2e000 0x1000>;
248 interrupts = <72 0x8>;
249 interrupt-parent = <&mpic>;
250 /* Filled in by U-Boot */
251 clock-frequency = <0>;
252 fsl,sdhci-auto-cmd12;
253 };
254
255 enet0: ethernet@b0000 {
256 #address-cells = <1>;
257 #size-cells = <1>;
258 device_type = "network";
259 model = "eTSEC";
260 compatible = "fsl,etsec2";
261 fsl,num_rx_queues = <0x8>;
262 fsl,num_tx_queues = <0x8>;
263 local-mac-address = [ 00 00 00 00 00 00 ];
264 interrupt-parent = <&mpic>;
265
266 queue-group@0 {
267 #address-cells = <1>;
268 #size-cells = <1>;
269 reg = <0xb0000 0x1000>;
270 fsl,rx-bit-map = <0xff>;
271 fsl,tx-bit-map = <0xff>;
272 interrupts = <29 2 30 2 34 2>;
273 };
274
275 };
276
277 enet1: ethernet@b1000 {
278 #address-cells = <1>;
279 #size-cells = <1>;
280 device_type = "network";
281 model = "eTSEC";
282 compatible = "fsl,etsec2";
283 fsl,num_rx_queues = <0x8>;
284 fsl,num_tx_queues = <0x8>;
285 local-mac-address = [ 00 00 00 00 00 00 ];
286 interrupt-parent = <&mpic>;
287
288 queue-group@0 {
289 #address-cells = <1>;
290 #size-cells = <1>;
291 reg = <0xb1000 0x1000>;
292 fsl,rx-bit-map = <0xff>;
293 fsl,tx-bit-map = <0xff>;
294 interrupts = <35 2 36 2 40 2>;
295 };
296
297 };
298
299 enet2: ethernet@b2000 {
300 #address-cells = <1>;
301 #size-cells = <1>;
302 device_type = "network";
303 model = "eTSEC";
304 compatible = "fsl,etsec2";
305 fsl,num_rx_queues = <0x8>;
306 fsl,num_tx_queues = <0x8>;
307 local-mac-address = [ 00 00 00 00 00 00 ];
308 interrupt-parent = <&mpic>;
309
310 queue-group@0 {
311 #address-cells = <1>;
312 #size-cells = <1>;
313 reg = <0xb2000 0x1000>;
314 fsl,rx-bit-map = <0xff>;
315 fsl,tx-bit-map = <0xff>;
316 interrupts = <31 2 32 2 33 2>;
317 };
318
319 };
320
321 mpic: pic@40000 {
322 interrupt-controller;
323 #address-cells = <0>;
324 #interrupt-cells = <2>;
325 reg = <0x40000 0x40000>;
326 compatible = "chrp,open-pic";
327 device_type = "open-pic";
328 };
329
330 msi@41600 {
331 compatible = "fsl,p1010-msi", "fsl,mpic-msi";
332 reg = <0x41600 0x80>;
333 msi-available-ranges = <0 0x100>;
334 interrupts = <
335 0xe0 0
336 0xe1 0
337 0xe2 0
338 0xe3 0
339 0xe4 0
340 0xe5 0
341 0xe6 0
342 0xe7 0>;
343 interrupt-parent = <&mpic>;
344 };
345
346 global-utilities@e0000 { //global utilities block
347 compatible = "fsl,p1010-guts";
348 reg = <0xe0000 0x1000>;
349 fsl,has-rstcr;
350 };
351 };
352
353 pci0: pcie@ffe09000 {
354 compatible = "fsl,p1010-pcie", "fsl,qoriq-pcie-v2.3", "fsl,qoriq-pcie-v2.2";
355 device_type = "pci";
356 #size-cells = <2>;
357 #address-cells = <3>;
358 reg = <0 0xffe09000 0 0x1000>;
359 bus-range = <0 255>;
360 clock-frequency = <33333333>;
361 interrupt-parent = <&mpic>;
362 interrupts = <16 2>;
363 };
364
365 pci1: pcie@ffe0a000 {
366 compatible = "fsl,p1010-pcie", "fsl,qoriq-pcie-v2.3", "fsl,qoriq-pcie-v2.2";
367 device_type = "pci";
368 #size-cells = <2>;
369 #address-cells = <3>;
370 reg = <0 0xffe0a000 0 0x1000>;
371 bus-range = <0 255>;
372 clock-frequency = <33333333>;
373 interrupt-parent = <&mpic>;
374 interrupts = <16 2>;
375 };
376};
diff --git a/arch/powerpc/configs/mpc85xx_defconfig b/arch/powerpc/configs/mpc85xx_defconfig
index 37839f1315e3..fcd85d2c72dc 100644
--- a/arch/powerpc/configs/mpc85xx_defconfig
+++ b/arch/powerpc/configs/mpc85xx_defconfig
@@ -26,6 +26,7 @@ CONFIG_MPC85xx_MDS=y
26CONFIG_MPC8536_DS=y 26CONFIG_MPC8536_DS=y
27CONFIG_MPC85xx_DS=y 27CONFIG_MPC85xx_DS=y
28CONFIG_MPC85xx_RDB=y 28CONFIG_MPC85xx_RDB=y
29CONFIG_P1010_RDB=y
29CONFIG_P1022_DS=y 30CONFIG_P1022_DS=y
30CONFIG_P1023_RDS=y 31CONFIG_P1023_RDS=y
31CONFIG_SOCRATES=y 32CONFIG_SOCRATES=y
diff --git a/arch/powerpc/platforms/85xx/Kconfig b/arch/powerpc/platforms/85xx/Kconfig
index 10e147a1f302..4706c71c9435 100644
--- a/arch/powerpc/platforms/85xx/Kconfig
+++ b/arch/powerpc/platforms/85xx/Kconfig
@@ -67,6 +67,16 @@ config MPC85xx_RDB
67 help 67 help
68 This option enables support for the MPC85xx RDB (P2020 RDB) board 68 This option enables support for the MPC85xx RDB (P2020 RDB) board
69 69
70config P1010_RDB
71 bool "Freescale P1010RDB"
72 select DEFAULT_UIMAGE
73 help
74 This option enables support for the MPC85xx RDB (P1010 RDB) board
75
76 P1010RDB contains P1010Si, which provides CPU performance up to 800
77 MHz and 1600 DMIPS, additional functionality and faster interfaces
78 (DDR3/3L, SATA II, and PCI Express).
79
70config P1022_DS 80config P1022_DS
71 bool "Freescale P1022 DS" 81 bool "Freescale P1022 DS"
72 select DEFAULT_UIMAGE 82 select DEFAULT_UIMAGE
diff --git a/arch/powerpc/platforms/85xx/Makefile b/arch/powerpc/platforms/85xx/Makefile
index 5c08be5b6020..06b0c0877864 100644
--- a/arch/powerpc/platforms/85xx/Makefile
+++ b/arch/powerpc/platforms/85xx/Makefile
@@ -10,6 +10,7 @@ obj-$(CONFIG_MPC8536_DS) += mpc8536_ds.o
10obj-$(CONFIG_MPC85xx_DS) += mpc85xx_ds.o 10obj-$(CONFIG_MPC85xx_DS) += mpc85xx_ds.o
11obj-$(CONFIG_MPC85xx_MDS) += mpc85xx_mds.o 11obj-$(CONFIG_MPC85xx_MDS) += mpc85xx_mds.o
12obj-$(CONFIG_MPC85xx_RDB) += mpc85xx_rdb.o 12obj-$(CONFIG_MPC85xx_RDB) += mpc85xx_rdb.o
13obj-$(CONFIG_P1010_RDB) += p1010rdb.o
13obj-$(CONFIG_P1022_DS) += p1022_ds.o 14obj-$(CONFIG_P1022_DS) += p1022_ds.o
14obj-$(CONFIG_P1023_RDS) += p1023_rds.o 15obj-$(CONFIG_P1023_RDS) += p1023_rds.o
15obj-$(CONFIG_P3041_DS) += p3041_ds.o corenet_ds.o 16obj-$(CONFIG_P3041_DS) += p3041_ds.o corenet_ds.o
diff --git a/arch/powerpc/platforms/85xx/p1010rdb.c b/arch/powerpc/platforms/85xx/p1010rdb.c
new file mode 100644
index 000000000000..d7387fa7f534
--- /dev/null
+++ b/arch/powerpc/platforms/85xx/p1010rdb.c
@@ -0,0 +1,122 @@
1/*
2 * P1010RDB Board Setup
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
11
12#include <linux/stddef.h>
13#include <linux/kernel.h>
14#include <linux/pci.h>
15#include <linux/delay.h>
16#include <linux/interrupt.h>
17#include <linux/of_platform.h>
18
19#include <asm/system.h>
20#include <asm/time.h>
21#include <asm/machdep.h>
22#include <asm/pci-bridge.h>
23#include <mm/mmu_decl.h>
24#include <asm/prom.h>
25#include <asm/udbg.h>
26#include <asm/mpic.h>
27
28#include <sysdev/fsl_soc.h>
29#include <sysdev/fsl_pci.h>
30
31void __init p1010_rdb_pic_init(void)
32{
33 struct mpic *mpic;
34 struct resource r;
35 struct device_node *np;
36
37 np = of_find_node_by_type(NULL, "open-pic");
38 if (np == NULL) {
39 printk(KERN_ERR "Could not find open-pic node\n");
40 return;
41 }
42
43 if (of_address_to_resource(np, 0, &r)) {
44 printk(KERN_ERR "Failed to map mpic register space\n");
45 of_node_put(np);
46 return;
47 }
48
49 mpic = mpic_alloc(np, r.start, MPIC_PRIMARY | MPIC_WANTS_RESET |
50 MPIC_BIG_ENDIAN | MPIC_BROKEN_FRR_NIRQS | MPIC_SINGLE_DEST_CPU,
51 0, 256, " OpenPIC ");
52
53 BUG_ON(mpic == NULL);
54 of_node_put(np);
55
56 mpic_init(mpic);
57
58}
59
60
61/*
62 * Setup the architecture
63 */
64static void __init p1010_rdb_setup_arch(void)
65{
66#ifdef CONFIG_PCI
67 struct device_node *np;
68#endif
69
70 if (ppc_md.progress)
71 ppc_md.progress("p1010_rdb_setup_arch()", 0);
72
73#ifdef CONFIG_PCI
74 for_each_node_by_type(np, "pci") {
75 if (of_device_is_compatible(np, "fsl,p1010-pcie"))
76 fsl_add_bridge(np, 0);
77 }
78
79#endif
80
81 printk(KERN_INFO "P1010 RDB board from Freescale Semiconductor\n");
82}
83
84static struct of_device_id __initdata p1010rdb_ids[] = {
85 { .type = "soc", },
86 { .compatible = "soc", },
87 { .compatible = "simple-bus", },
88 {},
89};
90
91static int __init p1010rdb_publish_devices(void)
92{
93 return of_platform_bus_probe(NULL, p1010rdb_ids, NULL);
94}
95machine_device_initcall(p1010_rdb, p1010rdb_publish_devices);
96machine_arch_initcall(p1010_rdb, swiotlb_setup_bus_notifier);
97
98/*
99 * Called very early, device-tree isn't unflattened
100 */
101static int __init p1010_rdb_probe(void)
102{
103 unsigned long root = of_get_flat_dt_root();
104
105 if (of_flat_dt_is_compatible(root, "fsl,P1010RDB"))
106 return 1;
107 return 0;
108}
109
110define_machine(p1010_rdb) {
111 .name = "P1010 RDB",
112 .probe = p1010_rdb_probe,
113 .setup_arch = p1010_rdb_setup_arch,
114 .init_IRQ = p1010_rdb_pic_init,
115#ifdef CONFIG_PCI
116 .pcibios_fixup_bus = fsl_pcibios_fixup_bus,
117#endif
118 .get_irq = mpic_get_irq,
119 .restart = fsl_rstcr_restart,
120 .calibrate_decr = generic_calibrate_decr,
121 .progress = udbg_progress,
122};
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-15 15:16:59 -0500