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-rw-r--r--arch/powerpc/platforms/83xx/mpc836x_mds.c31
1 files changed, 28 insertions, 3 deletions
diff --git a/arch/powerpc/platforms/83xx/mpc836x_mds.c b/arch/powerpc/platforms/83xx/mpc836x_mds.c
index 0f3855c95ff5..0a722601a2f0 100644
--- a/arch/powerpc/platforms/83xx/mpc836x_mds.c
+++ b/arch/powerpc/platforms/83xx/mpc836x_mds.c
@@ -96,14 +96,39 @@ static void __init mpc836x_mds_setup_arch(void)
96 96
97 if ((np = of_find_compatible_node(NULL, "network", "ucc_geth")) 97 if ((np = of_find_compatible_node(NULL, "network", "ucc_geth"))
98 != NULL){ 98 != NULL){
99 uint svid;
100
99 /* Reset the Ethernet PHY */ 101 /* Reset the Ethernet PHY */
100 bcsr_regs[9] &= ~0x20; 102#define BCSR9_GETHRST 0x20
103 clrbits8(&bcsr_regs[9], BCSR9_GETHRST);
101 udelay(1000); 104 udelay(1000);
102 bcsr_regs[9] |= 0x20; 105 setbits8(&bcsr_regs[9], BCSR9_GETHRST);
106
107 /* handle mpc8360ea rev.2.1 erratum 2: RGMII Timing */
108 svid = mfspr(SPRN_SVR);
109 if (svid == 0x80480021) {
110 void __iomem *immap;
111
112 immap = ioremap(get_immrbase() + 0x14a8, 8);
113
114 /*
115 * IMMR + 0x14A8[4:5] = 11 (clk delay for UCC 2)
116 * IMMR + 0x14A8[18:19] = 11 (clk delay for UCC 1)
117 */
118 setbits32(immap, 0x0c003000);
119
120 /*
121 * IMMR + 0x14AC[20:27] = 10101010
122 * (data delay for both UCC's)
123 */
124 clrsetbits_be32(immap + 4, 0xff0, 0xaa0);
125
126 iounmap(immap);
127 }
128
103 iounmap(bcsr_regs); 129 iounmap(bcsr_regs);
104 of_node_put(np); 130 of_node_put(np);
105 } 131 }
106
107#endif /* CONFIG_QUICC_ENGINE */ 132#endif /* CONFIG_QUICC_ENGINE */
108} 133}
109 134