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-rw-r--r--arch/powerpc/include/asm/cell-regs.h11
-rw-r--r--arch/powerpc/include/asm/iommu.h10
-rw-r--r--arch/powerpc/platforms/ps3/mm.c2
-rw-r--r--arch/powerpc/platforms/ps3/system-bus.c2
4 files changed, 13 insertions, 12 deletions
diff --git a/arch/powerpc/include/asm/cell-regs.h b/arch/powerpc/include/asm/cell-regs.h
index fd6fd00434ef..fdf64fd25950 100644
--- a/arch/powerpc/include/asm/cell-regs.h
+++ b/arch/powerpc/include/asm/cell-regs.h
@@ -303,6 +303,17 @@ struct cbe_mic_tm_regs {
303extern struct cbe_mic_tm_regs __iomem *cbe_get_mic_tm_regs(struct device_node *np); 303extern struct cbe_mic_tm_regs __iomem *cbe_get_mic_tm_regs(struct device_node *np);
304extern struct cbe_mic_tm_regs __iomem *cbe_get_cpu_mic_tm_regs(int cpu); 304extern struct cbe_mic_tm_regs __iomem *cbe_get_cpu_mic_tm_regs(int cpu);
305 305
306
307/* Cell page table entries */
308#define CBE_IOPTE_PP_W 0x8000000000000000ul /* protection: write */
309#define CBE_IOPTE_PP_R 0x4000000000000000ul /* protection: read */
310#define CBE_IOPTE_M 0x2000000000000000ul /* coherency required */
311#define CBE_IOPTE_SO_R 0x1000000000000000ul /* ordering: writes */
312#define CBE_IOPTE_SO_RW 0x1800000000000000ul /* ordering: r & w */
313#define CBE_IOPTE_RPN_Mask 0x07fffffffffff000ul /* RPN */
314#define CBE_IOPTE_H 0x0000000000000800ul /* cache hint */
315#define CBE_IOPTE_IOID_Mask 0x00000000000007fful /* ioid */
316
306/* some utility functions to deal with SMT */ 317/* some utility functions to deal with SMT */
307extern u32 cbe_get_hw_thread_id(int cpu); 318extern u32 cbe_get_hw_thread_id(int cpu);
308extern u32 cbe_cpu_to_node(int cpu); 319extern u32 cbe_cpu_to_node(int cpu);
diff --git a/arch/powerpc/include/asm/iommu.h b/arch/powerpc/include/asm/iommu.h
index 7ead7c16fb7c..7464c0daddd1 100644
--- a/arch/powerpc/include/asm/iommu.h
+++ b/arch/powerpc/include/asm/iommu.h
@@ -35,16 +35,6 @@
35#define IOMMU_PAGE_MASK (~((1 << IOMMU_PAGE_SHIFT) - 1)) 35#define IOMMU_PAGE_MASK (~((1 << IOMMU_PAGE_SHIFT) - 1))
36#define IOMMU_PAGE_ALIGN(addr) _ALIGN_UP(addr, IOMMU_PAGE_SIZE) 36#define IOMMU_PAGE_ALIGN(addr) _ALIGN_UP(addr, IOMMU_PAGE_SIZE)
37 37
38/* Cell page table entries */
39#define CBE_IOPTE_PP_W 0x8000000000000000ul /* protection: write */
40#define CBE_IOPTE_PP_R 0x4000000000000000ul /* protection: read */
41#define CBE_IOPTE_M 0x2000000000000000ul /* coherency required */
42#define CBE_IOPTE_SO_R 0x1000000000000000ul /* ordering: writes */
43#define CBE_IOPTE_SO_RW 0x1800000000000000ul /* ordering: r & w */
44#define CBE_IOPTE_RPN_Mask 0x07fffffffffff000ul /* RPN */
45#define CBE_IOPTE_H 0x0000000000000800ul /* cache hint */
46#define CBE_IOPTE_IOID_Mask 0x00000000000007fful /* ioid */
47
48/* Boot time flags */ 38/* Boot time flags */
49extern int iommu_is_off; 39extern int iommu_is_off;
50extern int iommu_force_on; 40extern int iommu_force_on;
diff --git a/arch/powerpc/platforms/ps3/mm.c b/arch/powerpc/platforms/ps3/mm.c
index 846eb8b57fd1..189a25b80735 100644
--- a/arch/powerpc/platforms/ps3/mm.c
+++ b/arch/powerpc/platforms/ps3/mm.c
@@ -23,8 +23,8 @@
23#include <linux/memory_hotplug.h> 23#include <linux/memory_hotplug.h>
24#include <linux/lmb.h> 24#include <linux/lmb.h>
25 25
26#include <asm/cell-regs.h>
26#include <asm/firmware.h> 27#include <asm/firmware.h>
27#include <asm/iommu.h>
28#include <asm/prom.h> 28#include <asm/prom.h>
29#include <asm/udbg.h> 29#include <asm/udbg.h>
30#include <asm/lv1call.h> 30#include <asm/lv1call.h>
diff --git a/arch/powerpc/platforms/ps3/system-bus.c b/arch/powerpc/platforms/ps3/system-bus.c
index 3f763c5284ac..676f989ed4e4 100644
--- a/arch/powerpc/platforms/ps3/system-bus.c
+++ b/arch/powerpc/platforms/ps3/system-bus.c
@@ -27,7 +27,7 @@
27#include <asm/udbg.h> 27#include <asm/udbg.h>
28#include <asm/lv1call.h> 28#include <asm/lv1call.h>
29#include <asm/firmware.h> 29#include <asm/firmware.h>
30#include <asm/iommu.h> 30#include <asm/cell-regs.h>
31 31
32#include "platform.h" 32#include "platform.h"
33 33