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-rw-r--r--arch/powerpc/xmon/Makefile9
-rw-r--r--arch/powerpc/xmon/dis-asm.h31
-rw-r--r--arch/powerpc/xmon/ppc-dis.c29
-rw-r--r--arch/powerpc/xmon/ppc-opc.c778
-rw-r--r--arch/powerpc/xmon/ppc.h39
-rw-r--r--arch/powerpc/xmon/spu-dis.c248
-rw-r--r--arch/powerpc/xmon/spu-insns.h410
-rw-r--r--arch/powerpc/xmon/spu-opc.c44
-rw-r--r--arch/powerpc/xmon/spu.h126
-rw-r--r--arch/powerpc/xmon/xmon.c356
10 files changed, 1812 insertions, 258 deletions
diff --git a/arch/powerpc/xmon/Makefile b/arch/powerpc/xmon/Makefile
index 109d874ecfbe..51d97588e762 100644
--- a/arch/powerpc/xmon/Makefile
+++ b/arch/powerpc/xmon/Makefile
@@ -3,5 +3,10 @@
3ifdef CONFIG_PPC64 3ifdef CONFIG_PPC64
4EXTRA_CFLAGS += -mno-minimal-toc 4EXTRA_CFLAGS += -mno-minimal-toc
5endif 5endif
6obj-y += xmon.o ppc-dis.o ppc-opc.o setjmp.o start.o \ 6
7 nonstdio.o 7obj-y += xmon.o setjmp.o start.o nonstdio.o
8
9ifdef CONFIG_XMON_DISASSEMBLY
10obj-y += ppc-dis.o ppc-opc.o
11obj-$(CONFIG_SPU_BASE) += spu-dis.o spu-opc.o
12endif
diff --git a/arch/powerpc/xmon/dis-asm.h b/arch/powerpc/xmon/dis-asm.h
new file mode 100644
index 000000000000..be3533b93f30
--- /dev/null
+++ b/arch/powerpc/xmon/dis-asm.h
@@ -0,0 +1,31 @@
1#ifndef _POWERPC_XMON_DIS_ASM_H
2#define _POWERPC_XMON_DIS_ASM_H
3/*
4 * Copyright (C) 2006 Michael Ellerman, IBM Corporation.
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
10 */
11
12extern void print_address (unsigned long memaddr);
13
14#ifdef CONFIG_XMON_DISASSEMBLY
15extern int print_insn_powerpc(unsigned long insn, unsigned long memaddr);
16extern int print_insn_spu(unsigned long insn, unsigned long memaddr);
17#else
18static inline int print_insn_powerpc(unsigned long insn, unsigned long memaddr)
19{
20 printf("%.8x", insn);
21 return 0;
22}
23
24static inline int print_insn_spu(unsigned long insn, unsigned long memaddr)
25{
26 printf("%.8x", insn);
27 return 0;
28}
29#endif
30
31#endif /* _POWERPC_XMON_DIS_ASM_H */
diff --git a/arch/powerpc/xmon/ppc-dis.c b/arch/powerpc/xmon/ppc-dis.c
index ac0a9d2427e0..89098f320ad5 100644
--- a/arch/powerpc/xmon/ppc-dis.c
+++ b/arch/powerpc/xmon/ppc-dis.c
@@ -1,5 +1,6 @@
1/* ppc-dis.c -- Disassemble PowerPC instructions 1/* ppc-dis.c -- Disassemble PowerPC instructions
2 Copyright 1994 Free Software Foundation, Inc. 2 Copyright 1994, 1995, 2000, 2001, 2002, 2003, 2004, 2005, 2006
3 Free Software Foundation, Inc.
3 Written by Ian Lance Taylor, Cygnus Support 4 Written by Ian Lance Taylor, Cygnus Support
4 5
5This file is part of GDB, GAS, and the GNU binutils. 6This file is part of GDB, GAS, and the GNU binutils.
@@ -16,27 +17,36 @@ the GNU General Public License for more details.
16 17
17You should have received a copy of the GNU General Public License 18You should have received a copy of the GNU General Public License
18along with this file; see the file COPYING. If not, write to the Free 19along with this file; see the file COPYING. If not, write to the Free
19Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ 20Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
20 21
22#include <asm/cputable.h>
21#include "nonstdio.h" 23#include "nonstdio.h"
22#include "ansidecl.h" 24#include "ansidecl.h"
23#include "ppc.h" 25#include "ppc.h"
24 26#include "dis-asm.h"
25extern void print_address (unsigned long memaddr);
26 27
27/* Print a PowerPC or POWER instruction. */ 28/* Print a PowerPC or POWER instruction. */
28 29
29int 30int
30print_insn_powerpc (unsigned long insn, unsigned long memaddr, int dialect) 31print_insn_powerpc (unsigned long insn, unsigned long memaddr)
31{ 32{
32 const struct powerpc_opcode *opcode; 33 const struct powerpc_opcode *opcode;
33 const struct powerpc_opcode *opcode_end; 34 const struct powerpc_opcode *opcode_end;
34 unsigned long op; 35 unsigned long op;
36 int dialect;
35 37
36 if (dialect == 0) 38 dialect = PPC_OPCODE_PPC | PPC_OPCODE_CLASSIC | PPC_OPCODE_COMMON
37 dialect = PPC_OPCODE_PPC | PPC_OPCODE_CLASSIC | PPC_OPCODE_COMMON
38 | PPC_OPCODE_64 | PPC_OPCODE_POWER4 | PPC_OPCODE_ALTIVEC; 39 | PPC_OPCODE_64 | PPC_OPCODE_POWER4 | PPC_OPCODE_ALTIVEC;
39 40
41 if (cpu_has_feature(CPU_FTRS_POWER5))
42 dialect |= PPC_OPCODE_POWER5;
43
44 if (cpu_has_feature(CPU_FTRS_CELL))
45 dialect |= PPC_OPCODE_CELL | PPC_OPCODE_ALTIVEC;
46
47 if (cpu_has_feature(CPU_FTRS_POWER6))
48 dialect |= PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 | PPC_OPCODE_ALTIVEC;
49
40 /* Get the major opcode of the instruction. */ 50 /* Get the major opcode of the instruction. */
41 op = PPC_OP (insn); 51 op = PPC_OP (insn);
42 52
@@ -121,7 +131,8 @@ print_insn_powerpc (unsigned long insn, unsigned long memaddr, int dialect)
121 } 131 }
122 132
123 /* Print the operand as directed by the flags. */ 133 /* Print the operand as directed by the flags. */
124 if ((operand->flags & PPC_OPERAND_GPR) != 0) 134 if ((operand->flags & PPC_OPERAND_GPR) != 0
135 || ((operand->flags & PPC_OPERAND_GPR_0) != 0 && value != 0))
125 printf("r%ld", value); 136 printf("r%ld", value);
126 else if ((operand->flags & PPC_OPERAND_FPR) != 0) 137 else if ((operand->flags & PPC_OPERAND_FPR) != 0)
127 printf("f%ld", value); 138 printf("f%ld", value);
@@ -137,7 +148,7 @@ print_insn_powerpc (unsigned long insn, unsigned long memaddr, int dialect)
137 else 148 else
138 { 149 {
139 if (operand->bits == 3) 150 if (operand->bits == 3)
140 printf("cr%d", value); 151 printf("cr%ld", value);
141 else 152 else
142 { 153 {
143 static const char *cbnames[4] = { "lt", "gt", "eq", "so" }; 154 static const char *cbnames[4] = { "lt", "gt", "eq", "so" };
diff --git a/arch/powerpc/xmon/ppc-opc.c b/arch/powerpc/xmon/ppc-opc.c
index 5ee8fc32f824..5d841f4b3530 100644
--- a/arch/powerpc/xmon/ppc-opc.c
+++ b/arch/powerpc/xmon/ppc-opc.c
@@ -1,6 +1,6 @@
1/* ppc-opc.c -- PowerPC opcode list 1/* ppc-opc.c -- PowerPC opcode list
2 Copyright 1994, 1995, 1996, 1997, 1998, 2000, 2001, 2002, 2003 2 Copyright 1994, 1995, 1996, 1997, 1998, 2000, 2001, 2002, 2003, 2004,
3 Free Software Foundation, Inc. 3 2005 Free Software Foundation, Inc.
4 Written by Ian Lance Taylor, Cygnus Support 4 Written by Ian Lance Taylor, Cygnus Support
5 5
6 This file is part of GDB, GAS, and the GNU binutils. 6 This file is part of GDB, GAS, and the GNU binutils.
@@ -17,8 +17,8 @@
17 17
18 You should have received a copy of the GNU General Public License 18 You should have received a copy of the GNU General Public License
19 along with this file; see the file COPYING. If not, write to the Free 19 along with this file; see the file COPYING. If not, write to the Free
20 Software Foundation, 59 Temple Place - Suite 330, Boston, MA 20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 02111-1307, USA. */ 21 02110-1301, USA. */
22 22
23#include <linux/stddef.h> 23#include <linux/stddef.h>
24#include "nonstdio.h" 24#include "nonstdio.h"
@@ -86,6 +86,8 @@ static unsigned long insert_sh6 (unsigned long, long, int, const char **);
86static long extract_sh6 (unsigned long, int, int *); 86static long extract_sh6 (unsigned long, int, int *);
87static unsigned long insert_spr (unsigned long, long, int, const char **); 87static unsigned long insert_spr (unsigned long, long, int, const char **);
88static long extract_spr (unsigned long, int, int *); 88static long extract_spr (unsigned long, int, int *);
89static unsigned long insert_sprg (unsigned long, long, int, const char **);
90static long extract_sprg (unsigned long, int, int *);
89static unsigned long insert_tbr (unsigned long, long, int, const char **); 91static unsigned long insert_tbr (unsigned long, long, int, const char **);
90static long extract_tbr (unsigned long, int, int *); 92static long extract_tbr (unsigned long, int, int *);
91static unsigned long insert_ev2 (unsigned long, long, int, const char **); 93static unsigned long insert_ev2 (unsigned long, long, int, const char **);
@@ -196,8 +198,11 @@ const struct powerpc_operand powerpc_operands[] =
196#define BOE BO + 1 198#define BOE BO + 1
197 { 5, 21, insert_boe, extract_boe, 0 }, 199 { 5, 21, insert_boe, extract_boe, 0 },
198 200
201#define BH BOE + 1
202 { 2, 11, NULL, NULL, PPC_OPERAND_OPTIONAL },
203
199 /* The BT field in an X or XL form instruction. */ 204 /* The BT field in an X or XL form instruction. */
200#define BT BOE + 1 205#define BT BH + 1
201 { 5, 21, NULL, NULL, PPC_OPERAND_CR }, 206 { 5, 21, NULL, NULL, PPC_OPERAND_CR },
202 207
203 /* The condition register number portion of the BI field in a B form 208 /* The condition register number portion of the BI field in a B form
@@ -301,10 +306,14 @@ const struct powerpc_operand powerpc_operands[] =
301#define L FXM4 + 1 306#define L FXM4 + 1
302 { 1, 21, NULL, NULL, PPC_OPERAND_OPTIONAL }, 307 { 1, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
303 308
304 /* The LEV field in a POWER SC form instruction. */ 309 /* The LEV field in a POWER SVC form instruction. */
305#define LEV L + 1 310#define SVC_LEV L + 1
306 { 7, 5, NULL, NULL, 0 }, 311 { 7, 5, NULL, NULL, 0 },
307 312
313 /* The LEV field in an SC form instruction. */
314#define LEV SVC_LEV + 1
315 { 7, 5, NULL, NULL, PPC_OPERAND_OPTIONAL },
316
308 /* The LI field in an I form instruction. The lower two bits are 317 /* The LI field in an I form instruction. The lower two bits are
309 forced to zero. */ 318 forced to zero. */
310#define LI LEV + 1 319#define LI LEV + 1
@@ -346,7 +355,7 @@ const struct powerpc_operand powerpc_operands[] =
346 355
347 /* The MO field in an mbar instruction. */ 356 /* The MO field in an mbar instruction. */
348#define MO MB6 + 1 357#define MO MB6 + 1
349 { 5, 21, NULL, NULL, 0 }, 358 { 5, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
350 359
351 /* The NB field in an X form instruction. The value 32 is stored as 360 /* The NB field in an X form instruction. The value 32 is stored as
352 0. */ 361 0. */
@@ -364,30 +373,38 @@ const struct powerpc_operand powerpc_operands[] =
364#define RA_MASK (0x1f << 16) 373#define RA_MASK (0x1f << 16)
365 { 5, 16, NULL, NULL, PPC_OPERAND_GPR }, 374 { 5, 16, NULL, NULL, PPC_OPERAND_GPR },
366 375
376 /* As above, but 0 in the RA field means zero, not r0. */
377#define RA0 RA + 1
378 { 5, 16, NULL, NULL, PPC_OPERAND_GPR_0 },
379
367 /* The RA field in the DQ form lq instruction, which has special 380 /* The RA field in the DQ form lq instruction, which has special
368 value restrictions. */ 381 value restrictions. */
369#define RAQ RA + 1 382#define RAQ RA0 + 1
370 { 5, 16, insert_raq, NULL, PPC_OPERAND_GPR }, 383 { 5, 16, insert_raq, NULL, PPC_OPERAND_GPR_0 },
371 384
372 /* The RA field in a D or X form instruction which is an updating 385 /* The RA field in a D or X form instruction which is an updating
373 load, which means that the RA field may not be zero and may not 386 load, which means that the RA field may not be zero and may not
374 equal the RT field. */ 387 equal the RT field. */
375#define RAL RAQ + 1 388#define RAL RAQ + 1
376 { 5, 16, insert_ral, NULL, PPC_OPERAND_GPR }, 389 { 5, 16, insert_ral, NULL, PPC_OPERAND_GPR_0 },
377 390
378 /* The RA field in an lmw instruction, which has special value 391 /* The RA field in an lmw instruction, which has special value
379 restrictions. */ 392 restrictions. */
380#define RAM RAL + 1 393#define RAM RAL + 1
381 { 5, 16, insert_ram, NULL, PPC_OPERAND_GPR }, 394 { 5, 16, insert_ram, NULL, PPC_OPERAND_GPR_0 },
382 395
383 /* The RA field in a D or X form instruction which is an updating 396 /* The RA field in a D or X form instruction which is an updating
384 store or an updating floating point load, which means that the RA 397 store or an updating floating point load, which means that the RA
385 field may not be zero. */ 398 field may not be zero. */
386#define RAS RAM + 1 399#define RAS RAM + 1
387 { 5, 16, insert_ras, NULL, PPC_OPERAND_GPR }, 400 { 5, 16, insert_ras, NULL, PPC_OPERAND_GPR_0 },
401
402 /* The RA field of the tlbwe instruction, which is optional. */
403#define RAOPT RAS + 1
404 { 5, 16, NULL, NULL, PPC_OPERAND_GPR | PPC_OPERAND_OPTIONAL },
388 405
389 /* The RB field in an X, XO, M, or MDS form instruction. */ 406 /* The RB field in an X, XO, M, or MDS form instruction. */
390#define RB RAS + 1 407#define RB RAOPT + 1
391#define RB_MASK (0x1f << 11) 408#define RB_MASK (0x1f << 11)
392 { 5, 11, NULL, NULL, PPC_OPERAND_GPR }, 409 { 5, 11, NULL, NULL, PPC_OPERAND_GPR },
393 410
@@ -408,15 +425,20 @@ const struct powerpc_operand powerpc_operands[] =
408 /* The RS field of the DS form stq instruction, which has special 425 /* The RS field of the DS form stq instruction, which has special
409 value restrictions. */ 426 value restrictions. */
410#define RSQ RS + 1 427#define RSQ RS + 1
411 { 5, 21, insert_rsq, NULL, PPC_OPERAND_GPR }, 428 { 5, 21, insert_rsq, NULL, PPC_OPERAND_GPR_0 },
412 429
413 /* The RT field of the DQ form lq instruction, which has special 430 /* The RT field of the DQ form lq instruction, which has special
414 value restrictions. */ 431 value restrictions. */
415#define RTQ RSQ + 1 432#define RTQ RSQ + 1
416 { 5, 21, insert_rtq, NULL, PPC_OPERAND_GPR }, 433 { 5, 21, insert_rtq, NULL, PPC_OPERAND_GPR_0 },
434
435 /* The RS field of the tlbwe instruction, which is optional. */
436#define RSO RTQ + 1
437#define RTO RSO
438 { 5, 21, NULL, NULL, PPC_OPERAND_GPR | PPC_OPERAND_OPTIONAL },
417 439
418 /* The SH field in an X or M form instruction. */ 440 /* The SH field in an X or M form instruction. */
419#define SH RTQ + 1 441#define SH RSO + 1
420#define SH_MASK (0x1f << 11) 442#define SH_MASK (0x1f << 11)
421 { 5, 11, NULL, NULL, 0 }, 443 { 5, 11, NULL, NULL, 0 },
422 444
@@ -425,8 +447,12 @@ const struct powerpc_operand powerpc_operands[] =
425#define SH6_MASK ((0x1f << 11) | (1 << 1)) 447#define SH6_MASK ((0x1f << 11) | (1 << 1))
426 { 6, 1, insert_sh6, extract_sh6, 0 }, 448 { 6, 1, insert_sh6, extract_sh6, 0 },
427 449
450 /* The SH field of the tlbwe instruction, which is optional. */
451#define SHO SH6 + 1
452 { 5, 11,NULL, NULL, PPC_OPERAND_OPTIONAL },
453
428 /* The SI field in a D form instruction. */ 454 /* The SI field in a D form instruction. */
429#define SI SH6 + 1 455#define SI SHO + 1
430 { 16, 0, NULL, NULL, PPC_OPERAND_SIGNED }, 456 { 16, 0, NULL, NULL, PPC_OPERAND_SIGNED },
431 457
432 /* The SI field in a D form instruction when we accept a wide range 458 /* The SI field in a D form instruction when we accept a wide range
@@ -448,8 +474,7 @@ const struct powerpc_operand powerpc_operands[] =
448 474
449 /* The SPRG register number in an XFX form m[ft]sprg instruction. */ 475 /* The SPRG register number in an XFX form m[ft]sprg instruction. */
450#define SPRG SPRBAT + 1 476#define SPRG SPRBAT + 1
451#define SPRG_MASK (0x3 << 16) 477 { 5, 16, insert_sprg, extract_sprg, 0 },
452 { 2, 16, NULL, NULL, 0 },
453 478
454 /* The SR field in an X form instruction. */ 479 /* The SR field in an X form instruction. */
455#define SR SPRG + 1 480#define SR SPRG + 1
@@ -536,10 +561,45 @@ const struct powerpc_operand powerpc_operands[] =
536#define WS_MASK (0x7 << 11) 561#define WS_MASK (0x7 << 11)
537 { 3, 11, NULL, NULL, 0 }, 562 { 3, 11, NULL, NULL, 0 },
538 563
539 /* The L field in an mtmsrd instruction */ 564 /* The L field in an mtmsrd or A form instruction. */
540#define MTMSRD_L WS + 1 565#define MTMSRD_L WS + 1
566#define A_L MTMSRD_L
541 { 1, 16, NULL, NULL, PPC_OPERAND_OPTIONAL }, 567 { 1, 16, NULL, NULL, PPC_OPERAND_OPTIONAL },
542 568
569 /* The DCM field in a Z form instruction. */
570#define DCM MTMSRD_L + 1
571 { 6, 16, NULL, NULL, 0 },
572
573 /* Likewise, the DGM field in a Z form instruction. */
574#define DGM DCM + 1
575 { 6, 16, NULL, NULL, 0 },
576
577#define TE DGM + 1
578 { 5, 11, NULL, NULL, 0 },
579
580#define RMC TE + 1
581 { 2, 21, NULL, NULL, 0 },
582
583#define R RMC + 1
584 { 1, 15, NULL, NULL, 0 },
585
586#define SP R + 1
587 { 2, 11, NULL, NULL, 0 },
588
589#define S SP + 1
590 { 1, 11, NULL, NULL, 0 },
591
592 /* SH field starting at bit position 16. */
593#define SH16 S + 1
594 { 6, 10, NULL, NULL, 0 },
595
596 /* The L field in an X form with the RT field fixed instruction. */
597#define XRT_L SH16 + 1
598 { 2, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
599
600 /* The EH field in larx instruction. */
601#define EH XRT_L + 1
602 { 1, 0, NULL, NULL, PPC_OPERAND_OPTIONAL },
543}; 603};
544 604
545/* The functions used to insert and extract complicated operands. */ 605/* The functions used to insert and extract complicated operands. */
@@ -550,7 +610,6 @@ const struct powerpc_operand powerpc_operands[] =
550 and the extraction function just checks that the fields are the 610 and the extraction function just checks that the fields are the
551 same. */ 611 same. */
552 612
553/*ARGSUSED*/
554static unsigned long 613static unsigned long
555insert_bat (unsigned long insn, 614insert_bat (unsigned long insn,
556 long value ATTRIBUTE_UNUSED, 615 long value ATTRIBUTE_UNUSED,
@@ -576,7 +635,6 @@ extract_bat (unsigned long insn,
576 and the extraction function just checks that the fields are the 635 and the extraction function just checks that the fields are the
577 same. */ 636 same. */
578 637
579/*ARGSUSED*/
580static unsigned long 638static unsigned long
581insert_bba (unsigned long insn, 639insert_bba (unsigned long insn,
582 long value ATTRIBUTE_UNUSED, 640 long value ATTRIBUTE_UNUSED,
@@ -599,7 +657,6 @@ extract_bba (unsigned long insn,
599/* The BD field in a B form instruction. The lower two bits are 657/* The BD field in a B form instruction. The lower two bits are
600 forced to zero. */ 658 forced to zero. */
601 659
602/*ARGSUSED*/
603static unsigned long 660static unsigned long
604insert_bd (unsigned long insn, 661insert_bd (unsigned long insn,
605 long value, 662 long value,
@@ -609,7 +666,6 @@ insert_bd (unsigned long insn,
609 return insn | (value & 0xfffc); 666 return insn | (value & 0xfffc);
610} 667}
611 668
612/*ARGSUSED*/
613static long 669static long
614extract_bd (unsigned long insn, 670extract_bd (unsigned long insn,
615 int dialect ATTRIBUTE_UNUSED, 671 int dialect ATTRIBUTE_UNUSED,
@@ -631,7 +687,6 @@ extract_bd (unsigned long insn,
631 in BO field, the "a" bit is 00010 for branch on CR(BI) and 01000 687 in BO field, the "a" bit is 00010 for branch on CR(BI) and 01000
632 for branch on CTR. We only handle the taken/not-taken hint here. */ 688 for branch on CTR. We only handle the taken/not-taken hint here. */
633 689
634/*ARGSUSED*/
635static unsigned long 690static unsigned long
636insert_bdm (unsigned long insn, 691insert_bdm (unsigned long insn,
637 long value, 692 long value,
@@ -677,7 +732,6 @@ extract_bdm (unsigned long insn,
677 This is like BDM, above, except that the branch is expected to be 732 This is like BDM, above, except that the branch is expected to be
678 taken. */ 733 taken. */
679 734
680/*ARGSUSED*/
681static unsigned long 735static unsigned long
682insert_bdp (unsigned long insn, 736insert_bdp (unsigned long insn,
683 long value, 737 long value,
@@ -831,7 +885,6 @@ extract_boe (unsigned long insn,
831/* The DQ field in a DQ form instruction. This is like D, but the 885/* The DQ field in a DQ form instruction. This is like D, but the
832 lower four bits are forced to zero. */ 886 lower four bits are forced to zero. */
833 887
834/*ARGSUSED*/
835static unsigned long 888static unsigned long
836insert_dq (unsigned long insn, 889insert_dq (unsigned long insn,
837 long value, 890 long value,
@@ -843,7 +896,6 @@ insert_dq (unsigned long insn,
843 return insn | (value & 0xfff0); 896 return insn | (value & 0xfff0);
844} 897}
845 898
846/*ARGSUSED*/
847static long 899static long
848extract_dq (unsigned long insn, 900extract_dq (unsigned long insn,
849 int dialect ATTRIBUTE_UNUSED, 901 int dialect ATTRIBUTE_UNUSED,
@@ -918,7 +970,6 @@ extract_ev8 (unsigned long insn,
918/* The DS field in a DS form instruction. This is like D, but the 970/* The DS field in a DS form instruction. This is like D, but the
919 lower two bits are forced to zero. */ 971 lower two bits are forced to zero. */
920 972
921/*ARGSUSED*/
922static unsigned long 973static unsigned long
923insert_ds (unsigned long insn, 974insert_ds (unsigned long insn,
924 long value, 975 long value,
@@ -930,7 +981,6 @@ insert_ds (unsigned long insn,
930 return insn | (value & 0xfffc); 981 return insn | (value & 0xfffc);
931} 982}
932 983
933/*ARGSUSED*/
934static long 984static long
935extract_ds (unsigned long insn, 985extract_ds (unsigned long insn,
936 int dialect ATTRIBUTE_UNUSED, 986 int dialect ATTRIBUTE_UNUSED,
@@ -941,7 +991,6 @@ extract_ds (unsigned long insn,
941 991
942/* The DE field in a DE form instruction. */ 992/* The DE field in a DE form instruction. */
943 993
944/*ARGSUSED*/
945static unsigned long 994static unsigned long
946insert_de (unsigned long insn, 995insert_de (unsigned long insn,
947 long value, 996 long value,
@@ -953,7 +1002,6 @@ insert_de (unsigned long insn,
953 return insn | ((value << 4) & 0xfff0); 1002 return insn | ((value << 4) & 0xfff0);
954} 1003}
955 1004
956/*ARGSUSED*/
957static long 1005static long
958extract_de (unsigned long insn, 1006extract_de (unsigned long insn,
959 int dialect ATTRIBUTE_UNUSED, 1007 int dialect ATTRIBUTE_UNUSED,
@@ -964,7 +1012,6 @@ extract_de (unsigned long insn,
964 1012
965/* The DES field in a DES form instruction. */ 1013/* The DES field in a DES form instruction. */
966 1014
967/*ARGSUSED*/
968static unsigned long 1015static unsigned long
969insert_des (unsigned long insn, 1016insert_des (unsigned long insn,
970 long value, 1017 long value,
@@ -978,7 +1025,6 @@ insert_des (unsigned long insn,
978 return insn | ((value << 2) & 0xfff0); 1025 return insn | ((value << 2) & 0xfff0);
979} 1026}
980 1027
981/*ARGSUSED*/
982static long 1028static long
983extract_des (unsigned long insn, 1029extract_des (unsigned long insn,
984 int dialect ATTRIBUTE_UNUSED, 1030 int dialect ATTRIBUTE_UNUSED,
@@ -995,17 +1041,33 @@ insert_fxm (unsigned long insn,
995 int dialect, 1041 int dialect,
996 const char **errmsg) 1042 const char **errmsg)
997{ 1043{
1044 /* If we're handling the mfocrf and mtocrf insns ensure that exactly
1045 one bit of the mask field is set. */
1046 if ((insn & (1 << 20)) != 0)
1047 {
1048 if (value == 0 || (value & -value) != value)
1049 {
1050 *errmsg = _("invalid mask field");
1051 value = 0;
1052 }
1053 }
1054
998 /* If the optional field on mfcr is missing that means we want to use 1055 /* If the optional field on mfcr is missing that means we want to use
999 the old form of the instruction that moves the whole cr. In that 1056 the old form of the instruction that moves the whole cr. In that
1000 case we'll have VALUE zero. There doesn't seem to be a way to 1057 case we'll have VALUE zero. There doesn't seem to be a way to
1001 distinguish this from the case where someone writes mfcr %r3,0. */ 1058 distinguish this from the case where someone writes mfcr %r3,0. */
1002 if (value == 0) 1059 else if (value == 0)
1003 ; 1060 ;
1004 1061
1005 /* If only one bit of the FXM field is set, we can use the new form 1062 /* If only one bit of the FXM field is set, we can use the new form
1006 of the instruction, which is faster. Unlike the Power4 branch hint 1063 of the instruction, which is faster. Unlike the Power4 branch hint
1007 encoding, this is not backward compatible. */ 1064 encoding, this is not backward compatible. Do not generate the
1008 else if ((dialect & PPC_OPCODE_POWER4) != 0 && (value & -value) == value) 1065 new form unless -mpower4 has been given, or -many and the two
1066 operand form of mfcr was used. */
1067 else if ((value & -value) == value
1068 && ((dialect & PPC_OPCODE_POWER4) != 0
1069 || ((dialect & PPC_OPCODE_ANY) != 0
1070 && (insn & (0x3ff << 1)) == 19 << 1)))
1009 insn |= 1 << 20; 1071 insn |= 1 << 20;
1010 1072
1011 /* Any other value on mfcr is an error. */ 1073 /* Any other value on mfcr is an error. */
@@ -1020,7 +1082,7 @@ insert_fxm (unsigned long insn,
1020 1082
1021static long 1083static long
1022extract_fxm (unsigned long insn, 1084extract_fxm (unsigned long insn,
1023 int dialect, 1085 int dialect ATTRIBUTE_UNUSED,
1024 int *invalid) 1086 int *invalid)
1025{ 1087{
1026 long mask = (insn >> 12) & 0xff; 1088 long mask = (insn >> 12) & 0xff;
@@ -1028,14 +1090,9 @@ extract_fxm (unsigned long insn,
1028 /* Is this a Power4 insn? */ 1090 /* Is this a Power4 insn? */
1029 if ((insn & (1 << 20)) != 0) 1091 if ((insn & (1 << 20)) != 0)
1030 { 1092 {
1031 if ((dialect & PPC_OPCODE_POWER4) == 0) 1093 /* Exactly one bit of MASK should be set. */
1094 if (mask == 0 || (mask & -mask) != mask)
1032 *invalid = 1; 1095 *invalid = 1;
1033 else
1034 {
1035 /* Exactly one bit of MASK should be set. */
1036 if (mask == 0 || (mask & -mask) != mask)
1037 *invalid = 1;
1038 }
1039 } 1096 }
1040 1097
1041 /* Check that non-power4 form of mfcr has a zero MASK. */ 1098 /* Check that non-power4 form of mfcr has a zero MASK. */
@@ -1051,7 +1108,6 @@ extract_fxm (unsigned long insn,
1051/* The LI field in an I form instruction. The lower two bits are 1108/* The LI field in an I form instruction. The lower two bits are
1052 forced to zero. */ 1109 forced to zero. */
1053 1110
1054/*ARGSUSED*/
1055static unsigned long 1111static unsigned long
1056insert_li (unsigned long insn, 1112insert_li (unsigned long insn,
1057 long value, 1113 long value,
@@ -1063,7 +1119,6 @@ insert_li (unsigned long insn,
1063 return insn | (value & 0x3fffffc); 1119 return insn | (value & 0x3fffffc);
1064} 1120}
1065 1121
1066/*ARGSUSED*/
1067static long 1122static long
1068extract_li (unsigned long insn, 1123extract_li (unsigned long insn,
1069 int dialect ATTRIBUTE_UNUSED, 1124 int dialect ATTRIBUTE_UNUSED,
@@ -1163,7 +1218,6 @@ extract_mbe (unsigned long insn,
1163/* The MB or ME field in an MD or MDS form instruction. The high bit 1218/* The MB or ME field in an MD or MDS form instruction. The high bit
1164 is wrapped to the low end. */ 1219 is wrapped to the low end. */
1165 1220
1166/*ARGSUSED*/
1167static unsigned long 1221static unsigned long
1168insert_mb6 (unsigned long insn, 1222insert_mb6 (unsigned long insn,
1169 long value, 1223 long value,
@@ -1173,7 +1227,6 @@ insert_mb6 (unsigned long insn,
1173 return insn | ((value & 0x1f) << 6) | (value & 0x20); 1227 return insn | ((value & 0x1f) << 6) | (value & 0x20);
1174} 1228}
1175 1229
1176/*ARGSUSED*/
1177static long 1230static long
1178extract_mb6 (unsigned long insn, 1231extract_mb6 (unsigned long insn,
1179 int dialect ATTRIBUTE_UNUSED, 1232 int dialect ATTRIBUTE_UNUSED,
@@ -1198,7 +1251,6 @@ insert_nb (unsigned long insn,
1198 return insn | ((value & 0x1f) << 11); 1251 return insn | ((value & 0x1f) << 11);
1199} 1252}
1200 1253
1201/*ARGSUSED*/
1202static long 1254static long
1203extract_nb (unsigned long insn, 1255extract_nb (unsigned long insn,
1204 int dialect ATTRIBUTE_UNUSED, 1256 int dialect ATTRIBUTE_UNUSED,
@@ -1217,7 +1269,6 @@ extract_nb (unsigned long insn,
1217 invalid, since we never want to recognize an instruction which uses 1269 invalid, since we never want to recognize an instruction which uses
1218 a field of this type. */ 1270 a field of this type. */
1219 1271
1220/*ARGSUSED*/
1221static unsigned long 1272static unsigned long
1222insert_nsi (unsigned long insn, 1273insert_nsi (unsigned long insn,
1223 long value, 1274 long value,
@@ -1269,7 +1320,6 @@ insert_ram (unsigned long insn,
1269/* The RA field in the DQ form lq instruction, which has special 1320/* The RA field in the DQ form lq instruction, which has special
1270 value restrictions. */ 1321 value restrictions. */
1271 1322
1272/*ARGSUSED*/
1273static unsigned long 1323static unsigned long
1274insert_raq (unsigned long insn, 1324insert_raq (unsigned long insn,
1275 long value, 1325 long value,
@@ -1304,7 +1354,6 @@ insert_ras (unsigned long insn,
1304 function just copies the BT field into the BA field, and the 1354 function just copies the BT field into the BA field, and the
1305 extraction function just checks that the fields are the same. */ 1355 extraction function just checks that the fields are the same. */
1306 1356
1307/*ARGSUSED*/
1308static unsigned long 1357static unsigned long
1309insert_rbs (unsigned long insn, 1358insert_rbs (unsigned long insn,
1310 long value ATTRIBUTE_UNUSED, 1359 long value ATTRIBUTE_UNUSED,
@@ -1327,7 +1376,6 @@ extract_rbs (unsigned long insn,
1327/* The RT field of the DQ form lq instruction, which has special 1376/* The RT field of the DQ form lq instruction, which has special
1328 value restrictions. */ 1377 value restrictions. */
1329 1378
1330/*ARGSUSED*/
1331static unsigned long 1379static unsigned long
1332insert_rtq (unsigned long insn, 1380insert_rtq (unsigned long insn,
1333 long value, 1381 long value,
@@ -1342,7 +1390,6 @@ insert_rtq (unsigned long insn,
1342/* The RS field of the DS form stq instruction, which has special 1390/* The RS field of the DS form stq instruction, which has special
1343 value restrictions. */ 1391 value restrictions. */
1344 1392
1345/*ARGSUSED*/
1346static unsigned long 1393static unsigned long
1347insert_rsq (unsigned long insn, 1394insert_rsq (unsigned long insn,
1348 long value ATTRIBUTE_UNUSED, 1395 long value ATTRIBUTE_UNUSED,
@@ -1356,7 +1403,6 @@ insert_rsq (unsigned long insn,
1356 1403
1357/* The SH field in an MD form instruction. This is split. */ 1404/* The SH field in an MD form instruction. This is split. */
1358 1405
1359/*ARGSUSED*/
1360static unsigned long 1406static unsigned long
1361insert_sh6 (unsigned long insn, 1407insert_sh6 (unsigned long insn,
1362 long value, 1408 long value,
@@ -1366,7 +1412,6 @@ insert_sh6 (unsigned long insn,
1366 return insn | ((value & 0x1f) << 11) | ((value & 0x20) >> 4); 1412 return insn | ((value & 0x1f) << 11) | ((value & 0x20) >> 4);
1367} 1413}
1368 1414
1369/*ARGSUSED*/
1370static long 1415static long
1371extract_sh6 (unsigned long insn, 1416extract_sh6 (unsigned long insn,
1372 int dialect ATTRIBUTE_UNUSED, 1417 int dialect ATTRIBUTE_UNUSED,
@@ -1395,6 +1440,47 @@ extract_spr (unsigned long insn,
1395 return ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0); 1440 return ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0);
1396} 1441}
1397 1442
1443/* Some dialects have 8 SPRG registers instead of the standard 4. */
1444
1445static unsigned long
1446insert_sprg (unsigned long insn,
1447 long value,
1448 int dialect,
1449 const char **errmsg)
1450{
1451 /* This check uses PPC_OPCODE_403 because PPC405 is later defined
1452 as a synonym. If ever a 405 specific dialect is added this
1453 check should use that instead. */
1454 if (value > 7
1455 || (value > 3
1456 && (dialect & (PPC_OPCODE_BOOKE | PPC_OPCODE_403)) == 0))
1457 *errmsg = _("invalid sprg number");
1458
1459 /* If this is mfsprg4..7 then use spr 260..263 which can be read in
1460 user mode. Anything else must use spr 272..279. */
1461 if (value <= 3 || (insn & 0x100) != 0)
1462 value |= 0x10;
1463
1464 return insn | ((value & 0x17) << 16);
1465}
1466
1467static long
1468extract_sprg (unsigned long insn,
1469 int dialect,
1470 int *invalid)
1471{
1472 unsigned long val = (insn >> 16) & 0x1f;
1473
1474 /* mfsprg can use 260..263 and 272..279. mtsprg only uses spr 272..279
1475 If not BOOKE or 405, then both use only 272..275. */
1476 if (val <= 3
1477 || (val < 0x10 && (insn & 0x100) != 0)
1478 || (val - 0x10 > 3
1479 && (dialect & (PPC_OPCODE_BOOKE | PPC_OPCODE_403)) == 0))
1480 *invalid = 1;
1481 return val & 7;
1482}
1483
1398/* The TBR field in an XFX instruction. This is just like SPR, but it 1484/* The TBR field in an XFX instruction. This is just like SPR, but it
1399 is optional. When TBR is omitted, it must be inserted as 268 (the 1485 is optional. When TBR is omitted, it must be inserted as 268 (the
1400 magic number of the TB register). These functions treat 0 1486 magic number of the TB register). These functions treat 0
@@ -1460,6 +1546,9 @@ extract_tbr (unsigned long insn,
1460/* An A_MASK with the FRA and FRC fields fixed. */ 1546/* An A_MASK with the FRA and FRC fields fixed. */
1461#define AFRAFRC_MASK (A_MASK | FRA_MASK | FRC_MASK) 1547#define AFRAFRC_MASK (A_MASK | FRA_MASK | FRC_MASK)
1462 1548
1549/* An AFRAFRC_MASK, but with L bit clear. */
1550#define AFRALFRC_MASK (AFRAFRC_MASK & ~((unsigned long) 1 << 16))
1551
1463/* A B form instruction. */ 1552/* A B form instruction. */
1464#define B(op, aa, lk) (OP (op) | ((((unsigned long)(aa)) & 1) << 1) | ((lk) & 1)) 1553#define B(op, aa, lk) (OP (op) | ((((unsigned long)(aa)) & 1) << 1) | ((lk) & 1))
1465#define B_MASK B (0x3f, 1, 1) 1554#define B_MASK B (0x3f, 1, 1)
@@ -1494,11 +1583,11 @@ extract_tbr (unsigned long insn,
1494 1583
1495/* An Context form instruction. */ 1584/* An Context form instruction. */
1496#define CTX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7)) 1585#define CTX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7))
1497#define CTX_MASK CTX(0x3f, 0x7) 1586#define CTX_MASK CTX(0x3f, 0x7)
1498 1587
1499/* An User Context form instruction. */ 1588/* An User Context form instruction. */
1500#define UCTX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f)) 1589#define UCTX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f))
1501#define UCTX_MASK UCTX(0x3f, 0x1f) 1590#define UCTX_MASK UCTX(0x3f, 0x1f)
1502 1591
1503/* The main opcode mask with the RA field clear. */ 1592/* The main opcode mask with the RA field clear. */
1504#define DRA_MASK (OP_MASK | RA_MASK) 1593#define DRA_MASK (OP_MASK | RA_MASK)
@@ -1570,12 +1659,21 @@ extract_tbr (unsigned long insn,
1570/* An X form instruction. */ 1659/* An X form instruction. */
1571#define X(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1)) 1660#define X(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1))
1572 1661
1662/* A Z form instruction. */
1663#define Z(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 1))
1664
1573/* An X form instruction with the RC bit specified. */ 1665/* An X form instruction with the RC bit specified. */
1574#define XRC(op, xop, rc) (X ((op), (xop)) | ((rc) & 1)) 1666#define XRC(op, xop, rc) (X ((op), (xop)) | ((rc) & 1))
1575 1667
1668/* A Z form instruction with the RC bit specified. */
1669#define ZRC(op, xop, rc) (Z ((op), (xop)) | ((rc) & 1))
1670
1576/* The mask for an X form instruction. */ 1671/* The mask for an X form instruction. */
1577#define X_MASK XRC (0x3f, 0x3ff, 1) 1672#define X_MASK XRC (0x3f, 0x3ff, 1)
1578 1673
1674/* The mask for a Z form instruction. */
1675#define Z_MASK ZRC (0x3f, 0x1ff, 1)
1676
1579/* An X_MASK with the RA field fixed. */ 1677/* An X_MASK with the RA field fixed. */
1580#define XRA_MASK (X_MASK | RA_MASK) 1678#define XRA_MASK (X_MASK | RA_MASK)
1581 1679
@@ -1585,6 +1683,9 @@ extract_tbr (unsigned long insn,
1585/* An X_MASK with the RT field fixed. */ 1683/* An X_MASK with the RT field fixed. */
1586#define XRT_MASK (X_MASK | RT_MASK) 1684#define XRT_MASK (X_MASK | RT_MASK)
1587 1685
1686/* An XRT_MASK mask with the L bits clear. */
1687#define XLRT_MASK (XRT_MASK & ~((unsigned long) 0x3 << 21))
1688
1588/* An X_MASK with the RA and RB fields fixed. */ 1689/* An X_MASK with the RA and RB fields fixed. */
1589#define XRARB_MASK (X_MASK | RA_MASK | RB_MASK) 1690#define XRARB_MASK (X_MASK | RA_MASK | RB_MASK)
1590 1691
@@ -1597,8 +1698,8 @@ extract_tbr (unsigned long insn,
1597/* An XRTRA_MASK, but with L bit clear. */ 1698/* An XRTRA_MASK, but with L bit clear. */
1598#define XRTLRA_MASK (XRTRA_MASK & ~((unsigned long) 1 << 21)) 1699#define XRTLRA_MASK (XRTRA_MASK & ~((unsigned long) 1 << 21))
1599 1700
1600/* An X form comparison instruction. */ 1701/* An X form instruction with the L bit specified. */
1601#define XCMPL(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 1) << 21)) 1702#define XOPL(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 1) << 21))
1602 1703
1603/* The mask for an X form comparison instruction. */ 1704/* The mask for an X form comparison instruction. */
1604#define XCMP_MASK (X_MASK | (((unsigned long)1) << 22)) 1705#define XCMP_MASK (X_MASK | (((unsigned long)1) << 22))
@@ -1621,6 +1722,9 @@ extract_tbr (unsigned long insn,
1621/* An X form sync instruction with everything filled in except the LS field. */ 1722/* An X form sync instruction with everything filled in except the LS field. */
1622#define XSYNC_MASK (0xff9fffff) 1723#define XSYNC_MASK (0xff9fffff)
1623 1724
1725/* An X_MASK, but with the EH bit clear. */
1726#define XEH_MASK (X_MASK & ~((unsigned long )1))
1727
1624/* An X form AltiVec dss instruction. */ 1728/* An X form AltiVec dss instruction. */
1625#define XDSS(op, xop, a) (X ((op), (xop)) | ((((unsigned long)(a)) & 1) << 25)) 1729#define XDSS(op, xop, a) (X ((op), (xop)) | ((((unsigned long)(a)) & 1) << 25))
1626#define XDSS_MASK XDSS(0x3f, 0x3ff, 1) 1730#define XDSS_MASK XDSS(0x3f, 0x3ff, 1)
@@ -1663,6 +1767,9 @@ extract_tbr (unsigned long insn,
1663#define XLYBB_MASK (XLYLK_MASK | BB_MASK) 1767#define XLYBB_MASK (XLYLK_MASK | BB_MASK)
1664#define XLBOCBBB_MASK (XLOCB_MASK | BB_MASK) 1768#define XLBOCBBB_MASK (XLOCB_MASK | BB_MASK)
1665 1769
1770/* A mask for branch instructions using the BH field. */
1771#define XLBH_MASK (XL_MASK | (0x1c << 11))
1772
1666/* An XL_MASK with the BO and BB fields fixed. */ 1773/* An XL_MASK with the BO and BB fields fixed. */
1667#define XLBOBB_MASK (XL_MASK | BO_MASK | BB_MASK) 1774#define XLBOBB_MASK (XL_MASK | BO_MASK | BB_MASK)
1668 1775
@@ -1682,11 +1789,12 @@ extract_tbr (unsigned long insn,
1682#define XS_MASK XS (0x3f, 0x1ff, 1) 1789#define XS_MASK XS (0x3f, 0x1ff, 1)
1683 1790
1684/* A mask for the FXM version of an XFX form instruction. */ 1791/* A mask for the FXM version of an XFX form instruction. */
1685#define XFXFXM_MASK (X_MASK | (1 << 11)) 1792#define XFXFXM_MASK (X_MASK | (1 << 11) | (1 << 20))
1686 1793
1687/* An XFX form instruction with the FXM field filled in. */ 1794/* An XFX form instruction with the FXM field filled in. */
1688#define XFXM(op, xop, fxm) \ 1795#define XFXM(op, xop, fxm, p4) \
1689 (X ((op), (xop)) | ((((unsigned long)(fxm)) & 0xff) << 12)) 1796 (X ((op), (xop)) | ((((unsigned long)(fxm)) & 0xff) << 12) \
1797 | ((unsigned long)(p4) << 20))
1690 1798
1691/* An XFX form instruction with the SPR field filled in. */ 1799/* An XFX form instruction with the SPR field filled in. */
1692#define XSPR(op, xop, spr) \ 1800#define XSPR(op, xop, spr) \
@@ -1699,7 +1807,7 @@ extract_tbr (unsigned long insn,
1699 1807
1700/* An XFX form instruction with the SPR field filled in except for the 1808/* An XFX form instruction with the SPR field filled in except for the
1701 SPRG field. */ 1809 SPRG field. */
1702#define XSPRG_MASK (XSPR_MASK &~ SPRG_MASK) 1810#define XSPRG_MASK (XSPR_MASK & ~(0x17 << 16))
1703 1811
1704/* An X form instruction with everything filled in except the E field. */ 1812/* An X form instruction with everything filled in except the E field. */
1705#define XE_MASK (0xffff7fff) 1813#define XE_MASK (0xffff7fff)
@@ -1769,6 +1877,9 @@ extract_tbr (unsigned long insn,
1769#define PPCCOM PPC_OPCODE_PPC | PPC_OPCODE_COMMON 1877#define PPCCOM PPC_OPCODE_PPC | PPC_OPCODE_COMMON
1770#define NOPOWER4 PPC_OPCODE_NOPOWER4 | PPCCOM 1878#define NOPOWER4 PPC_OPCODE_NOPOWER4 | PPCCOM
1771#define POWER4 PPC_OPCODE_POWER4 1879#define POWER4 PPC_OPCODE_POWER4
1880#define POWER5 PPC_OPCODE_POWER5
1881#define POWER6 PPC_OPCODE_POWER6
1882#define CELL PPC_OPCODE_CELL
1772#define PPC32 PPC_OPCODE_32 | PPC_OPCODE_PPC 1883#define PPC32 PPC_OPCODE_32 | PPC_OPCODE_PPC
1773#define PPC64 PPC_OPCODE_64 | PPC_OPCODE_PPC 1884#define PPC64 PPC_OPCODE_64 | PPC_OPCODE_PPC
1774#define PPC403 PPC_OPCODE_403 1885#define PPC403 PPC_OPCODE_403
@@ -1776,7 +1887,7 @@ extract_tbr (unsigned long insn,
1776#define PPC440 PPC_OPCODE_440 1887#define PPC440 PPC_OPCODE_440
1777#define PPC750 PPC 1888#define PPC750 PPC
1778#define PPC860 PPC 1889#define PPC860 PPC
1779#define PPCVEC PPC_OPCODE_ALTIVEC | PPC_OPCODE_PPC 1890#define PPCVEC PPC_OPCODE_ALTIVEC
1780#define POWER PPC_OPCODE_POWER 1891#define POWER PPC_OPCODE_POWER
1781#define POWER2 PPC_OPCODE_POWER | PPC_OPCODE_POWER2 1892#define POWER2 PPC_OPCODE_POWER | PPC_OPCODE_POWER2
1782#define PPCPWR2 PPC_OPCODE_PPC | PPC_OPCODE_POWER | PPC_OPCODE_POWER2 1893#define PPCPWR2 PPC_OPCODE_PPC | PPC_OPCODE_POWER | PPC_OPCODE_POWER2
@@ -1790,6 +1901,7 @@ extract_tbr (unsigned long insn,
1790#define BOOKE PPC_OPCODE_BOOKE 1901#define BOOKE PPC_OPCODE_BOOKE
1791#define BOOKE64 PPC_OPCODE_BOOKE64 1902#define BOOKE64 PPC_OPCODE_BOOKE64
1792#define CLASSIC PPC_OPCODE_CLASSIC 1903#define CLASSIC PPC_OPCODE_CLASSIC
1904#define PPCE300 PPC_OPCODE_E300
1793#define PPCSPE PPC_OPCODE_SPE 1905#define PPCSPE PPC_OPCODE_SPE
1794#define PPCISEL PPC_OPCODE_ISEL 1906#define PPCISEL PPC_OPCODE_ISEL
1795#define PPCEFS PPC_OPCODE_EFS 1907#define PPCEFS PPC_OPCODE_EFS
@@ -1952,6 +2064,41 @@ const struct powerpc_opcode powerpc_opcodes[] = {
1952{ "nmaclhwso.", XO(4,494,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 2064{ "nmaclhwso.", XO(4,494,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1953{ "mfvscr", VX(4, 1540), VX_MASK, PPCVEC, { VD } }, 2065{ "mfvscr", VX(4, 1540), VX_MASK, PPCVEC, { VD } },
1954{ "mtvscr", VX(4, 1604), VX_MASK, PPCVEC, { VB } }, 2066{ "mtvscr", VX(4, 1604), VX_MASK, PPCVEC, { VB } },
2067
2068 /* Double-precision opcodes. */
2069 /* Some of these conflict with AltiVec, so move them before, since
2070 PPCVEC includes the PPC_OPCODE_PPC set. */
2071{ "efscfd", VX(4, 719), VX_MASK, PPCEFS, { RS, RB } },
2072{ "efdabs", VX(4, 740), VX_MASK, PPCEFS, { RS, RA } },
2073{ "efdnabs", VX(4, 741), VX_MASK, PPCEFS, { RS, RA } },
2074{ "efdneg", VX(4, 742), VX_MASK, PPCEFS, { RS, RA } },
2075{ "efdadd", VX(4, 736), VX_MASK, PPCEFS, { RS, RA, RB } },
2076{ "efdsub", VX(4, 737), VX_MASK, PPCEFS, { RS, RA, RB } },
2077{ "efdmul", VX(4, 744), VX_MASK, PPCEFS, { RS, RA, RB } },
2078{ "efddiv", VX(4, 745), VX_MASK, PPCEFS, { RS, RA, RB } },
2079{ "efdcmpgt", VX(4, 748), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2080{ "efdcmplt", VX(4, 749), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2081{ "efdcmpeq", VX(4, 750), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2082{ "efdtstgt", VX(4, 764), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2083{ "efdtstlt", VX(4, 765), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2084{ "efdtsteq", VX(4, 766), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2085{ "efdcfsi", VX(4, 753), VX_MASK, PPCEFS, { RS, RB } },
2086{ "efdcfsid", VX(4, 739), VX_MASK, PPCEFS, { RS, RB } },
2087{ "efdcfui", VX(4, 752), VX_MASK, PPCEFS, { RS, RB } },
2088{ "efdcfuid", VX(4, 738), VX_MASK, PPCEFS, { RS, RB } },
2089{ "efdcfsf", VX(4, 755), VX_MASK, PPCEFS, { RS, RB } },
2090{ "efdcfuf", VX(4, 754), VX_MASK, PPCEFS, { RS, RB } },
2091{ "efdctsi", VX(4, 757), VX_MASK, PPCEFS, { RS, RB } },
2092{ "efdctsidz",VX(4, 747), VX_MASK, PPCEFS, { RS, RB } },
2093{ "efdctsiz", VX(4, 762), VX_MASK, PPCEFS, { RS, RB } },
2094{ "efdctui", VX(4, 756), VX_MASK, PPCEFS, { RS, RB } },
2095{ "efdctuidz",VX(4, 746), VX_MASK, PPCEFS, { RS, RB } },
2096{ "efdctuiz", VX(4, 760), VX_MASK, PPCEFS, { RS, RB } },
2097{ "efdctsf", VX(4, 759), VX_MASK, PPCEFS, { RS, RB } },
2098{ "efdctuf", VX(4, 758), VX_MASK, PPCEFS, { RS, RB } },
2099{ "efdcfs", VX(4, 751), VX_MASK, PPCEFS, { RS, RB } },
2100 /* End of double-precision opcodes. */
2101
1955{ "vaddcuw", VX(4, 384), VX_MASK, PPCVEC, { VD, VA, VB } }, 2102{ "vaddcuw", VX(4, 384), VX_MASK, PPCVEC, { VD, VA, VB } },
1956{ "vaddfp", VX(4, 10), VX_MASK, PPCVEC, { VD, VA, VB } }, 2103{ "vaddfp", VX(4, 10), VX_MASK, PPCVEC, { VD, VA, VB } },
1957{ "vaddsbs", VX(4, 768), VX_MASK, PPCVEC, { VD, VA, VB } }, 2104{ "vaddsbs", VX(4, 768), VX_MASK, PPCVEC, { VD, VA, VB } },
@@ -2389,16 +2536,16 @@ const struct powerpc_opcode powerpc_opcodes[] = {
2389 2536
2390{ "li", OP(14), DRA_MASK, PPCCOM, { RT, SI } }, 2537{ "li", OP(14), DRA_MASK, PPCCOM, { RT, SI } },
2391{ "lil", OP(14), DRA_MASK, PWRCOM, { RT, SI } }, 2538{ "lil", OP(14), DRA_MASK, PWRCOM, { RT, SI } },
2392{ "addi", OP(14), OP_MASK, PPCCOM, { RT, RA, SI } }, 2539{ "addi", OP(14), OP_MASK, PPCCOM, { RT, RA0, SI } },
2393{ "cal", OP(14), OP_MASK, PWRCOM, { RT, D, RA } }, 2540{ "cal", OP(14), OP_MASK, PWRCOM, { RT, D, RA0 } },
2394{ "subi", OP(14), OP_MASK, PPCCOM, { RT, RA, NSI } }, 2541{ "subi", OP(14), OP_MASK, PPCCOM, { RT, RA0, NSI } },
2395{ "la", OP(14), OP_MASK, PPCCOM, { RT, D, RA } }, 2542{ "la", OP(14), OP_MASK, PPCCOM, { RT, D, RA0 } },
2396 2543
2397{ "lis", OP(15), DRA_MASK, PPCCOM, { RT, SISIGNOPT } }, 2544{ "lis", OP(15), DRA_MASK, PPCCOM, { RT, SISIGNOPT } },
2398{ "liu", OP(15), DRA_MASK, PWRCOM, { RT, SISIGNOPT } }, 2545{ "liu", OP(15), DRA_MASK, PWRCOM, { RT, SISIGNOPT } },
2399{ "addis", OP(15), OP_MASK, PPCCOM, { RT,RA,SISIGNOPT } }, 2546{ "addis", OP(15), OP_MASK, PPCCOM, { RT,RA0,SISIGNOPT } },
2400{ "cau", OP(15), OP_MASK, PWRCOM, { RT,RA,SISIGNOPT } }, 2547{ "cau", OP(15), OP_MASK, PWRCOM, { RT,RA0,SISIGNOPT } },
2401{ "subis", OP(15), OP_MASK, PPCCOM, { RT, RA, NSI } }, 2548{ "subis", OP(15), OP_MASK, PPCCOM, { RT, RA0, NSI } },
2402 2549
2403{ "bdnz-", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, { BDM } }, 2550{ "bdnz-", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, { BDM } },
2404{ "bdnz+", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, { BDP } }, 2551{ "bdnz+", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, { BDP } },
@@ -2665,9 +2812,9 @@ const struct powerpc_opcode powerpc_opcodes[] = {
2665{ "bcla+", B(16,1,1), B_MASK, PPCCOM, { BOE, BI, BDPA } }, 2812{ "bcla+", B(16,1,1), B_MASK, PPCCOM, { BOE, BI, BDPA } },
2666{ "bcla", B(16,1,1), B_MASK, COM, { BO, BI, BDA } }, 2813{ "bcla", B(16,1,1), B_MASK, COM, { BO, BI, BDA } },
2667 2814
2668{ "sc", SC(17,1,0), 0xffffffff, PPC, { 0 } }, 2815{ "sc", SC(17,1,0), SC_MASK, PPC, { LEV } },
2669{ "svc", SC(17,0,0), SC_MASK, POWER, { LEV, FL1, FL2 } }, 2816{ "svc", SC(17,0,0), SC_MASK, POWER, { SVC_LEV, FL1, FL2 } },
2670{ "svcl", SC(17,0,1), SC_MASK, POWER, { LEV, FL1, FL2 } }, 2817{ "svcl", SC(17,0,1), SC_MASK, POWER, { SVC_LEV, FL1, FL2 } },
2671{ "svca", SC(17,1,0), SC_MASK, PWRCOM, { SV } }, 2818{ "svca", SC(17,1,0), SC_MASK, PWRCOM, { SV } },
2672{ "svcla", SC(17,1,1), SC_MASK, POWER, { SV } }, 2819{ "svcla", SC(17,1,1), SC_MASK, POWER, { SV } },
2673 2820
@@ -2890,12 +3037,12 @@ const struct powerpc_opcode powerpc_opcodes[] = {
2890{ "bdzflrl", XLO(19,BODZF,16,1), XLBOBB_MASK, PPCCOM, { BI } }, 3037{ "bdzflrl", XLO(19,BODZF,16,1), XLBOBB_MASK, PPCCOM, { BI } },
2891{ "bdzflrl-",XLO(19,BODZF,16,1), XLBOBB_MASK, NOPOWER4, { BI } }, 3038{ "bdzflrl-",XLO(19,BODZF,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2892{ "bdzflrl+",XLO(19,BODZFP,16,1), XLBOBB_MASK, NOPOWER4, { BI } }, 3039{ "bdzflrl+",XLO(19,BODZFP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2893{ "bclr", XLLK(19,16,0), XLYBB_MASK, PPCCOM, { BO, BI } },
2894{ "bclrl", XLLK(19,16,1), XLYBB_MASK, PPCCOM, { BO, BI } },
2895{ "bclr+", XLYLK(19,16,1,0), XLYBB_MASK, PPCCOM, { BOE, BI } }, 3040{ "bclr+", XLYLK(19,16,1,0), XLYBB_MASK, PPCCOM, { BOE, BI } },
2896{ "bclrl+", XLYLK(19,16,1,1), XLYBB_MASK, PPCCOM, { BOE, BI } }, 3041{ "bclrl+", XLYLK(19,16,1,1), XLYBB_MASK, PPCCOM, { BOE, BI } },
2897{ "bclr-", XLYLK(19,16,0,0), XLYBB_MASK, PPCCOM, { BOE, BI } }, 3042{ "bclr-", XLYLK(19,16,0,0), XLYBB_MASK, PPCCOM, { BOE, BI } },
2898{ "bclrl-", XLYLK(19,16,0,1), XLYBB_MASK, PPCCOM, { BOE, BI } }, 3043{ "bclrl-", XLYLK(19,16,0,1), XLYBB_MASK, PPCCOM, { BOE, BI } },
3044{ "bclr", XLLK(19,16,0), XLBH_MASK, PPCCOM, { BO, BI, BH } },
3045{ "bclrl", XLLK(19,16,1), XLBH_MASK, PPCCOM, { BO, BI, BH } },
2899{ "bcr", XLLK(19,16,0), XLBB_MASK, PWRCOM, { BO, BI } }, 3046{ "bcr", XLLK(19,16,0), XLBB_MASK, PWRCOM, { BO, BI } },
2900{ "bcrl", XLLK(19,16,1), XLBB_MASK, PWRCOM, { BO, BI } }, 3047{ "bcrl", XLLK(19,16,1), XLBB_MASK, PWRCOM, { BO, BI } },
2901{ "bclre", XLLK(19,17,0), XLBB_MASK, BOOKE64, { BO, BI } }, 3048{ "bclre", XLLK(19,17,0), XLBB_MASK, BOOKE64, { BO, BI } },
@@ -2924,14 +3071,23 @@ const struct powerpc_opcode powerpc_opcodes[] = {
2924 3071
2925{ "crand", XL(19,257), XL_MASK, COM, { BT, BA, BB } }, 3072{ "crand", XL(19,257), XL_MASK, COM, { BT, BA, BB } },
2926 3073
3074{ "hrfid", XL(19,274), 0xffffffff, POWER5 | CELL, { 0 } },
3075
2927{ "crset", XL(19,289), XL_MASK, PPCCOM, { BT, BAT, BBA } }, 3076{ "crset", XL(19,289), XL_MASK, PPCCOM, { BT, BAT, BBA } },
2928{ "creqv", XL(19,289), XL_MASK, COM, { BT, BA, BB } }, 3077{ "creqv", XL(19,289), XL_MASK, COM, { BT, BA, BB } },
2929 3078
3079{ "doze", XL(19,402), 0xffffffff, POWER6, { 0 } },
3080
2930{ "crorc", XL(19,417), XL_MASK, COM, { BT, BA, BB } }, 3081{ "crorc", XL(19,417), XL_MASK, COM, { BT, BA, BB } },
2931 3082
3083{ "nap", XL(19,434), 0xffffffff, POWER6, { 0 } },
3084
2932{ "crmove", XL(19,449), XL_MASK, PPCCOM, { BT, BA, BBA } }, 3085{ "crmove", XL(19,449), XL_MASK, PPCCOM, { BT, BA, BBA } },
2933{ "cror", XL(19,449), XL_MASK, COM, { BT, BA, BB } }, 3086{ "cror", XL(19,449), XL_MASK, COM, { BT, BA, BB } },
2934 3087
3088{ "sleep", XL(19,466), 0xffffffff, POWER6, { 0 } },
3089{ "rvwinkle", XL(19,498), 0xffffffff, POWER6, { 0 } },
3090
2935{ "bctr", XLO(19,BOU,528,0), XLBOBIBB_MASK, COM, { 0 } }, 3091{ "bctr", XLO(19,BOU,528,0), XLBOBIBB_MASK, COM, { 0 } },
2936{ "bctrl", XLO(19,BOU,528,1), XLBOBIBB_MASK, COM, { 0 } }, 3092{ "bctrl", XLO(19,BOU,528,1), XLBOBIBB_MASK, COM, { 0 } },
2937{ "bltctr", XLOCB(19,BOT,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, 3093{ "bltctr", XLOCB(19,BOT,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
@@ -3074,12 +3230,12 @@ const struct powerpc_opcode powerpc_opcodes[] = {
3074{ "bfctrl-", XLO(19,BOFM4,528,1), XLBOBB_MASK, POWER4, { BI } }, 3230{ "bfctrl-", XLO(19,BOFM4,528,1), XLBOBB_MASK, POWER4, { BI } },
3075{ "bfctrl+", XLO(19,BOFP,528,1), XLBOBB_MASK, NOPOWER4, { BI } }, 3231{ "bfctrl+", XLO(19,BOFP,528,1), XLBOBB_MASK, NOPOWER4, { BI } },
3076{ "bfctrl+", XLO(19,BOFP4,528,1), XLBOBB_MASK, POWER4, { BI } }, 3232{ "bfctrl+", XLO(19,BOFP4,528,1), XLBOBB_MASK, POWER4, { BI } },
3077{ "bcctr", XLLK(19,528,0), XLYBB_MASK, PPCCOM, { BO, BI } },
3078{ "bcctr-", XLYLK(19,528,0,0), XLYBB_MASK, PPCCOM, { BOE, BI } }, 3233{ "bcctr-", XLYLK(19,528,0,0), XLYBB_MASK, PPCCOM, { BOE, BI } },
3079{ "bcctr+", XLYLK(19,528,1,0), XLYBB_MASK, PPCCOM, { BOE, BI } }, 3234{ "bcctr+", XLYLK(19,528,1,0), XLYBB_MASK, PPCCOM, { BOE, BI } },
3080{ "bcctrl", XLLK(19,528,1), XLYBB_MASK, PPCCOM, { BO, BI } },
3081{ "bcctrl-", XLYLK(19,528,0,1), XLYBB_MASK, PPCCOM, { BOE, BI } }, 3235{ "bcctrl-", XLYLK(19,528,0,1), XLYBB_MASK, PPCCOM, { BOE, BI } },
3082{ "bcctrl+", XLYLK(19,528,1,1), XLYBB_MASK, PPCCOM, { BOE, BI } }, 3236{ "bcctrl+", XLYLK(19,528,1,1), XLYBB_MASK, PPCCOM, { BOE, BI } },
3237{ "bcctr", XLLK(19,528,0), XLBH_MASK, PPCCOM, { BO, BI, BH } },
3238{ "bcctrl", XLLK(19,528,1), XLBH_MASK, PPCCOM, { BO, BI, BH } },
3083{ "bcc", XLLK(19,528,0), XLBB_MASK, PWRCOM, { BO, BI } }, 3239{ "bcc", XLLK(19,528,0), XLBB_MASK, PWRCOM, { BO, BI } },
3084{ "bccl", XLLK(19,528,1), XLBB_MASK, PWRCOM, { BO, BI } }, 3240{ "bccl", XLLK(19,528,1), XLBB_MASK, PWRCOM, { BO, BI } },
3085{ "bcctre", XLLK(19,529,0), XLYBB_MASK, BOOKE64, { BO, BI } }, 3241{ "bcctre", XLLK(19,529,0), XLYBB_MASK, BOOKE64, { BO, BI } },
@@ -3158,8 +3314,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
3158{ "rldcr", MDS(30,9,0), MDS_MASK, PPC64, { RA, RS, RB, ME6 } }, 3314{ "rldcr", MDS(30,9,0), MDS_MASK, PPC64, { RA, RS, RB, ME6 } },
3159{ "rldcr.", MDS(30,9,1), MDS_MASK, PPC64, { RA, RS, RB, ME6 } }, 3315{ "rldcr.", MDS(30,9,1), MDS_MASK, PPC64, { RA, RS, RB, ME6 } },
3160 3316
3161{ "cmpw", XCMPL(31,0,0), XCMPL_MASK, PPCCOM, { OBF, RA, RB } }, 3317{ "cmpw", XOPL(31,0,0), XCMPL_MASK, PPCCOM, { OBF, RA, RB } },
3162{ "cmpd", XCMPL(31,0,1), XCMPL_MASK, PPC64, { OBF, RA, RB } }, 3318{ "cmpd", XOPL(31,0,1), XCMPL_MASK, PPC64, { OBF, RA, RB } },
3163{ "cmp", X(31,0), XCMP_MASK, PPC, { BF, L, RA, RB } }, 3319{ "cmp", X(31,0), XCMP_MASK, PPC, { BF, L, RA, RB } },
3164{ "cmp", X(31,0), XCMPL_MASK, PWRCOM, { BF, RA, RB } }, 3320{ "cmp", X(31,0), XCMPL_MASK, PWRCOM, { BF, RA, RB } },
3165 3321
@@ -3228,17 +3384,18 @@ const struct powerpc_opcode powerpc_opcodes[] = {
3228{ "iseleq", X(31,79), X_MASK, PPCISEL, { RT, RA, RB } }, 3384{ "iseleq", X(31,79), X_MASK, PPCISEL, { RT, RA, RB } },
3229{ "isel", XISEL(31,15), XISEL_MASK, PPCISEL, { RT, RA, RB, CRB } }, 3385{ "isel", XISEL(31,15), XISEL_MASK, PPCISEL, { RT, RA, RB, CRB } },
3230 3386
3231{ "mfcr", X(31,19), XRARB_MASK, NOPOWER4, { RT } }, 3387{ "mfocrf", XFXM(31,19,0,1), XFXFXM_MASK, COM, { RT, FXM } },
3388{ "mfcr", X(31,19), XRARB_MASK, NOPOWER4 | COM, { RT } },
3232{ "mfcr", X(31,19), XFXFXM_MASK, POWER4, { RT, FXM4 } }, 3389{ "mfcr", X(31,19), XFXFXM_MASK, POWER4, { RT, FXM4 } },
3233 3390
3234{ "lwarx", X(31,20), X_MASK, PPC, { RT, RA, RB } }, 3391{ "lwarx", X(31,20), XEH_MASK, PPC, { RT, RA0, RB, EH } },
3235 3392
3236{ "ldx", X(31,21), X_MASK, PPC64, { RT, RA, RB } }, 3393{ "ldx", X(31,21), X_MASK, PPC64, { RT, RA0, RB } },
3237 3394
3238{ "icbt", X(31,22), X_MASK, BOOKE, { CT, RA, RB } }, 3395{ "icbt", X(31,22), X_MASK, BOOKE|PPCE300, { CT, RA, RB } },
3239{ "icbt", X(31,262), XRT_MASK, PPC403, { RA, RB } }, 3396{ "icbt", X(31,262), XRT_MASK, PPC403, { RA, RB } },
3240 3397
3241{ "lwzx", X(31,23), X_MASK, PPCCOM, { RT, RA, RB } }, 3398{ "lwzx", X(31,23), X_MASK, PPCCOM, { RT, RA0, RB } },
3242{ "lx", X(31,23), X_MASK, PWRCOM, { RT, RA, RB } }, 3399{ "lx", X(31,23), X_MASK, PWRCOM, { RT, RA, RB } },
3243 3400
3244{ "slw", XRC(31,24,0), X_MASK, PPCCOM, { RA, RS, RB } }, 3401{ "slw", XRC(31,24,0), X_MASK, PPCCOM, { RA, RS, RB } },
@@ -3262,10 +3419,10 @@ const struct powerpc_opcode powerpc_opcodes[] = {
3262 3419
3263{ "icbte", X(31,30), X_MASK, BOOKE64, { CT, RA, RB } }, 3420{ "icbte", X(31,30), X_MASK, BOOKE64, { CT, RA, RB } },
3264 3421
3265{ "lwzxe", X(31,31), X_MASK, BOOKE64, { RT, RA, RB } }, 3422{ "lwzxe", X(31,31), X_MASK, BOOKE64, { RT, RA0, RB } },
3266 3423
3267{ "cmplw", XCMPL(31,32,0), XCMPL_MASK, PPCCOM, { OBF, RA, RB } }, 3424{ "cmplw", XOPL(31,32,0), XCMPL_MASK, PPCCOM, { OBF, RA, RB } },
3268{ "cmpld", XCMPL(31,32,1), XCMPL_MASK, PPC64, { OBF, RA, RB } }, 3425{ "cmpld", XOPL(31,32,1), XCMPL_MASK, PPC64, { OBF, RA, RB } },
3269{ "cmpl", X(31,32), XCMP_MASK, PPC, { BF, L, RA, RB } }, 3426{ "cmpl", X(31,32), XCMP_MASK, PPC, { BF, L, RA, RB } },
3270{ "cmpl", X(31,32), XCMPL_MASK, PWRCOM, { BF, RA, RB } }, 3427{ "cmpl", X(31,32), XCMPL_MASK, PWRCOM, { BF, RA, RB } },
3271 3428
@@ -3324,15 +3481,16 @@ const struct powerpc_opcode powerpc_opcodes[] = {
3324 3481
3325{ "mfmsr", X(31,83), XRARB_MASK, COM, { RT } }, 3482{ "mfmsr", X(31,83), XRARB_MASK, COM, { RT } },
3326 3483
3327{ "ldarx", X(31,84), X_MASK, PPC64, { RT, RA, RB } }, 3484{ "ldarx", X(31,84), XEH_MASK, PPC64, { RT, RA0, RB, EH } },
3328 3485
3329{ "dcbf", X(31,86), XRT_MASK, PPC, { RA, RB } }, 3486{ "dcbfl", XOPL(31,86,1), XRT_MASK, POWER5, { RA, RB } },
3487{ "dcbf", X(31,86), XLRT_MASK, PPC, { RA, RB, XRT_L } },
3330 3488
3331{ "lbzx", X(31,87), X_MASK, COM, { RT, RA, RB } }, 3489{ "lbzx", X(31,87), X_MASK, COM, { RT, RA0, RB } },
3332 3490
3333{ "dcbfe", X(31,94), XRT_MASK, BOOKE64, { RA, RB } }, 3491{ "dcbfe", X(31,94), XRT_MASK, BOOKE64, { RA, RB } },
3334 3492
3335{ "lbzxe", X(31,95), X_MASK, BOOKE64, { RT, RA, RB } }, 3493{ "lbzxe", X(31,95), X_MASK, BOOKE64, { RT, RA0, RB } },
3336 3494
3337{ "neg", XO(31,104,0,0), XORB_MASK, COM, { RT, RA } }, 3495{ "neg", XO(31,104,0,0), XORB_MASK, COM, { RT, RA } },
3338{ "neg.", XO(31,104,0,1), XORB_MASK, COM, { RT, RA } }, 3496{ "neg.", XO(31,104,0,1), XORB_MASK, COM, { RT, RA } },
@@ -3350,12 +3508,14 @@ const struct powerpc_opcode powerpc_opcodes[] = {
3350 3508
3351{ "lbzux", X(31,119), X_MASK, COM, { RT, RAL, RB } }, 3509{ "lbzux", X(31,119), X_MASK, COM, { RT, RAL, RB } },
3352 3510
3511{ "popcntb", X(31,122), XRB_MASK, POWER5, { RA, RS } },
3512
3353{ "not", XRC(31,124,0), X_MASK, COM, { RA, RS, RBS } }, 3513{ "not", XRC(31,124,0), X_MASK, COM, { RA, RS, RBS } },
3354{ "nor", XRC(31,124,0), X_MASK, COM, { RA, RS, RB } }, 3514{ "nor", XRC(31,124,0), X_MASK, COM, { RA, RS, RB } },
3355{ "not.", XRC(31,124,1), X_MASK, COM, { RA, RS, RBS } }, 3515{ "not.", XRC(31,124,1), X_MASK, COM, { RA, RS, RBS } },
3356{ "nor.", XRC(31,124,1), X_MASK, COM, { RA, RS, RB } }, 3516{ "nor.", XRC(31,124,1), X_MASK, COM, { RA, RS, RB } },
3357 3517
3358{ "lwarxe", X(31,126), X_MASK, BOOKE64, { RT, RA, RB } }, 3518{ "lwarxe", X(31,126), X_MASK, BOOKE64, { RT, RA0, RB } },
3359 3519
3360{ "lbzuxe", X(31,127), X_MASK, BOOKE64, { RT, RAL, RB } }, 3520{ "lbzuxe", X(31,127), X_MASK, BOOKE64, { RT, RAL, RB } },
3361 3521
@@ -3383,21 +3543,22 @@ const struct powerpc_opcode powerpc_opcodes[] = {
3383 3543
3384{ "dcbtstlse",X(31,142),X_MASK, PPCCHLK64, { CT, RA, RB }}, 3544{ "dcbtstlse",X(31,142),X_MASK, PPCCHLK64, { CT, RA, RB }},
3385 3545
3386{ "mtcr", XFXM(31,144,0xff), XRARB_MASK, COM, { RS }}, 3546{ "mtocrf", XFXM(31,144,0,1), XFXFXM_MASK, COM, { FXM, RS } },
3547{ "mtcr", XFXM(31,144,0xff,0), XRARB_MASK, COM, { RS }},
3387{ "mtcrf", X(31,144), XFXFXM_MASK, COM, { FXM, RS } }, 3548{ "mtcrf", X(31,144), XFXFXM_MASK, COM, { FXM, RS } },
3388 3549
3389{ "mtmsr", X(31,146), XRARB_MASK, COM, { RS } }, 3550{ "mtmsr", X(31,146), XRARB_MASK, COM, { RS } },
3390 3551
3391{ "stdx", X(31,149), X_MASK, PPC64, { RS, RA, RB } }, 3552{ "stdx", X(31,149), X_MASK, PPC64, { RS, RA0, RB } },
3392 3553
3393{ "stwcx.", XRC(31,150,1), X_MASK, PPC, { RS, RA, RB } }, 3554{ "stwcx.", XRC(31,150,1), X_MASK, PPC, { RS, RA0, RB } },
3394 3555
3395{ "stwx", X(31,151), X_MASK, PPCCOM, { RS, RA, RB } }, 3556{ "stwx", X(31,151), X_MASK, PPCCOM, { RS, RA0, RB } },
3396{ "stx", X(31,151), X_MASK, PWRCOM, { RS, RA, RB } }, 3557{ "stx", X(31,151), X_MASK, PWRCOM, { RS, RA, RB } },
3397 3558
3398{ "stwcxe.", XRC(31,158,1), X_MASK, BOOKE64, { RS, RA, RB } }, 3559{ "stwcxe.", XRC(31,158,1), X_MASK, BOOKE64, { RS, RA0, RB } },
3399 3560
3400{ "stwxe", X(31,159), X_MASK, BOOKE64, { RS, RA, RB } }, 3561{ "stwxe", X(31,159), X_MASK, BOOKE64, { RS, RA0, RB } },
3401 3562
3402{ "slq", XRC(31,152,0), X_MASK, M601, { RA, RS, RB } }, 3563{ "slq", XRC(31,152,0), X_MASK, M601, { RA, RS, RB } },
3403{ "slq.", XRC(31,152,1), X_MASK, M601, { RA, RS, RB } }, 3564{ "slq.", XRC(31,152,1), X_MASK, M601, { RA, RS, RB } },
@@ -3405,6 +3566,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
3405{ "sle", XRC(31,153,0), X_MASK, M601, { RA, RS, RB } }, 3566{ "sle", XRC(31,153,0), X_MASK, M601, { RA, RS, RB } },
3406{ "sle.", XRC(31,153,1), X_MASK, M601, { RA, RS, RB } }, 3567{ "sle.", XRC(31,153,1), X_MASK, M601, { RA, RS, RB } },
3407 3568
3569{ "prtyw", X(31,154), XRB_MASK, POWER6, { RA, RS } },
3570
3408{ "wrteei", X(31,163), XE_MASK, PPC403 | BOOKE, { E } }, 3571{ "wrteei", X(31,163), XE_MASK, PPC403 | BOOKE, { E } },
3409 3572
3410{ "dcbtls", X(31,166), X_MASK, PPCCHLK, { CT, RA, RB }}, 3573{ "dcbtls", X(31,166), X_MASK, PPCCHLK, { CT, RA, RB }},
@@ -3415,11 +3578,13 @@ const struct powerpc_opcode powerpc_opcodes[] = {
3415{ "stdux", X(31,181), X_MASK, PPC64, { RS, RAS, RB } }, 3578{ "stdux", X(31,181), X_MASK, PPC64, { RS, RAS, RB } },
3416 3579
3417{ "stwux", X(31,183), X_MASK, PPCCOM, { RS, RAS, RB } }, 3580{ "stwux", X(31,183), X_MASK, PPCCOM, { RS, RAS, RB } },
3418{ "stux", X(31,183), X_MASK, PWRCOM, { RS, RA, RB } }, 3581{ "stux", X(31,183), X_MASK, PWRCOM, { RS, RA0, RB } },
3419 3582
3420{ "sliq", XRC(31,184,0), X_MASK, M601, { RA, RS, SH } }, 3583{ "sliq", XRC(31,184,0), X_MASK, M601, { RA, RS, SH } },
3421{ "sliq.", XRC(31,184,1), X_MASK, M601, { RA, RS, SH } }, 3584{ "sliq.", XRC(31,184,1), X_MASK, M601, { RA, RS, SH } },
3422 3585
3586{ "prtyd", X(31,186), XRB_MASK, POWER6, { RA, RS } },
3587
3423{ "stwuxe", X(31,191), X_MASK, BOOKE64, { RS, RAS, RB } }, 3588{ "stwuxe", X(31,191), X_MASK, BOOKE64, { RS, RAS, RB } },
3424 3589
3425{ "subfze", XO(31,200,0,0), XORB_MASK, PPCCOM, { RT, RA } }, 3590{ "subfze", XO(31,200,0,0), XORB_MASK, PPCCOM, { RT, RA } },
@@ -3442,9 +3607,9 @@ const struct powerpc_opcode powerpc_opcodes[] = {
3442 3607
3443{ "mtsr", X(31,210), XRB_MASK|(1<<20), COM32, { SR, RS } }, 3608{ "mtsr", X(31,210), XRB_MASK|(1<<20), COM32, { SR, RS } },
3444 3609
3445{ "stdcx.", XRC(31,214,1), X_MASK, PPC64, { RS, RA, RB } }, 3610{ "stdcx.", XRC(31,214,1), X_MASK, PPC64, { RS, RA0, RB } },
3446 3611
3447{ "stbx", X(31,215), X_MASK, COM, { RS, RA, RB } }, 3612{ "stbx", X(31,215), X_MASK, COM, { RS, RA0, RB } },
3448 3613
3449{ "sllq", XRC(31,216,0), X_MASK, M601, { RA, RS, RB } }, 3614{ "sllq", XRC(31,216,0), X_MASK, M601, { RA, RS, RB } },
3450{ "sllq.", XRC(31,216,1), X_MASK, M601, { RA, RS, RB } }, 3615{ "sllq.", XRC(31,216,1), X_MASK, M601, { RA, RS, RB } },
@@ -3452,7 +3617,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
3452{ "sleq", XRC(31,217,0), X_MASK, M601, { RA, RS, RB } }, 3617{ "sleq", XRC(31,217,0), X_MASK, M601, { RA, RS, RB } },
3453{ "sleq.", XRC(31,217,1), X_MASK, M601, { RA, RS, RB } }, 3618{ "sleq.", XRC(31,217,1), X_MASK, M601, { RA, RS, RB } },
3454 3619
3455{ "stbxe", X(31,223), X_MASK, BOOKE64, { RS, RA, RB } }, 3620{ "stbxe", X(31,223), X_MASK, BOOKE64, { RS, RA0, RB } },
3456 3621
3457{ "icblc", X(31,230), X_MASK, PPCCHLK, { CT, RA, RB }}, 3622{ "icblc", X(31,230), X_MASK, PPCCHLK, { CT, RA, RB }},
3458 3623
@@ -3492,7 +3657,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
3492{ "mtsrin", X(31,242), XRA_MASK, PPC32, { RS, RB } }, 3657{ "mtsrin", X(31,242), XRA_MASK, PPC32, { RS, RB } },
3493{ "mtsri", X(31,242), XRA_MASK, POWER32, { RS, RB } }, 3658{ "mtsri", X(31,242), XRA_MASK, POWER32, { RS, RB } },
3494 3659
3495{ "dcbtst", X(31,246), XRT_MASK, PPC, { CT, RA, RB } }, 3660{ "dcbtst", X(31,246), X_MASK, PPC, { CT, RA, RB } },
3496 3661
3497{ "stbux", X(31,247), X_MASK, COM, { RS, RAS, RB } }, 3662{ "stbux", X(31,247), X_MASK, COM, { RS, RAS, RB } },
3498 3663
@@ -3519,26 +3684,26 @@ const struct powerpc_opcode powerpc_opcodes[] = {
3519{ "addo.", XO(31,266,1,1), XO_MASK, PPCCOM, { RT, RA, RB } }, 3684{ "addo.", XO(31,266,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3520{ "caxo.", XO(31,266,1,1), XO_MASK, PWRCOM, { RT, RA, RB } }, 3685{ "caxo.", XO(31,266,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3521 3686
3522{ "tlbiel", X(31,274), XRTRA_MASK, POWER4, { RB } }, 3687{ "tlbiel", X(31,274), XRTLRA_MASK, POWER4, { RB, L } },
3523 3688
3524{ "mfapidi", X(31,275), X_MASK, BOOKE, { RT, RA } }, 3689{ "mfapidi", X(31,275), X_MASK, BOOKE, { RT, RA } },
3525 3690
3526{ "lscbx", XRC(31,277,0), X_MASK, M601, { RT, RA, RB } }, 3691{ "lscbx", XRC(31,277,0), X_MASK, M601, { RT, RA, RB } },
3527{ "lscbx.", XRC(31,277,1), X_MASK, M601, { RT, RA, RB } }, 3692{ "lscbx.", XRC(31,277,1), X_MASK, M601, { RT, RA, RB } },
3528 3693
3529{ "dcbt", X(31,278), XRT_MASK, PPC, { CT, RA, RB } }, 3694{ "dcbt", X(31,278), X_MASK, PPC, { CT, RA, RB } },
3530 3695
3531{ "lhzx", X(31,279), X_MASK, COM, { RT, RA, RB } }, 3696{ "lhzx", X(31,279), X_MASK, COM, { RT, RA0, RB } },
3532 3697
3533{ "eqv", XRC(31,284,0), X_MASK, COM, { RA, RS, RB } }, 3698{ "eqv", XRC(31,284,0), X_MASK, COM, { RA, RS, RB } },
3534{ "eqv.", XRC(31,284,1), X_MASK, COM, { RA, RS, RB } }, 3699{ "eqv.", XRC(31,284,1), X_MASK, COM, { RA, RS, RB } },
3535 3700
3536{ "dcbte", X(31,286), X_MASK, BOOKE64, { CT, RA, RB } }, 3701{ "dcbte", X(31,286), X_MASK, BOOKE64, { CT, RA, RB } },
3537 3702
3538{ "lhzxe", X(31,287), X_MASK, BOOKE64, { RT, RA, RB } }, 3703{ "lhzxe", X(31,287), X_MASK, BOOKE64, { RT, RA0, RB } },
3539 3704
3540{ "tlbie", X(31,306), XRTLRA_MASK, PPC, { RB, L } }, 3705{ "tlbie", X(31,306), XRTLRA_MASK, PPC, { RB, L } },
3541{ "tlbi", X(31,306), XRT_MASK, POWER, { RA, RB } }, 3706{ "tlbi", X(31,306), XRT_MASK, POWER, { RA0, RB } },
3542 3707
3543{ "eciwx", X(31,310), X_MASK, PPC, { RT, RA, RB } }, 3708{ "eciwx", X(31,310), X_MASK, PPC, { RT, RA, RB } },
3544 3709
@@ -3607,6 +3772,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
3607{ "mfsdr1", XSPR(31,339,25), XSPR_MASK, COM, { RT } }, 3772{ "mfsdr1", XSPR(31,339,25), XSPR_MASK, COM, { RT } },
3608{ "mfsrr0", XSPR(31,339,26), XSPR_MASK, COM, { RT } }, 3773{ "mfsrr0", XSPR(31,339,26), XSPR_MASK, COM, { RT } },
3609{ "mfsrr1", XSPR(31,339,27), XSPR_MASK, COM, { RT } }, 3774{ "mfsrr1", XSPR(31,339,27), XSPR_MASK, COM, { RT } },
3775{ "mfcfar", XSPR(31,339,28), XSPR_MASK, POWER6, { RT } },
3610{ "mfpid", XSPR(31,339,48), XSPR_MASK, BOOKE, { RT } }, 3776{ "mfpid", XSPR(31,339,48), XSPR_MASK, BOOKE, { RT } },
3611{ "mfpid", XSPR(31,339,945), XSPR_MASK, PPC403, { RT } }, 3777{ "mfpid", XSPR(31,339,945), XSPR_MASK, PPC403, { RT } },
3612{ "mfcsrr0", XSPR(31,339,58), XSPR_MASK, BOOKE, { RT } }, 3778{ "mfcsrr0", XSPR(31,339,58), XSPR_MASK, BOOKE, { RT } },
@@ -3634,21 +3800,21 @@ const struct powerpc_opcode powerpc_opcodes[] = {
3634{ "mfbar", XSPR(31,339,159), XSPR_MASK, PPC860, { RT } }, 3800{ "mfbar", XSPR(31,339,159), XSPR_MASK, PPC860, { RT } },
3635{ "mfvrsave", XSPR(31,339,256), XSPR_MASK, PPCVEC, { RT } }, 3801{ "mfvrsave", XSPR(31,339,256), XSPR_MASK, PPCVEC, { RT } },
3636{ "mfusprg0", XSPR(31,339,256), XSPR_MASK, BOOKE, { RT } }, 3802{ "mfusprg0", XSPR(31,339,256), XSPR_MASK, BOOKE, { RT } },
3637{ "mfsprg4", XSPR(31,339,260), XSPR_MASK, PPC405, { RT } },
3638{ "mfsprg5", XSPR(31,339,261), XSPR_MASK, PPC405, { RT } },
3639{ "mfsprg6", XSPR(31,339,262), XSPR_MASK, PPC405, { RT } },
3640{ "mfsprg7", XSPR(31,339,263), XSPR_MASK, PPC405, { RT } },
3641{ "mftb", X(31,371), X_MASK, CLASSIC, { RT, TBR } }, 3803{ "mftb", X(31,371), X_MASK, CLASSIC, { RT, TBR } },
3642{ "mftb", XSPR(31,339,268), XSPR_MASK, BOOKE, { RT } }, 3804{ "mftb", XSPR(31,339,268), XSPR_MASK, BOOKE, { RT } },
3643{ "mftbl", XSPR(31,371,268), XSPR_MASK, CLASSIC, { RT } }, 3805{ "mftbl", XSPR(31,371,268), XSPR_MASK, CLASSIC, { RT } },
3644{ "mftbl", XSPR(31,339,268), XSPR_MASK, BOOKE, { RT } }, 3806{ "mftbl", XSPR(31,339,268), XSPR_MASK, BOOKE, { RT } },
3645{ "mftbu", XSPR(31,371,269), XSPR_MASK, CLASSIC, { RT } }, 3807{ "mftbu", XSPR(31,371,269), XSPR_MASK, CLASSIC, { RT } },
3646{ "mftbu", XSPR(31,339,269), XSPR_MASK, BOOKE, { RT } }, 3808{ "mftbu", XSPR(31,339,269), XSPR_MASK, BOOKE, { RT } },
3647{ "mfsprg", XSPR(31,339,272), XSPRG_MASK, PPC, { RT, SPRG } }, 3809{ "mfsprg", XSPR(31,339,256), XSPRG_MASK, PPC, { RT, SPRG } },
3648{ "mfsprg0", XSPR(31,339,272), XSPR_MASK, PPC, { RT } }, 3810{ "mfsprg0", XSPR(31,339,272), XSPR_MASK, PPC, { RT } },
3649{ "mfsprg1", XSPR(31,339,273), XSPR_MASK, PPC, { RT } }, 3811{ "mfsprg1", XSPR(31,339,273), XSPR_MASK, PPC, { RT } },
3650{ "mfsprg2", XSPR(31,339,274), XSPR_MASK, PPC, { RT } }, 3812{ "mfsprg2", XSPR(31,339,274), XSPR_MASK, PPC, { RT } },
3651{ "mfsprg3", XSPR(31,339,275), XSPR_MASK, PPC, { RT } }, 3813{ "mfsprg3", XSPR(31,339,275), XSPR_MASK, PPC, { RT } },
3814{ "mfsprg4", XSPR(31,339,260), XSPR_MASK, PPC405 | BOOKE, { RT } },
3815{ "mfsprg5", XSPR(31,339,261), XSPR_MASK, PPC405 | BOOKE, { RT } },
3816{ "mfsprg6", XSPR(31,339,262), XSPR_MASK, PPC405 | BOOKE, { RT } },
3817{ "mfsprg7", XSPR(31,339,263), XSPR_MASK, PPC405 | BOOKE, { RT } },
3652{ "mfasr", XSPR(31,339,280), XSPR_MASK, PPC64, { RT } }, 3818{ "mfasr", XSPR(31,339,280), XSPR_MASK, PPC64, { RT } },
3653{ "mfear", XSPR(31,339,282), XSPR_MASK, PPC, { RT } }, 3819{ "mfear", XSPR(31,339,282), XSPR_MASK, PPC, { RT } },
3654{ "mfpir", XSPR(31,339,286), XSPR_MASK, BOOKE, { RT } }, 3820{ "mfpir", XSPR(31,339,286), XSPR_MASK, BOOKE, { RT } },
@@ -3699,6 +3865,10 @@ const struct powerpc_opcode powerpc_opcodes[] = {
3699{ "mfspefscr", XSPR(31,339,512), XSPR_MASK, PPCSPE, { RT } }, 3865{ "mfspefscr", XSPR(31,339,512), XSPR_MASK, PPCSPE, { RT } },
3700{ "mfbbear", XSPR(31,339,513), XSPR_MASK, PPCBRLK, { RT } }, 3866{ "mfbbear", XSPR(31,339,513), XSPR_MASK, PPCBRLK, { RT } },
3701{ "mfbbtar", XSPR(31,339,514), XSPR_MASK, PPCBRLK, { RT } }, 3867{ "mfbbtar", XSPR(31,339,514), XSPR_MASK, PPCBRLK, { RT } },
3868{ "mfivor32", XSPR(31,339,528), XSPR_MASK, PPCSPE, { RT } },
3869{ "mfivor33", XSPR(31,339,529), XSPR_MASK, PPCSPE, { RT } },
3870{ "mfivor34", XSPR(31,339,530), XSPR_MASK, PPCSPE, { RT } },
3871{ "mfivor35", XSPR(31,339,531), XSPR_MASK, PPCPMR, { RT } },
3702{ "mfibatu", XSPR(31,339,528), XSPRBAT_MASK, PPC, { RT, SPRBAT } }, 3872{ "mfibatu", XSPR(31,339,528), XSPRBAT_MASK, PPC, { RT, SPRBAT } },
3703{ "mfibatl", XSPR(31,339,529), XSPRBAT_MASK, PPC, { RT, SPRBAT } }, 3873{ "mfibatl", XSPR(31,339,529), XSPRBAT_MASK, PPC, { RT, SPRBAT } },
3704{ "mfdbatu", XSPR(31,339,536), XSPRBAT_MASK, PPC, { RT, SPRBAT } }, 3874{ "mfdbatu", XSPR(31,339,536), XSPRBAT_MASK, PPC, { RT, SPRBAT } },
@@ -3708,10 +3878,11 @@ const struct powerpc_opcode powerpc_opcodes[] = {
3708{ "mfic_dat", XSPR(31,339,562), XSPR_MASK, PPC860, { RT } }, 3878{ "mfic_dat", XSPR(31,339,562), XSPR_MASK, PPC860, { RT } },
3709{ "mfdc_cst", XSPR(31,339,568), XSPR_MASK, PPC860, { RT } }, 3879{ "mfdc_cst", XSPR(31,339,568), XSPR_MASK, PPC860, { RT } },
3710{ "mfdc_adr", XSPR(31,339,569), XSPR_MASK, PPC860, { RT } }, 3880{ "mfdc_adr", XSPR(31,339,569), XSPR_MASK, PPC860, { RT } },
3711{ "mfdc_dat", XSPR(31,339,570), XSPR_MASK, PPC860, { RT } },
3712{ "mfmcsrr0", XSPR(31,339,570), XSPR_MASK, PPCRFMCI, { RT } }, 3881{ "mfmcsrr0", XSPR(31,339,570), XSPR_MASK, PPCRFMCI, { RT } },
3882{ "mfdc_dat", XSPR(31,339,570), XSPR_MASK, PPC860, { RT } },
3713{ "mfmcsrr1", XSPR(31,339,571), XSPR_MASK, PPCRFMCI, { RT } }, 3883{ "mfmcsrr1", XSPR(31,339,571), XSPR_MASK, PPCRFMCI, { RT } },
3714{ "mfmcsr", XSPR(31,339,572), XSPR_MASK, PPCRFMCI, { RT } }, 3884{ "mfmcsr", XSPR(31,339,572), XSPR_MASK, PPCRFMCI, { RT } },
3885{ "mfmcar", XSPR(31,339,573), XSPR_MASK, PPCRFMCI, { RT } },
3715{ "mfdpdr", XSPR(31,339,630), XSPR_MASK, PPC860, { RT } }, 3886{ "mfdpdr", XSPR(31,339,630), XSPR_MASK, PPC860, { RT } },
3716{ "mfdpir", XSPR(31,339,631), XSPR_MASK, PPC860, { RT } }, 3887{ "mfdpir", XSPR(31,339,631), XSPR_MASK, PPC860, { RT } },
3717{ "mfimmr", XSPR(31,339,638), XSPR_MASK, PPC860, { RT } }, 3888{ "mfimmr", XSPR(31,339,638), XSPR_MASK, PPC860, { RT } },
@@ -3775,14 +3946,14 @@ const struct powerpc_opcode powerpc_opcodes[] = {
3775{ "mfpbu2", XSPR(31,339,1023), XSPR_MASK, PPC403, { RT } }, 3946{ "mfpbu2", XSPR(31,339,1023), XSPR_MASK, PPC403, { RT } },
3776{ "mfspr", X(31,339), X_MASK, COM, { RT, SPR } }, 3947{ "mfspr", X(31,339), X_MASK, COM, { RT, SPR } },
3777 3948
3778{ "lwax", X(31,341), X_MASK, PPC64, { RT, RA, RB } }, 3949{ "lwax", X(31,341), X_MASK, PPC64, { RT, RA0, RB } },
3779 3950
3780{ "dst", XDSS(31,342,0), XDSS_MASK, PPCVEC, { RA, RB, STRM } }, 3951{ "dst", XDSS(31,342,0), XDSS_MASK, PPCVEC, { RA, RB, STRM } },
3781{ "dstt", XDSS(31,342,1), XDSS_MASK, PPCVEC, { RA, RB, STRM } }, 3952{ "dstt", XDSS(31,342,1), XDSS_MASK, PPCVEC, { RA, RB, STRM } },
3782 3953
3783{ "lhax", X(31,343), X_MASK, COM, { RT, RA, RB } }, 3954{ "lhax", X(31,343), X_MASK, COM, { RT, RA0, RB } },
3784 3955
3785{ "lhaxe", X(31,351), X_MASK, BOOKE64, { RT, RA, RB } }, 3956{ "lhaxe", X(31,351), X_MASK, BOOKE64, { RT, RA0, RB } },
3786 3957
3787{ "dstst", XDSS(31,374,0), XDSS_MASK, PPCVEC, { RA, RB, STRM } }, 3958{ "dstst", XDSS(31,374,0), XDSS_MASK, PPCVEC, { RA, RB, STRM } },
3788{ "dststt", XDSS(31,374,1), XDSS_MASK, PPCVEC, { RA, RB, STRM } }, 3959{ "dststt", XDSS(31,374,1), XDSS_MASK, PPCVEC, { RA, RB, STRM } },
@@ -3821,14 +3992,20 @@ const struct powerpc_opcode powerpc_opcodes[] = {
3821 3992
3822{ "slbmte", X(31,402), XRA_MASK, PPC64, { RS, RB } }, 3993{ "slbmte", X(31,402), XRA_MASK, PPC64, { RS, RB } },
3823 3994
3824{ "sthx", X(31,407), X_MASK, COM, { RS, RA, RB } }, 3995{ "sthx", X(31,407), X_MASK, COM, { RS, RA0, RB } },
3996
3997{ "cmpb", X(31,508), X_MASK, POWER6, { RA, RS, RB } },
3825 3998
3826{ "lfqx", X(31,791), X_MASK, POWER2, { FRT, RA, RB } }, 3999{ "lfqx", X(31,791), X_MASK, POWER2, { FRT, RA, RB } },
3827 4000
4001{ "lfdpx", X(31,791), X_MASK, POWER6, { FRT, RA, RB } },
4002
3828{ "lfqux", X(31,823), X_MASK, POWER2, { FRT, RA, RB } }, 4003{ "lfqux", X(31,823), X_MASK, POWER2, { FRT, RA, RB } },
3829 4004
3830{ "stfqx", X(31,919), X_MASK, POWER2, { FRS, RA, RB } }, 4005{ "stfqx", X(31,919), X_MASK, POWER2, { FRS, RA, RB } },
3831 4006
4007{ "stfdpx", X(31,919), X_MASK, POWER6, { FRS, RA, RB } },
4008
3832{ "stfqux", X(31,951), X_MASK, POWER2, { FRS, RA, RB } }, 4009{ "stfqux", X(31,951), X_MASK, POWER2, { FRS, RA, RB } },
3833 4010
3834{ "orc", XRC(31,412,0), X_MASK, COM, { RA, RS, RB } }, 4011{ "orc", XRC(31,412,0), X_MASK, COM, { RA, RS, RB } },
@@ -3837,7 +4014,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
3837{ "sradi", XS(31,413,0), XS_MASK, PPC64, { RA, RS, SH6 } }, 4014{ "sradi", XS(31,413,0), XS_MASK, PPC64, { RA, RS, SH6 } },
3838{ "sradi.", XS(31,413,1), XS_MASK, PPC64, { RA, RS, SH6 } }, 4015{ "sradi.", XS(31,413,1), XS_MASK, PPC64, { RA, RS, SH6 } },
3839 4016
3840{ "sthxe", X(31,415), X_MASK, BOOKE64, { RS, RA, RB } }, 4017{ "sthxe", X(31,415), X_MASK, BOOKE64, { RS, RA0, RB } },
3841 4018
3842{ "slbie", X(31,434), XRTRA_MASK, PPC64, { RB } }, 4019{ "slbie", X(31,434), XRTRA_MASK, PPC64, { RB } },
3843 4020
@@ -3918,6 +4095,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
3918{ "mtsdr1", XSPR(31,467,25), XSPR_MASK, COM, { RS } }, 4095{ "mtsdr1", XSPR(31,467,25), XSPR_MASK, COM, { RS } },
3919{ "mtsrr0", XSPR(31,467,26), XSPR_MASK, COM, { RS } }, 4096{ "mtsrr0", XSPR(31,467,26), XSPR_MASK, COM, { RS } },
3920{ "mtsrr1", XSPR(31,467,27), XSPR_MASK, COM, { RS } }, 4097{ "mtsrr1", XSPR(31,467,27), XSPR_MASK, COM, { RS } },
4098{ "mtcfar", XSPR(31,467,28), XSPR_MASK, POWER6, { RS } },
3921{ "mtpid", XSPR(31,467,48), XSPR_MASK, BOOKE, { RS } }, 4099{ "mtpid", XSPR(31,467,48), XSPR_MASK, BOOKE, { RS } },
3922{ "mtpid", XSPR(31,467,945), XSPR_MASK, PPC403, { RS } }, 4100{ "mtpid", XSPR(31,467,945), XSPR_MASK, PPC403, { RS } },
3923{ "mtdecar", XSPR(31,467,54), XSPR_MASK, BOOKE, { RS } }, 4101{ "mtdecar", XSPR(31,467,54), XSPR_MASK, BOOKE, { RS } },
@@ -3946,7 +4124,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
3946{ "mtbar", XSPR(31,467,159), XSPR_MASK, PPC860, { RS } }, 4124{ "mtbar", XSPR(31,467,159), XSPR_MASK, PPC860, { RS } },
3947{ "mtvrsave", XSPR(31,467,256), XSPR_MASK, PPCVEC, { RS } }, 4125{ "mtvrsave", XSPR(31,467,256), XSPR_MASK, PPCVEC, { RS } },
3948{ "mtusprg0", XSPR(31,467,256), XSPR_MASK, BOOKE, { RS } }, 4126{ "mtusprg0", XSPR(31,467,256), XSPR_MASK, BOOKE, { RS } },
3949{ "mtsprg", XSPR(31,467,272), XSPRG_MASK,PPC, { SPRG, RS } }, 4127{ "mtsprg", XSPR(31,467,256), XSPRG_MASK,PPC, { SPRG, RS } },
3950{ "mtsprg0", XSPR(31,467,272), XSPR_MASK, PPC, { RS } }, 4128{ "mtsprg0", XSPR(31,467,272), XSPR_MASK, PPC, { RS } },
3951{ "mtsprg1", XSPR(31,467,273), XSPR_MASK, PPC, { RS } }, 4129{ "mtsprg1", XSPR(31,467,273), XSPR_MASK, PPC, { RS } },
3952{ "mtsprg2", XSPR(31,467,274), XSPR_MASK, PPC, { RS } }, 4130{ "mtsprg2", XSPR(31,467,274), XSPR_MASK, PPC, { RS } },
@@ -4005,6 +4183,10 @@ const struct powerpc_opcode powerpc_opcodes[] = {
4005{ "mtspefscr", XSPR(31,467,512), XSPR_MASK, PPCSPE, { RS } }, 4183{ "mtspefscr", XSPR(31,467,512), XSPR_MASK, PPCSPE, { RS } },
4006{ "mtbbear", XSPR(31,467,513), XSPR_MASK, PPCBRLK, { RS } }, 4184{ "mtbbear", XSPR(31,467,513), XSPR_MASK, PPCBRLK, { RS } },
4007{ "mtbbtar", XSPR(31,467,514), XSPR_MASK, PPCBRLK, { RS } }, 4185{ "mtbbtar", XSPR(31,467,514), XSPR_MASK, PPCBRLK, { RS } },
4186{ "mtivor32", XSPR(31,467,528), XSPR_MASK, PPCSPE, { RS } },
4187{ "mtivor33", XSPR(31,467,529), XSPR_MASK, PPCSPE, { RS } },
4188{ "mtivor34", XSPR(31,467,530), XSPR_MASK, PPCSPE, { RS } },
4189{ "mtivor35", XSPR(31,467,531), XSPR_MASK, PPCPMR, { RS } },
4008{ "mtibatu", XSPR(31,467,528), XSPRBAT_MASK, PPC, { SPRBAT, RS } }, 4190{ "mtibatu", XSPR(31,467,528), XSPRBAT_MASK, PPC, { SPRBAT, RS } },
4009{ "mtibatl", XSPR(31,467,529), XSPRBAT_MASK, PPC, { SPRBAT, RS } }, 4191{ "mtibatl", XSPR(31,467,529), XSPRBAT_MASK, PPC, { SPRBAT, RS } },
4010{ "mtdbatu", XSPR(31,467,536), XSPRBAT_MASK, PPC, { SPRBAT, RS } }, 4192{ "mtdbatu", XSPR(31,467,536), XSPRBAT_MASK, PPC, { SPRBAT, RS } },
@@ -4101,13 +4283,15 @@ const struct powerpc_opcode powerpc_opcodes[] = {
4101 4283
4102{ "clcs", X(31,531), XRB_MASK, M601, { RT, RA } }, 4284{ "clcs", X(31,531), XRB_MASK, M601, { RT, RA } },
4103 4285
4104{ "lswx", X(31,533), X_MASK, PPCCOM, { RT, RA, RB } }, 4286{ "ldbrx", X(31,532), X_MASK, CELL, { RT, RA0, RB } },
4287
4288{ "lswx", X(31,533), X_MASK, PPCCOM, { RT, RA0, RB } },
4105{ "lsx", X(31,533), X_MASK, PWRCOM, { RT, RA, RB } }, 4289{ "lsx", X(31,533), X_MASK, PWRCOM, { RT, RA, RB } },
4106 4290
4107{ "lwbrx", X(31,534), X_MASK, PPCCOM, { RT, RA, RB } }, 4291{ "lwbrx", X(31,534), X_MASK, PPCCOM, { RT, RA0, RB } },
4108{ "lbrx", X(31,534), X_MASK, PWRCOM, { RT, RA, RB } }, 4292{ "lbrx", X(31,534), X_MASK, PWRCOM, { RT, RA, RB } },
4109 4293
4110{ "lfsx", X(31,535), X_MASK, COM, { FRT, RA, RB } }, 4294{ "lfsx", X(31,535), X_MASK, COM, { FRT, RA0, RB } },
4111 4295
4112{ "srw", XRC(31,536,0), X_MASK, PPCCOM, { RA, RS, RB } }, 4296{ "srw", XRC(31,536,0), X_MASK, PPCCOM, { RA, RS, RB } },
4113{ "sr", XRC(31,536,0), X_MASK, PWRCOM, { RA, RS, RB } }, 4297{ "sr", XRC(31,536,0), X_MASK, PWRCOM, { RA, RS, RB } },
@@ -4123,11 +4307,12 @@ const struct powerpc_opcode powerpc_opcodes[] = {
4123{ "maskir", XRC(31,541,0), X_MASK, M601, { RA, RS, RB } }, 4307{ "maskir", XRC(31,541,0), X_MASK, M601, { RA, RS, RB } },
4124{ "maskir.", XRC(31,541,1), X_MASK, M601, { RA, RS, RB } }, 4308{ "maskir.", XRC(31,541,1), X_MASK, M601, { RA, RS, RB } },
4125 4309
4126{ "lwbrxe", X(31,542), X_MASK, BOOKE64, { RT, RA, RB } }, 4310{ "lwbrxe", X(31,542), X_MASK, BOOKE64, { RT, RA0, RB } },
4127 4311
4128{ "lfsxe", X(31,543), X_MASK, BOOKE64, { FRT, RA, RB } }, 4312{ "lfsxe", X(31,543), X_MASK, BOOKE64, { FRT, RA0, RB } },
4129 4313
4130{ "bbelr", X(31,550), X_MASK, PPCBRLK, { 0 }}, 4314{ "bbelr", X(31,550), X_MASK, PPCBRLK, { 0 }},
4315
4131{ "tlbsync", X(31,566), 0xffffffff, PPC, { 0 } }, 4316{ "tlbsync", X(31,566), 0xffffffff, PPC, { 0 } },
4132 4317
4133{ "lfsux", X(31,567), X_MASK, COM, { FRT, RAS, RB } }, 4318{ "lfsux", X(31,567), X_MASK, COM, { FRT, RAS, RB } },
@@ -4136,8 +4321,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
4136 4321
4137{ "mfsr", X(31,595), XRB_MASK|(1<<20), COM32, { RT, SR } }, 4322{ "mfsr", X(31,595), XRB_MASK|(1<<20), COM32, { RT, SR } },
4138 4323
4139{ "lswi", X(31,597), X_MASK, PPCCOM, { RT, RA, NB } }, 4324{ "lswi", X(31,597), X_MASK, PPCCOM, { RT, RA0, NB } },
4140{ "lsi", X(31,597), X_MASK, PWRCOM, { RT, RA, NB } }, 4325{ "lsi", X(31,597), X_MASK, PWRCOM, { RT, RA0, NB } },
4141 4326
4142{ "lwsync", XSYNC(31,598,1), 0xffffffff, PPC, { 0 } }, 4327{ "lwsync", XSYNC(31,598,1), 0xffffffff, PPC, { 0 } },
4143{ "ptesync", XSYNC(31,598,2), 0xffffffff, PPC64, { 0 } }, 4328{ "ptesync", XSYNC(31,598,2), 0xffffffff, PPC64, { 0 } },
@@ -4145,9 +4330,11 @@ const struct powerpc_opcode powerpc_opcodes[] = {
4145{ "sync", X(31,598), XSYNC_MASK, PPCCOM, { LS } }, 4330{ "sync", X(31,598), XSYNC_MASK, PPCCOM, { LS } },
4146{ "dcs", X(31,598), 0xffffffff, PWRCOM, { 0 } }, 4331{ "dcs", X(31,598), 0xffffffff, PWRCOM, { 0 } },
4147 4332
4148{ "lfdx", X(31,599), X_MASK, COM, { FRT, RA, RB } }, 4333{ "lfdx", X(31,599), X_MASK, COM, { FRT, RA0, RB } },
4334
4335{ "lfdxe", X(31,607), X_MASK, BOOKE64, { FRT, RA0, RB } },
4149 4336
4150{ "lfdxe", X(31,607), X_MASK, BOOKE64, { FRT, RA, RB } }, 4337{ "mffgpr", XRC(31,607,0), XRA_MASK, POWER6, { FRT, RB } },
4151 4338
4152{ "mfsri", X(31,627), X_MASK, PWRCOM, { RT, RA, RB } }, 4339{ "mfsri", X(31,627), X_MASK, PWRCOM, { RT, RA, RB } },
4153 4340
@@ -4159,13 +4346,15 @@ const struct powerpc_opcode powerpc_opcodes[] = {
4159 4346
4160{ "mfsrin", X(31,659), XRA_MASK, PPC32, { RT, RB } }, 4347{ "mfsrin", X(31,659), XRA_MASK, PPC32, { RT, RB } },
4161 4348
4162{ "stswx", X(31,661), X_MASK, PPCCOM, { RS, RA, RB } }, 4349{ "stdbrx", X(31,660), X_MASK, CELL, { RS, RA0, RB } },
4163{ "stsx", X(31,661), X_MASK, PWRCOM, { RS, RA, RB } }, 4350
4351{ "stswx", X(31,661), X_MASK, PPCCOM, { RS, RA0, RB } },
4352{ "stsx", X(31,661), X_MASK, PWRCOM, { RS, RA0, RB } },
4164 4353
4165{ "stwbrx", X(31,662), X_MASK, PPCCOM, { RS, RA, RB } }, 4354{ "stwbrx", X(31,662), X_MASK, PPCCOM, { RS, RA0, RB } },
4166{ "stbrx", X(31,662), X_MASK, PWRCOM, { RS, RA, RB } }, 4355{ "stbrx", X(31,662), X_MASK, PWRCOM, { RS, RA0, RB } },
4167 4356
4168{ "stfsx", X(31,663), X_MASK, COM, { FRS, RA, RB } }, 4357{ "stfsx", X(31,663), X_MASK, COM, { FRS, RA0, RB } },
4169 4358
4170{ "srq", XRC(31,664,0), X_MASK, M601, { RA, RS, RB } }, 4359{ "srq", XRC(31,664,0), X_MASK, M601, { RA, RS, RB } },
4171{ "srq.", XRC(31,664,1), X_MASK, M601, { RA, RS, RB } }, 4360{ "srq.", XRC(31,664,1), X_MASK, M601, { RA, RS, RB } },
@@ -4173,9 +4362,9 @@ const struct powerpc_opcode powerpc_opcodes[] = {
4173{ "sre", XRC(31,665,0), X_MASK, M601, { RA, RS, RB } }, 4362{ "sre", XRC(31,665,0), X_MASK, M601, { RA, RS, RB } },
4174{ "sre.", XRC(31,665,1), X_MASK, M601, { RA, RS, RB } }, 4363{ "sre.", XRC(31,665,1), X_MASK, M601, { RA, RS, RB } },
4175 4364
4176{ "stwbrxe", X(31,670), X_MASK, BOOKE64, { RS, RA, RB } }, 4365{ "stwbrxe", X(31,670), X_MASK, BOOKE64, { RS, RA0, RB } },
4177 4366
4178{ "stfsxe", X(31,671), X_MASK, BOOKE64, { FRS, RA, RB } }, 4367{ "stfsxe", X(31,671), X_MASK, BOOKE64, { FRS, RA0, RB } },
4179 4368
4180{ "stfsux", X(31,695), X_MASK, COM, { FRS, RAS, RB } }, 4369{ "stfsux", X(31,695), X_MASK, COM, { FRS, RAS, RB } },
4181 4370
@@ -4184,10 +4373,10 @@ const struct powerpc_opcode powerpc_opcodes[] = {
4184 4373
4185{ "stfsuxe", X(31,703), X_MASK, BOOKE64, { FRS, RAS, RB } }, 4374{ "stfsuxe", X(31,703), X_MASK, BOOKE64, { FRS, RAS, RB } },
4186 4375
4187{ "stswi", X(31,725), X_MASK, PPCCOM, { RS, RA, NB } }, 4376{ "stswi", X(31,725), X_MASK, PPCCOM, { RS, RA0, NB } },
4188{ "stsi", X(31,725), X_MASK, PWRCOM, { RS, RA, NB } }, 4377{ "stsi", X(31,725), X_MASK, PWRCOM, { RS, RA0, NB } },
4189 4378
4190{ "stfdx", X(31,727), X_MASK, COM, { FRS, RA, RB } }, 4379{ "stfdx", X(31,727), X_MASK, COM, { FRS, RA0, RB } },
4191 4380
4192{ "srlq", XRC(31,728,0), X_MASK, M601, { RA, RS, RB } }, 4381{ "srlq", XRC(31,728,0), X_MASK, M601, { RA, RS, RB } },
4193{ "srlq.", XRC(31,728,1), X_MASK, M601, { RA, RS, RB } }, 4382{ "srlq.", XRC(31,728,1), X_MASK, M601, { RA, RS, RB } },
@@ -4195,7 +4384,9 @@ const struct powerpc_opcode powerpc_opcodes[] = {
4195{ "sreq", XRC(31,729,0), X_MASK, M601, { RA, RS, RB } }, 4384{ "sreq", XRC(31,729,0), X_MASK, M601, { RA, RS, RB } },
4196{ "sreq.", XRC(31,729,1), X_MASK, M601, { RA, RS, RB } }, 4385{ "sreq.", XRC(31,729,1), X_MASK, M601, { RA, RS, RB } },
4197 4386
4198{ "stfdxe", X(31,735), X_MASK, BOOKE64, { FRS, RA, RB } }, 4387{ "stfdxe", X(31,735), X_MASK, BOOKE64, { FRS, RA0, RB } },
4388
4389{ "mftgpr", XRC(31,735,0), XRA_MASK, POWER6, { RT, FRB } },
4199 4390
4200{ "dcba", X(31,758), XRT_MASK, PPC405 | BOOKE, { RA, RB } }, 4391{ "dcba", X(31,758), XRT_MASK, PPC405 | BOOKE, { RA, RB } },
4201 4392
@@ -4211,7 +4402,9 @@ const struct powerpc_opcode powerpc_opcodes[] = {
4211{ "tlbivax", X(31,786), XRT_MASK, BOOKE, { RA, RB } }, 4402{ "tlbivax", X(31,786), XRT_MASK, BOOKE, { RA, RB } },
4212{ "tlbivaxe",X(31,787), XRT_MASK, BOOKE64, { RA, RB } }, 4403{ "tlbivaxe",X(31,787), XRT_MASK, BOOKE64, { RA, RB } },
4213 4404
4214{ "lhbrx", X(31,790), X_MASK, COM, { RT, RA, RB } }, 4405{ "lwzcix", X(31,789), X_MASK, POWER6, { RT, RA0, RB } },
4406
4407{ "lhbrx", X(31,790), X_MASK, COM, { RT, RA0, RB } },
4215 4408
4216{ "sraw", XRC(31,792,0), X_MASK, PPCCOM, { RA, RS, RB } }, 4409{ "sraw", XRC(31,792,0), X_MASK, PPCCOM, { RA, RS, RB } },
4217{ "sra", XRC(31,792,0), X_MASK, PWRCOM, { RA, RS, RB } }, 4410{ "sra", XRC(31,792,0), X_MASK, PWRCOM, { RA, RS, RB } },
@@ -4221,13 +4414,15 @@ const struct powerpc_opcode powerpc_opcodes[] = {
4221{ "srad", XRC(31,794,0), X_MASK, PPC64, { RA, RS, RB } }, 4414{ "srad", XRC(31,794,0), X_MASK, PPC64, { RA, RS, RB } },
4222{ "srad.", XRC(31,794,1), X_MASK, PPC64, { RA, RS, RB } }, 4415{ "srad.", XRC(31,794,1), X_MASK, PPC64, { RA, RS, RB } },
4223 4416
4224{ "lhbrxe", X(31,798), X_MASK, BOOKE64, { RT, RA, RB } }, 4417{ "lhbrxe", X(31,798), X_MASK, BOOKE64, { RT, RA0, RB } },
4225 4418
4226{ "ldxe", X(31,799), X_MASK, BOOKE64, { RT, RA, RB } }, 4419{ "ldxe", X(31,799), X_MASK, BOOKE64, { RT, RA0, RB } },
4227{ "lduxe", X(31,831), X_MASK, BOOKE64, { RT, RA, RB } }, 4420{ "lduxe", X(31,831), X_MASK, BOOKE64, { RT, RA0, RB } },
4228 4421
4229{ "rac", X(31,818), X_MASK, PWRCOM, { RT, RA, RB } }, 4422{ "rac", X(31,818), X_MASK, PWRCOM, { RT, RA, RB } },
4230 4423
4424{ "lhzcix", X(31,821), X_MASK, POWER6, { RT, RA0, RB } },
4425
4231{ "dss", XDSS(31,822,0), XDSS_MASK, PPCVEC, { STRM } }, 4426{ "dss", XDSS(31,822,0), XDSS_MASK, PPCVEC, { STRM } },
4232{ "dssall", XDSS(31,822,1), XDSS_MASK, PPCVEC, { 0 } }, 4427{ "dssall", XDSS(31,822,1), XDSS_MASK, PPCVEC, { 0 } },
4233 4428
@@ -4238,19 +4433,25 @@ const struct powerpc_opcode powerpc_opcodes[] = {
4238 4433
4239{ "slbmfev", X(31,851), XRA_MASK, PPC64, { RT, RB } }, 4434{ "slbmfev", X(31,851), XRA_MASK, PPC64, { RT, RB } },
4240 4435
4436{ "lbzcix", X(31,853), X_MASK, POWER6, { RT, RA0, RB } },
4437
4241{ "mbar", X(31,854), X_MASK, BOOKE, { MO } }, 4438{ "mbar", X(31,854), X_MASK, BOOKE, { MO } },
4242{ "eieio", X(31,854), 0xffffffff, PPC, { 0 } }, 4439{ "eieio", X(31,854), 0xffffffff, PPC, { 0 } },
4243 4440
4244{ "tlbsx", XRC(31,914,0), X_MASK, BOOKE, { RA, RB } }, 4441{ "lfiwax", X(31,855), X_MASK, POWER6, { FRT, RA0, RB } },
4245{ "tlbsx", XRC(31,914,0), X_MASK, PPC403, { RT, RA, RB } }, 4442
4246{ "tlbsx.", XRC(31,914,1), X_MASK, BOOKE, { RA, RB } }, 4443{ "ldcix", X(31,885), X_MASK, POWER6, { RT, RA0, RB } },
4247{ "tlbsx.", XRC(31,914,1), X_MASK, PPC403, { RT, RA, RB } }, 4444
4445{ "tlbsx", XRC(31,914,0), X_MASK, PPC403|BOOKE, { RTO, RA, RB } },
4446{ "tlbsx.", XRC(31,914,1), X_MASK, PPC403|BOOKE, { RTO, RA, RB } },
4248{ "tlbsxe", XRC(31,915,0), X_MASK, BOOKE64, { RA, RB } }, 4447{ "tlbsxe", XRC(31,915,0), X_MASK, BOOKE64, { RA, RB } },
4249{ "tlbsxe.", XRC(31,915,1), X_MASK, BOOKE64, { RA, RB } }, 4448{ "tlbsxe.", XRC(31,915,1), X_MASK, BOOKE64, { RA, RB } },
4250 4449
4251{ "slbmfee", X(31,915), XRA_MASK, PPC64, { RT, RB } }, 4450{ "slbmfee", X(31,915), XRA_MASK, PPC64, { RT, RB } },
4252 4451
4253{ "sthbrx", X(31,918), X_MASK, COM, { RS, RA, RB } }, 4452{ "stwcix", X(31,917), X_MASK, POWER6, { RS, RA0, RB } },
4453
4454{ "sthbrx", X(31,918), X_MASK, COM, { RS, RA0, RB } },
4254 4455
4255{ "sraq", XRC(31,920,0), X_MASK, M601, { RA, RS, RB } }, 4456{ "sraq", XRC(31,920,0), X_MASK, M601, { RA, RS, RB } },
4256{ "sraq.", XRC(31,920,1), X_MASK, M601, { RA, RS, RB } }, 4457{ "sraq.", XRC(31,920,1), X_MASK, M601, { RA, RS, RB } },
@@ -4263,14 +4464,15 @@ const struct powerpc_opcode powerpc_opcodes[] = {
4263{ "extsh.", XRC(31,922,1), XRB_MASK, PPCCOM, { RA, RS } }, 4464{ "extsh.", XRC(31,922,1), XRB_MASK, PPCCOM, { RA, RS } },
4264{ "exts.", XRC(31,922,1), XRB_MASK, PWRCOM, { RA, RS } }, 4465{ "exts.", XRC(31,922,1), XRB_MASK, PWRCOM, { RA, RS } },
4265 4466
4266{ "sthbrxe", X(31,926), X_MASK, BOOKE64, { RS, RA, RB } }, 4467{ "sthbrxe", X(31,926), X_MASK, BOOKE64, { RS, RA0, RB } },
4267 4468
4268{ "stdxe", X(31,927), X_MASK, BOOKE64, { RS, RA, RB } }, 4469{ "stdxe", X(31,927), X_MASK, BOOKE64, { RS, RA0, RB } },
4269 4470
4270{ "tlbrehi", XTLB(31,946,0), XTLB_MASK, PPC403, { RT, RA } }, 4471{ "tlbrehi", XTLB(31,946,0), XTLB_MASK, PPC403, { RT, RA } },
4271{ "tlbrelo", XTLB(31,946,1), XTLB_MASK, PPC403, { RT, RA } }, 4472{ "tlbrelo", XTLB(31,946,1), XTLB_MASK, PPC403, { RT, RA } },
4272{ "tlbre", X(31,946), X_MASK, BOOKE, { 0 } }, 4473{ "tlbre", X(31,946), X_MASK, PPC403|BOOKE, { RSO, RAOPT, SHO } },
4273{ "tlbre", X(31,946), X_MASK, PPC403, { RS, RA, SH } }, 4474
4475{ "sthcix", X(31,949), X_MASK, POWER6, { RS, RA0, RB } },
4274 4476
4275{ "sraiq", XRC(31,952,0), X_MASK, M601, { RA, RS, SH } }, 4477{ "sraiq", XRC(31,952,0), X_MASK, M601, { RA, RS, SH } },
4276{ "sraiq.", XRC(31,952,1), X_MASK, M601, { RA, RS, SH } }, 4478{ "sraiq.", XRC(31,952,1), X_MASK, M601, { RA, RS, SH } },
@@ -4284,13 +4486,14 @@ const struct powerpc_opcode powerpc_opcodes[] = {
4284 4486
4285{ "tlbwehi", XTLB(31,978,0), XTLB_MASK, PPC403, { RT, RA } }, 4487{ "tlbwehi", XTLB(31,978,0), XTLB_MASK, PPC403, { RT, RA } },
4286{ "tlbwelo", XTLB(31,978,1), XTLB_MASK, PPC403, { RT, RA } }, 4488{ "tlbwelo", XTLB(31,978,1), XTLB_MASK, PPC403, { RT, RA } },
4287{ "tlbwe", X(31,978), X_MASK, BOOKE, { 0 } }, 4489{ "tlbwe", X(31,978), X_MASK, PPC403|BOOKE, { RSO, RAOPT, SHO } },
4288{ "tlbwe", X(31,978), X_MASK, PPC403, { RS, RA, SH } },
4289{ "tlbld", X(31,978), XRTRA_MASK, PPC, { RB } }, 4490{ "tlbld", X(31,978), XRTRA_MASK, PPC, { RB } },
4290 4491
4492{ "stbcix", X(31,981), X_MASK, POWER6, { RS, RA0, RB } },
4493
4291{ "icbi", X(31,982), XRT_MASK, PPC, { RA, RB } }, 4494{ "icbi", X(31,982), XRT_MASK, PPC, { RA, RB } },
4292 4495
4293{ "stfiwx", X(31,983), X_MASK, PPC, { FRS, RA, RB } }, 4496{ "stfiwx", X(31,983), X_MASK, PPC, { FRS, RA0, RB } },
4294 4497
4295{ "extsw", XRC(31,986,0), XRB_MASK, PPC64 | BOOKE64,{ RA, RS } }, 4498{ "extsw", XRC(31,986,0), XRB_MASK, PPC64 | BOOKE64,{ RA, RS } },
4296{ "extsw.", XRC(31,986,1), XRB_MASK, PPC64, { RA, RS } }, 4499{ "extsw.", XRC(31,986,1), XRB_MASK, PPC64, { RA, RS } },
@@ -4298,10 +4501,13 @@ const struct powerpc_opcode powerpc_opcodes[] = {
4298{ "icread", X(31,998), XRT_MASK, PPC403|PPC440, { RA, RB } }, 4501{ "icread", X(31,998), XRT_MASK, PPC403|PPC440, { RA, RB } },
4299 4502
4300{ "icbie", X(31,990), XRT_MASK, BOOKE64, { RA, RB } }, 4503{ "icbie", X(31,990), XRT_MASK, BOOKE64, { RA, RB } },
4301{ "stfiwxe", X(31,991), X_MASK, BOOKE64, { FRS, RA, RB } }, 4504{ "stfiwxe", X(31,991), X_MASK, BOOKE64, { FRS, RA0, RB } },
4302 4505
4303{ "tlbli", X(31,1010), XRTRA_MASK, PPC, { RB } }, 4506{ "tlbli", X(31,1010), XRTRA_MASK, PPC, { RB } },
4304 4507
4508{ "stdcix", X(31,1013), X_MASK, POWER6, { RS, RA0, RB } },
4509
4510{ "dcbzl", XOPL(31,1014,1), XRT_MASK,POWER4, { RA, RB } },
4305{ "dcbz", X(31,1014), XRT_MASK, PPC, { RA, RB } }, 4511{ "dcbz", X(31,1014), XRT_MASK, PPC, { RA, RB } },
4306{ "dclz", X(31,1014), XRT_MASK, PPC, { RA, RB } }, 4512{ "dclz", X(31,1014), XRT_MASK, PPC, { RA, RB } },
4307 4513
@@ -4320,86 +4526,104 @@ const struct powerpc_opcode powerpc_opcodes[] = {
4320{ "stvx", X(31, 231), X_MASK, PPCVEC, { VS, RA, RB } }, 4526{ "stvx", X(31, 231), X_MASK, PPCVEC, { VS, RA, RB } },
4321{ "stvxl", X(31, 487), X_MASK, PPCVEC, { VS, RA, RB } }, 4527{ "stvxl", X(31, 487), X_MASK, PPCVEC, { VS, RA, RB } },
4322 4528
4323{ "lwz", OP(32), OP_MASK, PPCCOM, { RT, D, RA } }, 4529/* New load/store left/right index vector instructions that are in the Cell only. */
4324{ "l", OP(32), OP_MASK, PWRCOM, { RT, D, RA } }, 4530{ "lvlx", X(31, 519), X_MASK, CELL, { VD, RA0, RB } },
4531{ "lvlxl", X(31, 775), X_MASK, CELL, { VD, RA0, RB } },
4532{ "lvrx", X(31, 551), X_MASK, CELL, { VD, RA0, RB } },
4533{ "lvrxl", X(31, 807), X_MASK, CELL, { VD, RA0, RB } },
4534{ "stvlx", X(31, 647), X_MASK, CELL, { VS, RA0, RB } },
4535{ "stvlxl", X(31, 903), X_MASK, CELL, { VS, RA0, RB } },
4536{ "stvrx", X(31, 679), X_MASK, CELL, { VS, RA0, RB } },
4537{ "stvrxl", X(31, 935), X_MASK, CELL, { VS, RA0, RB } },
4538
4539{ "lwz", OP(32), OP_MASK, PPCCOM, { RT, D, RA0 } },
4540{ "l", OP(32), OP_MASK, PWRCOM, { RT, D, RA0 } },
4325 4541
4326{ "lwzu", OP(33), OP_MASK, PPCCOM, { RT, D, RAL } }, 4542{ "lwzu", OP(33), OP_MASK, PPCCOM, { RT, D, RAL } },
4327{ "lu", OP(33), OP_MASK, PWRCOM, { RT, D, RA } }, 4543{ "lu", OP(33), OP_MASK, PWRCOM, { RT, D, RA0 } },
4328 4544
4329{ "lbz", OP(34), OP_MASK, COM, { RT, D, RA } }, 4545{ "lbz", OP(34), OP_MASK, COM, { RT, D, RA0 } },
4330 4546
4331{ "lbzu", OP(35), OP_MASK, COM, { RT, D, RAL } }, 4547{ "lbzu", OP(35), OP_MASK, COM, { RT, D, RAL } },
4332 4548
4333{ "stw", OP(36), OP_MASK, PPCCOM, { RS, D, RA } }, 4549{ "stw", OP(36), OP_MASK, PPCCOM, { RS, D, RA0 } },
4334{ "st", OP(36), OP_MASK, PWRCOM, { RS, D, RA } }, 4550{ "st", OP(36), OP_MASK, PWRCOM, { RS, D, RA0 } },
4335 4551
4336{ "stwu", OP(37), OP_MASK, PPCCOM, { RS, D, RAS } }, 4552{ "stwu", OP(37), OP_MASK, PPCCOM, { RS, D, RAS } },
4337{ "stu", OP(37), OP_MASK, PWRCOM, { RS, D, RA } }, 4553{ "stu", OP(37), OP_MASK, PWRCOM, { RS, D, RA0 } },
4338 4554
4339{ "stb", OP(38), OP_MASK, COM, { RS, D, RA } }, 4555{ "stb", OP(38), OP_MASK, COM, { RS, D, RA0 } },
4340 4556
4341{ "stbu", OP(39), OP_MASK, COM, { RS, D, RAS } }, 4557{ "stbu", OP(39), OP_MASK, COM, { RS, D, RAS } },
4342 4558
4343{ "lhz", OP(40), OP_MASK, COM, { RT, D, RA } }, 4559{ "lhz", OP(40), OP_MASK, COM, { RT, D, RA0 } },
4344 4560
4345{ "lhzu", OP(41), OP_MASK, COM, { RT, D, RAL } }, 4561{ "lhzu", OP(41), OP_MASK, COM, { RT, D, RAL } },
4346 4562
4347{ "lha", OP(42), OP_MASK, COM, { RT, D, RA } }, 4563{ "lha", OP(42), OP_MASK, COM, { RT, D, RA0 } },
4348 4564
4349{ "lhau", OP(43), OP_MASK, COM, { RT, D, RAL } }, 4565{ "lhau", OP(43), OP_MASK, COM, { RT, D, RAL } },
4350 4566
4351{ "sth", OP(44), OP_MASK, COM, { RS, D, RA } }, 4567{ "sth", OP(44), OP_MASK, COM, { RS, D, RA0 } },
4352 4568
4353{ "sthu", OP(45), OP_MASK, COM, { RS, D, RAS } }, 4569{ "sthu", OP(45), OP_MASK, COM, { RS, D, RAS } },
4354 4570
4355{ "lmw", OP(46), OP_MASK, PPCCOM, { RT, D, RAM } }, 4571{ "lmw", OP(46), OP_MASK, PPCCOM, { RT, D, RAM } },
4356{ "lm", OP(46), OP_MASK, PWRCOM, { RT, D, RA } }, 4572{ "lm", OP(46), OP_MASK, PWRCOM, { RT, D, RA0 } },
4357 4573
4358{ "stmw", OP(47), OP_MASK, PPCCOM, { RS, D, RA } }, 4574{ "stmw", OP(47), OP_MASK, PPCCOM, { RS, D, RA0 } },
4359{ "stm", OP(47), OP_MASK, PWRCOM, { RS, D, RA } }, 4575{ "stm", OP(47), OP_MASK, PWRCOM, { RS, D, RA0 } },
4360 4576
4361{ "lfs", OP(48), OP_MASK, COM, { FRT, D, RA } }, 4577{ "lfs", OP(48), OP_MASK, COM, { FRT, D, RA0 } },
4362 4578
4363{ "lfsu", OP(49), OP_MASK, COM, { FRT, D, RAS } }, 4579{ "lfsu", OP(49), OP_MASK, COM, { FRT, D, RAS } },
4364 4580
4365{ "lfd", OP(50), OP_MASK, COM, { FRT, D, RA } }, 4581{ "lfd", OP(50), OP_MASK, COM, { FRT, D, RA0 } },
4366 4582
4367{ "lfdu", OP(51), OP_MASK, COM, { FRT, D, RAS } }, 4583{ "lfdu", OP(51), OP_MASK, COM, { FRT, D, RAS } },
4368 4584
4369{ "stfs", OP(52), OP_MASK, COM, { FRS, D, RA } }, 4585{ "stfs", OP(52), OP_MASK, COM, { FRS, D, RA0 } },
4370 4586
4371{ "stfsu", OP(53), OP_MASK, COM, { FRS, D, RAS } }, 4587{ "stfsu", OP(53), OP_MASK, COM, { FRS, D, RAS } },
4372 4588
4373{ "stfd", OP(54), OP_MASK, COM, { FRS, D, RA } }, 4589{ "stfd", OP(54), OP_MASK, COM, { FRS, D, RA0 } },
4374 4590
4375{ "stfdu", OP(55), OP_MASK, COM, { FRS, D, RAS } }, 4591{ "stfdu", OP(55), OP_MASK, COM, { FRS, D, RAS } },
4376 4592
4377{ "lq", OP(56), OP_MASK, POWER4, { RTQ, DQ, RAQ } }, 4593{ "lq", OP(56), OP_MASK, POWER4, { RTQ, DQ, RAQ } },
4378 4594
4379{ "lfq", OP(56), OP_MASK, POWER2, { FRT, D, RA } }, 4595{ "lfq", OP(56), OP_MASK, POWER2, { FRT, D, RA0 } },
4596
4597{ "lfqu", OP(57), OP_MASK, POWER2, { FRT, D, RA0 } },
4380 4598
4381{ "lfqu", OP(57), OP_MASK, POWER2, { FRT, D, RA } }, 4599{ "lfdp", OP(57), OP_MASK, POWER6, { FRT, D, RA0 } },
4382 4600
4383{ "lbze", DEO(58,0), DE_MASK, BOOKE64, { RT, DE, RA } }, 4601{ "lbze", DEO(58,0), DE_MASK, BOOKE64, { RT, DE, RA0 } },
4384{ "lbzue", DEO(58,1), DE_MASK, BOOKE64, { RT, DE, RAL } }, 4602{ "lbzue", DEO(58,1), DE_MASK, BOOKE64, { RT, DE, RAL } },
4385{ "lhze", DEO(58,2), DE_MASK, BOOKE64, { RT, DE, RA } }, 4603{ "lhze", DEO(58,2), DE_MASK, BOOKE64, { RT, DE, RA0 } },
4386{ "lhzue", DEO(58,3), DE_MASK, BOOKE64, { RT, DE, RAL } }, 4604{ "lhzue", DEO(58,3), DE_MASK, BOOKE64, { RT, DE, RAL } },
4387{ "lhae", DEO(58,4), DE_MASK, BOOKE64, { RT, DE, RA } }, 4605{ "lhae", DEO(58,4), DE_MASK, BOOKE64, { RT, DE, RA0 } },
4388{ "lhaue", DEO(58,5), DE_MASK, BOOKE64, { RT, DE, RAL } }, 4606{ "lhaue", DEO(58,5), DE_MASK, BOOKE64, { RT, DE, RAL } },
4389{ "lwze", DEO(58,6), DE_MASK, BOOKE64, { RT, DE, RA } }, 4607{ "lwze", DEO(58,6), DE_MASK, BOOKE64, { RT, DE, RA0 } },
4390{ "lwzue", DEO(58,7), DE_MASK, BOOKE64, { RT, DE, RAL } }, 4608{ "lwzue", DEO(58,7), DE_MASK, BOOKE64, { RT, DE, RAL } },
4391{ "stbe", DEO(58,8), DE_MASK, BOOKE64, { RS, DE, RA } }, 4609{ "stbe", DEO(58,8), DE_MASK, BOOKE64, { RS, DE, RA0 } },
4392{ "stbue", DEO(58,9), DE_MASK, BOOKE64, { RS, DE, RAS } }, 4610{ "stbue", DEO(58,9), DE_MASK, BOOKE64, { RS, DE, RAS } },
4393{ "sthe", DEO(58,10), DE_MASK, BOOKE64, { RS, DE, RA } }, 4611{ "sthe", DEO(58,10), DE_MASK, BOOKE64, { RS, DE, RA0 } },
4394{ "sthue", DEO(58,11), DE_MASK, BOOKE64, { RS, DE, RAS } }, 4612{ "sthue", DEO(58,11), DE_MASK, BOOKE64, { RS, DE, RAS } },
4395{ "stwe", DEO(58,14), DE_MASK, BOOKE64, { RS, DE, RA } }, 4613{ "stwe", DEO(58,14), DE_MASK, BOOKE64, { RS, DE, RA0 } },
4396{ "stwue", DEO(58,15), DE_MASK, BOOKE64, { RS, DE, RAS } }, 4614{ "stwue", DEO(58,15), DE_MASK, BOOKE64, { RS, DE, RAS } },
4397 4615
4398{ "ld", DSO(58,0), DS_MASK, PPC64, { RT, DS, RA } }, 4616{ "ld", DSO(58,0), DS_MASK, PPC64, { RT, DS, RA0 } },
4399 4617
4400{ "ldu", DSO(58,1), DS_MASK, PPC64, { RT, DS, RAL } }, 4618{ "ldu", DSO(58,1), DS_MASK, PPC64, { RT, DS, RAL } },
4401 4619
4402{ "lwa", DSO(58,2), DS_MASK, PPC64, { RT, DS, RA } }, 4620{ "lwa", DSO(58,2), DS_MASK, PPC64, { RT, DS, RA0 } },
4621
4622{ "dadd", XRC(59,2,0), X_MASK, POWER6, { FRT, FRA, FRB } },
4623{ "dadd.", XRC(59,2,1), X_MASK, POWER6, { FRT, FRA, FRB } },
4624
4625{ "dqua", ZRC(59,3,0), Z_MASK, POWER6, { FRT, FRA, FRB, RMC } },
4626{ "dqua.", ZRC(59,3,1), Z_MASK, POWER6, { FRT, FRA, FRB, RMC } },
4403 4627
4404{ "fdivs", A(59,18,0), AFRC_MASK, PPC, { FRT, FRA, FRB } }, 4628{ "fdivs", A(59,18,0), AFRC_MASK, PPC, { FRT, FRA, FRB } },
4405{ "fdivs.", A(59,18,1), AFRC_MASK, PPC, { FRT, FRA, FRB } }, 4629{ "fdivs.", A(59,18,1), AFRC_MASK, PPC, { FRT, FRA, FRB } },
@@ -4413,12 +4637,15 @@ const struct powerpc_opcode powerpc_opcodes[] = {
4413{ "fsqrts", A(59,22,0), AFRAFRC_MASK, PPC, { FRT, FRB } }, 4637{ "fsqrts", A(59,22,0), AFRAFRC_MASK, PPC, { FRT, FRB } },
4414{ "fsqrts.", A(59,22,1), AFRAFRC_MASK, PPC, { FRT, FRB } }, 4638{ "fsqrts.", A(59,22,1), AFRAFRC_MASK, PPC, { FRT, FRB } },
4415 4639
4416{ "fres", A(59,24,0), AFRAFRC_MASK, PPC, { FRT, FRB } }, 4640{ "fres", A(59,24,0), AFRALFRC_MASK, PPC, { FRT, FRB, A_L } },
4417{ "fres.", A(59,24,1), AFRAFRC_MASK, PPC, { FRT, FRB } }, 4641{ "fres.", A(59,24,1), AFRALFRC_MASK, PPC, { FRT, FRB, A_L } },
4418 4642
4419{ "fmuls", A(59,25,0), AFRB_MASK, PPC, { FRT, FRA, FRC } }, 4643{ "fmuls", A(59,25,0), AFRB_MASK, PPC, { FRT, FRA, FRC } },
4420{ "fmuls.", A(59,25,1), AFRB_MASK, PPC, { FRT, FRA, FRC } }, 4644{ "fmuls.", A(59,25,1), AFRB_MASK, PPC, { FRT, FRA, FRC } },
4421 4645
4646{ "frsqrtes", A(59,26,0), AFRALFRC_MASK,POWER5, { FRT, FRB, A_L } },
4647{ "frsqrtes.",A(59,26,1), AFRALFRC_MASK,POWER5, { FRT, FRB, A_L } },
4648
4422{ "fmsubs", A(59,28,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } }, 4649{ "fmsubs", A(59,28,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4423{ "fmsubs.", A(59,28,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } }, 4650{ "fmsubs.", A(59,28,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4424 4651
@@ -4431,31 +4658,103 @@ const struct powerpc_opcode powerpc_opcodes[] = {
4431{ "fnmadds", A(59,31,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } }, 4658{ "fnmadds", A(59,31,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4432{ "fnmadds.",A(59,31,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } }, 4659{ "fnmadds.",A(59,31,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4433 4660
4661{ "dmul", XRC(59,34,0), X_MASK, POWER6, { FRT, FRA, FRB } },
4662{ "dmul.", XRC(59,34,1), X_MASK, POWER6, { FRT, FRA, FRB } },
4663
4664{ "drrnd", ZRC(59,35,0), Z_MASK, POWER6, { FRT, FRA, FRB, RMC } },
4665{ "drrnd.", ZRC(59,35,1), Z_MASK, POWER6, { FRT, FRA, FRB, RMC } },
4666
4667{ "dscli", ZRC(59,66,0), Z_MASK, POWER6, { FRT, FRA, SH16 } },
4668{ "dscli.", ZRC(59,66,1), Z_MASK, POWER6, { FRT, FRA, SH16 } },
4669
4670{ "dquai", ZRC(59,67,0), Z_MASK, POWER6, { TE, FRT, FRB, RMC } },
4671{ "dquai.", ZRC(59,67,1), Z_MASK, POWER6, { TE, FRT, FRB, RMC } },
4672
4673{ "dscri", ZRC(59,98,0), Z_MASK, POWER6, { FRT, FRA, SH16 } },
4674{ "dscri.", ZRC(59,98,1), Z_MASK, POWER6, { FRT, FRA, SH16 } },
4675
4676{ "drintx", ZRC(59,99,0), Z_MASK, POWER6, { R, FRT, FRB, RMC } },
4677{ "drintx.", ZRC(59,99,1), Z_MASK, POWER6, { R, FRT, FRB, RMC } },
4678
4679{ "dcmpo", X(59,130), X_MASK, POWER6, { BF, FRA, FRB } },
4680
4681{ "dtstex", X(59,162), X_MASK, POWER6, { BF, FRA, FRB } },
4682{ "dtstdc", Z(59,194), Z_MASK, POWER6, { BF, FRA, DCM } },
4683{ "dtstdg", Z(59,226), Z_MASK, POWER6, { BF, FRA, DGM } },
4684
4685{ "drintn", ZRC(59,227,0), Z_MASK, POWER6, { R, FRT, FRB, RMC } },
4686{ "drintn.", ZRC(59,227,1), Z_MASK, POWER6, { R, FRT, FRB, RMC } },
4687
4688{ "dctdp", XRC(59,258,0), X_MASK, POWER6, { FRT, FRB } },
4689{ "dctdp.", XRC(59,258,1), X_MASK, POWER6, { FRT, FRB } },
4690
4691{ "dctfix", XRC(59,290,0), X_MASK, POWER6, { FRT, FRB } },
4692{ "dctfix.", XRC(59,290,1), X_MASK, POWER6, { FRT, FRB } },
4693
4694{ "ddedpd", XRC(59,322,0), X_MASK, POWER6, { SP, FRT, FRB } },
4695{ "ddedpd.", XRC(59,322,1), X_MASK, POWER6, { SP, FRT, FRB } },
4696
4697{ "dxex", XRC(59,354,0), X_MASK, POWER6, { FRT, FRB } },
4698{ "dxex.", XRC(59,354,1), X_MASK, POWER6, { FRT, FRB } },
4699
4700{ "dsub", XRC(59,514,0), X_MASK, POWER6, { FRT, FRA, FRB } },
4701{ "dsub.", XRC(59,514,1), X_MASK, POWER6, { FRT, FRA, FRB } },
4702
4703{ "ddiv", XRC(59,546,0), X_MASK, POWER6, { FRT, FRA, FRB } },
4704{ "ddiv.", XRC(59,546,1), X_MASK, POWER6, { FRT, FRA, FRB } },
4705
4706{ "dcmpu", X(59,642), X_MASK, POWER6, { BF, FRA, FRB } },
4707
4708{ "dtstsf", X(59,674), X_MASK, POWER6, { BF, FRA, FRB } },
4709
4710{ "drsp", XRC(59,770,0), X_MASK, POWER6, { FRT, FRB } },
4711{ "drsp.", XRC(59,770,1), X_MASK, POWER6, { FRT, FRB } },
4712
4713{ "dcffix", XRC(59,802,0), X_MASK, POWER6, { FRT, FRB } },
4714{ "dcffix.", XRC(59,802,1), X_MASK, POWER6, { FRT, FRB } },
4715
4716{ "denbcd", XRC(59,834,0), X_MASK, POWER6, { S, FRT, FRB } },
4717{ "denbcd.", XRC(59,834,1), X_MASK, POWER6, { S, FRT, FRB } },
4718
4719{ "diex", XRC(59,866,0), X_MASK, POWER6, { FRT, FRA, FRB } },
4720{ "diex.", XRC(59,866,1), X_MASK, POWER6, { FRT, FRA, FRB } },
4721
4434{ "stfq", OP(60), OP_MASK, POWER2, { FRS, D, RA } }, 4722{ "stfq", OP(60), OP_MASK, POWER2, { FRS, D, RA } },
4435 4723
4436{ "stfqu", OP(61), OP_MASK, POWER2, { FRS, D, RA } }, 4724{ "stfqu", OP(61), OP_MASK, POWER2, { FRS, D, RA } },
4437 4725
4438{ "lde", DEO(62,0), DE_MASK, BOOKE64, { RT, DES, RA } }, 4726{ "stfdp", OP(61), OP_MASK, POWER6, { FRT, D, RA0 } },
4439{ "ldue", DEO(62,1), DE_MASK, BOOKE64, { RT, DES, RA } }, 4727
4440{ "lfse", DEO(62,4), DE_MASK, BOOKE64, { FRT, DES, RA } }, 4728{ "lde", DEO(62,0), DE_MASK, BOOKE64, { RT, DES, RA0 } },
4729{ "ldue", DEO(62,1), DE_MASK, BOOKE64, { RT, DES, RA0 } },
4730{ "lfse", DEO(62,4), DE_MASK, BOOKE64, { FRT, DES, RA0 } },
4441{ "lfsue", DEO(62,5), DE_MASK, BOOKE64, { FRT, DES, RAS } }, 4731{ "lfsue", DEO(62,5), DE_MASK, BOOKE64, { FRT, DES, RAS } },
4442{ "lfde", DEO(62,6), DE_MASK, BOOKE64, { FRT, DES, RA } }, 4732{ "lfde", DEO(62,6), DE_MASK, BOOKE64, { FRT, DES, RA0 } },
4443{ "lfdue", DEO(62,7), DE_MASK, BOOKE64, { FRT, DES, RAS } }, 4733{ "lfdue", DEO(62,7), DE_MASK, BOOKE64, { FRT, DES, RAS } },
4444{ "stde", DEO(62,8), DE_MASK, BOOKE64, { RS, DES, RA } }, 4734{ "stde", DEO(62,8), DE_MASK, BOOKE64, { RS, DES, RA0 } },
4445{ "stdue", DEO(62,9), DE_MASK, BOOKE64, { RS, DES, RAS } }, 4735{ "stdue", DEO(62,9), DE_MASK, BOOKE64, { RS, DES, RAS } },
4446{ "stfse", DEO(62,12), DE_MASK, BOOKE64, { FRS, DES, RA } }, 4736{ "stfse", DEO(62,12), DE_MASK, BOOKE64, { FRS, DES, RA0 } },
4447{ "stfsue", DEO(62,13), DE_MASK, BOOKE64, { FRS, DES, RAS } }, 4737{ "stfsue", DEO(62,13), DE_MASK, BOOKE64, { FRS, DES, RAS } },
4448{ "stfde", DEO(62,14), DE_MASK, BOOKE64, { FRS, DES, RA } }, 4738{ "stfde", DEO(62,14), DE_MASK, BOOKE64, { FRS, DES, RA0 } },
4449{ "stfdue", DEO(62,15), DE_MASK, BOOKE64, { FRS, DES, RAS } }, 4739{ "stfdue", DEO(62,15), DE_MASK, BOOKE64, { FRS, DES, RAS } },
4450 4740
4451{ "std", DSO(62,0), DS_MASK, PPC64, { RS, DS, RA } }, 4741{ "std", DSO(62,0), DS_MASK, PPC64, { RS, DS, RA0 } },
4452 4742
4453{ "stdu", DSO(62,1), DS_MASK, PPC64, { RS, DS, RAS } }, 4743{ "stdu", DSO(62,1), DS_MASK, PPC64, { RS, DS, RAS } },
4454 4744
4455{ "stq", DSO(62,2), DS_MASK, POWER4, { RSQ, DS, RA } }, 4745{ "stq", DSO(62,2), DS_MASK, POWER4, { RSQ, DS, RA0 } },
4456 4746
4457{ "fcmpu", X(63,0), X_MASK|(3<<21), COM, { BF, FRA, FRB } }, 4747{ "fcmpu", X(63,0), X_MASK|(3<<21), COM, { BF, FRA, FRB } },
4458 4748
4749{ "daddq", XRC(63,2,0), X_MASK, POWER6, { FRT, FRA, FRB } },
4750{ "daddq.", XRC(63,2,1), X_MASK, POWER6, { FRT, FRA, FRB } },
4751
4752{ "dquaq", ZRC(63,3,0), Z_MASK, POWER6, { FRT, FRA, FRB, RMC } },
4753{ "dquaq.", ZRC(63,3,1), Z_MASK, POWER6, { FRT, FRA, FRB, RMC } },
4754
4755{ "fcpsgn", XRC(63,8,0), X_MASK, POWER6, { FRT, FRA, FRB } },
4756{ "fcpsgn.", XRC(63,8,1), X_MASK, POWER6, { FRT, FRA, FRB } },
4757
4459{ "frsp", XRC(63,12,0), XRA_MASK, COM, { FRT, FRB } }, 4758{ "frsp", XRC(63,12,0), XRA_MASK, COM, { FRT, FRB } },
4460{ "frsp.", XRC(63,12,1), XRA_MASK, COM, { FRT, FRB } }, 4759{ "frsp.", XRC(63,12,1), XRA_MASK, COM, { FRT, FRB } },
4461 4760
@@ -4490,13 +4789,16 @@ const struct powerpc_opcode powerpc_opcodes[] = {
4490{ "fsel", A(63,23,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } }, 4789{ "fsel", A(63,23,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4491{ "fsel.", A(63,23,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } }, 4790{ "fsel.", A(63,23,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4492 4791
4792{ "fre", A(63,24,0), AFRALFRC_MASK, POWER5, { FRT, FRB, A_L } },
4793{ "fre.", A(63,24,1), AFRALFRC_MASK, POWER5, { FRT, FRB, A_L } },
4794
4493{ "fmul", A(63,25,0), AFRB_MASK, PPCCOM, { FRT, FRA, FRC } }, 4795{ "fmul", A(63,25,0), AFRB_MASK, PPCCOM, { FRT, FRA, FRC } },
4494{ "fm", A(63,25,0), AFRB_MASK, PWRCOM, { FRT, FRA, FRC } }, 4796{ "fm", A(63,25,0), AFRB_MASK, PWRCOM, { FRT, FRA, FRC } },
4495{ "fmul.", A(63,25,1), AFRB_MASK, PPCCOM, { FRT, FRA, FRC } }, 4797{ "fmul.", A(63,25,1), AFRB_MASK, PPCCOM, { FRT, FRA, FRC } },
4496{ "fm.", A(63,25,1), AFRB_MASK, PWRCOM, { FRT, FRA, FRC } }, 4798{ "fm.", A(63,25,1), AFRB_MASK, PWRCOM, { FRT, FRA, FRC } },
4497 4799
4498{ "frsqrte", A(63,26,0), AFRAFRC_MASK, PPC, { FRT, FRB } }, 4800{ "frsqrte", A(63,26,0), AFRALFRC_MASK, PPC, { FRT, FRB, A_L } },
4499{ "frsqrte.",A(63,26,1), AFRAFRC_MASK, PPC, { FRT, FRB } }, 4801{ "frsqrte.",A(63,26,1), AFRALFRC_MASK, PPC, { FRT, FRB, A_L } },
4500 4802
4501{ "fmsub", A(63,28,0), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } }, 4803{ "fmsub", A(63,28,0), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
4502{ "fms", A(63,28,0), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } }, 4804{ "fms", A(63,28,0), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
@@ -4520,6 +4822,12 @@ const struct powerpc_opcode powerpc_opcodes[] = {
4520 4822
4521{ "fcmpo", X(63,32), X_MASK|(3<<21), COM, { BF, FRA, FRB } }, 4823{ "fcmpo", X(63,32), X_MASK|(3<<21), COM, { BF, FRA, FRB } },
4522 4824
4825{ "dmulq", XRC(63,34,0), X_MASK, POWER6, { FRT, FRA, FRB } },
4826{ "dmulq.", XRC(63,34,1), X_MASK, POWER6, { FRT, FRA, FRB } },
4827
4828{ "drrndq", ZRC(63,35,0), Z_MASK, POWER6, { FRT, FRA, FRB, RMC } },
4829{ "drrndq.", ZRC(63,35,1), Z_MASK, POWER6, { FRT, FRA, FRB, RMC } },
4830
4523{ "mtfsb1", XRC(63,38,0), XRARB_MASK, COM, { BT } }, 4831{ "mtfsb1", XRC(63,38,0), XRARB_MASK, COM, { BT } },
4524{ "mtfsb1.", XRC(63,38,1), XRARB_MASK, COM, { BT } }, 4832{ "mtfsb1.", XRC(63,38,1), XRARB_MASK, COM, { BT } },
4525 4833
@@ -4528,36 +4836,100 @@ const struct powerpc_opcode powerpc_opcodes[] = {
4528 4836
4529{ "mcrfs", X(63,64), XRB_MASK|(3<<21)|(3<<16), COM, { BF, BFA } }, 4837{ "mcrfs", X(63,64), XRB_MASK|(3<<21)|(3<<16), COM, { BF, BFA } },
4530 4838
4839{ "dscliq", ZRC(63,66,0), Z_MASK, POWER6, { FRT, FRA, SH16 } },
4840{ "dscliq.", ZRC(63,66,1), Z_MASK, POWER6, { FRT, FRA, SH16 } },
4841
4842{ "dquaiq", ZRC(63,67,0), Z_MASK, POWER6, { TE, FRT, FRB, RMC } },
4843{ "dquaiq.", ZRC(63,67,1), Z_MASK, POWER6, { FRT, FRA, FRB, RMC } },
4844
4531{ "mtfsb0", XRC(63,70,0), XRARB_MASK, COM, { BT } }, 4845{ "mtfsb0", XRC(63,70,0), XRARB_MASK, COM, { BT } },
4532{ "mtfsb0.", XRC(63,70,1), XRARB_MASK, COM, { BT } }, 4846{ "mtfsb0.", XRC(63,70,1), XRARB_MASK, COM, { BT } },
4533 4847
4534{ "fmr", XRC(63,72,0), XRA_MASK, COM, { FRT, FRB } }, 4848{ "fmr", XRC(63,72,0), XRA_MASK, COM, { FRT, FRB } },
4535{ "fmr.", XRC(63,72,1), XRA_MASK, COM, { FRT, FRB } }, 4849{ "fmr.", XRC(63,72,1), XRA_MASK, COM, { FRT, FRB } },
4536 4850
4851{ "dscriq", ZRC(63,98,0), Z_MASK, POWER6, { FRT, FRA, SH16 } },
4852{ "dscriq.", ZRC(63,98,1), Z_MASK, POWER6, { FRT, FRA, SH16 } },
4853
4854{ "drintxq", ZRC(63,99,0), Z_MASK, POWER6, { R, FRT, FRB, RMC } },
4855{ "drintxq.",ZRC(63,99,1), Z_MASK, POWER6, { R, FRT, FRB, RMC } },
4856
4857{ "dcmpoq", X(63,130), X_MASK, POWER6, { BF, FRA, FRB } },
4858
4537{ "mtfsfi", XRC(63,134,0), XRA_MASK|(3<<21)|(1<<11), COM, { BF, U } }, 4859{ "mtfsfi", XRC(63,134,0), XRA_MASK|(3<<21)|(1<<11), COM, { BF, U } },
4538{ "mtfsfi.", XRC(63,134,1), XRA_MASK|(3<<21)|(1<<11), COM, { BF, U } }, 4860{ "mtfsfi.", XRC(63,134,1), XRA_MASK|(3<<21)|(1<<11), COM, { BF, U } },
4539 4861
4540{ "fnabs", XRC(63,136,0), XRA_MASK, COM, { FRT, FRB } }, 4862{ "fnabs", XRC(63,136,0), XRA_MASK, COM, { FRT, FRB } },
4541{ "fnabs.", XRC(63,136,1), XRA_MASK, COM, { FRT, FRB } }, 4863{ "fnabs.", XRC(63,136,1), XRA_MASK, COM, { FRT, FRB } },
4542 4864
4865{ "dtstexq", X(63,162), X_MASK, POWER6, { BF, FRA, FRB } },
4866{ "dtstdcq", Z(63,194), Z_MASK, POWER6, { BF, FRA, DCM } },
4867{ "dtstdgq", Z(63,226), Z_MASK, POWER6, { BF, FRA, DGM } },
4868
4869{ "drintnq", ZRC(63,227,0), Z_MASK, POWER6, { R, FRT, FRB, RMC } },
4870{ "drintnq.",ZRC(63,227,1), Z_MASK, POWER6, { R, FRT, FRB, RMC } },
4871
4872{ "dctqpq", XRC(63,258,0), X_MASK, POWER6, { FRT, FRB } },
4873{ "dctqpq.", XRC(63,258,1), X_MASK, POWER6, { FRT, FRB } },
4874
4543{ "fabs", XRC(63,264,0), XRA_MASK, COM, { FRT, FRB } }, 4875{ "fabs", XRC(63,264,0), XRA_MASK, COM, { FRT, FRB } },
4544{ "fabs.", XRC(63,264,1), XRA_MASK, COM, { FRT, FRB } }, 4876{ "fabs.", XRC(63,264,1), XRA_MASK, COM, { FRT, FRB } },
4545 4877
4878{ "dctfixq", XRC(63,290,0), X_MASK, POWER6, { FRT, FRB } },
4879{ "dctfixq.",XRC(63,290,1), X_MASK, POWER6, { FRT, FRB } },
4880
4881{ "ddedpdq", XRC(63,322,0), X_MASK, POWER6, { SP, FRT, FRB } },
4882{ "ddedpdq.",XRC(63,322,1), X_MASK, POWER6, { SP, FRT, FRB } },
4883
4884{ "dxexq", XRC(63,354,0), X_MASK, POWER6, { FRT, FRB } },
4885{ "dxexq.", XRC(63,354,1), X_MASK, POWER6, { FRT, FRB } },
4886
4887{ "frin", XRC(63,392,0), XRA_MASK, POWER5, { FRT, FRB } },
4888{ "frin.", XRC(63,392,1), XRA_MASK, POWER5, { FRT, FRB } },
4889{ "friz", XRC(63,424,0), XRA_MASK, POWER5, { FRT, FRB } },
4890{ "friz.", XRC(63,424,1), XRA_MASK, POWER5, { FRT, FRB } },
4891{ "frip", XRC(63,456,0), XRA_MASK, POWER5, { FRT, FRB } },
4892{ "frip.", XRC(63,456,1), XRA_MASK, POWER5, { FRT, FRB } },
4893{ "frim", XRC(63,488,0), XRA_MASK, POWER5, { FRT, FRB } },
4894{ "frim.", XRC(63,488,1), XRA_MASK, POWER5, { FRT, FRB } },
4895
4896{ "dsubq", XRC(63,514,0), X_MASK, POWER6, { FRT, FRA, FRB } },
4897{ "dsubq.", XRC(63,514,1), X_MASK, POWER6, { FRT, FRA, FRB } },
4898
4899{ "ddivq", XRC(63,546,0), X_MASK, POWER6, { FRT, FRA, FRB } },
4900{ "ddivq.", XRC(63,546,1), X_MASK, POWER6, { FRT, FRA, FRB } },
4901
4546{ "mffs", XRC(63,583,0), XRARB_MASK, COM, { FRT } }, 4902{ "mffs", XRC(63,583,0), XRARB_MASK, COM, { FRT } },
4547{ "mffs.", XRC(63,583,1), XRARB_MASK, COM, { FRT } }, 4903{ "mffs.", XRC(63,583,1), XRARB_MASK, COM, { FRT } },
4548 4904
4905{ "dcmpuq", X(63,642), X_MASK, POWER6, { BF, FRA, FRB } },
4906
4907{ "dtstsfq", X(63,674), X_MASK, POWER6, { BF, FRA, FRB } },
4908
4549{ "mtfsf", XFL(63,711,0), XFL_MASK, COM, { FLM, FRB } }, 4909{ "mtfsf", XFL(63,711,0), XFL_MASK, COM, { FLM, FRB } },
4550{ "mtfsf.", XFL(63,711,1), XFL_MASK, COM, { FLM, FRB } }, 4910{ "mtfsf.", XFL(63,711,1), XFL_MASK, COM, { FLM, FRB } },
4551 4911
4912{ "drdpq", XRC(63,770,0), X_MASK, POWER6, { FRT, FRB } },
4913{ "drdpq.", XRC(63,770,1), X_MASK, POWER6, { FRT, FRB } },
4914
4915{ "dcffixq", XRC(63,802,0), X_MASK, POWER6, { FRT, FRB } },
4916{ "dcffixq.",XRC(63,802,1), X_MASK, POWER6, { FRT, FRB } },
4917
4552{ "fctid", XRC(63,814,0), XRA_MASK, PPC64, { FRT, FRB } }, 4918{ "fctid", XRC(63,814,0), XRA_MASK, PPC64, { FRT, FRB } },
4553{ "fctid.", XRC(63,814,1), XRA_MASK, PPC64, { FRT, FRB } }, 4919{ "fctid.", XRC(63,814,1), XRA_MASK, PPC64, { FRT, FRB } },
4554 4920
4555{ "fctidz", XRC(63,815,0), XRA_MASK, PPC64, { FRT, FRB } }, 4921{ "fctidz", XRC(63,815,0), XRA_MASK, PPC64, { FRT, FRB } },
4556{ "fctidz.", XRC(63,815,1), XRA_MASK, PPC64, { FRT, FRB } }, 4922{ "fctidz.", XRC(63,815,1), XRA_MASK, PPC64, { FRT, FRB } },
4557 4923
4924{ "denbcdq", XRC(63,834,0), X_MASK, POWER6, { S, FRT, FRB } },
4925{ "denbcdq.",XRC(63,834,1), X_MASK, POWER6, { S, FRT, FRB } },
4926
4558{ "fcfid", XRC(63,846,0), XRA_MASK, PPC64, { FRT, FRB } }, 4927{ "fcfid", XRC(63,846,0), XRA_MASK, PPC64, { FRT, FRB } },
4559{ "fcfid.", XRC(63,846,1), XRA_MASK, PPC64, { FRT, FRB } }, 4928{ "fcfid.", XRC(63,846,1), XRA_MASK, PPC64, { FRT, FRB } },
4560 4929
4930{ "diexq", XRC(63,866,0), X_MASK, POWER6, { FRT, FRA, FRB } },
4931{ "diexq.", XRC(63,866,1), X_MASK, POWER6, { FRT, FRA, FRB } },
4932
4561}; 4933};
4562 4934
4563const int powerpc_num_opcodes = 4935const int powerpc_num_opcodes =
diff --git a/arch/powerpc/xmon/ppc.h b/arch/powerpc/xmon/ppc.h
index 342237e8dd69..110df96354b4 100644
--- a/arch/powerpc/xmon/ppc.h
+++ b/arch/powerpc/xmon/ppc.h
@@ -1,5 +1,5 @@
1/* ppc.h -- Header file for PowerPC opcode table 1/* ppc.h -- Header file for PowerPC opcode table
2 Copyright 1994, 1995, 1999, 2000, 2001, 2002, 2003 2 Copyright 1994, 1995, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006
3 Free Software Foundation, Inc. 3 Free Software Foundation, Inc.
4 Written by Ian Lance Taylor, Cygnus Support 4 Written by Ian Lance Taylor, Cygnus Support
5 5
@@ -17,7 +17,7 @@ the GNU General Public License for more details.
17 17
18You should have received a copy of the GNU General Public License 18You should have received a copy of the GNU General Public License
19along with this file; see the file COPYING. If not, write to the Free 19along with this file; see the file COPYING. If not, write to the Free
20Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ 20Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
21 21
22#ifndef PPC_H 22#ifndef PPC_H
23#define PPC_H 23#define PPC_H
@@ -134,6 +134,18 @@ extern const int powerpc_num_opcodes;
134/* Opcode is supported by machine check APU. */ 134/* Opcode is supported by machine check APU. */
135#define PPC_OPCODE_RFMCI 0x800000 135#define PPC_OPCODE_RFMCI 0x800000
136 136
137/* Opcode is only supported by Power5 architecture. */
138#define PPC_OPCODE_POWER5 0x1000000
139
140/* Opcode is supported by PowerPC e300 family. */
141#define PPC_OPCODE_E300 0x2000000
142
143/* Opcode is only supported by Power6 architecture. */
144#define PPC_OPCODE_POWER6 0x4000000
145
146/* Opcode is only supported by PowerPC Cell family. */
147#define PPC_OPCODE_CELL 0x8000000
148
137/* A macro to extract the major opcode from an instruction. */ 149/* A macro to extract the major opcode from an instruction. */
138#define PPC_OP(i) (((i) >> 26) & 0x3f) 150#define PPC_OP(i) (((i) >> 26) & 0x3f)
139 151
@@ -233,25 +245,28 @@ extern const struct powerpc_operand powerpc_operands[];
233 register names with a leading 'r'. */ 245 register names with a leading 'r'. */
234#define PPC_OPERAND_GPR (040) 246#define PPC_OPERAND_GPR (040)
235 247
248/* Like PPC_OPERAND_GPR, but don't print a leading 'r' for r0. */
249#define PPC_OPERAND_GPR_0 (0100)
250
236/* This operand names a floating point register. The disassembler 251/* This operand names a floating point register. The disassembler
237 prints these with a leading 'f'. */ 252 prints these with a leading 'f'. */
238#define PPC_OPERAND_FPR (0100) 253#define PPC_OPERAND_FPR (0200)
239 254
240/* This operand is a relative branch displacement. The disassembler 255/* This operand is a relative branch displacement. The disassembler
241 prints these symbolically if possible. */ 256 prints these symbolically if possible. */
242#define PPC_OPERAND_RELATIVE (0200) 257#define PPC_OPERAND_RELATIVE (0400)
243 258
244/* This operand is an absolute branch address. The disassembler 259/* This operand is an absolute branch address. The disassembler
245 prints these symbolically if possible. */ 260 prints these symbolically if possible. */
246#define PPC_OPERAND_ABSOLUTE (0400) 261#define PPC_OPERAND_ABSOLUTE (01000)
247 262
248/* This operand is optional, and is zero if omitted. This is used for 263/* This operand is optional, and is zero if omitted. This is used for
249 the optional BF and L fields in the comparison instructions. The 264 example, in the optional BF field in the comparison instructions. The
250 assembler must count the number of operands remaining on the line, 265 assembler must count the number of operands remaining on the line,
251 and the number of operands remaining for the opcode, and decide 266 and the number of operands remaining for the opcode, and decide
252 whether this operand is present or not. The disassembler should 267 whether this operand is present or not. The disassembler should
253 print this operand out only if it is not zero. */ 268 print this operand out only if it is not zero. */
254#define PPC_OPERAND_OPTIONAL (01000) 269#define PPC_OPERAND_OPTIONAL (02000)
255 270
256/* This flag is only used with PPC_OPERAND_OPTIONAL. If this operand 271/* This flag is only used with PPC_OPERAND_OPTIONAL. If this operand
257 is omitted, then for the next operand use this operand value plus 272 is omitted, then for the next operand use this operand value plus
@@ -259,24 +274,24 @@ extern const struct powerpc_operand powerpc_operands[];
259 hack is needed because the Power rotate instructions can take 274 hack is needed because the Power rotate instructions can take
260 either 4 or 5 operands. The disassembler should print this operand 275 either 4 or 5 operands. The disassembler should print this operand
261 out regardless of the PPC_OPERAND_OPTIONAL field. */ 276 out regardless of the PPC_OPERAND_OPTIONAL field. */
262#define PPC_OPERAND_NEXT (02000) 277#define PPC_OPERAND_NEXT (04000)
263 278
264/* This operand should be regarded as a negative number for the 279/* This operand should be regarded as a negative number for the
265 purposes of overflow checking (i.e., the normal most negative 280 purposes of overflow checking (i.e., the normal most negative
266 number is disallowed and one more than the normal most positive 281 number is disallowed and one more than the normal most positive
267 number is allowed). This flag will only be set for a signed 282 number is allowed). This flag will only be set for a signed
268 operand. */ 283 operand. */
269#define PPC_OPERAND_NEGATIVE (04000) 284#define PPC_OPERAND_NEGATIVE (010000)
270 285
271/* This operand names a vector unit register. The disassembler 286/* This operand names a vector unit register. The disassembler
272 prints these with a leading 'v'. */ 287 prints these with a leading 'v'. */
273#define PPC_OPERAND_VR (010000) 288#define PPC_OPERAND_VR (020000)
274 289
275/* This operand is for the DS field in a DS form instruction. */ 290/* This operand is for the DS field in a DS form instruction. */
276#define PPC_OPERAND_DS (020000) 291#define PPC_OPERAND_DS (040000)
277 292
278/* This operand is for the DQ field in a DQ form instruction. */ 293/* This operand is for the DQ field in a DQ form instruction. */
279#define PPC_OPERAND_DQ (040000) 294#define PPC_OPERAND_DQ (0100000)
280 295
281/* The POWER and PowerPC assemblers use a few macros. We keep them 296/* The POWER and PowerPC assemblers use a few macros. We keep them
282 with the operands table for simplicity. The macro table is an 297 with the operands table for simplicity. The macro table is an
diff --git a/arch/powerpc/xmon/spu-dis.c b/arch/powerpc/xmon/spu-dis.c
new file mode 100644
index 000000000000..ee929c641bf3
--- /dev/null
+++ b/arch/powerpc/xmon/spu-dis.c
@@ -0,0 +1,248 @@
1/* Disassemble SPU instructions
2
3 Copyright 2006 Free Software Foundation, Inc.
4
5 This file is part of GDB, GAS, and the GNU binutils.
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License along
18 with this program; if not, write to the Free Software Foundation, Inc.,
19 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
20
21#include <linux/string.h>
22#include "nonstdio.h"
23#include "ansidecl.h"
24#include "spu.h"
25#include "dis-asm.h"
26
27/* This file provides a disassembler function which uses
28 the disassembler interface defined in dis-asm.h. */
29
30extern const struct spu_opcode spu_opcodes[];
31extern const int spu_num_opcodes;
32
33#define SPU_DISASM_TBL_SIZE (1 << 11)
34static const struct spu_opcode *spu_disassemble_table[SPU_DISASM_TBL_SIZE];
35
36static void
37init_spu_disassemble (void)
38{
39 int i;
40
41 /* If two instructions have the same opcode then we prefer the first
42 * one. In most cases it is just an alternate mnemonic. */
43 for (i = 0; i < spu_num_opcodes; i++)
44 {
45 int o = spu_opcodes[i].opcode;
46 if (o >= SPU_DISASM_TBL_SIZE)
47 continue; /* abort (); */
48 if (spu_disassemble_table[o] == 0)
49 spu_disassemble_table[o] = &spu_opcodes[i];
50 }
51}
52
53/* Determine the instruction from the 10 least significant bits. */
54static const struct spu_opcode *
55get_index_for_opcode (unsigned int insn)
56{
57 const struct spu_opcode *index;
58 unsigned int opcode = insn >> (32-11);
59
60 /* Init the table. This assumes that element 0/opcode 0 (currently
61 * NOP) is always used */
62 if (spu_disassemble_table[0] == 0)
63 init_spu_disassemble ();
64
65 if ((index = spu_disassemble_table[opcode & 0x780]) != 0
66 && index->insn_type == RRR)
67 return index;
68
69 if ((index = spu_disassemble_table[opcode & 0x7f0]) != 0
70 && (index->insn_type == RI18 || index->insn_type == LBT))
71 return index;
72
73 if ((index = spu_disassemble_table[opcode & 0x7f8]) != 0
74 && index->insn_type == RI10)
75 return index;
76
77 if ((index = spu_disassemble_table[opcode & 0x7fc]) != 0
78 && (index->insn_type == RI16))
79 return index;
80
81 if ((index = spu_disassemble_table[opcode & 0x7fe]) != 0
82 && (index->insn_type == RI8))
83 return index;
84
85 if ((index = spu_disassemble_table[opcode & 0x7ff]) != 0)
86 return index;
87
88 return 0;
89}
90
91/* Print a Spu instruction. */
92
93int
94print_insn_spu (unsigned long insn, unsigned long memaddr)
95{
96 int value;
97 int hex_value;
98 const struct spu_opcode *index;
99 enum spu_insns tag;
100
101 index = get_index_for_opcode (insn);
102
103 if (index == 0)
104 {
105 printf(".long 0x%x", insn);
106 }
107 else
108 {
109 int i;
110 int paren = 0;
111 tag = (enum spu_insns)(index - spu_opcodes);
112 printf("%s", index->mnemonic);
113 if (tag == M_BI || tag == M_BISL || tag == M_IRET || tag == M_BISLED
114 || tag == M_BIHNZ || tag == M_BIHZ || tag == M_BINZ || tag == M_BIZ
115 || tag == M_SYNC || tag == M_HBR)
116 {
117 int fb = (insn >> (32-18)) & 0x7f;
118 if (fb & 0x40)
119 printf(tag == M_SYNC ? "c" : "p");
120 if (fb & 0x20)
121 printf("d");
122 if (fb & 0x10)
123 printf("e");
124 }
125 if (index->arg[0] != 0)
126 printf("\t");
127 hex_value = 0;
128 for (i = 1; i <= index->arg[0]; i++)
129 {
130 int arg = index->arg[i];
131 if (arg != A_P && !paren && i > 1)
132 printf(",");
133
134 switch (arg)
135 {
136 case A_T:
137 printf("$%d",
138 DECODE_INSN_RT (insn));
139 break;
140 case A_A:
141 printf("$%d",
142 DECODE_INSN_RA (insn));
143 break;
144 case A_B:
145 printf("$%d",
146 DECODE_INSN_RB (insn));
147 break;
148 case A_C:
149 printf("$%d",
150 DECODE_INSN_RC (insn));
151 break;
152 case A_S:
153 printf("$sp%d",
154 DECODE_INSN_RA (insn));
155 break;
156 case A_H:
157 printf("$ch%d",
158 DECODE_INSN_RA (insn));
159 break;
160 case A_P:
161 paren++;
162 printf("(");
163 break;
164 case A_U7A:
165 printf("%d",
166 173 - DECODE_INSN_U8 (insn));
167 break;
168 case A_U7B:
169 printf("%d",
170 155 - DECODE_INSN_U8 (insn));
171 break;
172 case A_S3:
173 case A_S6:
174 case A_S7:
175 case A_S7N:
176 case A_U3:
177 case A_U5:
178 case A_U6:
179 case A_U7:
180 hex_value = DECODE_INSN_I7 (insn);
181 printf("%d", hex_value);
182 break;
183 case A_S11:
184 print_address(memaddr + DECODE_INSN_I9a (insn) * 4);
185 break;
186 case A_S11I:
187 print_address(memaddr + DECODE_INSN_I9b (insn) * 4);
188 break;
189 case A_S10:
190 case A_S10B:
191 hex_value = DECODE_INSN_I10 (insn);
192 printf("%d", hex_value);
193 break;
194 case A_S14:
195 hex_value = DECODE_INSN_I10 (insn) * 16;
196 printf("%d", hex_value);
197 break;
198 case A_S16:
199 hex_value = DECODE_INSN_I16 (insn);
200 printf("%d", hex_value);
201 break;
202 case A_X16:
203 hex_value = DECODE_INSN_U16 (insn);
204 printf("%u", hex_value);
205 break;
206 case A_R18:
207 value = DECODE_INSN_I16 (insn) * 4;
208 if (value == 0)
209 printf("%d", value);
210 else
211 {
212 hex_value = memaddr + value;
213 print_address(hex_value & 0x3ffff);
214 }
215 break;
216 case A_S18:
217 value = DECODE_INSN_U16 (insn) * 4;
218 if (value == 0)
219 printf("%d", value);
220 else
221 print_address(value);
222 break;
223 case A_U18:
224 value = DECODE_INSN_U18 (insn);
225 if (value == 0 || 1)
226 {
227 hex_value = value;
228 printf("%u", value);
229 }
230 else
231 print_address(value);
232 break;
233 case A_U14:
234 hex_value = DECODE_INSN_U14 (insn);
235 printf("%u", hex_value);
236 break;
237 }
238 if (arg != A_P && paren)
239 {
240 printf(")");
241 paren--;
242 }
243 }
244 if (hex_value > 16)
245 printf("\t# %x", hex_value);
246 }
247 return 4;
248}
diff --git a/arch/powerpc/xmon/spu-insns.h b/arch/powerpc/xmon/spu-insns.h
new file mode 100644
index 000000000000..99dc452821ac
--- /dev/null
+++ b/arch/powerpc/xmon/spu-insns.h
@@ -0,0 +1,410 @@
1/* SPU ELF support for BFD.
2
3 Copyright 2006 Free Software Foundation, Inc.
4
5 This file is part of BFD, the Binary File Descriptor library.
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software Foundation,
19 Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
20
21/* SPU Opcode Table
22
23-=-=-= FORMAT =-=-=-
24
25 +----+-------+-------+-------+-------+ +------------+-------+-------+-------+
26RRR | op | RC | RB | RA | RT | RI7 | op | I7 | RA | RT |
27 +----+-------+-------+-------+-------+ +------------+-------+-------+-------+
28 0 3 1 1 2 3 0 1 1 2 3
29 0 7 4 1 0 7 4 1
30
31 +-----------+--------+-------+-------+ +---------+----------+-------+-------+
32RI8 | op | I8 | RA | RT | RI10 | op | I10 | RA | RT |
33 +-----------+--------+-------+-------+ +---------+----------+-------+-------+
34 0 9 1 2 3 0 7 1 2 3
35 7 4 1 7 4 1
36
37 +----------+-----------------+-------+ +--------+-------------------+-------+
38RI16 | op | I16 | RT | RI18 | op | I18 | RT |
39 +----------+-----------------+-------+ +--------+-------------------+-------+
40 0 8 2 3 0 6 2 3
41 4 1 4 1
42
43 +------------+-------+-------+-------+ +-------+--+-----------------+-------+
44RR | op | RB | RA | RT | LBT | op |RO| I16 | RO |
45 +------------+-------+-------+-------+ +-------+--+-----------------+-------+
46 0 1 1 2 3 0 6 8 2 3
47 0 7 4 1 4 1
48
49 +------------+----+--+-------+-------+
50 LBTI | op | // |RO| RA | RO |
51 +------------+----+--+-------+-------+
52 0 1 1 1 2 3
53 0 5 7 4 1
54
55-=-=-= OPCODE =-=-=-
56
57OPCODE field specifies the most significant 11bit of the instruction. Some formats don't have 11bits for opcode field, and in this
58case, bit field other than op are defined as 0s. For example, opcode of fma instruction which is RRR format is defined as 0x700,
59since 0x700 -> 11'b11100000000, this means opcode is 4'b1110, and other 7bits are defined as 7'b0000000.
60
61-=-=-= ASM_FORMAT =-=-=-
62
63RRR category RI7 category
64 ASM_RRR mnemonic RC, RA, RB, RT ASM_RI4 mnemonic RT, RA, I4
65 ASM_RI7 mnemonic RT, RA, I7
66
67RI8 category RI10 category
68 ASM_RUI8 mnemonic RT, RA, UI8 ASM_AI10 mnemonic RA, I10
69 ASM_RI10 mnemonic RT, RA, R10
70 ASM_RI10IDX mnemonic RT, I10(RA)
71
72RI16 category RI18 category
73 ASM_I16W mnemonic I16W ASM_RI18 mnemonic RT, I18
74 ASM_RI16 mnemonic RT, I16
75 ASM_RI16W mnemonic RT, I16W
76
77RR category LBT category
78 ASM_MFSPR mnemonic RT, SA ASM_LBT mnemonic brinst, brtarg
79 ASM_MTSPR mnemonic SA, RT
80 ASM_NOOP mnemonic LBTI category
81 ASM_RA mnemonic RA ASM_LBTI mnemonic brinst, RA
82 ASM_RAB mnemonic RA, RB
83 ASM_RDCH mnemonic RT, CA
84 ASM_RR mnemonic RT, RA, RB
85 ASM_RT mnemonic RT
86 ASM_RTA mnemonic RT, RA
87 ASM_WRCH mnemonic CA, RT
88
89Note that RRR instructions have the names for RC and RT reversed from
90what's in the ISA, in order to put RT in the same position it appears
91for other formats.
92
93-=-=-= DEPENDENCY =-=-=-
94
95DEPENDENCY filed consists of 5 digits. This represents which register is used as source and which register is used as target.
96The first(most significant) digit is always 0. Then it is followd by RC, RB, RA and RT digits.
97If the digit is 0, this means the corresponding register is not used in the instruction.
98If the digit is 1, this means the corresponding register is used as a source in the instruction.
99If the digit is 2, this means the corresponding register is used as a target in the instruction.
100If the digit is 3, this means the corresponding register is used as both source and target in the instruction.
101For example, fms instruction has 00113 as the DEPENDENCY field. This means RC is not used in this operation, RB and RA are
102used as sources and RT is the target.
103
104-=-=-= PIPE =-=-=-
105
106This field shows which execution pipe is used for the instruction
107
108pipe0 execution pipelines:
109 FP6 SP floating pipeline
110 FP7 integer operations executed in SP floating pipeline
111 FPD DP floating pipeline
112 FX2 FXU pipeline
113 FX3 Rotate/Shift pipeline
114 FXB Byte pipeline
115 NOP No pipeline
116
117pipe1 execution pipelines:
118 BR Branch pipeline
119 LNOP No pipeline
120 LS Load/Store pipeline
121 SHUF Shuffle pipeline
122 SPR SPR/CH pipeline
123
124*/
125
126#define _A0() {0}
127#define _A1(a) {1,a}
128#define _A2(a,b) {2,a,b}
129#define _A3(a,b,c) {3,a,b,c}
130#define _A4(a,b,c,d) {4,a,b,c,d}
131
132/* TAG FORMAT OPCODE MNEMONIC ASM_FORMAT DEPENDENCY PIPE COMMENT */
133/* 0[RC][RB][RA][RT] */
134/* 1:src, 2:target */
135
136APUOP(M_BR, RI16, 0x190, "br", _A1(A_R18), 00000, BR) /* BRel IP<-IP+I16 */
137APUOP(M_BRSL, RI16, 0x198, "brsl", _A2(A_T,A_R18), 00002, BR) /* BRelSetLink RT,IP<-IP,IP+I16 */
138APUOP(M_BRA, RI16, 0x180, "bra", _A1(A_S18), 00000, BR) /* BRAbs IP<-I16 */
139APUOP(M_BRASL, RI16, 0x188, "brasl", _A2(A_T,A_S18), 00002, BR) /* BRAbsSetLink RT,IP<-IP,I16 */
140APUOP(M_FSMBI, RI16, 0x194, "fsmbi", _A2(A_T,A_X16), 00002, SHUF) /* FormSelMask%I RT<-fsm(I16) */
141APUOP(M_LQA, RI16, 0x184, "lqa", _A2(A_T,A_S18), 00002, LS) /* LoadQAbs RT<-M[I16] */
142APUOP(M_LQR, RI16, 0x19C, "lqr", _A2(A_T,A_R18), 00002, LS) /* LoadQRel RT<-M[IP+I16] */
143APUOP(M_STOP, RR, 0x000, "stop", _A0(), 00000, BR) /* STOP stop */
144APUOP(M_STOP2, RR, 0x000, "stop", _A1(A_U14), 00000, BR) /* STOP stop */
145APUOP(M_STOPD, RR, 0x140, "stopd", _A3(A_T,A_A,A_B), 00111, BR) /* STOPD stop (with register dependencies) */
146APUOP(M_LNOP, RR, 0x001, "lnop", _A0(), 00000, LNOP) /* LNOP no_operation */
147APUOP(M_SYNC, RR, 0x002, "sync", _A0(), 00000, BR) /* SYNC flush_pipe */
148APUOP(M_DSYNC, RR, 0x003, "dsync", _A0(), 00000, BR) /* DSYNC flush_store_queue */
149APUOP(M_MFSPR, RR, 0x00c, "mfspr", _A2(A_T,A_S), 00002, SPR) /* MFSPR RT<-SA */
150APUOP(M_RDCH, RR, 0x00d, "rdch", _A2(A_T,A_H), 00002, SPR) /* ReaDCHannel RT<-CA:data */
151APUOP(M_RCHCNT, RR, 0x00f, "rchcnt", _A2(A_T,A_H), 00002, SPR) /* ReaDCHanCouNT RT<-CA:count */
152APUOP(M_HBRA, LBT, 0x080, "hbra", _A2(A_S11,A_S18), 00000, LS) /* HBRA BTB[B9]<-M[I16] */
153APUOP(M_HBRR, LBT, 0x090, "hbrr", _A2(A_S11,A_R18), 00000, LS) /* HBRR BTB[B9]<-M[IP+I16] */
154APUOP(M_BRZ, RI16, 0x100, "brz", _A2(A_T,A_R18), 00001, BR) /* BRZ IP<-IP+I16_if(RT) */
155APUOP(M_BRNZ, RI16, 0x108, "brnz", _A2(A_T,A_R18), 00001, BR) /* BRNZ IP<-IP+I16_if(RT) */
156APUOP(M_BRHZ, RI16, 0x110, "brhz", _A2(A_T,A_R18), 00001, BR) /* BRHZ IP<-IP+I16_if(RT) */
157APUOP(M_BRHNZ, RI16, 0x118, "brhnz", _A2(A_T,A_R18), 00001, BR) /* BRHNZ IP<-IP+I16_if(RT) */
158APUOP(M_STQA, RI16, 0x104, "stqa", _A2(A_T,A_S18), 00001, LS) /* SToreQAbs M[I16]<-RT */
159APUOP(M_STQR, RI16, 0x11C, "stqr", _A2(A_T,A_R18), 00001, LS) /* SToreQRel M[IP+I16]<-RT */
160APUOP(M_MTSPR, RR, 0x10c, "mtspr", _A2(A_S,A_T), 00001, SPR) /* MTSPR SA<-RT */
161APUOP(M_WRCH, RR, 0x10d, "wrch", _A2(A_H,A_T), 00001, SPR) /* ChanWRite CA<-RT */
162APUOP(M_LQD, RI10, 0x1a0, "lqd", _A4(A_T,A_S14,A_P,A_A), 00012, LS) /* LoadQDisp RT<-M[Ra+I10] */
163APUOP(M_BI, RR, 0x1a8, "bi", _A1(A_A), 00010, BR) /* BI IP<-RA */
164APUOP(M_BISL, RR, 0x1a9, "bisl", _A2(A_T,A_A), 00012, BR) /* BISL RT,IP<-IP,RA */
165APUOP(M_IRET, RR, 0x1aa, "iret", _A1(A_A), 00010, BR) /* IRET IP<-SRR0 */
166APUOP(M_IRET2, RR, 0x1aa, "iret", _A0(), 00010, BR) /* IRET IP<-SRR0 */
167APUOP(M_BISLED, RR, 0x1ab, "bisled", _A2(A_T,A_A), 00012, BR) /* BISLED RT,IP<-IP,RA_if(ext) */
168APUOP(M_HBR, LBTI, 0x1ac, "hbr", _A2(A_S11I,A_A), 00010, LS) /* HBR BTB[B9]<-M[Ra] */
169APUOP(M_FREST, RR, 0x1b8, "frest", _A2(A_T,A_A), 00012, SHUF) /* FREST RT<-recip(RA) */
170APUOP(M_FRSQEST, RR, 0x1b9, "frsqest", _A2(A_T,A_A), 00012, SHUF) /* FRSQEST RT<-rsqrt(RA) */
171APUOP(M_FSM, RR, 0x1b4, "fsm", _A2(A_T,A_A), 00012, SHUF) /* FormSelMask% RT<-expand(Ra) */
172APUOP(M_FSMH, RR, 0x1b5, "fsmh", _A2(A_T,A_A), 00012, SHUF) /* FormSelMask% RT<-expand(Ra) */
173APUOP(M_FSMB, RR, 0x1b6, "fsmb", _A2(A_T,A_A), 00012, SHUF) /* FormSelMask% RT<-expand(Ra) */
174APUOP(M_GB, RR, 0x1b0, "gb", _A2(A_T,A_A), 00012, SHUF) /* GatherBits% RT<-gather(RA) */
175APUOP(M_GBH, RR, 0x1b1, "gbh", _A2(A_T,A_A), 00012, SHUF) /* GatherBits% RT<-gather(RA) */
176APUOP(M_GBB, RR, 0x1b2, "gbb", _A2(A_T,A_A), 00012, SHUF) /* GatherBits% RT<-gather(RA) */
177APUOP(M_CBD, RI7, 0x1f4, "cbd", _A4(A_T,A_U7,A_P,A_A), 00012, SHUF) /* genCtl%%insD RT<-sta(Ra+I4,siz) */
178APUOP(M_CHD, RI7, 0x1f5, "chd", _A4(A_T,A_U7,A_P,A_A), 00012, SHUF) /* genCtl%%insD RT<-sta(Ra+I4,siz) */
179APUOP(M_CWD, RI7, 0x1f6, "cwd", _A4(A_T,A_U7,A_P,A_A), 00012, SHUF) /* genCtl%%insD RT<-sta(Ra+I4,siz) */
180APUOP(M_CDD, RI7, 0x1f7, "cdd", _A4(A_T,A_U7,A_P,A_A), 00012, SHUF) /* genCtl%%insD RT<-sta(Ra+I4,siz) */
181APUOP(M_ROTQBII, RI7, 0x1f8, "rotqbii", _A3(A_T,A_A,A_U3), 00012, SHUF) /* ROTQBII RT<-RA<<<I7 */
182APUOP(M_ROTQBYI, RI7, 0x1fc, "rotqbyi", _A3(A_T,A_A,A_S7N), 00012, SHUF) /* ROTQBYI RT<-RA<<<(I7*8) */
183APUOP(M_ROTQMBII, RI7, 0x1f9, "rotqmbii", _A3(A_T,A_A,A_S3), 00012, SHUF) /* ROTQMBII RT<-RA<<I7 */
184APUOP(M_ROTQMBYI, RI7, 0x1fd, "rotqmbyi", _A3(A_T,A_A,A_S6), 00012, SHUF) /* ROTQMBYI RT<-RA<<I7 */
185APUOP(M_SHLQBII, RI7, 0x1fb, "shlqbii", _A3(A_T,A_A,A_U3), 00012, SHUF) /* SHLQBII RT<-RA<<I7 */
186APUOP(M_SHLQBYI, RI7, 0x1ff, "shlqbyi", _A3(A_T,A_A,A_U5), 00012, SHUF) /* SHLQBYI RT<-RA<<I7 */
187APUOP(M_STQD, RI10, 0x120, "stqd", _A4(A_T,A_S14,A_P,A_A), 00011, LS) /* SToreQDisp M[Ra+I10]<-RT */
188APUOP(M_BIHNZ, RR, 0x12b, "bihnz", _A2(A_T,A_A), 00011, BR) /* BIHNZ IP<-RA_if(RT) */
189APUOP(M_BIHZ, RR, 0x12a, "bihz", _A2(A_T,A_A), 00011, BR) /* BIHZ IP<-RA_if(RT) */
190APUOP(M_BINZ, RR, 0x129, "binz", _A2(A_T,A_A), 00011, BR) /* BINZ IP<-RA_if(RT) */
191APUOP(M_BIZ, RR, 0x128, "biz", _A2(A_T,A_A), 00011, BR) /* BIZ IP<-RA_if(RT) */
192APUOP(M_CBX, RR, 0x1d4, "cbx", _A3(A_T,A_A,A_B), 00112, SHUF) /* genCtl%%insX RT<-sta(Ra+Rb,siz) */
193APUOP(M_CHX, RR, 0x1d5, "chx", _A3(A_T,A_A,A_B), 00112, SHUF) /* genCtl%%insX RT<-sta(Ra+Rb,siz) */
194APUOP(M_CWX, RR, 0x1d6, "cwx", _A3(A_T,A_A,A_B), 00112, SHUF) /* genCtl%%insX RT<-sta(Ra+Rb,siz) */
195APUOP(M_CDX, RR, 0x1d7, "cdx", _A3(A_T,A_A,A_B), 00112, SHUF) /* genCtl%%insX RT<-sta(Ra+Rb,siz) */
196APUOP(M_LQX, RR, 0x1c4, "lqx", _A3(A_T,A_A,A_B), 00112, LS) /* LoadQindeX RT<-M[Ra+Rb] */
197APUOP(M_ROTQBI, RR, 0x1d8, "rotqbi", _A3(A_T,A_A,A_B), 00112, SHUF) /* ROTQBI RT<-RA<<<Rb */
198APUOP(M_ROTQMBI, RR, 0x1d9, "rotqmbi", _A3(A_T,A_A,A_B), 00112, SHUF) /* ROTQMBI RT<-RA<<Rb */
199APUOP(M_SHLQBI, RR, 0x1db, "shlqbi", _A3(A_T,A_A,A_B), 00112, SHUF) /* SHLQBI RT<-RA<<Rb */
200APUOP(M_ROTQBY, RR, 0x1dc, "rotqby", _A3(A_T,A_A,A_B), 00112, SHUF) /* ROTQBY RT<-RA<<<(Rb*8) */
201APUOP(M_ROTQMBY, RR, 0x1dd, "rotqmby", _A3(A_T,A_A,A_B), 00112, SHUF) /* ROTQMBY RT<-RA<<Rb */
202APUOP(M_SHLQBY, RR, 0x1df, "shlqby", _A3(A_T,A_A,A_B), 00112, SHUF) /* SHLQBY RT<-RA<<Rb */
203APUOP(M_ROTQBYBI, RR, 0x1cc, "rotqbybi", _A3(A_T,A_A,A_B), 00112, SHUF) /* ROTQBYBI RT<-RA<<Rb */
204APUOP(M_ROTQMBYBI, RR, 0x1cd, "rotqmbybi", _A3(A_T,A_A,A_B), 00112, SHUF) /* ROTQMBYBI RT<-RA<<Rb */
205APUOP(M_SHLQBYBI, RR, 0x1cf, "shlqbybi", _A3(A_T,A_A,A_B), 00112, SHUF) /* SHLQBYBI RT<-RA<<Rb */
206APUOP(M_STQX, RR, 0x144, "stqx", _A3(A_T,A_A,A_B), 00111, LS) /* SToreQindeX M[Ra+Rb]<-RT */
207APUOP(M_SHUFB, RRR, 0x580, "shufb", _A4(A_C,A_A,A_B,A_T), 02111, SHUF) /* SHUFfleBytes RC<-f(RA,RB,RT) */
208APUOP(M_IL, RI16, 0x204, "il", _A2(A_T,A_S16), 00002, FX2) /* ImmLoad RT<-sxt(I16) */
209APUOP(M_ILH, RI16, 0x20c, "ilh", _A2(A_T,A_X16), 00002, FX2) /* ImmLoadH RT<-I16 */
210APUOP(M_ILHU, RI16, 0x208, "ilhu", _A2(A_T,A_X16), 00002, FX2) /* ImmLoadHUpper RT<-I16<<16 */
211APUOP(M_ILA, RI18, 0x210, "ila", _A2(A_T,A_U18), 00002, FX2) /* ImmLoadAddr RT<-zxt(I18) */
212APUOP(M_NOP, RR, 0x201, "nop", _A1(A_T), 00000, NOP) /* XNOP no_operation */
213APUOP(M_NOP2, RR, 0x201, "nop", _A0(), 00000, NOP) /* XNOP no_operation */
214APUOP(M_IOHL, RI16, 0x304, "iohl", _A2(A_T,A_X16), 00003, FX2) /* AddImmeXt RT<-RT+sxt(I16) */
215APUOP(M_ANDBI, RI10, 0x0b0, "andbi", _A3(A_T,A_A,A_S10B), 00012, FX2) /* AND%I RT<-RA&I10 */
216APUOP(M_ANDHI, RI10, 0x0a8, "andhi", _A3(A_T,A_A,A_S10), 00012, FX2) /* AND%I RT<-RA&I10 */
217APUOP(M_ANDI, RI10, 0x0a0, "andi", _A3(A_T,A_A,A_S10), 00012, FX2) /* AND%I RT<-RA&I10 */
218APUOP(M_ORBI, RI10, 0x030, "orbi", _A3(A_T,A_A,A_S10B), 00012, FX2) /* OR%I RT<-RA|I10 */
219APUOP(M_ORHI, RI10, 0x028, "orhi", _A3(A_T,A_A,A_S10), 00012, FX2) /* OR%I RT<-RA|I10 */
220APUOP(M_ORI, RI10, 0x020, "ori", _A3(A_T,A_A,A_S10), 00012, FX2) /* OR%I RT<-RA|I10 */
221APUOP(M_ORX, RR, 0x1f0, "orx", _A2(A_T,A_A), 00012, BR) /* ORX RT<-RA.w0|RA.w1|RA.w2|RA.w3 */
222APUOP(M_XORBI, RI10, 0x230, "xorbi", _A3(A_T,A_A,A_S10B), 00012, FX2) /* XOR%I RT<-RA^I10 */
223APUOP(M_XORHI, RI10, 0x228, "xorhi", _A3(A_T,A_A,A_S10), 00012, FX2) /* XOR%I RT<-RA^I10 */
224APUOP(M_XORI, RI10, 0x220, "xori", _A3(A_T,A_A,A_S10), 00012, FX2) /* XOR%I RT<-RA^I10 */
225APUOP(M_AHI, RI10, 0x0e8, "ahi", _A3(A_T,A_A,A_S10), 00012, FX2) /* Add%Immed RT<-RA+I10 */
226APUOP(M_AI, RI10, 0x0e0, "ai", _A3(A_T,A_A,A_S10), 00012, FX2) /* Add%Immed RT<-RA+I10 */
227APUOP(M_SFHI, RI10, 0x068, "sfhi", _A3(A_T,A_A,A_S10), 00012, FX2) /* SubFrom%Imm RT<-I10-RA */
228APUOP(M_SFI, RI10, 0x060, "sfi", _A3(A_T,A_A,A_S10), 00012, FX2) /* SubFrom%Imm RT<-I10-RA */
229APUOP(M_CGTBI, RI10, 0x270, "cgtbi", _A3(A_T,A_A,A_S10B), 00012, FX2) /* CGT%I RT<-(RA>I10) */
230APUOP(M_CGTHI, RI10, 0x268, "cgthi", _A3(A_T,A_A,A_S10), 00012, FX2) /* CGT%I RT<-(RA>I10) */
231APUOP(M_CGTI, RI10, 0x260, "cgti", _A3(A_T,A_A,A_S10), 00012, FX2) /* CGT%I RT<-(RA>I10) */
232APUOP(M_CLGTBI, RI10, 0x2f0, "clgtbi", _A3(A_T,A_A,A_S10B), 00012, FX2) /* CLGT%I RT<-(RA>I10) */
233APUOP(M_CLGTHI, RI10, 0x2e8, "clgthi", _A3(A_T,A_A,A_S10), 00012, FX2) /* CLGT%I RT<-(RA>I10) */
234APUOP(M_CLGTI, RI10, 0x2e0, "clgti", _A3(A_T,A_A,A_S10), 00012, FX2) /* CLGT%I RT<-(RA>I10) */
235APUOP(M_CEQBI, RI10, 0x3f0, "ceqbi", _A3(A_T,A_A,A_S10B), 00012, FX2) /* CEQ%I RT<-(RA=I10) */
236APUOP(M_CEQHI, RI10, 0x3e8, "ceqhi", _A3(A_T,A_A,A_S10), 00012, FX2) /* CEQ%I RT<-(RA=I10) */
237APUOP(M_CEQI, RI10, 0x3e0, "ceqi", _A3(A_T,A_A,A_S10), 00012, FX2) /* CEQ%I RT<-(RA=I10) */
238APUOP(M_HGTI, RI10, 0x278, "hgti", _A3(A_T,A_A,A_S10), 00010, FX2) /* HaltGTI halt_if(RA>I10) */
239APUOP(M_HGTI2, RI10, 0x278, "hgti", _A2(A_A,A_S10), 00010, FX2) /* HaltGTI halt_if(RA>I10) */
240APUOP(M_HLGTI, RI10, 0x2f8, "hlgti", _A3(A_T,A_A,A_S10), 00010, FX2) /* HaltLGTI halt_if(RA>I10) */
241APUOP(M_HLGTI2, RI10, 0x2f8, "hlgti", _A2(A_A,A_S10), 00010, FX2) /* HaltLGTI halt_if(RA>I10) */
242APUOP(M_HEQI, RI10, 0x3f8, "heqi", _A3(A_T,A_A,A_S10), 00010, FX2) /* HaltEQImm halt_if(RA=I10) */
243APUOP(M_HEQI2, RI10, 0x3f8, "heqi", _A2(A_A,A_S10), 00010, FX2) /* HaltEQImm halt_if(RA=I10) */
244APUOP(M_MPYI, RI10, 0x3a0, "mpyi", _A3(A_T,A_A,A_S10), 00012, FP7) /* MPYI RT<-RA*I10 */
245APUOP(M_MPYUI, RI10, 0x3a8, "mpyui", _A3(A_T,A_A,A_S10), 00012, FP7) /* MPYUI RT<-RA*I10 */
246APUOP(M_CFLTS, RI8, 0x3b0, "cflts", _A3(A_T,A_A,A_U7A), 00012, FP7) /* CFLTS RT<-int(RA,I8) */
247APUOP(M_CFLTU, RI8, 0x3b2, "cfltu", _A3(A_T,A_A,A_U7A), 00012, FP7) /* CFLTU RT<-int(RA,I8) */
248APUOP(M_CSFLT, RI8, 0x3b4, "csflt", _A3(A_T,A_A,A_U7B), 00012, FP7) /* CSFLT RT<-flt(RA,I8) */
249APUOP(M_CUFLT, RI8, 0x3b6, "cuflt", _A3(A_T,A_A,A_U7B), 00012, FP7) /* CUFLT RT<-flt(RA,I8) */
250APUOP(M_FESD, RR, 0x3b8, "fesd", _A2(A_T,A_A), 00012, FPD) /* FESD RT<-double(RA) */
251APUOP(M_FRDS, RR, 0x3b9, "frds", _A2(A_T,A_A), 00012, FPD) /* FRDS RT<-single(RA) */
252APUOP(M_FSCRRD, RR, 0x398, "fscrrd", _A1(A_T), 00002, FPD) /* FSCRRD RT<-FP_status */
253APUOP(M_FSCRWR, RR, 0x3ba, "fscrwr", _A2(A_T,A_A), 00010, FP7) /* FSCRWR FP_status<-RA */
254APUOP(M_FSCRWR2, RR, 0x3ba, "fscrwr", _A1(A_A), 00010, FP7) /* FSCRWR FP_status<-RA */
255APUOP(M_CLZ, RR, 0x2a5, "clz", _A2(A_T,A_A), 00012, FX2) /* CLZ RT<-clz(RA) */
256APUOP(M_CNTB, RR, 0x2b4, "cntb", _A2(A_T,A_A), 00012, FXB) /* CNT RT<-pop(RA) */
257APUOP(M_XSBH, RR, 0x2b6, "xsbh", _A2(A_T,A_A), 00012, FX2) /* eXtSignBtoH RT<-sign_ext(RA) */
258APUOP(M_XSHW, RR, 0x2ae, "xshw", _A2(A_T,A_A), 00012, FX2) /* eXtSignHtoW RT<-sign_ext(RA) */
259APUOP(M_XSWD, RR, 0x2a6, "xswd", _A2(A_T,A_A), 00012, FX2) /* eXtSignWtoD RT<-sign_ext(RA) */
260APUOP(M_ROTI, RI7, 0x078, "roti", _A3(A_T,A_A,A_S7N), 00012, FX3) /* ROT%I RT<-RA<<<I7 */
261APUOP(M_ROTMI, RI7, 0x079, "rotmi", _A3(A_T,A_A,A_S7), 00012, FX3) /* ROT%MI RT<-RA<<I7 */
262APUOP(M_ROTMAI, RI7, 0x07a, "rotmai", _A3(A_T,A_A,A_S7), 00012, FX3) /* ROTMA%I RT<-RA<<I7 */
263APUOP(M_SHLI, RI7, 0x07b, "shli", _A3(A_T,A_A,A_U6), 00012, FX3) /* SHL%I RT<-RA<<I7 */
264APUOP(M_ROTHI, RI7, 0x07c, "rothi", _A3(A_T,A_A,A_S7N), 00012, FX3) /* ROT%I RT<-RA<<<I7 */
265APUOP(M_ROTHMI, RI7, 0x07d, "rothmi", _A3(A_T,A_A,A_S6), 00012, FX3) /* ROT%MI RT<-RA<<I7 */
266APUOP(M_ROTMAHI, RI7, 0x07e, "rotmahi", _A3(A_T,A_A,A_S6), 00012, FX3) /* ROTMA%I RT<-RA<<I7 */
267APUOP(M_SHLHI, RI7, 0x07f, "shlhi", _A3(A_T,A_A,A_U5), 00012, FX3) /* SHL%I RT<-RA<<I7 */
268APUOP(M_A, RR, 0x0c0, "a", _A3(A_T,A_A,A_B), 00112, FX2) /* Add% RT<-RA+RB */
269APUOP(M_AH, RR, 0x0c8, "ah", _A3(A_T,A_A,A_B), 00112, FX2) /* Add% RT<-RA+RB */
270APUOP(M_SF, RR, 0x040, "sf", _A3(A_T,A_A,A_B), 00112, FX2) /* SubFrom% RT<-RB-RA */
271APUOP(M_SFH, RR, 0x048, "sfh", _A3(A_T,A_A,A_B), 00112, FX2) /* SubFrom% RT<-RB-RA */
272APUOP(M_CGT, RR, 0x240, "cgt", _A3(A_T,A_A,A_B), 00112, FX2) /* CGT% RT<-(RA>RB) */
273APUOP(M_CGTB, RR, 0x250, "cgtb", _A3(A_T,A_A,A_B), 00112, FX2) /* CGT% RT<-(RA>RB) */
274APUOP(M_CGTH, RR, 0x248, "cgth", _A3(A_T,A_A,A_B), 00112, FX2) /* CGT% RT<-(RA>RB) */
275APUOP(M_CLGT, RR, 0x2c0, "clgt", _A3(A_T,A_A,A_B), 00112, FX2) /* CLGT% RT<-(RA>RB) */
276APUOP(M_CLGTB, RR, 0x2d0, "clgtb", _A3(A_T,A_A,A_B), 00112, FX2) /* CLGT% RT<-(RA>RB) */
277APUOP(M_CLGTH, RR, 0x2c8, "clgth", _A3(A_T,A_A,A_B), 00112, FX2) /* CLGT% RT<-(RA>RB) */
278APUOP(M_CEQ, RR, 0x3c0, "ceq", _A3(A_T,A_A,A_B), 00112, FX2) /* CEQ% RT<-(RA=RB) */
279APUOP(M_CEQB, RR, 0x3d0, "ceqb", _A3(A_T,A_A,A_B), 00112, FX2) /* CEQ% RT<-(RA=RB) */
280APUOP(M_CEQH, RR, 0x3c8, "ceqh", _A3(A_T,A_A,A_B), 00112, FX2) /* CEQ% RT<-(RA=RB) */
281APUOP(M_HGT, RR, 0x258, "hgt", _A3(A_T,A_A,A_B), 00110, FX2) /* HaltGT halt_if(RA>RB) */
282APUOP(M_HGT2, RR, 0x258, "hgt", _A2(A_A,A_B), 00110, FX2) /* HaltGT halt_if(RA>RB) */
283APUOP(M_HLGT, RR, 0x2d8, "hlgt", _A3(A_T,A_A,A_B), 00110, FX2) /* HaltLGT halt_if(RA>RB) */
284APUOP(M_HLGT2, RR, 0x2d8, "hlgt", _A2(A_A,A_B), 00110, FX2) /* HaltLGT halt_if(RA>RB) */
285APUOP(M_HEQ, RR, 0x3d8, "heq", _A3(A_T,A_A,A_B), 00110, FX2) /* HaltEQ halt_if(RA=RB) */
286APUOP(M_HEQ2, RR, 0x3d8, "heq", _A2(A_A,A_B), 00110, FX2) /* HaltEQ halt_if(RA=RB) */
287APUOP(M_FCEQ, RR, 0x3c2, "fceq", _A3(A_T,A_A,A_B), 00112, FX2) /* FCEQ RT<-(RA=RB) */
288APUOP(M_FCMEQ, RR, 0x3ca, "fcmeq", _A3(A_T,A_A,A_B), 00112, FX2) /* FCMEQ RT<-(|RA|=|RB|) */
289APUOP(M_FCGT, RR, 0x2c2, "fcgt", _A3(A_T,A_A,A_B), 00112, FX2) /* FCGT RT<-(RA<RB) */
290APUOP(M_FCMGT, RR, 0x2ca, "fcmgt", _A3(A_T,A_A,A_B), 00112, FX2) /* FCMGT RT<-(|RA|<|RB|) */
291APUOP(M_AND, RR, 0x0c1, "and", _A3(A_T,A_A,A_B), 00112, FX2) /* AND RT<-RA&RB */
292APUOP(M_NAND, RR, 0x0c9, "nand", _A3(A_T,A_A,A_B), 00112, FX2) /* NAND RT<-!(RA&RB) */
293APUOP(M_OR, RR, 0x041, "or", _A3(A_T,A_A,A_B), 00112, FX2) /* OR RT<-RA|RB */
294APUOP(M_NOR, RR, 0x049, "nor", _A3(A_T,A_A,A_B), 00112, FX2) /* NOR RT<-!(RA&RB) */
295APUOP(M_XOR, RR, 0x241, "xor", _A3(A_T,A_A,A_B), 00112, FX2) /* XOR RT<-RA^RB */
296APUOP(M_EQV, RR, 0x249, "eqv", _A3(A_T,A_A,A_B), 00112, FX2) /* EQuiValent RT<-!(RA^RB) */
297APUOP(M_ANDC, RR, 0x2c1, "andc", _A3(A_T,A_A,A_B), 00112, FX2) /* ANDComplement RT<-RA&!RB */
298APUOP(M_ORC, RR, 0x2c9, "orc", _A3(A_T,A_A,A_B), 00112, FX2) /* ORComplement RT<-RA|!RB */
299APUOP(M_ABSDB, RR, 0x053, "absdb", _A3(A_T,A_A,A_B), 00112, FXB) /* ABSoluteDiff RT<-|RA-RB| */
300APUOP(M_AVGB, RR, 0x0d3, "avgb", _A3(A_T,A_A,A_B), 00112, FXB) /* AVG% RT<-(RA+RB+1)/2 */
301APUOP(M_SUMB, RR, 0x253, "sumb", _A3(A_T,A_A,A_B), 00112, FXB) /* SUM% RT<-f(RA,RB) */
302APUOP(M_DFA, RR, 0x2cc, "dfa", _A3(A_T,A_A,A_B), 00112, FPD) /* DFAdd RT<-RA+RB */
303APUOP(M_DFM, RR, 0x2ce, "dfm", _A3(A_T,A_A,A_B), 00112, FPD) /* DFMul RT<-RA*RB */
304APUOP(M_DFS, RR, 0x2cd, "dfs", _A3(A_T,A_A,A_B), 00112, FPD) /* DFSub RT<-RA-RB */
305APUOP(M_FA, RR, 0x2c4, "fa", _A3(A_T,A_A,A_B), 00112, FP6) /* FAdd RT<-RA+RB */
306APUOP(M_FM, RR, 0x2c6, "fm", _A3(A_T,A_A,A_B), 00112, FP6) /* FMul RT<-RA*RB */
307APUOP(M_FS, RR, 0x2c5, "fs", _A3(A_T,A_A,A_B), 00112, FP6) /* FSub RT<-RA-RB */
308APUOP(M_MPY, RR, 0x3c4, "mpy", _A3(A_T,A_A,A_B), 00112, FP7) /* MPY RT<-RA*RB */
309APUOP(M_MPYH, RR, 0x3c5, "mpyh", _A3(A_T,A_A,A_B), 00112, FP7) /* MPYH RT<-(RAh*RB)<<16 */
310APUOP(M_MPYHH, RR, 0x3c6, "mpyhh", _A3(A_T,A_A,A_B), 00112, FP7) /* MPYHH RT<-RAh*RBh */
311APUOP(M_MPYHHU, RR, 0x3ce, "mpyhhu", _A3(A_T,A_A,A_B), 00112, FP7) /* MPYHHU RT<-RAh*RBh */
312APUOP(M_MPYS, RR, 0x3c7, "mpys", _A3(A_T,A_A,A_B), 00112, FP7) /* MPYS RT<-(RA*RB)>>16 */
313APUOP(M_MPYU, RR, 0x3cc, "mpyu", _A3(A_T,A_A,A_B), 00112, FP7) /* MPYU RT<-RA*RB */
314APUOP(M_FI, RR, 0x3d4, "fi", _A3(A_T,A_A,A_B), 00112, FP7) /* FInterpolate RT<-f(RA,RB) */
315APUOP(M_ROT, RR, 0x058, "rot", _A3(A_T,A_A,A_B), 00112, FX3) /* ROT% RT<-RA<<<RB */
316APUOP(M_ROTM, RR, 0x059, "rotm", _A3(A_T,A_A,A_B), 00112, FX3) /* ROT%M RT<-RA<<Rb */
317APUOP(M_ROTMA, RR, 0x05a, "rotma", _A3(A_T,A_A,A_B), 00112, FX3) /* ROTMA% RT<-RA<<Rb */
318APUOP(M_SHL, RR, 0x05b, "shl", _A3(A_T,A_A,A_B), 00112, FX3) /* SHL% RT<-RA<<Rb */
319APUOP(M_ROTH, RR, 0x05c, "roth", _A3(A_T,A_A,A_B), 00112, FX3) /* ROT% RT<-RA<<<RB */
320APUOP(M_ROTHM, RR, 0x05d, "rothm", _A3(A_T,A_A,A_B), 00112, FX3) /* ROT%M RT<-RA<<Rb */
321APUOP(M_ROTMAH, RR, 0x05e, "rotmah", _A3(A_T,A_A,A_B), 00112, FX3) /* ROTMA% RT<-RA<<Rb */
322APUOP(M_SHLH, RR, 0x05f, "shlh", _A3(A_T,A_A,A_B), 00112, FX3) /* SHL% RT<-RA<<Rb */
323APUOP(M_MPYHHA, RR, 0x346, "mpyhha", _A3(A_T,A_A,A_B), 00113, FP7) /* MPYHHA RT<-RAh*RBh+RT */
324APUOP(M_MPYHHAU, RR, 0x34e, "mpyhhau", _A3(A_T,A_A,A_B), 00113, FP7) /* MPYHHAU RT<-RAh*RBh+RT */
325APUOP(M_DFMA, RR, 0x35c, "dfma", _A3(A_T,A_A,A_B), 00113, FPD) /* DFMAdd RT<-RT+RA*RB */
326APUOP(M_DFMS, RR, 0x35d, "dfms", _A3(A_T,A_A,A_B), 00113, FPD) /* DFMSub RT<-RA*RB-RT */
327APUOP(M_DFNMS, RR, 0x35e, "dfnms", _A3(A_T,A_A,A_B), 00113, FPD) /* DFNMSub RT<-RT-RA*RB */
328APUOP(M_DFNMA, RR, 0x35f, "dfnma", _A3(A_T,A_A,A_B), 00113, FPD) /* DFNMAdd RT<-(-RT)-RA*RB */
329APUOP(M_FMA, RRR, 0x700, "fma", _A4(A_C,A_A,A_B,A_T), 02111, FP6) /* FMAdd RC<-RT+RA*RB */
330APUOP(M_FMS, RRR, 0x780, "fms", _A4(A_C,A_A,A_B,A_T), 02111, FP6) /* FMSub RC<-RA*RB-RT */
331APUOP(M_FNMS, RRR, 0x680, "fnms", _A4(A_C,A_A,A_B,A_T), 02111, FP6) /* FNMSub RC<-RT-RA*RB */
332APUOP(M_MPYA, RRR, 0x600, "mpya", _A4(A_C,A_A,A_B,A_T), 02111, FP7) /* MPYA RC<-RA*RB+RT */
333APUOP(M_SELB, RRR, 0x400, "selb", _A4(A_C,A_A,A_B,A_T), 02111, FX2) /* SELectBits RC<-RA&RT|RB&!RT */
334/* for system function call, this uses op-code of mtspr */
335APUOP(M_SYSCALL, RI7, 0x10c, "syscall", _A3(A_T,A_A,A_S7N), 00002, SPR) /* System Call */
336/*
337pseudo instruction:
338system call
339value of I9 operation
3400 halt
3411 rt[0] = open(MEM[ra[0]], ra[1])
3422 rt[0] = close(ra[0])
3433 rt[0] = read(ra[0], MEM[ra[1]], ra[2])
3444 rt[0] = write(ra[0], MEM[ra[1]], ra[2])
3455 printf(MEM[ra[0]], ra[1], ra[2], ra[3])
34642 rt[0] = clock()
34752 rt[0] = lseek(ra0, ra1, ra2)
348
349*/
350
351
352/* new multiprecision add/sub */
353APUOP(M_ADDX, RR, 0x340, "addx", _A3(A_T,A_A,A_B), 00113, FX2) /* Add_eXtended RT<-RA+RB+RT */
354APUOP(M_CG, RR, 0x0c2, "cg", _A3(A_T,A_A,A_B), 00112, FX2) /* CarryGenerate RT<-cout(RA+RB) */
355APUOP(M_CGX, RR, 0x342, "cgx", _A3(A_T,A_A,A_B), 00113, FX2) /* CarryGen_eXtd RT<-cout(RA+RB+RT) */
356APUOP(M_SFX, RR, 0x341, "sfx", _A3(A_T,A_A,A_B), 00113, FX2) /* Add_eXtended RT<-RA+RB+RT */
357APUOP(M_BG, RR, 0x042, "bg", _A3(A_T,A_A,A_B), 00112, FX2) /* CarryGenerate RT<-cout(RA+RB) */
358APUOP(M_BGX, RR, 0x343, "bgx", _A3(A_T,A_A,A_B), 00113, FX2) /* CarryGen_eXtd RT<-cout(RA+RB+RT) */
359
360/*
361
362The following ops are a subset of above except with feature bits set.
363Feature bits are bits 11-17 of the instruction:
364
365 11 - C & P feature bit
366 12 - disable interrupts
367 13 - enable interrupts
368
369*/
370APUOPFB(M_BID, RR, 0x1a8, 0x20, "bid", _A1(A_A), 00010, BR) /* BI IP<-RA */
371APUOPFB(M_BIE, RR, 0x1a8, 0x10, "bie", _A1(A_A), 00010, BR) /* BI IP<-RA */
372APUOPFB(M_BISLD, RR, 0x1a9, 0x20, "bisld", _A2(A_T,A_A), 00012, BR) /* BISL RT,IP<-IP,RA */
373APUOPFB(M_BISLE, RR, 0x1a9, 0x10, "bisle", _A2(A_T,A_A), 00012, BR) /* BISL RT,IP<-IP,RA */
374APUOPFB(M_IRETD, RR, 0x1aa, 0x20, "iretd", _A1(A_A), 00010, BR) /* IRET IP<-SRR0 */
375APUOPFB(M_IRETD2, RR, 0x1aa, 0x20, "iretd", _A0(), 00010, BR) /* IRET IP<-SRR0 */
376APUOPFB(M_IRETE, RR, 0x1aa, 0x10, "irete", _A1(A_A), 00010, BR) /* IRET IP<-SRR0 */
377APUOPFB(M_IRETE2, RR, 0x1aa, 0x10, "irete", _A0(), 00010, BR) /* IRET IP<-SRR0 */
378APUOPFB(M_BISLEDD, RR, 0x1ab, 0x20, "bisledd", _A2(A_T,A_A), 00012, BR) /* BISLED RT,IP<-IP,RA_if(ext) */
379APUOPFB(M_BISLEDE, RR, 0x1ab, 0x10, "bislede", _A2(A_T,A_A), 00012, BR) /* BISLED RT,IP<-IP,RA_if(ext) */
380APUOPFB(M_BIHNZD, RR, 0x12b, 0x20, "bihnzd", _A2(A_T,A_A), 00011, BR) /* BIHNZ IP<-RA_if(RT) */
381APUOPFB(M_BIHNZE, RR, 0x12b, 0x10, "bihnze", _A2(A_T,A_A), 00011, BR) /* BIHNZ IP<-RA_if(RT) */
382APUOPFB(M_BIHZD, RR, 0x12a, 0x20, "bihzd", _A2(A_T,A_A), 00011, BR) /* BIHZ IP<-RA_if(RT) */
383APUOPFB(M_BIHZE, RR, 0x12a, 0x10, "bihze", _A2(A_T,A_A), 00011, BR) /* BIHZ IP<-RA_if(RT) */
384APUOPFB(M_BINZD, RR, 0x129, 0x20, "binzd", _A2(A_T,A_A), 00011, BR) /* BINZ IP<-RA_if(RT) */
385APUOPFB(M_BINZE, RR, 0x129, 0x10, "binze", _A2(A_T,A_A), 00011, BR) /* BINZ IP<-RA_if(RT) */
386APUOPFB(M_BIZD, RR, 0x128, 0x20, "bizd", _A2(A_T,A_A), 00011, BR) /* BIZ IP<-RA_if(RT) */
387APUOPFB(M_BIZE, RR, 0x128, 0x10, "bize", _A2(A_T,A_A), 00011, BR) /* BIZ IP<-RA_if(RT) */
388APUOPFB(M_SYNCC, RR, 0x002, 0x40, "syncc", _A0(), 00000, BR) /* SYNCC flush_pipe */
389APUOPFB(M_HBRP, LBTI, 0x1ac, 0x40, "hbrp", _A0(), 00010, LS) /* HBR BTB[B9]<-M[Ra] */
390
391/* Synonyms required by the AS manual. */
392APUOP(M_LR, RI10, 0x020, "lr", _A2(A_T,A_A), 00012, FX2) /* OR%I RT<-RA|I10 */
393APUOP(M_BIHT, RR, 0x12b, "biht", _A2(A_T,A_A), 00011, BR) /* BIHNZ IP<-RA_if(RT) */
394APUOP(M_BIHF, RR, 0x12a, "bihf", _A2(A_T,A_A), 00011, BR) /* BIHZ IP<-RA_if(RT) */
395APUOP(M_BIT, RR, 0x129, "bit", _A2(A_T,A_A), 00011, BR) /* BINZ IP<-RA_if(RT) */
396APUOP(M_BIF, RR, 0x128, "bif", _A2(A_T,A_A), 00011, BR) /* BIZ IP<-RA_if(RT) */
397APUOPFB(M_BIHTD, RR, 0x12b, 0x20, "bihtd", _A2(A_T,A_A), 00011, BR) /* BIHNF IP<-RA_if(RT) */
398APUOPFB(M_BIHTE, RR, 0x12b, 0x10, "bihte", _A2(A_T,A_A), 00011, BR) /* BIHNF IP<-RA_if(RT) */
399APUOPFB(M_BIHFD, RR, 0x12a, 0x20, "bihfd", _A2(A_T,A_A), 00011, BR) /* BIHZ IP<-RA_if(RT) */
400APUOPFB(M_BIHFE, RR, 0x12a, 0x10, "bihfe", _A2(A_T,A_A), 00011, BR) /* BIHZ IP<-RA_if(RT) */
401APUOPFB(M_BITD, RR, 0x129, 0x20, "bitd", _A2(A_T,A_A), 00011, BR) /* BINF IP<-RA_if(RT) */
402APUOPFB(M_BITE, RR, 0x129, 0x10, "bite", _A2(A_T,A_A), 00011, BR) /* BINF IP<-RA_if(RT) */
403APUOPFB(M_BIFD, RR, 0x128, 0x20, "bifd", _A2(A_T,A_A), 00011, BR) /* BIZ IP<-RA_if(RT) */
404APUOPFB(M_BIFE, RR, 0x128, 0x10, "bife", _A2(A_T,A_A), 00011, BR) /* BIZ IP<-RA_if(RT) */
405
406#undef _A0
407#undef _A1
408#undef _A2
409#undef _A3
410#undef _A4
diff --git a/arch/powerpc/xmon/spu-opc.c b/arch/powerpc/xmon/spu-opc.c
new file mode 100644
index 000000000000..efffde9edc6e
--- /dev/null
+++ b/arch/powerpc/xmon/spu-opc.c
@@ -0,0 +1,44 @@
1/* SPU opcode list
2
3 Copyright 2006 Free Software Foundation, Inc.
4
5 This file is part of GDB, GAS, and the GNU binutils.
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License along
18 with this program; if not, write to the Free Software Foundation, Inc.,
19 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
20
21#include "spu.h"
22
23/* This file holds the Spu opcode table */
24
25
26/*
27 Example contents of spu-insn.h
28 id_tag mode mode type opcode mnemonic asmtype dependency FPU L/S? branch? instruction
29 QUAD WORD (0,RC,RB,RA,RT) latency
30 APUOP(M_LQD, 1, 0, RI9, 0x1f8, "lqd", ASM_RI9IDX, 00012, FXU, 1, 0) Load Quadword d-form
31 */
32
33const struct spu_opcode spu_opcodes[] = {
34#define APUOP(TAG,MACFORMAT,OPCODE,MNEMONIC,ASMFORMAT,DEP,PIPE) \
35 { MACFORMAT, OPCODE, MNEMONIC, ASMFORMAT },
36#define APUOPFB(TAG,MACFORMAT,OPCODE,FB,MNEMONIC,ASMFORMAT,DEP,PIPE) \
37 { MACFORMAT, OPCODE, MNEMONIC, ASMFORMAT },
38#include "spu-insns.h"
39#undef APUOP
40#undef APUOPFB
41};
42
43const int spu_num_opcodes =
44 sizeof (spu_opcodes) / sizeof (spu_opcodes[0]);
diff --git a/arch/powerpc/xmon/spu.h b/arch/powerpc/xmon/spu.h
new file mode 100644
index 000000000000..c761fc8f35d8
--- /dev/null
+++ b/arch/powerpc/xmon/spu.h
@@ -0,0 +1,126 @@
1/* SPU ELF support for BFD.
2
3 Copyright 2006 Free Software Foundation, Inc.
4
5 This file is part of GDB, GAS, and the GNU binutils.
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software Foundation,
19 Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
20
21
22/* These two enums are from rel_apu/common/spu_asm_format.h */
23/* definition of instruction format */
24typedef enum {
25 RRR,
26 RI18,
27 RI16,
28 RI10,
29 RI8,
30 RI7,
31 RR,
32 LBT,
33 LBTI,
34 IDATA,
35 UNKNOWN_IFORMAT
36} spu_iformat;
37
38/* These values describe assembly instruction arguments. They indicate
39 * how to encode, range checking and which relocation to use. */
40typedef enum {
41 A_T, /* register at pos 0 */
42 A_A, /* register at pos 7 */
43 A_B, /* register at pos 14 */
44 A_C, /* register at pos 21 */
45 A_S, /* special purpose register at pos 7 */
46 A_H, /* channel register at pos 7 */
47 A_P, /* parenthesis, this has to separate regs from immediates */
48 A_S3,
49 A_S6,
50 A_S7N,
51 A_S7,
52 A_U7A,
53 A_U7B,
54 A_S10B,
55 A_S10,
56 A_S11,
57 A_S11I,
58 A_S14,
59 A_S16,
60 A_S18,
61 A_R18,
62 A_U3,
63 A_U5,
64 A_U6,
65 A_U7,
66 A_U14,
67 A_X16,
68 A_U18,
69 A_MAX
70} spu_aformat;
71
72enum spu_insns {
73#define APUOP(TAG,MACFORMAT,OPCODE,MNEMONIC,ASMFORMAT,DEP,PIPE) \
74 TAG,
75#define APUOPFB(TAG,MACFORMAT,OPCODE,FB,MNEMONIC,ASMFORMAT,DEP,PIPE) \
76 TAG,
77#include "spu-insns.h"
78#undef APUOP
79#undef APUOPFB
80 M_SPU_MAX
81};
82
83struct spu_opcode
84{
85 spu_iformat insn_type;
86 unsigned int opcode;
87 char *mnemonic;
88 int arg[5];
89};
90
91#define SIGNED_EXTRACT(insn,size,pos) (((int)((insn) << (32-size-pos))) >> (32-size))
92#define UNSIGNED_EXTRACT(insn,size,pos) (((insn) >> pos) & ((1 << size)-1))
93
94#define DECODE_INSN_RT(insn) (insn & 0x7f)
95#define DECODE_INSN_RA(insn) ((insn >> 7) & 0x7f)
96#define DECODE_INSN_RB(insn) ((insn >> 14) & 0x7f)
97#define DECODE_INSN_RC(insn) ((insn >> 21) & 0x7f)
98
99#define DECODE_INSN_I10(insn) SIGNED_EXTRACT(insn,10,14)
100#define DECODE_INSN_U10(insn) UNSIGNED_EXTRACT(insn,10,14)
101
102/* For branching, immediate loads, hbr and lqa/stqa. */
103#define DECODE_INSN_I16(insn) SIGNED_EXTRACT(insn,16,7)
104#define DECODE_INSN_U16(insn) UNSIGNED_EXTRACT(insn,16,7)
105
106/* for stop */
107#define DECODE_INSN_U14(insn) UNSIGNED_EXTRACT(insn,14,0)
108
109/* For ila */
110#define DECODE_INSN_I18(insn) SIGNED_EXTRACT(insn,18,7)
111#define DECODE_INSN_U18(insn) UNSIGNED_EXTRACT(insn,18,7)
112
113/* For rotate and shift and generate control mask */
114#define DECODE_INSN_I7(insn) SIGNED_EXTRACT(insn,7,14)
115#define DECODE_INSN_U7(insn) UNSIGNED_EXTRACT(insn,7,14)
116
117/* For float <-> int conversion */
118#define DECODE_INSN_I8(insn) SIGNED_EXTRACT(insn,8,14)
119#define DECODE_INSN_U8(insn) UNSIGNED_EXTRACT(insn,8,14)
120
121/* For hbr */
122#define DECODE_INSN_I9a(insn) ((SIGNED_EXTRACT(insn,2,23) << 7) | UNSIGNED_EXTRACT(insn,7,0))
123#define DECODE_INSN_I9b(insn) ((SIGNED_EXTRACT(insn,2,14) << 7) | UNSIGNED_EXTRACT(insn,7,0))
124#define DECODE_INSN_U9a(insn) ((UNSIGNED_EXTRACT(insn,2,23) << 7) | UNSIGNED_EXTRACT(insn,7,0))
125#define DECODE_INSN_U9b(insn) ((UNSIGNED_EXTRACT(insn,2,14) << 7) | UNSIGNED_EXTRACT(insn,7,0))
126
diff --git a/arch/powerpc/xmon/xmon.c b/arch/powerpc/xmon/xmon.c
index f56ffef4defa..a34ed49e0356 100644
--- a/arch/powerpc/xmon/xmon.c
+++ b/arch/powerpc/xmon/xmon.c
@@ -37,13 +37,18 @@
37#include <asm/sstep.h> 37#include <asm/sstep.h>
38#include <asm/bug.h> 38#include <asm/bug.h>
39#include <asm/irq_regs.h> 39#include <asm/irq_regs.h>
40#include <asm/spu.h>
41#include <asm/spu_priv1.h>
42#include <asm/firmware.h>
40 43
41#ifdef CONFIG_PPC64 44#ifdef CONFIG_PPC64
42#include <asm/hvcall.h> 45#include <asm/hvcall.h>
43#include <asm/paca.h> 46#include <asm/paca.h>
47#include <asm/iseries/it_lp_reg_save.h>
44#endif 48#endif
45 49
46#include "nonstdio.h" 50#include "nonstdio.h"
51#include "dis-asm.h"
47 52
48#define scanhex xmon_scanhex 53#define scanhex xmon_scanhex
49#define skipbl xmon_skipbl 54#define skipbl xmon_skipbl
@@ -107,7 +112,6 @@ static int bsesc(void);
107static void dump(void); 112static void dump(void);
108static void prdump(unsigned long, long); 113static void prdump(unsigned long, long);
109static int ppc_inst_dump(unsigned long, long, int); 114static int ppc_inst_dump(unsigned long, long, int);
110void print_address(unsigned long);
111static void backtrace(struct pt_regs *); 115static void backtrace(struct pt_regs *);
112static void excprint(struct pt_regs *); 116static void excprint(struct pt_regs *);
113static void prregs(struct pt_regs *); 117static void prregs(struct pt_regs *);
@@ -147,9 +151,9 @@ static void xmon_print_symbol(unsigned long address, const char *mid,
147 const char *after); 151 const char *after);
148static const char *getvecname(unsigned long vec); 152static const char *getvecname(unsigned long vec);
149 153
150int xmon_no_auto_backtrace; 154static int do_spu_cmd(void);
151 155
152extern int print_insn_powerpc(unsigned long, unsigned long, int); 156int xmon_no_auto_backtrace;
153 157
154extern void xmon_enter(void); 158extern void xmon_enter(void);
155extern void xmon_leave(void); 159extern void xmon_leave(void);
@@ -209,8 +213,15 @@ Commands:\n\
209 mi show information about memory allocation\n\ 213 mi show information about memory allocation\n\
210 p call a procedure\n\ 214 p call a procedure\n\
211 r print registers\n\ 215 r print registers\n\
212 s single step\n\ 216 s single step\n"
213 S print special registers\n\ 217#ifdef CONFIG_SPU_BASE
218" ss stop execution on all spus\n\
219 sr restore execution on stopped spus\n\
220 sf # dump spu fields for spu # (in hex)\n\
221 sd # dump spu local store for spu # (in hex)\
222 sdi # disassemble spu local store for spu # (in hex)\n"
223#endif
224" S print special registers\n\
214 t print backtrace\n\ 225 t print backtrace\n\
215 x exit monitor and recover\n\ 226 x exit monitor and recover\n\
216 X exit monitor and dont recover\n" 227 X exit monitor and dont recover\n"
@@ -518,6 +529,7 @@ int xmon(struct pt_regs *excp)
518 xmon_save_regs(&regs); 529 xmon_save_regs(&regs);
519 excp = &regs; 530 excp = &regs;
520 } 531 }
532
521 return xmon_core(excp, 0); 533 return xmon_core(excp, 0);
522} 534}
523EXPORT_SYMBOL(xmon); 535EXPORT_SYMBOL(xmon);
@@ -809,6 +821,8 @@ cmds(struct pt_regs *excp)
809 cacheflush(); 821 cacheflush();
810 break; 822 break;
811 case 's': 823 case 's':
824 if (do_spu_cmd() == 0)
825 break;
812 if (do_step(excp)) 826 if (do_step(excp))
813 return cmd; 827 return cmd;
814 break; 828 break;
@@ -1555,11 +1569,6 @@ void super_regs(void)
1555{ 1569{
1556 int cmd; 1570 int cmd;
1557 unsigned long val; 1571 unsigned long val;
1558#ifdef CONFIG_PPC_ISERIES
1559 struct paca_struct *ptrPaca = NULL;
1560 struct lppaca *ptrLpPaca = NULL;
1561 struct ItLpRegSave *ptrLpRegSave = NULL;
1562#endif
1563 1572
1564 cmd = skipbl(); 1573 cmd = skipbl();
1565 if (cmd == '\n') { 1574 if (cmd == '\n') {
@@ -1576,26 +1585,32 @@ void super_regs(void)
1576 printf("sp = "REG" sprg3= "REG"\n", sp, mfspr(SPRN_SPRG3)); 1585 printf("sp = "REG" sprg3= "REG"\n", sp, mfspr(SPRN_SPRG3));
1577 printf("toc = "REG" dar = "REG"\n", toc, mfspr(SPRN_DAR)); 1586 printf("toc = "REG" dar = "REG"\n", toc, mfspr(SPRN_DAR));
1578#ifdef CONFIG_PPC_ISERIES 1587#ifdef CONFIG_PPC_ISERIES
1579 // Dump out relevant Paca data areas. 1588 if (firmware_has_feature(FW_FEATURE_ISERIES)) {
1580 printf("Paca: \n"); 1589 struct paca_struct *ptrPaca;
1581 ptrPaca = get_paca(); 1590 struct lppaca *ptrLpPaca;
1582 1591 struct ItLpRegSave *ptrLpRegSave;
1583 printf(" Local Processor Control Area (LpPaca): \n"); 1592
1584 ptrLpPaca = ptrPaca->lppaca_ptr; 1593 /* Dump out relevant Paca data areas. */
1585 printf(" Saved Srr0=%.16lx Saved Srr1=%.16lx \n", 1594 printf("Paca: \n");
1586 ptrLpPaca->saved_srr0, ptrLpPaca->saved_srr1); 1595 ptrPaca = get_paca();
1587 printf(" Saved Gpr3=%.16lx Saved Gpr4=%.16lx \n", 1596
1588 ptrLpPaca->saved_gpr3, ptrLpPaca->saved_gpr4); 1597 printf(" Local Processor Control Area (LpPaca): \n");
1589 printf(" Saved Gpr5=%.16lx \n", ptrLpPaca->saved_gpr5); 1598 ptrLpPaca = ptrPaca->lppaca_ptr;
1590 1599 printf(" Saved Srr0=%.16lx Saved Srr1=%.16lx \n",
1591 printf(" Local Processor Register Save Area (LpRegSave): \n"); 1600 ptrLpPaca->saved_srr0, ptrLpPaca->saved_srr1);
1592 ptrLpRegSave = ptrPaca->reg_save_ptr; 1601 printf(" Saved Gpr3=%.16lx Saved Gpr4=%.16lx \n",
1593 printf(" Saved Sprg0=%.16lx Saved Sprg1=%.16lx \n", 1602 ptrLpPaca->saved_gpr3, ptrLpPaca->saved_gpr4);
1594 ptrLpRegSave->xSPRG0, ptrLpRegSave->xSPRG0); 1603 printf(" Saved Gpr5=%.16lx \n", ptrLpPaca->saved_gpr5);
1595 printf(" Saved Sprg2=%.16lx Saved Sprg3=%.16lx \n", 1604
1596 ptrLpRegSave->xSPRG2, ptrLpRegSave->xSPRG3); 1605 printf(" Local Processor Register Save Area (LpRegSave): \n");
1597 printf(" Saved Msr =%.16lx Saved Nia =%.16lx \n", 1606 ptrLpRegSave = ptrPaca->reg_save_ptr;
1598 ptrLpRegSave->xMSR, ptrLpRegSave->xNIA); 1607 printf(" Saved Sprg0=%.16lx Saved Sprg1=%.16lx \n",
1608 ptrLpRegSave->xSPRG0, ptrLpRegSave->xSPRG0);
1609 printf(" Saved Sprg2=%.16lx Saved Sprg3=%.16lx \n",
1610 ptrLpRegSave->xSPRG2, ptrLpRegSave->xSPRG3);
1611 printf(" Saved Msr =%.16lx Saved Nia =%.16lx \n",
1612 ptrLpRegSave->xMSR, ptrLpRegSave->xNIA);
1613 }
1599#endif 1614#endif
1600 1615
1601 return; 1616 return;
@@ -2053,8 +2068,11 @@ prdump(unsigned long adrs, long ndump)
2053 } 2068 }
2054} 2069}
2055 2070
2071typedef int (*instruction_dump_func)(unsigned long inst, unsigned long addr);
2072
2056int 2073int
2057ppc_inst_dump(unsigned long adr, long count, int praddr) 2074generic_inst_dump(unsigned long adr, long count, int praddr,
2075 instruction_dump_func dump_func)
2058{ 2076{
2059 int nr, dotted; 2077 int nr, dotted;
2060 unsigned long first_adr; 2078 unsigned long first_adr;
@@ -2084,12 +2102,18 @@ ppc_inst_dump(unsigned long adr, long count, int praddr)
2084 if (praddr) 2102 if (praddr)
2085 printf(REG" %.8x", adr, inst); 2103 printf(REG" %.8x", adr, inst);
2086 printf("\t"); 2104 printf("\t");
2087 print_insn_powerpc(inst, adr, 0); /* always returns 4 */ 2105 dump_func(inst, adr);
2088 printf("\n"); 2106 printf("\n");
2089 } 2107 }
2090 return adr - first_adr; 2108 return adr - first_adr;
2091} 2109}
2092 2110
2111int
2112ppc_inst_dump(unsigned long adr, long count, int praddr)
2113{
2114 return generic_inst_dump(adr, count, praddr, print_insn_powerpc);
2115}
2116
2093void 2117void
2094print_address(unsigned long addr) 2118print_address(unsigned long addr)
2095{ 2119{
@@ -2557,6 +2581,10 @@ void dump_segments(void)
2557 2581
2558void xmon_init(int enable) 2582void xmon_init(int enable)
2559{ 2583{
2584#ifdef CONFIG_PPC_ISERIES
2585 if (firmware_has_feature(FW_FEATURE_ISERIES))
2586 return;
2587#endif
2560 if (enable) { 2588 if (enable) {
2561 __debugger = xmon; 2589 __debugger = xmon;
2562 __debugger_ipi = xmon_ipi; 2590 __debugger_ipi = xmon_ipi;
@@ -2594,6 +2622,10 @@ static struct sysrq_key_op sysrq_xmon_op =
2594 2622
2595static int __init setup_xmon_sysrq(void) 2623static int __init setup_xmon_sysrq(void)
2596{ 2624{
2625#ifdef CONFIG_PPC_ISERIES
2626 if (firmware_has_feature(FW_FEATURE_ISERIES))
2627 return 0;
2628#endif
2597 register_sysrq_key('x', &sysrq_xmon_op); 2629 register_sysrq_key('x', &sysrq_xmon_op);
2598 return 0; 2630 return 0;
2599} 2631}
@@ -2630,3 +2662,263 @@ void __init xmon_setup(void)
2630 if (xmon_early) 2662 if (xmon_early)
2631 debugger(NULL); 2663 debugger(NULL);
2632} 2664}
2665
2666#ifdef CONFIG_SPU_BASE
2667
2668struct spu_info {
2669 struct spu *spu;
2670 u64 saved_mfc_sr1_RW;
2671 u32 saved_spu_runcntl_RW;
2672 unsigned long dump_addr;
2673 u8 stopped_ok;
2674};
2675
2676#define XMON_NUM_SPUS 16 /* Enough for current hardware */
2677
2678static struct spu_info spu_info[XMON_NUM_SPUS];
2679
2680void xmon_register_spus(struct list_head *list)
2681{
2682 struct spu *spu;
2683
2684 list_for_each_entry(spu, list, full_list) {
2685 if (spu->number >= XMON_NUM_SPUS) {
2686 WARN_ON(1);
2687 continue;
2688 }
2689
2690 spu_info[spu->number].spu = spu;
2691 spu_info[spu->number].stopped_ok = 0;
2692 spu_info[spu->number].dump_addr = (unsigned long)
2693 spu_info[spu->number].spu->local_store;
2694 }
2695}
2696
2697static void stop_spus(void)
2698{
2699 struct spu *spu;
2700 int i;
2701 u64 tmp;
2702
2703 for (i = 0; i < XMON_NUM_SPUS; i++) {
2704 if (!spu_info[i].spu)
2705 continue;
2706
2707 if (setjmp(bus_error_jmp) == 0) {
2708 catch_memory_errors = 1;
2709 sync();
2710
2711 spu = spu_info[i].spu;
2712
2713 spu_info[i].saved_spu_runcntl_RW =
2714 in_be32(&spu->problem->spu_runcntl_RW);
2715
2716 tmp = spu_mfc_sr1_get(spu);
2717 spu_info[i].saved_mfc_sr1_RW = tmp;
2718
2719 tmp &= ~MFC_STATE1_MASTER_RUN_CONTROL_MASK;
2720 spu_mfc_sr1_set(spu, tmp);
2721
2722 sync();
2723 __delay(200);
2724
2725 spu_info[i].stopped_ok = 1;
2726
2727 printf("Stopped spu %.2d (was %s)\n", i,
2728 spu_info[i].saved_spu_runcntl_RW ?
2729 "running" : "stopped");
2730 } else {
2731 catch_memory_errors = 0;
2732 printf("*** Error stopping spu %.2d\n", i);
2733 }
2734 catch_memory_errors = 0;
2735 }
2736}
2737
2738static void restart_spus(void)
2739{
2740 struct spu *spu;
2741 int i;
2742
2743 for (i = 0; i < XMON_NUM_SPUS; i++) {
2744 if (!spu_info[i].spu)
2745 continue;
2746
2747 if (!spu_info[i].stopped_ok) {
2748 printf("*** Error, spu %d was not successfully stopped"
2749 ", not restarting\n", i);
2750 continue;
2751 }
2752
2753 if (setjmp(bus_error_jmp) == 0) {
2754 catch_memory_errors = 1;
2755 sync();
2756
2757 spu = spu_info[i].spu;
2758 spu_mfc_sr1_set(spu, spu_info[i].saved_mfc_sr1_RW);
2759 out_be32(&spu->problem->spu_runcntl_RW,
2760 spu_info[i].saved_spu_runcntl_RW);
2761
2762 sync();
2763 __delay(200);
2764
2765 printf("Restarted spu %.2d\n", i);
2766 } else {
2767 catch_memory_errors = 0;
2768 printf("*** Error restarting spu %.2d\n", i);
2769 }
2770 catch_memory_errors = 0;
2771 }
2772}
2773
2774#define DUMP_WIDTH 23
2775#define DUMP_VALUE(format, field, value) \
2776do { \
2777 if (setjmp(bus_error_jmp) == 0) { \
2778 catch_memory_errors = 1; \
2779 sync(); \
2780 printf(" %-*s = "format"\n", DUMP_WIDTH, \
2781 #field, value); \
2782 sync(); \
2783 __delay(200); \
2784 } else { \
2785 catch_memory_errors = 0; \
2786 printf(" %-*s = *** Error reading field.\n", \
2787 DUMP_WIDTH, #field); \
2788 } \
2789 catch_memory_errors = 0; \
2790} while (0)
2791
2792#define DUMP_FIELD(obj, format, field) \
2793 DUMP_VALUE(format, field, obj->field)
2794
2795static void dump_spu_fields(struct spu *spu)
2796{
2797 printf("Dumping spu fields at address %p:\n", spu);
2798
2799 DUMP_FIELD(spu, "0x%x", number);
2800 DUMP_FIELD(spu, "%s", name);
2801 DUMP_FIELD(spu, "0x%lx", local_store_phys);
2802 DUMP_FIELD(spu, "0x%p", local_store);
2803 DUMP_FIELD(spu, "0x%lx", ls_size);
2804 DUMP_FIELD(spu, "0x%x", node);
2805 DUMP_FIELD(spu, "0x%lx", flags);
2806 DUMP_FIELD(spu, "0x%lx", dar);
2807 DUMP_FIELD(spu, "0x%lx", dsisr);
2808 DUMP_FIELD(spu, "%d", class_0_pending);
2809 DUMP_FIELD(spu, "0x%lx", irqs[0]);
2810 DUMP_FIELD(spu, "0x%lx", irqs[1]);
2811 DUMP_FIELD(spu, "0x%lx", irqs[2]);
2812 DUMP_FIELD(spu, "0x%x", slb_replace);
2813 DUMP_FIELD(spu, "%d", pid);
2814 DUMP_FIELD(spu, "%d", prio);
2815 DUMP_FIELD(spu, "0x%p", mm);
2816 DUMP_FIELD(spu, "0x%p", ctx);
2817 DUMP_FIELD(spu, "0x%p", rq);
2818 DUMP_FIELD(spu, "0x%p", timestamp);
2819 DUMP_FIELD(spu, "0x%lx", problem_phys);
2820 DUMP_FIELD(spu, "0x%p", problem);
2821 DUMP_VALUE("0x%x", problem->spu_runcntl_RW,
2822 in_be32(&spu->problem->spu_runcntl_RW));
2823 DUMP_VALUE("0x%x", problem->spu_status_R,
2824 in_be32(&spu->problem->spu_status_R));
2825 DUMP_VALUE("0x%x", problem->spu_npc_RW,
2826 in_be32(&spu->problem->spu_npc_RW));
2827 DUMP_FIELD(spu, "0x%p", priv2);
2828 DUMP_FIELD(spu, "0x%p", pdata);
2829}
2830
2831int
2832spu_inst_dump(unsigned long adr, long count, int praddr)
2833{
2834 return generic_inst_dump(adr, count, praddr, print_insn_spu);
2835}
2836
2837static void dump_spu_ls(unsigned long num, int subcmd)
2838{
2839 unsigned long offset, addr, ls_addr;
2840
2841 if (setjmp(bus_error_jmp) == 0) {
2842 catch_memory_errors = 1;
2843 sync();
2844 ls_addr = (unsigned long)spu_info[num].spu->local_store;
2845 sync();
2846 __delay(200);
2847 } else {
2848 catch_memory_errors = 0;
2849 printf("*** Error: accessing spu info for spu %d\n", num);
2850 return;
2851 }
2852 catch_memory_errors = 0;
2853
2854 if (scanhex(&offset))
2855 addr = ls_addr + offset;
2856 else
2857 addr = spu_info[num].dump_addr;
2858
2859 if (addr >= ls_addr + LS_SIZE) {
2860 printf("*** Error: address outside of local store\n");
2861 return;
2862 }
2863
2864 switch (subcmd) {
2865 case 'i':
2866 addr += spu_inst_dump(addr, 16, 1);
2867 last_cmd = "sdi\n";
2868 break;
2869 default:
2870 prdump(addr, 64);
2871 addr += 64;
2872 last_cmd = "sd\n";
2873 break;
2874 }
2875
2876 spu_info[num].dump_addr = addr;
2877}
2878
2879static int do_spu_cmd(void)
2880{
2881 static unsigned long num = 0;
2882 int cmd, subcmd = 0;
2883
2884 cmd = inchar();
2885 switch (cmd) {
2886 case 's':
2887 stop_spus();
2888 break;
2889 case 'r':
2890 restart_spus();
2891 break;
2892 case 'd':
2893 subcmd = inchar();
2894 if (isxdigit(subcmd) || subcmd == '\n')
2895 termch = subcmd;
2896 case 'f':
2897 scanhex(&num);
2898 if (num >= XMON_NUM_SPUS || !spu_info[num].spu) {
2899 printf("*** Error: invalid spu number\n");
2900 return 0;
2901 }
2902
2903 switch (cmd) {
2904 case 'f':
2905 dump_spu_fields(spu_info[num].spu);
2906 break;
2907 default:
2908 dump_spu_ls(num, subcmd);
2909 break;
2910 }
2911
2912 break;
2913 default:
2914 return -1;
2915 }
2916
2917 return 0;
2918}
2919#else /* ! CONFIG_SPU_BASE */
2920static int do_spu_cmd(void)
2921{
2922 return -1;
2923}
2924#endif
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