diff options
Diffstat (limited to 'arch/powerpc/sysdev')
-rw-r--r-- | arch/powerpc/sysdev/ppc4xx_pci.c | 8 |
1 files changed, 0 insertions, 8 deletions
diff --git a/arch/powerpc/sysdev/ppc4xx_pci.c b/arch/powerpc/sysdev/ppc4xx_pci.c index 6c925b7975f9..aa856ea9fed8 100644 --- a/arch/powerpc/sysdev/ppc4xx_pci.c +++ b/arch/powerpc/sysdev/ppc4xx_pci.c | |||
@@ -940,17 +940,9 @@ static int ppc405ex_pciex_init_port_hw(struct ppc4xx_pciex_port *port) | |||
940 | * PCIe boards don't show this problem. | 940 | * PCIe boards don't show this problem. |
941 | * This has to be re-tested and fixed in a later release! | 941 | * This has to be re-tested and fixed in a later release! |
942 | */ | 942 | */ |
943 | #if 0 /* XXX FIXME: Not resetting the PHY will leave all resources | ||
944 | * configured as done previously by U-Boot. Then Linux will currently | ||
945 | * not reassign them. So the PHY reset is now done always. This will | ||
946 | * lead to problems with the Atheros PCIe board again. | ||
947 | */ | ||
948 | val = mfdcri(SDR0, port->sdr_base + PESDRn_LOOP); | 943 | val = mfdcri(SDR0, port->sdr_base + PESDRn_LOOP); |
949 | if (!(val & 0x00001000)) | 944 | if (!(val & 0x00001000)) |
950 | ppc405ex_pcie_phy_reset(port); | 945 | ppc405ex_pcie_phy_reset(port); |
951 | #else | ||
952 | ppc405ex_pcie_phy_reset(port); | ||
953 | #endif | ||
954 | 946 | ||
955 | dcr_write(port->dcrs, DCRO_PEGPL_CFG, 0x10000000); /* guarded on */ | 947 | dcr_write(port->dcrs, DCRO_PEGPL_CFG, 0x10000000); /* guarded on */ |
956 | 948 | ||