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-rw-r--r--arch/powerpc/sysdev/Makefile2
-rw-r--r--arch/powerpc/sysdev/cpm1.c114
-rw-r--r--arch/powerpc/sysdev/cpm2.c105
-rw-r--r--arch/powerpc/sysdev/cpm_common.c3
-rw-r--r--arch/powerpc/sysdev/dart_iommu.c2
-rw-r--r--arch/powerpc/sysdev/fsl_lbc.c129
-rw-r--r--arch/powerpc/sysdev/fsl_soc.c611
-rw-r--r--arch/powerpc/sysdev/fsl_soc.h1
-rw-r--r--arch/powerpc/sysdev/mpic.c41
-rw-r--r--arch/powerpc/sysdev/mv64x60_dev.c78
-rw-r--r--arch/powerpc/sysdev/mv64x60_pci.c6
-rw-r--r--arch/powerpc/sysdev/mv64x60_pic.c4
-rw-r--r--arch/powerpc/sysdev/mv64x60_udbg.c2
-rw-r--r--arch/powerpc/sysdev/ppc4xx_pci.c133
-rw-r--r--arch/powerpc/sysdev/ppc4xx_pci.h59
-rw-r--r--arch/powerpc/sysdev/ppc4xx_soc.c200
-rw-r--r--arch/powerpc/sysdev/qe_lib/qe.c13
-rw-r--r--arch/powerpc/sysdev/qe_lib/qe_io.c7
-rw-r--r--arch/powerpc/sysdev/qe_lib/ucc_fast.c32
-rw-r--r--arch/powerpc/sysdev/qe_lib/ucc_slow.c18
-rw-r--r--arch/powerpc/sysdev/rtc_cmos_setup.c2
-rw-r--r--arch/powerpc/sysdev/tsi108_dev.c4
-rw-r--r--arch/powerpc/sysdev/tsi108_pci.c4
23 files changed, 656 insertions, 914 deletions
diff --git a/arch/powerpc/sysdev/Makefile b/arch/powerpc/sysdev/Makefile
index 15f3e8527d77..6d386d0071a0 100644
--- a/arch/powerpc/sysdev/Makefile
+++ b/arch/powerpc/sysdev/Makefile
@@ -12,6 +12,7 @@ obj-$(CONFIG_U3_DART) += dart_iommu.o
12obj-$(CONFIG_MMIO_NVRAM) += mmio_nvram.o 12obj-$(CONFIG_MMIO_NVRAM) += mmio_nvram.o
13obj-$(CONFIG_FSL_SOC) += fsl_soc.o 13obj-$(CONFIG_FSL_SOC) += fsl_soc.o
14obj-$(CONFIG_FSL_PCI) += fsl_pci.o 14obj-$(CONFIG_FSL_PCI) += fsl_pci.o
15obj-$(CONFIG_FSL_LBC) += fsl_lbc.o
15obj-$(CONFIG_RAPIDIO) += fsl_rio.o 16obj-$(CONFIG_RAPIDIO) += fsl_rio.o
16obj-$(CONFIG_TSI108_BRIDGE) += tsi108_pci.o tsi108_dev.o 17obj-$(CONFIG_TSI108_BRIDGE) += tsi108_pci.o tsi108_dev.o
17obj-$(CONFIG_QUICC_ENGINE) += qe_lib/ 18obj-$(CONFIG_QUICC_ENGINE) += qe_lib/
@@ -27,6 +28,7 @@ obj-$(CONFIG_PPC_INDIRECT_PCI) += indirect_pci.o
27obj-$(CONFIG_PPC_I8259) += i8259.o 28obj-$(CONFIG_PPC_I8259) += i8259.o
28obj-$(CONFIG_IPIC) += ipic.o 29obj-$(CONFIG_IPIC) += ipic.o
29obj-$(CONFIG_4xx) += uic.o 30obj-$(CONFIG_4xx) += uic.o
31obj-$(CONFIG_4xx_SOC) += ppc4xx_soc.o
30obj-$(CONFIG_XILINX_VIRTEX) += xilinx_intc.o 32obj-$(CONFIG_XILINX_VIRTEX) += xilinx_intc.o
31obj-$(CONFIG_OF_RTC) += of_rtc.o 33obj-$(CONFIG_OF_RTC) += of_rtc.o
32ifeq ($(CONFIG_PCI),y) 34ifeq ($(CONFIG_PCI),y)
diff --git a/arch/powerpc/sysdev/cpm1.c b/arch/powerpc/sysdev/cpm1.c
index df8bd2b64796..58292a086c16 100644
--- a/arch/powerpc/sysdev/cpm1.c
+++ b/arch/powerpc/sysdev/cpm1.c
@@ -44,9 +44,6 @@
44 44
45#define CPM_MAP_SIZE (0x4000) 45#define CPM_MAP_SIZE (0x4000)
46 46
47#ifndef CONFIG_PPC_CPM_NEW_BINDING
48static void m8xx_cpm_dpinit(void);
49#endif
50cpm8xx_t __iomem *cpmp; /* Pointer to comm processor space */ 47cpm8xx_t __iomem *cpmp; /* Pointer to comm processor space */
51immap_t __iomem *mpc8xx_immr; 48immap_t __iomem *mpc8xx_immr;
52static cpic8xx_t __iomem *cpic_reg; 49static cpic8xx_t __iomem *cpic_reg;
@@ -229,12 +226,7 @@ void __init cpm_reset(void)
229 out_be32(&siu_conf->sc_sdcr, 1); 226 out_be32(&siu_conf->sc_sdcr, 1);
230 immr_unmap(siu_conf); 227 immr_unmap(siu_conf);
231 228
232#ifdef CONFIG_PPC_CPM_NEW_BINDING
233 cpm_muram_init(); 229 cpm_muram_init();
234#else
235 /* Reclaim the DP memory for our use. */
236 m8xx_cpm_dpinit();
237#endif
238} 230}
239 231
240static DEFINE_SPINLOCK(cmd_lock); 232static DEFINE_SPINLOCK(cmd_lock);
@@ -257,7 +249,7 @@ int cpm_command(u32 command, u8 opcode)
257 if ((in_be16(&cpmp->cp_cpcr) & CPM_CR_FLG) == 0) 249 if ((in_be16(&cpmp->cp_cpcr) & CPM_CR_FLG) == 0)
258 goto out; 250 goto out;
259 251
260 printk(KERN_ERR "%s(): Not able to issue CPM command\n", __FUNCTION__); 252 printk(KERN_ERR "%s(): Not able to issue CPM command\n", __func__);
261 ret = -EIO; 253 ret = -EIO;
262out: 254out:
263 spin_unlock_irqrestore(&cmd_lock, flags); 255 spin_unlock_irqrestore(&cmd_lock, flags);
@@ -293,110 +285,6 @@ cpm_setbrg(uint brg, uint rate)
293 CPM_BRG_EN | CPM_BRG_DIV16); 285 CPM_BRG_EN | CPM_BRG_DIV16);
294} 286}
295 287
296#ifndef CONFIG_PPC_CPM_NEW_BINDING
297/*
298 * dpalloc / dpfree bits.
299 */
300static spinlock_t cpm_dpmem_lock;
301/*
302 * 16 blocks should be enough to satisfy all requests
303 * until the memory subsystem goes up...
304 */
305static rh_block_t cpm_boot_dpmem_rh_block[16];
306static rh_info_t cpm_dpmem_info;
307
308#define CPM_DPMEM_ALIGNMENT 8
309static u8 __iomem *dpram_vbase;
310static phys_addr_t dpram_pbase;
311
312static void m8xx_cpm_dpinit(void)
313{
314 spin_lock_init(&cpm_dpmem_lock);
315
316 dpram_vbase = cpmp->cp_dpmem;
317 dpram_pbase = get_immrbase() + offsetof(immap_t, im_cpm.cp_dpmem);
318
319 /* Initialize the info header */
320 rh_init(&cpm_dpmem_info, CPM_DPMEM_ALIGNMENT,
321 sizeof(cpm_boot_dpmem_rh_block) /
322 sizeof(cpm_boot_dpmem_rh_block[0]),
323 cpm_boot_dpmem_rh_block);
324
325 /*
326 * Attach the usable dpmem area.
327 * XXX: This is actually crap. CPM_DATAONLY_BASE and
328 * CPM_DATAONLY_SIZE are a subset of the available dparm. It varies
329 * with the processor and the microcode patches applied / activated.
330 * But the following should be at least safe.
331 */
332 rh_attach_region(&cpm_dpmem_info, CPM_DATAONLY_BASE, CPM_DATAONLY_SIZE);
333}
334
335/*
336 * Allocate the requested size worth of DP memory.
337 * This function returns an offset into the DPRAM area.
338 * Use cpm_dpram_addr() to get the virtual address of the area.
339 */
340unsigned long cpm_dpalloc(uint size, uint align)
341{
342 unsigned long start;
343 unsigned long flags;
344
345 spin_lock_irqsave(&cpm_dpmem_lock, flags);
346 cpm_dpmem_info.alignment = align;
347 start = rh_alloc(&cpm_dpmem_info, size, "commproc");
348 spin_unlock_irqrestore(&cpm_dpmem_lock, flags);
349
350 return (uint)start;
351}
352EXPORT_SYMBOL(cpm_dpalloc);
353
354int cpm_dpfree(unsigned long offset)
355{
356 int ret;
357 unsigned long flags;
358
359 spin_lock_irqsave(&cpm_dpmem_lock, flags);
360 ret = rh_free(&cpm_dpmem_info, offset);
361 spin_unlock_irqrestore(&cpm_dpmem_lock, flags);
362
363 return ret;
364}
365EXPORT_SYMBOL(cpm_dpfree);
366
367unsigned long cpm_dpalloc_fixed(unsigned long offset, uint size, uint align)
368{
369 unsigned long start;
370 unsigned long flags;
371
372 spin_lock_irqsave(&cpm_dpmem_lock, flags);
373 cpm_dpmem_info.alignment = align;
374 start = rh_alloc_fixed(&cpm_dpmem_info, offset, size, "commproc");
375 spin_unlock_irqrestore(&cpm_dpmem_lock, flags);
376
377 return start;
378}
379EXPORT_SYMBOL(cpm_dpalloc_fixed);
380
381void cpm_dpdump(void)
382{
383 rh_dump(&cpm_dpmem_info);
384}
385EXPORT_SYMBOL(cpm_dpdump);
386
387void *cpm_dpram_addr(unsigned long offset)
388{
389 return (void *)(dpram_vbase + offset);
390}
391EXPORT_SYMBOL(cpm_dpram_addr);
392
393uint cpm_dpram_phys(u8 *addr)
394{
395 return (dpram_pbase + (uint)(addr - dpram_vbase));
396}
397EXPORT_SYMBOL(cpm_dpram_phys);
398#endif /* !CONFIG_PPC_CPM_NEW_BINDING */
399
400struct cpm_ioport16 { 288struct cpm_ioport16 {
401 __be16 dir, par, odr_sor, dat, intr; 289 __be16 dir, par, odr_sor, dat, intr;
402 __be16 res[3]; 290 __be16 res[3];
diff --git a/arch/powerpc/sysdev/cpm2.c b/arch/powerpc/sysdev/cpm2.c
index dd066bb1d562..5a6c5dfc53ef 100644
--- a/arch/powerpc/sysdev/cpm2.c
+++ b/arch/powerpc/sysdev/cpm2.c
@@ -46,10 +46,6 @@
46 46
47#include <sysdev/fsl_soc.h> 47#include <sysdev/fsl_soc.h>
48 48
49#ifndef CONFIG_PPC_CPM_NEW_BINDING
50static void cpm2_dpinit(void);
51#endif
52
53cpm_cpm2_t __iomem *cpmp; /* Pointer to comm processor space */ 49cpm_cpm2_t __iomem *cpmp; /* Pointer to comm processor space */
54 50
55/* We allocate this here because it is used almost exclusively for 51/* We allocate this here because it is used almost exclusively for
@@ -71,15 +67,17 @@ void __init cpm2_reset(void)
71 67
72 /* Reclaim the DP memory for our use. 68 /* Reclaim the DP memory for our use.
73 */ 69 */
74#ifdef CONFIG_PPC_CPM_NEW_BINDING
75 cpm_muram_init(); 70 cpm_muram_init();
76#else
77 cpm2_dpinit();
78#endif
79 71
80 /* Tell everyone where the comm processor resides. 72 /* Tell everyone where the comm processor resides.
81 */ 73 */
82 cpmp = &cpm2_immr->im_cpm; 74 cpmp = &cpm2_immr->im_cpm;
75
76#ifndef CONFIG_PPC_EARLY_DEBUG_CPM
77 /* Reset the CPM.
78 */
79 cpm_command(CPM_CR_RST, 0);
80#endif
83} 81}
84 82
85static DEFINE_SPINLOCK(cmd_lock); 83static DEFINE_SPINLOCK(cmd_lock);
@@ -99,7 +97,7 @@ int cpm_command(u32 command, u8 opcode)
99 if ((in_be32(&cpmp->cp_cpcr) & CPM_CR_FLG) == 0) 97 if ((in_be32(&cpmp->cp_cpcr) & CPM_CR_FLG) == 0)
100 goto out; 98 goto out;
101 99
102 printk(KERN_ERR "%s(): Not able to issue CPM command\n", __FUNCTION__); 100 printk(KERN_ERR "%s(): Not able to issue CPM command\n", __func__);
103 ret = -EIO; 101 ret = -EIO;
104out: 102out:
105 spin_unlock_irqrestore(&cmd_lock, flags); 103 spin_unlock_irqrestore(&cmd_lock, flags);
@@ -347,95 +345,6 @@ int cpm2_smc_clk_setup(enum cpm_clk_target target, int clock)
347 return ret; 345 return ret;
348} 346}
349 347
350#ifndef CONFIG_PPC_CPM_NEW_BINDING
351/*
352 * dpalloc / dpfree bits.
353 */
354static spinlock_t cpm_dpmem_lock;
355/* 16 blocks should be enough to satisfy all requests
356 * until the memory subsystem goes up... */
357static rh_block_t cpm_boot_dpmem_rh_block[16];
358static rh_info_t cpm_dpmem_info;
359static u8 __iomem *im_dprambase;
360
361static void cpm2_dpinit(void)
362{
363 spin_lock_init(&cpm_dpmem_lock);
364
365 /* initialize the info header */
366 rh_init(&cpm_dpmem_info, 1,
367 sizeof(cpm_boot_dpmem_rh_block) /
368 sizeof(cpm_boot_dpmem_rh_block[0]),
369 cpm_boot_dpmem_rh_block);
370
371 im_dprambase = cpm2_immr;
372
373 /* Attach the usable dpmem area */
374 /* XXX: This is actually crap. CPM_DATAONLY_BASE and
375 * CPM_DATAONLY_SIZE is only a subset of the available dpram. It
376 * varies with the processor and the microcode patches activated.
377 * But the following should be at least safe.
378 */
379 rh_attach_region(&cpm_dpmem_info, CPM_DATAONLY_BASE, CPM_DATAONLY_SIZE);
380}
381
382/* This function returns an index into the DPRAM area.
383 */
384unsigned long cpm_dpalloc(uint size, uint align)
385{
386 unsigned long start;
387 unsigned long flags;
388
389 spin_lock_irqsave(&cpm_dpmem_lock, flags);
390 cpm_dpmem_info.alignment = align;
391 start = rh_alloc(&cpm_dpmem_info, size, "commproc");
392 spin_unlock_irqrestore(&cpm_dpmem_lock, flags);
393
394 return (uint)start;
395}
396EXPORT_SYMBOL(cpm_dpalloc);
397
398int cpm_dpfree(unsigned long offset)
399{
400 int ret;
401 unsigned long flags;
402
403 spin_lock_irqsave(&cpm_dpmem_lock, flags);
404 ret = rh_free(&cpm_dpmem_info, offset);
405 spin_unlock_irqrestore(&cpm_dpmem_lock, flags);
406
407 return ret;
408}
409EXPORT_SYMBOL(cpm_dpfree);
410
411/* not sure if this is ever needed */
412unsigned long cpm_dpalloc_fixed(unsigned long offset, uint size, uint align)
413{
414 unsigned long start;
415 unsigned long flags;
416
417 spin_lock_irqsave(&cpm_dpmem_lock, flags);
418 cpm_dpmem_info.alignment = align;
419 start = rh_alloc_fixed(&cpm_dpmem_info, offset, size, "commproc");
420 spin_unlock_irqrestore(&cpm_dpmem_lock, flags);
421
422 return start;
423}
424EXPORT_SYMBOL(cpm_dpalloc_fixed);
425
426void cpm_dpdump(void)
427{
428 rh_dump(&cpm_dpmem_info);
429}
430EXPORT_SYMBOL(cpm_dpdump);
431
432void *cpm_dpram_addr(unsigned long offset)
433{
434 return (void *)(im_dprambase + offset);
435}
436EXPORT_SYMBOL(cpm_dpram_addr);
437#endif /* !CONFIG_PPC_CPM_NEW_BINDING */
438
439struct cpm2_ioports { 348struct cpm2_ioports {
440 u32 dir, par, sor, odr, dat; 349 u32 dir, par, sor, odr, dat;
441 u32 res[3]; 350 u32 res[3];
diff --git a/arch/powerpc/sysdev/cpm_common.c b/arch/powerpc/sysdev/cpm_common.c
index 165981c87786..cb7df2dce44f 100644
--- a/arch/powerpc/sysdev/cpm_common.c
+++ b/arch/powerpc/sysdev/cpm_common.c
@@ -58,7 +58,6 @@ void __init udbg_init_cpm(void)
58} 58}
59#endif 59#endif
60 60
61#ifdef CONFIG_PPC_CPM_NEW_BINDING
62static spinlock_t cpm_muram_lock; 61static spinlock_t cpm_muram_lock;
63static rh_block_t cpm_boot_muram_rh_block[16]; 62static rh_block_t cpm_boot_muram_rh_block[16];
64static rh_info_t cpm_muram_info; 63static rh_info_t cpm_muram_info;
@@ -199,5 +198,3 @@ dma_addr_t cpm_muram_dma(void __iomem *addr)
199 return muram_pbase + ((u8 __iomem *)addr - muram_vbase); 198 return muram_pbase + ((u8 __iomem *)addr - muram_vbase);
200} 199}
201EXPORT_SYMBOL(cpm_muram_dma); 200EXPORT_SYMBOL(cpm_muram_dma);
202
203#endif /* CONFIG_PPC_CPM_NEW_BINDING */
diff --git a/arch/powerpc/sysdev/dart_iommu.c b/arch/powerpc/sysdev/dart_iommu.c
index e0e24b01e3a6..005c2ecf976f 100644
--- a/arch/powerpc/sysdev/dart_iommu.c
+++ b/arch/powerpc/sysdev/dart_iommu.c
@@ -37,6 +37,7 @@
37#include <linux/dma-mapping.h> 37#include <linux/dma-mapping.h>
38#include <linux/vmalloc.h> 38#include <linux/vmalloc.h>
39#include <linux/suspend.h> 39#include <linux/suspend.h>
40#include <linux/lmb.h>
40#include <asm/io.h> 41#include <asm/io.h>
41#include <asm/prom.h> 42#include <asm/prom.h>
42#include <asm/iommu.h> 43#include <asm/iommu.h>
@@ -44,7 +45,6 @@
44#include <asm/machdep.h> 45#include <asm/machdep.h>
45#include <asm/abs_addr.h> 46#include <asm/abs_addr.h>
46#include <asm/cacheflush.h> 47#include <asm/cacheflush.h>
47#include <asm/lmb.h>
48#include <asm/ppc-pci.h> 48#include <asm/ppc-pci.h>
49 49
50#include "dart.h" 50#include "dart.h"
diff --git a/arch/powerpc/sysdev/fsl_lbc.c b/arch/powerpc/sysdev/fsl_lbc.c
new file mode 100644
index 000000000000..422c8faef593
--- /dev/null
+++ b/arch/powerpc/sysdev/fsl_lbc.c
@@ -0,0 +1,129 @@
1/*
2 * Freescale LBC and UPM routines.
3 *
4 * Copyright (c) 2007-2008 MontaVista Software, Inc.
5 *
6 * Author: Anton Vorontsov <avorontsov@ru.mvista.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 */
13
14#include <linux/kernel.h>
15#include <linux/of.h>
16#include <asm/fsl_lbc.h>
17
18spinlock_t fsl_lbc_lock = __SPIN_LOCK_UNLOCKED(fsl_lbc_lock);
19
20struct fsl_lbc_regs __iomem *fsl_lbc_regs;
21EXPORT_SYMBOL(fsl_lbc_regs);
22
23static char __initdata *compat_lbc[] = {
24 "fsl,pq2-localbus",
25 "fsl,pq2pro-localbus",
26 "fsl,pq3-localbus",
27 "fsl,elbc",
28};
29
30static int __init fsl_lbc_init(void)
31{
32 struct device_node *lbus;
33 int i;
34
35 for (i = 0; i < ARRAY_SIZE(compat_lbc); i++) {
36 lbus = of_find_compatible_node(NULL, NULL, compat_lbc[i]);
37 if (lbus)
38 goto found;
39 }
40 return -ENODEV;
41
42found:
43 fsl_lbc_regs = of_iomap(lbus, 0);
44 of_node_put(lbus);
45 if (!fsl_lbc_regs)
46 return -ENOMEM;
47 return 0;
48}
49arch_initcall(fsl_lbc_init);
50
51/**
52 * fsl_lbc_find - find Localbus bank
53 * @addr_base: base address of the memory bank
54 *
55 * This function walks LBC banks comparing "Base address" field of the BR
56 * registers with the supplied addr_base argument. When bases match this
57 * function returns bank number (starting with 0), otherwise it returns
58 * appropriate errno value.
59 */
60int fsl_lbc_find(phys_addr_t addr_base)
61{
62 int i;
63
64 if (!fsl_lbc_regs)
65 return -ENODEV;
66
67 for (i = 0; i < ARRAY_SIZE(fsl_lbc_regs->bank); i++) {
68 __be32 br = in_be32(&fsl_lbc_regs->bank[i].br);
69 __be32 or = in_be32(&fsl_lbc_regs->bank[i].or);
70
71 if (br & BR_V && (br & or & BR_BA) == addr_base)
72 return i;
73 }
74
75 return -ENOENT;
76}
77EXPORT_SYMBOL(fsl_lbc_find);
78
79/**
80 * fsl_upm_find - find pre-programmed UPM via base address
81 * @addr_base: base address of the memory bank controlled by the UPM
82 * @upm: pointer to the allocated fsl_upm structure
83 *
84 * This function fills fsl_upm structure so you can use it with the rest of
85 * UPM API. On success this function returns 0, otherwise it returns
86 * appropriate errno value.
87 */
88int fsl_upm_find(phys_addr_t addr_base, struct fsl_upm *upm)
89{
90 int bank;
91 __be32 br;
92
93 bank = fsl_lbc_find(addr_base);
94 if (bank < 0)
95 return bank;
96
97 br = in_be32(&fsl_lbc_regs->bank[bank].br);
98
99 switch (br & BR_MSEL) {
100 case BR_MS_UPMA:
101 upm->mxmr = &fsl_lbc_regs->mamr;
102 break;
103 case BR_MS_UPMB:
104 upm->mxmr = &fsl_lbc_regs->mbmr;
105 break;
106 case BR_MS_UPMC:
107 upm->mxmr = &fsl_lbc_regs->mcmr;
108 break;
109 default:
110 return -EINVAL;
111 }
112
113 switch (br & BR_PS) {
114 case BR_PS_8:
115 upm->width = 8;
116 break;
117 case BR_PS_16:
118 upm->width = 16;
119 break;
120 case BR_PS_32:
121 upm->width = 32;
122 break;
123 default:
124 return -EINVAL;
125 }
126
127 return 0;
128}
129EXPORT_SYMBOL(fsl_upm_find);
diff --git a/arch/powerpc/sysdev/fsl_soc.c b/arch/powerpc/sysdev/fsl_soc.c
index 3581416905ea..5c1b246aaccc 100644
--- a/arch/powerpc/sysdev/fsl_soc.c
+++ b/arch/powerpc/sysdev/fsl_soc.c
@@ -75,6 +75,33 @@ phys_addr_t get_immrbase(void)
75 75
76EXPORT_SYMBOL(get_immrbase); 76EXPORT_SYMBOL(get_immrbase);
77 77
78static u32 sysfreq = -1;
79
80u32 fsl_get_sys_freq(void)
81{
82 struct device_node *soc;
83 const u32 *prop;
84 int size;
85
86 if (sysfreq != -1)
87 return sysfreq;
88
89 soc = of_find_node_by_type(NULL, "soc");
90 if (!soc)
91 return -1;
92
93 prop = of_get_property(soc, "clock-frequency", &size);
94 if (!prop || size != sizeof(*prop) || *prop == 0)
95 prop = of_get_property(soc, "bus-frequency", &size);
96
97 if (prop && size == sizeof(*prop))
98 sysfreq = *prop;
99
100 of_node_put(soc);
101 return sysfreq;
102}
103EXPORT_SYMBOL(fsl_get_sys_freq);
104
78#if defined(CONFIG_CPM2) || defined(CONFIG_QUICC_ENGINE) || defined(CONFIG_8xx) 105#if defined(CONFIG_CPM2) || defined(CONFIG_QUICC_ENGINE) || defined(CONFIG_8xx)
79 106
80static u32 brgfreq = -1; 107static u32 brgfreq = -1;
@@ -517,9 +544,9 @@ arch_initcall(fsl_i2c_of_init);
517static int __init mpc83xx_wdt_init(void) 544static int __init mpc83xx_wdt_init(void)
518{ 545{
519 struct resource r; 546 struct resource r;
520 struct device_node *soc, *np; 547 struct device_node *np;
521 struct platform_device *dev; 548 struct platform_device *dev;
522 const unsigned int *freq; 549 u32 freq = fsl_get_sys_freq();
523 int ret; 550 int ret;
524 551
525 np = of_find_compatible_node(NULL, "watchdog", "mpc83xx_wdt"); 552 np = of_find_compatible_node(NULL, "watchdog", "mpc83xx_wdt");
@@ -529,19 +556,6 @@ static int __init mpc83xx_wdt_init(void)
529 goto nodev; 556 goto nodev;
530 } 557 }
531 558
532 soc = of_find_node_by_type(NULL, "soc");
533
534 if (!soc) {
535 ret = -ENODEV;
536 goto nosoc;
537 }
538
539 freq = of_get_property(soc, "bus-frequency", NULL);
540 if (!freq) {
541 ret = -ENODEV;
542 goto err;
543 }
544
545 memset(&r, 0, sizeof(r)); 559 memset(&r, 0, sizeof(r));
546 560
547 ret = of_address_to_resource(np, 0, &r); 561 ret = of_address_to_resource(np, 0, &r);
@@ -554,20 +568,16 @@ static int __init mpc83xx_wdt_init(void)
554 goto err; 568 goto err;
555 } 569 }
556 570
557 ret = platform_device_add_data(dev, freq, sizeof(int)); 571 ret = platform_device_add_data(dev, &freq, sizeof(freq));
558 if (ret) 572 if (ret)
559 goto unreg; 573 goto unreg;
560 574
561 of_node_put(soc);
562 of_node_put(np); 575 of_node_put(np);
563
564 return 0; 576 return 0;
565 577
566unreg: 578unreg:
567 platform_device_unregister(dev); 579 platform_device_unregister(dev);
568err: 580err:
569 of_node_put(soc);
570nosoc:
571 of_node_put(np); 581 of_node_put(np);
572nodev: 582nodev:
573 return ret; 583 return ret;
@@ -736,547 +746,6 @@ err:
736 746
737arch_initcall(fsl_usb_of_init); 747arch_initcall(fsl_usb_of_init);
738 748
739#ifndef CONFIG_PPC_CPM_NEW_BINDING
740#ifdef CONFIG_CPM2
741
742extern void init_scc_ioports(struct fs_uart_platform_info*);
743
744static const char fcc_regs[] = "fcc_regs";
745static const char fcc_regs_c[] = "fcc_regs_c";
746static const char fcc_pram[] = "fcc_pram";
747static char bus_id[9][BUS_ID_SIZE];
748
749static int __init fs_enet_of_init(void)
750{
751 struct device_node *np;
752 unsigned int i;
753 struct platform_device *fs_enet_dev;
754 struct resource res;
755 int ret;
756
757 for (np = NULL, i = 0;
758 (np = of_find_compatible_node(np, "network", "fs_enet")) != NULL;
759 i++) {
760 struct resource r[4];
761 struct device_node *phy, *mdio;
762 struct fs_platform_info fs_enet_data;
763 const unsigned int *id, *phy_addr, *phy_irq;
764 const void *mac_addr;
765 const phandle *ph;
766 const char *model;
767
768 memset(r, 0, sizeof(r));
769 memset(&fs_enet_data, 0, sizeof(fs_enet_data));
770
771 ret = of_address_to_resource(np, 0, &r[0]);
772 if (ret)
773 goto err;
774 r[0].name = fcc_regs;
775
776 ret = of_address_to_resource(np, 1, &r[1]);
777 if (ret)
778 goto err;
779 r[1].name = fcc_pram;
780
781 ret = of_address_to_resource(np, 2, &r[2]);
782 if (ret)
783 goto err;
784 r[2].name = fcc_regs_c;
785 fs_enet_data.fcc_regs_c = r[2].start;
786
787 of_irq_to_resource(np, 0, &r[3]);
788
789 fs_enet_dev =
790 platform_device_register_simple("fsl-cpm-fcc", i, &r[0], 4);
791
792 if (IS_ERR(fs_enet_dev)) {
793 ret = PTR_ERR(fs_enet_dev);
794 goto err;
795 }
796
797 model = of_get_property(np, "model", NULL);
798 if (model == NULL) {
799 ret = -ENODEV;
800 goto unreg;
801 }
802
803 mac_addr = of_get_mac_address(np);
804 if (mac_addr)
805 memcpy(fs_enet_data.macaddr, mac_addr, 6);
806
807 ph = of_get_property(np, "phy-handle", NULL);
808 phy = of_find_node_by_phandle(*ph);
809
810 if (phy == NULL) {
811 ret = -ENODEV;
812 goto unreg;
813 }
814
815 phy_addr = of_get_property(phy, "reg", NULL);
816 fs_enet_data.phy_addr = *phy_addr;
817
818 phy_irq = of_get_property(phy, "interrupts", NULL);
819
820 id = of_get_property(np, "device-id", NULL);
821 fs_enet_data.fs_no = *id;
822 strcpy(fs_enet_data.fs_type, model);
823
824 mdio = of_get_parent(phy);
825 ret = of_address_to_resource(mdio, 0, &res);
826 if (ret) {
827 of_node_put(phy);
828 of_node_put(mdio);
829 goto unreg;
830 }
831
832 fs_enet_data.clk_rx = *((u32 *)of_get_property(np,
833 "rx-clock", NULL));
834 fs_enet_data.clk_tx = *((u32 *)of_get_property(np,
835 "tx-clock", NULL));
836
837 if (strstr(model, "FCC")) {
838 int fcc_index = *id - 1;
839 const unsigned char *mdio_bb_prop;
840
841 fs_enet_data.dpram_offset = (u32)cpm_dpram_addr(0);
842 fs_enet_data.rx_ring = 32;
843 fs_enet_data.tx_ring = 32;
844 fs_enet_data.rx_copybreak = 240;
845 fs_enet_data.use_napi = 0;
846 fs_enet_data.napi_weight = 17;
847 fs_enet_data.mem_offset = FCC_MEM_OFFSET(fcc_index);
848 fs_enet_data.cp_page = CPM_CR_FCC_PAGE(fcc_index);
849 fs_enet_data.cp_block = CPM_CR_FCC_SBLOCK(fcc_index);
850
851 snprintf((char*)&bus_id[(*id)], BUS_ID_SIZE, "%x:%02x",
852 (u32)res.start, fs_enet_data.phy_addr);
853 fs_enet_data.bus_id = (char*)&bus_id[(*id)];
854 fs_enet_data.init_ioports = init_fcc_ioports;
855
856 mdio_bb_prop = of_get_property(phy, "bitbang", NULL);
857 if (mdio_bb_prop) {
858 struct platform_device *fs_enet_mdio_bb_dev;
859 struct fs_mii_bb_platform_info fs_enet_mdio_bb_data;
860
861 fs_enet_mdio_bb_dev =
862 platform_device_register_simple("fsl-bb-mdio",
863 i, NULL, 0);
864 memset(&fs_enet_mdio_bb_data, 0,
865 sizeof(struct fs_mii_bb_platform_info));
866 fs_enet_mdio_bb_data.mdio_dat.bit =
867 mdio_bb_prop[0];
868 fs_enet_mdio_bb_data.mdio_dir.bit =
869 mdio_bb_prop[1];
870 fs_enet_mdio_bb_data.mdc_dat.bit =
871 mdio_bb_prop[2];
872 fs_enet_mdio_bb_data.mdio_port =
873 mdio_bb_prop[3];
874 fs_enet_mdio_bb_data.mdc_port =
875 mdio_bb_prop[4];
876 fs_enet_mdio_bb_data.delay =
877 mdio_bb_prop[5];
878
879 fs_enet_mdio_bb_data.irq[0] = phy_irq[0];
880 fs_enet_mdio_bb_data.irq[1] = -1;
881 fs_enet_mdio_bb_data.irq[2] = -1;
882 fs_enet_mdio_bb_data.irq[3] = phy_irq[0];
883 fs_enet_mdio_bb_data.irq[31] = -1;
884
885 fs_enet_mdio_bb_data.mdio_dat.offset =
886 (u32)&cpm2_immr->im_ioport.iop_pdatc;
887 fs_enet_mdio_bb_data.mdio_dir.offset =
888 (u32)&cpm2_immr->im_ioport.iop_pdirc;
889 fs_enet_mdio_bb_data.mdc_dat.offset =
890 (u32)&cpm2_immr->im_ioport.iop_pdatc;
891
892 ret = platform_device_add_data(
893 fs_enet_mdio_bb_dev,
894 &fs_enet_mdio_bb_data,
895 sizeof(struct fs_mii_bb_platform_info));
896 if (ret)
897 goto unreg;
898 }
899
900 of_node_put(phy);
901 of_node_put(mdio);
902
903 ret = platform_device_add_data(fs_enet_dev, &fs_enet_data,
904 sizeof(struct
905 fs_platform_info));
906 if (ret)
907 goto unreg;
908 }
909 }
910 return 0;
911
912unreg:
913 platform_device_unregister(fs_enet_dev);
914err:
915 return ret;
916}
917
918arch_initcall(fs_enet_of_init);
919
920static const char scc_regs[] = "regs";
921static const char scc_pram[] = "pram";
922
923static int __init cpm_uart_of_init(void)
924{
925 struct device_node *np;
926 unsigned int i;
927 struct platform_device *cpm_uart_dev;
928 int ret;
929
930 for (np = NULL, i = 0;
931 (np = of_find_compatible_node(np, "serial", "cpm_uart")) != NULL;
932 i++) {
933 struct resource r[3];
934 struct fs_uart_platform_info cpm_uart_data;
935 const int *id;
936 const char *model;
937
938 memset(r, 0, sizeof(r));
939 memset(&cpm_uart_data, 0, sizeof(cpm_uart_data));
940
941 ret = of_address_to_resource(np, 0, &r[0]);
942 if (ret)
943 goto err;
944
945 r[0].name = scc_regs;
946
947 ret = of_address_to_resource(np, 1, &r[1]);
948 if (ret)
949 goto err;
950 r[1].name = scc_pram;
951
952 of_irq_to_resource(np, 0, &r[2]);
953
954 cpm_uart_dev =
955 platform_device_register_simple("fsl-cpm-scc:uart", i, &r[0], 3);
956
957 if (IS_ERR(cpm_uart_dev)) {
958 ret = PTR_ERR(cpm_uart_dev);
959 goto err;
960 }
961
962 id = of_get_property(np, "device-id", NULL);
963 cpm_uart_data.fs_no = *id;
964
965 model = of_get_property(np, "model", NULL);
966 strcpy(cpm_uart_data.fs_type, model);
967
968 cpm_uart_data.uart_clk = ppc_proc_freq;
969
970 cpm_uart_data.tx_num_fifo = 4;
971 cpm_uart_data.tx_buf_size = 32;
972 cpm_uart_data.rx_num_fifo = 4;
973 cpm_uart_data.rx_buf_size = 32;
974 cpm_uart_data.clk_rx = *((u32 *)of_get_property(np,
975 "rx-clock", NULL));
976 cpm_uart_data.clk_tx = *((u32 *)of_get_property(np,
977 "tx-clock", NULL));
978
979 ret =
980 platform_device_add_data(cpm_uart_dev, &cpm_uart_data,
981 sizeof(struct
982 fs_uart_platform_info));
983 if (ret)
984 goto unreg;
985 }
986
987 return 0;
988
989unreg:
990 platform_device_unregister(cpm_uart_dev);
991err:
992 return ret;
993}
994
995arch_initcall(cpm_uart_of_init);
996#endif /* CONFIG_CPM2 */
997
998#ifdef CONFIG_8xx
999
1000extern void init_scc_ioports(struct fs_platform_info*);
1001extern int platform_device_skip(const char *model, int id);
1002
1003static int __init fs_enet_mdio_of_init(void)
1004{
1005 struct device_node *np;
1006 unsigned int i;
1007 struct platform_device *mdio_dev;
1008 struct resource res;
1009 int ret;
1010
1011 for (np = NULL, i = 0;
1012 (np = of_find_compatible_node(np, "mdio", "fs_enet")) != NULL;
1013 i++) {
1014 struct fs_mii_fec_platform_info mdio_data;
1015
1016 memset(&res, 0, sizeof(res));
1017 memset(&mdio_data, 0, sizeof(mdio_data));
1018
1019 ret = of_address_to_resource(np, 0, &res);
1020 if (ret)
1021 goto err;
1022
1023 mdio_dev =
1024 platform_device_register_simple("fsl-cpm-fec-mdio",
1025 res.start, &res, 1);
1026 if (IS_ERR(mdio_dev)) {
1027 ret = PTR_ERR(mdio_dev);
1028 goto err;
1029 }
1030
1031 mdio_data.mii_speed = ((((ppc_proc_freq + 4999999) / 2500000) / 2) & 0x3F) << 1;
1032
1033 ret =
1034 platform_device_add_data(mdio_dev, &mdio_data,
1035 sizeof(struct fs_mii_fec_platform_info));
1036 if (ret)
1037 goto unreg;
1038 }
1039 return 0;
1040
1041unreg:
1042 platform_device_unregister(mdio_dev);
1043err:
1044 return ret;
1045}
1046
1047arch_initcall(fs_enet_mdio_of_init);
1048
1049static const char *enet_regs = "regs";
1050static const char *enet_pram = "pram";
1051static const char *enet_irq = "interrupt";
1052static char bus_id[9][BUS_ID_SIZE];
1053
1054static int __init fs_enet_of_init(void)
1055{
1056 struct device_node *np;
1057 unsigned int i;
1058 struct platform_device *fs_enet_dev = NULL;
1059 struct resource res;
1060 int ret;
1061
1062 for (np = NULL, i = 0;
1063 (np = of_find_compatible_node(np, "network", "fs_enet")) != NULL;
1064 i++) {
1065 struct resource r[4];
1066 struct device_node *phy = NULL, *mdio = NULL;
1067 struct fs_platform_info fs_enet_data;
1068 const unsigned int *id;
1069 const unsigned int *phy_addr;
1070 const void *mac_addr;
1071 const phandle *ph;
1072 const char *model;
1073
1074 memset(r, 0, sizeof(r));
1075 memset(&fs_enet_data, 0, sizeof(fs_enet_data));
1076
1077 model = of_get_property(np, "model", NULL);
1078 if (model == NULL) {
1079 ret = -ENODEV;
1080 goto unreg;
1081 }
1082
1083 id = of_get_property(np, "device-id", NULL);
1084 fs_enet_data.fs_no = *id;
1085
1086 if (platform_device_skip(model, *id))
1087 continue;
1088
1089 ret = of_address_to_resource(np, 0, &r[0]);
1090 if (ret)
1091 goto err;
1092 r[0].name = enet_regs;
1093
1094 mac_addr = of_get_mac_address(np);
1095 if (mac_addr)
1096 memcpy(fs_enet_data.macaddr, mac_addr, 6);
1097
1098 ph = of_get_property(np, "phy-handle", NULL);
1099 if (ph != NULL)
1100 phy = of_find_node_by_phandle(*ph);
1101
1102 if (phy != NULL) {
1103 phy_addr = of_get_property(phy, "reg", NULL);
1104 fs_enet_data.phy_addr = *phy_addr;
1105 fs_enet_data.has_phy = 1;
1106
1107 mdio = of_get_parent(phy);
1108 ret = of_address_to_resource(mdio, 0, &res);
1109 if (ret) {
1110 of_node_put(phy);
1111 of_node_put(mdio);
1112 goto unreg;
1113 }
1114 }
1115
1116 model = of_get_property(np, "model", NULL);
1117 strcpy(fs_enet_data.fs_type, model);
1118
1119 if (strstr(model, "FEC")) {
1120 r[1].start = r[1].end = irq_of_parse_and_map(np, 0);
1121 r[1].flags = IORESOURCE_IRQ;
1122 r[1].name = enet_irq;
1123
1124 fs_enet_dev =
1125 platform_device_register_simple("fsl-cpm-fec", i, &r[0], 2);
1126
1127 if (IS_ERR(fs_enet_dev)) {
1128 ret = PTR_ERR(fs_enet_dev);
1129 goto err;
1130 }
1131
1132 fs_enet_data.rx_ring = 128;
1133 fs_enet_data.tx_ring = 16;
1134 fs_enet_data.rx_copybreak = 240;
1135 fs_enet_data.use_napi = 1;
1136 fs_enet_data.napi_weight = 17;
1137
1138 snprintf((char*)&bus_id[i], BUS_ID_SIZE, "%x:%02x",
1139 (u32)res.start, fs_enet_data.phy_addr);
1140 fs_enet_data.bus_id = (char*)&bus_id[i];
1141 fs_enet_data.init_ioports = init_fec_ioports;
1142 }
1143 if (strstr(model, "SCC")) {
1144 ret = of_address_to_resource(np, 1, &r[1]);
1145 if (ret)
1146 goto err;
1147 r[1].name = enet_pram;
1148
1149 r[2].start = r[2].end = irq_of_parse_and_map(np, 0);
1150 r[2].flags = IORESOURCE_IRQ;
1151 r[2].name = enet_irq;
1152
1153 fs_enet_dev =
1154 platform_device_register_simple("fsl-cpm-scc", i, &r[0], 3);
1155
1156 if (IS_ERR(fs_enet_dev)) {
1157 ret = PTR_ERR(fs_enet_dev);
1158 goto err;
1159 }
1160
1161 fs_enet_data.rx_ring = 64;
1162 fs_enet_data.tx_ring = 8;
1163 fs_enet_data.rx_copybreak = 240;
1164 fs_enet_data.use_napi = 1;
1165 fs_enet_data.napi_weight = 17;
1166
1167 snprintf((char*)&bus_id[i], BUS_ID_SIZE, "%s", "fixed@10:1");
1168 fs_enet_data.bus_id = (char*)&bus_id[i];
1169 fs_enet_data.init_ioports = init_scc_ioports;
1170 }
1171
1172 of_node_put(phy);
1173 of_node_put(mdio);
1174
1175 ret = platform_device_add_data(fs_enet_dev, &fs_enet_data,
1176 sizeof(struct
1177 fs_platform_info));
1178 if (ret)
1179 goto unreg;
1180 }
1181 return 0;
1182
1183unreg:
1184 platform_device_unregister(fs_enet_dev);
1185err:
1186 return ret;
1187}
1188
1189arch_initcall(fs_enet_of_init);
1190
1191static int __init fsl_pcmcia_of_init(void)
1192{
1193 struct device_node *np;
1194 /*
1195 * Register all the devices which type is "pcmcia"
1196 */
1197 for_each_compatible_node(np, "pcmcia", "fsl,pq-pcmcia")
1198 of_platform_device_create(np, "m8xx-pcmcia", NULL);
1199 return 0;
1200}
1201
1202arch_initcall(fsl_pcmcia_of_init);
1203
1204static const char *smc_regs = "regs";
1205static const char *smc_pram = "pram";
1206
1207static int __init cpm_smc_uart_of_init(void)
1208{
1209 struct device_node *np;
1210 unsigned int i;
1211 struct platform_device *cpm_uart_dev;
1212 int ret;
1213
1214 for (np = NULL, i = 0;
1215 (np = of_find_compatible_node(np, "serial", "cpm_uart")) != NULL;
1216 i++) {
1217 struct resource r[3];
1218 struct fs_uart_platform_info cpm_uart_data;
1219 const int *id;
1220 const char *model;
1221
1222 memset(r, 0, sizeof(r));
1223 memset(&cpm_uart_data, 0, sizeof(cpm_uart_data));
1224
1225 ret = of_address_to_resource(np, 0, &r[0]);
1226 if (ret)
1227 goto err;
1228
1229 r[0].name = smc_regs;
1230
1231 ret = of_address_to_resource(np, 1, &r[1]);
1232 if (ret)
1233 goto err;
1234 r[1].name = smc_pram;
1235
1236 r[2].start = r[2].end = irq_of_parse_and_map(np, 0);
1237 r[2].flags = IORESOURCE_IRQ;
1238
1239 cpm_uart_dev =
1240 platform_device_register_simple("fsl-cpm-smc:uart", i, &r[0], 3);
1241
1242 if (IS_ERR(cpm_uart_dev)) {
1243 ret = PTR_ERR(cpm_uart_dev);
1244 goto err;
1245 }
1246
1247 model = of_get_property(np, "model", NULL);
1248 strcpy(cpm_uart_data.fs_type, model);
1249
1250 id = of_get_property(np, "device-id", NULL);
1251 cpm_uart_data.fs_no = *id;
1252 cpm_uart_data.uart_clk = ppc_proc_freq;
1253
1254 cpm_uart_data.tx_num_fifo = 4;
1255 cpm_uart_data.tx_buf_size = 32;
1256 cpm_uart_data.rx_num_fifo = 4;
1257 cpm_uart_data.rx_buf_size = 32;
1258
1259 ret =
1260 platform_device_add_data(cpm_uart_dev, &cpm_uart_data,
1261 sizeof(struct
1262 fs_uart_platform_info));
1263 if (ret)
1264 goto unreg;
1265 }
1266
1267 return 0;
1268
1269unreg:
1270 platform_device_unregister(cpm_uart_dev);
1271err:
1272 return ret;
1273}
1274
1275arch_initcall(cpm_smc_uart_of_init);
1276
1277#endif /* CONFIG_8xx */
1278#endif /* CONFIG_PPC_CPM_NEW_BINDING */
1279
1280static int __init of_fsl_spi_probe(char *type, char *compatible, u32 sysclk, 749static int __init of_fsl_spi_probe(char *type, char *compatible, u32 sysclk,
1281 struct spi_board_info *board_infos, 750 struct spi_board_info *board_infos,
1282 unsigned int num_board_infos, 751 unsigned int num_board_infos,
@@ -1372,25 +841,9 @@ int __init fsl_spi_init(struct spi_board_info *board_infos,
1372 sysclk = get_brgfreq(); 841 sysclk = get_brgfreq();
1373#endif 842#endif
1374 if (sysclk == -1) { 843 if (sysclk == -1) {
1375 struct device_node *np; 844 sysclk = fsl_get_sys_freq();
1376 const u32 *freq; 845 if (sysclk == -1)
1377 int size;
1378
1379 np = of_find_node_by_type(NULL, "soc");
1380 if (!np)
1381 return -ENODEV; 846 return -ENODEV;
1382
1383 freq = of_get_property(np, "clock-frequency", &size);
1384 if (!freq || size != sizeof(*freq) || *freq == 0) {
1385 freq = of_get_property(np, "bus-frequency", &size);
1386 if (!freq || size != sizeof(*freq) || *freq == 0) {
1387 of_node_put(np);
1388 return -ENODEV;
1389 }
1390 }
1391
1392 sysclk = *freq;
1393 of_node_put(np);
1394 } 847 }
1395 848
1396 ret = of_fsl_spi_probe(NULL, "fsl,spi", sysclk, board_infos, 849 ret = of_fsl_spi_probe(NULL, "fsl,spi", sysclk, board_infos,
diff --git a/arch/powerpc/sysdev/fsl_soc.h b/arch/powerpc/sysdev/fsl_soc.h
index 63e7db30a4cd..74c4a9657b33 100644
--- a/arch/powerpc/sysdev/fsl_soc.h
+++ b/arch/powerpc/sysdev/fsl_soc.h
@@ -7,6 +7,7 @@
7extern phys_addr_t get_immrbase(void); 7extern phys_addr_t get_immrbase(void);
8extern u32 get_brgfreq(void); 8extern u32 get_brgfreq(void);
9extern u32 get_baudrate(void); 9extern u32 get_baudrate(void);
10extern u32 fsl_get_sys_freq(void);
10 11
11struct spi_board_info; 12struct spi_board_info;
12 13
diff --git a/arch/powerpc/sysdev/mpic.c b/arch/powerpc/sysdev/mpic.c
index 6ffdda244bb1..8619f2a3f1f6 100644
--- a/arch/powerpc/sysdev/mpic.c
+++ b/arch/powerpc/sysdev/mpic.c
@@ -175,13 +175,16 @@ static inline void _mpic_write(enum mpic_reg_type type,
175 switch(type) { 175 switch(type) {
176#ifdef CONFIG_PPC_DCR 176#ifdef CONFIG_PPC_DCR
177 case mpic_access_dcr: 177 case mpic_access_dcr:
178 return dcr_write(rb->dhost, reg, value); 178 dcr_write(rb->dhost, reg, value);
179 break;
179#endif 180#endif
180 case mpic_access_mmio_be: 181 case mpic_access_mmio_be:
181 return out_be32(rb->base + (reg >> 2), value); 182 out_be32(rb->base + (reg >> 2), value);
183 break;
182 case mpic_access_mmio_le: 184 case mpic_access_mmio_le:
183 default: 185 default:
184 return out_le32(rb->base + (reg >> 2), value); 186 out_le32(rb->base + (reg >> 2), value);
187 break;
185 } 188 }
186} 189}
187 190
@@ -1000,7 +1003,7 @@ struct mpic * __init mpic_alloc(struct device_node *node,
1000 const char *name) 1003 const char *name)
1001{ 1004{
1002 struct mpic *mpic; 1005 struct mpic *mpic;
1003 u32 reg; 1006 u32 greg_feature;
1004 const char *vers; 1007 const char *vers;
1005 int i; 1008 int i;
1006 int intvec_top; 1009 int intvec_top;
@@ -1064,7 +1067,8 @@ struct mpic * __init mpic_alloc(struct device_node *node,
1064 1067
1065 /* Look for protected sources */ 1068 /* Look for protected sources */
1066 if (node) { 1069 if (node) {
1067 unsigned int psize, bits, mapsize; 1070 int psize;
1071 unsigned int bits, mapsize;
1068 const u32 *psrc = 1072 const u32 *psrc =
1069 of_get_property(node, "protected-sources", &psize); 1073 of_get_property(node, "protected-sources", &psize);
1070 if (psrc) { 1074 if (psrc) {
@@ -1107,8 +1111,7 @@ struct mpic * __init mpic_alloc(struct device_node *node,
1107 * in, try to obtain one 1111 * in, try to obtain one
1108 */ 1112 */
1109 if (paddr == 0 && !(mpic->flags & MPIC_USES_DCR)) { 1113 if (paddr == 0 && !(mpic->flags & MPIC_USES_DCR)) {
1110 const u32 *reg; 1114 const u32 *reg = of_get_property(node, "reg", NULL);
1111 reg = of_get_property(node, "reg", NULL);
1112 BUG_ON(reg == NULL); 1115 BUG_ON(reg == NULL);
1113 paddr = of_translate_address(node, reg); 1116 paddr = of_translate_address(node, reg);
1114 BUG_ON(paddr == OF_BAD_ADDR); 1117 BUG_ON(paddr == OF_BAD_ADDR);
@@ -1137,12 +1140,13 @@ struct mpic * __init mpic_alloc(struct device_node *node,
1137 * MPICs, num sources as well. On ISU MPICs, sources are counted 1140 * MPICs, num sources as well. On ISU MPICs, sources are counted
1138 * as ISUs are added 1141 * as ISUs are added
1139 */ 1142 */
1140 reg = mpic_read(mpic->gregs, MPIC_INFO(GREG_FEATURE_0)); 1143 greg_feature = mpic_read(mpic->gregs, MPIC_INFO(GREG_FEATURE_0));
1141 mpic->num_cpus = ((reg & MPIC_GREG_FEATURE_LAST_CPU_MASK) 1144 mpic->num_cpus = ((greg_feature & MPIC_GREG_FEATURE_LAST_CPU_MASK)
1142 >> MPIC_GREG_FEATURE_LAST_CPU_SHIFT) + 1; 1145 >> MPIC_GREG_FEATURE_LAST_CPU_SHIFT) + 1;
1143 if (isu_size == 0) 1146 if (isu_size == 0)
1144 mpic->num_sources = ((reg & MPIC_GREG_FEATURE_LAST_SRC_MASK) 1147 mpic->num_sources =
1145 >> MPIC_GREG_FEATURE_LAST_SRC_SHIFT) + 1; 1148 ((greg_feature & MPIC_GREG_FEATURE_LAST_SRC_MASK)
1149 >> MPIC_GREG_FEATURE_LAST_SRC_SHIFT) + 1;
1146 1150
1147 /* Map the per-CPU registers */ 1151 /* Map the per-CPU registers */
1148 for (i = 0; i < mpic->num_cpus; i++) { 1152 for (i = 0; i < mpic->num_cpus; i++) {
@@ -1161,7 +1165,7 @@ struct mpic * __init mpic_alloc(struct device_node *node,
1161 mpic->isu_mask = (1 << mpic->isu_shift) - 1; 1165 mpic->isu_mask = (1 << mpic->isu_shift) - 1;
1162 1166
1163 /* Display version */ 1167 /* Display version */
1164 switch (reg & MPIC_GREG_FEATURE_VERSION_MASK) { 1168 switch (greg_feature & MPIC_GREG_FEATURE_VERSION_MASK) {
1165 case 1: 1169 case 1:
1166 vers = "1.0"; 1170 vers = "1.0";
1167 break; 1171 break;
@@ -1321,7 +1325,7 @@ void __init mpic_set_serial_int(struct mpic *mpic, int enable)
1321 1325
1322void mpic_irq_set_priority(unsigned int irq, unsigned int pri) 1326void mpic_irq_set_priority(unsigned int irq, unsigned int pri)
1323{ 1327{
1324 int is_ipi; 1328 unsigned int is_ipi;
1325 struct mpic *mpic = mpic_find(irq, &is_ipi); 1329 struct mpic *mpic = mpic_find(irq, &is_ipi);
1326 unsigned int src = mpic_irq_to_hw(irq); 1330 unsigned int src = mpic_irq_to_hw(irq);
1327 unsigned long flags; 1331 unsigned long flags;
@@ -1344,7 +1348,7 @@ void mpic_irq_set_priority(unsigned int irq, unsigned int pri)
1344 1348
1345unsigned int mpic_irq_get_priority(unsigned int irq) 1349unsigned int mpic_irq_get_priority(unsigned int irq)
1346{ 1350{
1347 int is_ipi; 1351 unsigned int is_ipi;
1348 struct mpic *mpic = mpic_find(irq, &is_ipi); 1352 struct mpic *mpic = mpic_find(irq, &is_ipi);
1349 unsigned int src = mpic_irq_to_hw(irq); 1353 unsigned int src = mpic_irq_to_hw(irq);
1350 unsigned long flags; 1354 unsigned long flags;
@@ -1406,11 +1410,6 @@ void mpic_cpu_set_priority(int prio)
1406 mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), prio); 1410 mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), prio);
1407} 1411}
1408 1412
1409/*
1410 * XXX: someone who knows mpic should check this.
1411 * do we need to eoi the ipi including for kexec cpu here (see xics comments)?
1412 * or can we reset the mpic in the new kernel?
1413 */
1414void mpic_teardown_this_cpu(int secondary) 1413void mpic_teardown_this_cpu(int secondary)
1415{ 1414{
1416 struct mpic *mpic = mpic_primary; 1415 struct mpic *mpic = mpic_primary;
@@ -1430,6 +1429,10 @@ void mpic_teardown_this_cpu(int secondary)
1430 1429
1431 /* Set current processor priority to max */ 1430 /* Set current processor priority to max */
1432 mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0xf); 1431 mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0xf);
1432 /* We need to EOI the IPI since not all platforms reset the MPIC
1433 * on boot and new interrupts wouldn't get delivered otherwise.
1434 */
1435 mpic_eoi(mpic);
1433 1436
1434 spin_unlock_irqrestore(&mpic_lock, flags); 1437 spin_unlock_irqrestore(&mpic_lock, flags);
1435} 1438}
diff --git a/arch/powerpc/sysdev/mv64x60_dev.c b/arch/powerpc/sysdev/mv64x60_dev.c
index efda0028909d..047b31027fa6 100644
--- a/arch/powerpc/sysdev/mv64x60_dev.c
+++ b/arch/powerpc/sysdev/mv64x60_dev.c
@@ -127,7 +127,7 @@ static int __init mv64x60_mpsc_device_setup(struct device_node *np, int id)
127 if (err) 127 if (err)
128 return err; 128 return err;
129 129
130 prop = of_get_property(np, "block-index", NULL); 130 prop = of_get_property(np, "cell-index", NULL);
131 if (!prop) 131 if (!prop)
132 return -ENODEV; 132 return -ENODEV;
133 port_number = *(int *)prop; 133 port_number = *(int *)prop;
@@ -136,6 +136,7 @@ static int __init mv64x60_mpsc_device_setup(struct device_node *np, int id)
136 136
137 pdata.cache_mgmt = 1; /* All current revs need this set */ 137 pdata.cache_mgmt = 1; /* All current revs need this set */
138 138
139 pdata.max_idle = 40; /* default */
139 prop = of_get_property(np, "max_idle", NULL); 140 prop = of_get_property(np, "max_idle", NULL);
140 if (prop) 141 if (prop)
141 pdata.max_idle = *prop; 142 pdata.max_idle = *prop;
@@ -205,30 +206,24 @@ error:
205/* 206/*
206 * Create mv64x60_eth platform devices 207 * Create mv64x60_eth platform devices
207 */ 208 */
208static int __init eth_register_shared_pdev(struct device_node *np) 209static struct platform_device * __init mv64x60_eth_register_shared_pdev(
210 struct device_node *np, int id)
209{ 211{
210 struct platform_device *pdev; 212 struct platform_device *pdev;
211 struct resource r[1]; 213 struct resource r[1];
212 int err; 214 int err;
213 215
214 np = of_get_parent(np);
215 if (!np)
216 return -ENODEV;
217
218 err = of_address_to_resource(np, 0, &r[0]); 216 err = of_address_to_resource(np, 0, &r[0]);
219 of_node_put(np);
220 if (err) 217 if (err)
221 return err; 218 return ERR_PTR(err);
222 219
223 pdev = platform_device_register_simple(MV643XX_ETH_SHARED_NAME, 0, 220 pdev = platform_device_register_simple(MV643XX_ETH_SHARED_NAME, id,
224 r, 1); 221 r, 1);
225 if (IS_ERR(pdev)) 222 return pdev;
226 return PTR_ERR(pdev);
227
228 return 0;
229} 223}
230 224
231static int __init mv64x60_eth_device_setup(struct device_node *np, int id) 225static int __init mv64x60_eth_device_setup(struct device_node *np, int id,
226 struct platform_device *shared_pdev)
232{ 227{
233 struct resource r[1]; 228 struct resource r[1];
234 struct mv643xx_eth_platform_data pdata; 229 struct mv643xx_eth_platform_data pdata;
@@ -239,16 +234,12 @@ static int __init mv64x60_eth_device_setup(struct device_node *np, int id)
239 const phandle *ph; 234 const phandle *ph;
240 int err; 235 int err;
241 236
242 /* only register the shared platform device the first time through */
243 if (id == 0 && (err = eth_register_shared_pdev(np)))
244 return err;
245
246 memset(r, 0, sizeof(r)); 237 memset(r, 0, sizeof(r));
247 of_irq_to_resource(np, 0, &r[0]); 238 of_irq_to_resource(np, 0, &r[0]);
248 239
249 memset(&pdata, 0, sizeof(pdata)); 240 memset(&pdata, 0, sizeof(pdata));
250 241
251 prop = of_get_property(np, "block-index", NULL); 242 prop = of_get_property(np, "reg", NULL);
252 if (!prop) 243 if (!prop)
253 return -ENODEV; 244 return -ENODEV;
254 pdata.port_number = *prop; 245 pdata.port_number = *prop;
@@ -301,7 +292,7 @@ static int __init mv64x60_eth_device_setup(struct device_node *np, int id)
301 292
302 of_node_put(phy); 293 of_node_put(phy);
303 294
304 pdev = platform_device_alloc(MV643XX_ETH_NAME, pdata.port_number); 295 pdev = platform_device_alloc(MV643XX_ETH_NAME, id);
305 if (!pdev) 296 if (!pdev)
306 return -ENOMEM; 297 return -ENOMEM;
307 298
@@ -345,21 +336,19 @@ static int __init mv64x60_i2c_device_setup(struct device_node *np, int id)
345 336
346 memset(&pdata, 0, sizeof(pdata)); 337 memset(&pdata, 0, sizeof(pdata));
347 338
339 pdata.freq_m = 8; /* default */
348 prop = of_get_property(np, "freq_m", NULL); 340 prop = of_get_property(np, "freq_m", NULL);
349 if (!prop) 341 if (!prop)
350 return -ENODEV; 342 return -ENODEV;
351 pdata.freq_m = *prop; 343 pdata.freq_m = *prop;
352 344
345 pdata.freq_m = 3; /* default */
353 prop = of_get_property(np, "freq_n", NULL); 346 prop = of_get_property(np, "freq_n", NULL);
354 if (!prop) 347 if (!prop)
355 return -ENODEV; 348 return -ENODEV;
356 pdata.freq_n = *prop; 349 pdata.freq_n = *prop;
357 350
358 prop = of_get_property(np, "timeout", NULL); 351 pdata.timeout = 1000; /* default: 1 second */
359 if (prop)
360 pdata.timeout = *prop;
361 else
362 pdata.timeout = 1000; /* 1 second */
363 352
364 pdev = platform_device_alloc(MV64XXX_I2C_CTLR_NAME, id); 353 pdev = platform_device_alloc(MV64XXX_I2C_CTLR_NAME, id);
365 if (!pdev) 354 if (!pdev)
@@ -401,10 +390,7 @@ static int __init mv64x60_wdt_device_setup(struct device_node *np, int id)
401 390
402 memset(&pdata, 0, sizeof(pdata)); 391 memset(&pdata, 0, sizeof(pdata));
403 392
404 prop = of_get_property(np, "timeout", NULL); 393 pdata.timeout = 10; /* Default: 10 seconds */
405 if (!prop)
406 return -ENODEV;
407 pdata.timeout = *prop;
408 394
409 np = of_get_parent(np); 395 np = of_get_parent(np);
410 if (!np) 396 if (!np)
@@ -441,27 +427,43 @@ error:
441 427
442static int __init mv64x60_device_setup(void) 428static int __init mv64x60_device_setup(void)
443{ 429{
444 struct device_node *np = NULL; 430 struct device_node *np, *np2;
445 int id; 431 struct platform_device *pdev;
432 int id, id2;
446 int err; 433 int err;
447 434
448 id = 0; 435 id = 0;
449 for_each_compatible_node(np, "serial", "marvell,mpsc") 436 for_each_compatible_node(np, "serial", "marvell,mv64360-mpsc")
450 if ((err = mv64x60_mpsc_device_setup(np, id++))) 437 if ((err = mv64x60_mpsc_device_setup(np, id++)))
451 goto error; 438 goto error;
452 439
453 id = 0; 440 id = 0;
454 for_each_compatible_node(np, "network", "marvell,mv64x60-eth") 441 id2 = 0;
455 if ((err = mv64x60_eth_device_setup(np, id++))) 442 for_each_compatible_node(np, NULL, "marvell,mv64360-eth-group") {
443 pdev = mv64x60_eth_register_shared_pdev(np, id++);
444 if (IS_ERR(pdev)) {
445 err = PTR_ERR(pdev);
456 goto error; 446 goto error;
447 }
448 for_each_child_of_node(np, np2) {
449 if (!of_device_is_compatible(np2,
450 "marvell,mv64360-eth"))
451 continue;
452 err = mv64x60_eth_device_setup(np2, id2++, pdev);
453 if (err) {
454 of_node_put(np2);
455 goto error;
456 }
457 }
458 }
457 459
458 id = 0; 460 id = 0;
459 for_each_compatible_node(np, "i2c", "marvell,mv64x60-i2c") 461 for_each_compatible_node(np, "i2c", "marvell,mv64360-i2c")
460 if ((err = mv64x60_i2c_device_setup(np, id++))) 462 if ((err = mv64x60_i2c_device_setup(np, id++)))
461 goto error; 463 goto error;
462 464
463 /* support up to one watchdog timer */ 465 /* support up to one watchdog timer */
464 np = of_find_compatible_node(np, NULL, "marvell,mv64x60-wdt"); 466 np = of_find_compatible_node(np, NULL, "marvell,mv64360-wdt");
465 if (np) { 467 if (np) {
466 if ((err = mv64x60_wdt_device_setup(np, id))) 468 if ((err = mv64x60_wdt_device_setup(np, id)))
467 goto error; 469 goto error;
@@ -489,10 +491,10 @@ static int __init mv64x60_add_mpsc_console(void)
489 if (!np) 491 if (!np)
490 goto not_mpsc; 492 goto not_mpsc;
491 493
492 if (!of_device_is_compatible(np, "marvell,mpsc")) 494 if (!of_device_is_compatible(np, "marvell,mv64360-mpsc"))
493 goto not_mpsc; 495 goto not_mpsc;
494 496
495 prop = of_get_property(np, "block-index", NULL); 497 prop = of_get_property(np, "cell-index", NULL);
496 if (!prop) 498 if (!prop)
497 goto not_mpsc; 499 goto not_mpsc;
498 500
diff --git a/arch/powerpc/sysdev/mv64x60_pci.c b/arch/powerpc/sysdev/mv64x60_pci.c
index d21ab8fa4993..1456015a22d8 100644
--- a/arch/powerpc/sysdev/mv64x60_pci.c
+++ b/arch/powerpc/sysdev/mv64x60_pci.c
@@ -86,14 +86,14 @@ static int __init mv64x60_sysfs_init(void)
86 struct platform_device *pdev; 86 struct platform_device *pdev;
87 const unsigned int *prop; 87 const unsigned int *prop;
88 88
89 np = of_find_compatible_node(NULL, NULL, "marvell,mv64x60"); 89 np = of_find_compatible_node(NULL, NULL, "marvell,mv64360");
90 if (!np) 90 if (!np)
91 return 0; 91 return 0;
92 92
93 prop = of_get_property(np, "hs_reg_valid", NULL); 93 prop = of_get_property(np, "hs_reg_valid", NULL);
94 of_node_put(np); 94 of_node_put(np);
95 95
96 pdev = platform_device_register_simple("marvell,mv64x60", 0, NULL, 0); 96 pdev = platform_device_register_simple("marvell,mv64360", 0, NULL, 0);
97 if (IS_ERR(pdev)) 97 if (IS_ERR(pdev))
98 return PTR_ERR(pdev); 98 return PTR_ERR(pdev);
99 99
@@ -166,6 +166,6 @@ void __init mv64x60_pci_init(void)
166{ 166{
167 struct device_node *np; 167 struct device_node *np;
168 168
169 for_each_compatible_node(np, "pci", "marvell,mv64x60-pci") 169 for_each_compatible_node(np, "pci", "marvell,mv64360-pci")
170 mv64x60_add_bridge(np); 170 mv64x60_add_bridge(np);
171} 171}
diff --git a/arch/powerpc/sysdev/mv64x60_pic.c b/arch/powerpc/sysdev/mv64x60_pic.c
index 19e6ef263797..2aa4ed066db1 100644
--- a/arch/powerpc/sysdev/mv64x60_pic.c
+++ b/arch/powerpc/sysdev/mv64x60_pic.c
@@ -238,13 +238,13 @@ void __init mv64x60_init_irq(void)
238 const unsigned int *reg; 238 const unsigned int *reg;
239 unsigned long flags; 239 unsigned long flags;
240 240
241 np = of_find_compatible_node(NULL, NULL, "marvell,mv64x60-gpp"); 241 np = of_find_compatible_node(NULL, NULL, "marvell,mv64360-gpp");
242 reg = of_get_property(np, "reg", &size); 242 reg = of_get_property(np, "reg", &size);
243 paddr = of_translate_address(np, reg); 243 paddr = of_translate_address(np, reg);
244 mv64x60_gpp_reg_base = ioremap(paddr, reg[1]); 244 mv64x60_gpp_reg_base = ioremap(paddr, reg[1]);
245 of_node_put(np); 245 of_node_put(np);
246 246
247 np = of_find_compatible_node(NULL, NULL, "marvell,mv64x60-pic"); 247 np = of_find_compatible_node(NULL, NULL, "marvell,mv64360-pic");
248 reg = of_get_property(np, "reg", &size); 248 reg = of_get_property(np, "reg", &size);
249 paddr = of_translate_address(np, reg); 249 paddr = of_translate_address(np, reg);
250 mv64x60_irq_reg_base = ioremap(paddr, reg[1]); 250 mv64x60_irq_reg_base = ioremap(paddr, reg[1]);
diff --git a/arch/powerpc/sysdev/mv64x60_udbg.c b/arch/powerpc/sysdev/mv64x60_udbg.c
index 35c77c7d0616..ccdb3b0418fc 100644
--- a/arch/powerpc/sysdev/mv64x60_udbg.c
+++ b/arch/powerpc/sysdev/mv64x60_udbg.c
@@ -85,7 +85,7 @@ static void mv64x60_udbg_init(void)
85 if (!stdout) 85 if (!stdout)
86 return; 86 return;
87 87
88 for_each_compatible_node(np, "serial", "marvell,mpsc") { 88 for_each_compatible_node(np, "serial", "marvell,mv64360-mpsc") {
89 if (np == stdout) 89 if (np == stdout)
90 break; 90 break;
91 } 91 }
diff --git a/arch/powerpc/sysdev/ppc4xx_pci.c b/arch/powerpc/sysdev/ppc4xx_pci.c
index 5abfcd157483..1814adbd2236 100644
--- a/arch/powerpc/sysdev/ppc4xx_pci.c
+++ b/arch/powerpc/sysdev/ppc4xx_pci.c
@@ -527,6 +527,7 @@ static void __init ppc4xx_probe_pcix_bridge(struct device_node *np)
527 * 527 *
528 * ibm,plb-pciex-440spe 528 * ibm,plb-pciex-440spe
529 * ibm,plb-pciex-405ex 529 * ibm,plb-pciex-405ex
530 * ibm,plb-pciex-460ex
530 * 531 *
531 * Anything else will be rejected for now as they are all subtly 532 * Anything else will be rejected for now as they are all subtly
532 * different unfortunately. 533 * different unfortunately.
@@ -645,7 +646,7 @@ static int __init ppc440spe_pciex_core_init(struct device_node *np)
645 int time_out = 20; 646 int time_out = 20;
646 647
647 /* Set PLL clock receiver to LVPECL */ 648 /* Set PLL clock receiver to LVPECL */
648 mtdcri(SDR0, PESDR0_PLLLCT1, mfdcri(SDR0, PESDR0_PLLLCT1) | 1 << 28); 649 dcri_clrset(SDR0, PESDR0_PLLLCT1, 0, 1 << 28);
649 650
650 /* Shouldn't we do all the calibration stuff etc... here ? */ 651 /* Shouldn't we do all the calibration stuff etc... here ? */
651 if (ppc440spe_pciex_check_reset(np)) 652 if (ppc440spe_pciex_check_reset(np))
@@ -659,8 +660,7 @@ static int __init ppc440spe_pciex_core_init(struct device_node *np)
659 } 660 }
660 661
661 /* De-assert reset of PCIe PLL, wait for lock */ 662 /* De-assert reset of PCIe PLL, wait for lock */
662 mtdcri(SDR0, PESDR0_PLLLCT1, 663 dcri_clrset(SDR0, PESDR0_PLLLCT1, 1 << 24, 0);
663 mfdcri(SDR0, PESDR0_PLLLCT1) & ~(1 << 24));
664 udelay(3); 664 udelay(3);
665 665
666 while (time_out) { 666 while (time_out) {
@@ -712,9 +712,8 @@ static int ppc440spe_pciex_init_port_hw(struct ppc4xx_pciex_port *port)
712 mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL7SET1, 712 mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL7SET1,
713 0x35000000); 713 0x35000000);
714 } 714 }
715 val = mfdcri(SDR0, port->sdr_base + PESDRn_RCSSET); 715 dcri_clrset(SDR0, port->sdr_base + PESDRn_RCSSET,
716 mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET, 716 (1 << 24) | (1 << 16), 1 << 12);
717 (val & ~(1 << 24 | 1 << 16)) | 1 << 12);
718 717
719 return 0; 718 return 0;
720} 719}
@@ -775,6 +774,115 @@ static struct ppc4xx_pciex_hwops ppc440speB_pcie_hwops __initdata =
775 .setup_utl = ppc440speB_pciex_init_utl, 774 .setup_utl = ppc440speB_pciex_init_utl,
776}; 775};
777 776
777static int __init ppc460ex_pciex_core_init(struct device_node *np)
778{
779 /* Nothing to do, return 2 ports */
780 return 2;
781}
782
783static int ppc460ex_pciex_init_port_hw(struct ppc4xx_pciex_port *port)
784{
785 u32 val;
786 u32 utlset1;
787
788 if (port->endpoint)
789 val = PTYPE_LEGACY_ENDPOINT << 20;
790 else
791 val = PTYPE_ROOT_PORT << 20;
792
793 if (port->index == 0) {
794 val |= LNKW_X1 << 12;
795 utlset1 = 0x20000000;
796 } else {
797 val |= LNKW_X4 << 12;
798 utlset1 = 0x20101101;
799 }
800
801 mtdcri(SDR0, port->sdr_base + PESDRn_DLPSET, val);
802 mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET1, utlset1);
803 mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET2, 0x01210000);
804
805 switch (port->index) {
806 case 0:
807 mtdcri(SDR0, PESDR0_460EX_L0CDRCTL, 0x00003230);
808 mtdcri(SDR0, PESDR0_460EX_L0DRV, 0x00000136);
809 mtdcri(SDR0, PESDR0_460EX_L0CLK, 0x00000006);
810
811 mtdcri(SDR0, PESDR0_460EX_PHY_CTL_RST,0x10000000);
812 break;
813
814 case 1:
815 mtdcri(SDR0, PESDR1_460EX_L0CDRCTL, 0x00003230);
816 mtdcri(SDR0, PESDR1_460EX_L1CDRCTL, 0x00003230);
817 mtdcri(SDR0, PESDR1_460EX_L2CDRCTL, 0x00003230);
818 mtdcri(SDR0, PESDR1_460EX_L3CDRCTL, 0x00003230);
819 mtdcri(SDR0, PESDR1_460EX_L0DRV, 0x00000136);
820 mtdcri(SDR0, PESDR1_460EX_L1DRV, 0x00000136);
821 mtdcri(SDR0, PESDR1_460EX_L2DRV, 0x00000136);
822 mtdcri(SDR0, PESDR1_460EX_L3DRV, 0x00000136);
823 mtdcri(SDR0, PESDR1_460EX_L0CLK, 0x00000006);
824 mtdcri(SDR0, PESDR1_460EX_L1CLK, 0x00000006);
825 mtdcri(SDR0, PESDR1_460EX_L2CLK, 0x00000006);
826 mtdcri(SDR0, PESDR1_460EX_L3CLK, 0x00000006);
827
828 mtdcri(SDR0, PESDR1_460EX_PHY_CTL_RST,0x10000000);
829 break;
830 }
831
832 mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET,
833 mfdcri(SDR0, port->sdr_base + PESDRn_RCSSET) |
834 (PESDRx_RCSSET_RSTGU | PESDRx_RCSSET_RSTPYN));
835
836 /* Poll for PHY reset */
837 /* XXX FIXME add timeout */
838 switch (port->index) {
839 case 0:
840 while (!(mfdcri(SDR0, PESDR0_460EX_RSTSTA) & 0x1))
841 udelay(10);
842 break;
843 case 1:
844 while (!(mfdcri(SDR0, PESDR1_460EX_RSTSTA) & 0x1))
845 udelay(10);
846 break;
847 }
848
849 mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET,
850 (mfdcri(SDR0, port->sdr_base + PESDRn_RCSSET) &
851 ~(PESDRx_RCSSET_RSTGU | PESDRx_RCSSET_RSTDL)) |
852 PESDRx_RCSSET_RSTPYN);
853
854 port->has_ibpre = 1;
855
856 return 0;
857}
858
859static int ppc460ex_pciex_init_utl(struct ppc4xx_pciex_port *port)
860{
861 dcr_write(port->dcrs, DCRO_PEGPL_SPECIAL, 0x0);
862
863 /*
864 * Set buffer allocations and then assert VRB and TXE.
865 */
866 out_be32(port->utl_base + PEUTL_PBCTL, 0x0800000c);
867 out_be32(port->utl_base + PEUTL_OUTTR, 0x08000000);
868 out_be32(port->utl_base + PEUTL_INTR, 0x02000000);
869 out_be32(port->utl_base + PEUTL_OPDBSZ, 0x04000000);
870 out_be32(port->utl_base + PEUTL_PBBSZ, 0x00000000);
871 out_be32(port->utl_base + PEUTL_IPHBSZ, 0x02000000);
872 out_be32(port->utl_base + PEUTL_IPDBSZ, 0x04000000);
873 out_be32(port->utl_base + PEUTL_RCIRQEN,0x00f00000);
874 out_be32(port->utl_base + PEUTL_PCTL, 0x80800066);
875
876 return 0;
877}
878
879static struct ppc4xx_pciex_hwops ppc460ex_pcie_hwops __initdata =
880{
881 .core_init = ppc460ex_pciex_core_init,
882 .port_init_hw = ppc460ex_pciex_init_port_hw,
883 .setup_utl = ppc460ex_pciex_init_utl,
884};
885
778#endif /* CONFIG_44x */ 886#endif /* CONFIG_44x */
779 887
780#ifdef CONFIG_40x 888#ifdef CONFIG_40x
@@ -830,17 +938,9 @@ static int ppc405ex_pciex_init_port_hw(struct ppc4xx_pciex_port *port)
830 * PCIe boards don't show this problem. 938 * PCIe boards don't show this problem.
831 * This has to be re-tested and fixed in a later release! 939 * This has to be re-tested and fixed in a later release!
832 */ 940 */
833#if 0 /* XXX FIXME: Not resetting the PHY will leave all resources
834 * configured as done previously by U-Boot. Then Linux will currently
835 * not reassign them. So the PHY reset is now done always. This will
836 * lead to problems with the Atheros PCIe board again.
837 */
838 val = mfdcri(SDR0, port->sdr_base + PESDRn_LOOP); 941 val = mfdcri(SDR0, port->sdr_base + PESDRn_LOOP);
839 if (!(val & 0x00001000)) 942 if (!(val & 0x00001000))
840 ppc405ex_pcie_phy_reset(port); 943 ppc405ex_pcie_phy_reset(port);
841#else
842 ppc405ex_pcie_phy_reset(port);
843#endif
844 944
845 dcr_write(port->dcrs, DCRO_PEGPL_CFG, 0x10000000); /* guarded on */ 945 dcr_write(port->dcrs, DCRO_PEGPL_CFG, 0x10000000); /* guarded on */
846 946
@@ -896,6 +996,8 @@ static int __init ppc4xx_pciex_check_core_init(struct device_node *np)
896 else 996 else
897 ppc4xx_pciex_hwops = &ppc440speB_pcie_hwops; 997 ppc4xx_pciex_hwops = &ppc440speB_pcie_hwops;
898 } 998 }
999 if (of_device_is_compatible(np, "ibm,plb-pciex-460ex"))
1000 ppc4xx_pciex_hwops = &ppc460ex_pcie_hwops;
899#endif /* CONFIG_44x */ 1001#endif /* CONFIG_44x */
900#ifdef CONFIG_40x 1002#ifdef CONFIG_40x
901 if (of_device_is_compatible(np, "ibm,plb-pciex-405ex")) 1003 if (of_device_is_compatible(np, "ibm,plb-pciex-405ex"))
@@ -1042,8 +1144,7 @@ static int __init ppc4xx_pciex_port_init(struct ppc4xx_pciex_port *port)
1042 port->link = 0; 1144 port->link = 0;
1043 } 1145 }
1044 1146
1045 mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET, 1147 dcri_clrset(SDR0, port->sdr_base + PESDRn_RCSSET, 0, 1 << 20);
1046 mfdcri(SDR0, port->sdr_base + PESDRn_RCSSET) | 1 << 20);
1047 msleep(100); 1148 msleep(100);
1048 1149
1049 return 0; 1150 return 0;
diff --git a/arch/powerpc/sysdev/ppc4xx_pci.h b/arch/powerpc/sysdev/ppc4xx_pci.h
index 1c07908dc6ef..d04e40b306fb 100644
--- a/arch/powerpc/sysdev/ppc4xx_pci.h
+++ b/arch/powerpc/sysdev/ppc4xx_pci.h
@@ -271,6 +271,59 @@
271#define PESDR1_405EX_PHYSTA 0x044C 271#define PESDR1_405EX_PHYSTA 0x044C
272 272
273/* 273/*
274 * 460EX additional DCRs
275 */
276#define PESDR0_460EX_L0BIST 0x0308
277#define PESDR0_460EX_L0BISTSTS 0x0309
278#define PESDR0_460EX_L0CDRCTL 0x030A
279#define PESDR0_460EX_L0DRV 0x030B
280#define PESDR0_460EX_L0REC 0x030C
281#define PESDR0_460EX_L0LPB 0x030D
282#define PESDR0_460EX_L0CLK 0x030E
283#define PESDR0_460EX_PHY_CTL_RST 0x030F
284#define PESDR0_460EX_RSTSTA 0x0310
285#define PESDR0_460EX_OBS 0x0311
286#define PESDR0_460EX_L0ERRC 0x0320
287
288#define PESDR1_460EX_L0BIST 0x0348
289#define PESDR1_460EX_L1BIST 0x0349
290#define PESDR1_460EX_L2BIST 0x034A
291#define PESDR1_460EX_L3BIST 0x034B
292#define PESDR1_460EX_L0BISTSTS 0x034C
293#define PESDR1_460EX_L1BISTSTS 0x034D
294#define PESDR1_460EX_L2BISTSTS 0x034E
295#define PESDR1_460EX_L3BISTSTS 0x034F
296#define PESDR1_460EX_L0CDRCTL 0x0350
297#define PESDR1_460EX_L1CDRCTL 0x0351
298#define PESDR1_460EX_L2CDRCTL 0x0352
299#define PESDR1_460EX_L3CDRCTL 0x0353
300#define PESDR1_460EX_L0DRV 0x0354
301#define PESDR1_460EX_L1DRV 0x0355
302#define PESDR1_460EX_L2DRV 0x0356
303#define PESDR1_460EX_L3DRV 0x0357
304#define PESDR1_460EX_L0REC 0x0358
305#define PESDR1_460EX_L1REC 0x0359
306#define PESDR1_460EX_L2REC 0x035A
307#define PESDR1_460EX_L3REC 0x035B
308#define PESDR1_460EX_L0LPB 0x035C
309#define PESDR1_460EX_L1LPB 0x035D
310#define PESDR1_460EX_L2LPB 0x035E
311#define PESDR1_460EX_L3LPB 0x035F
312#define PESDR1_460EX_L0CLK 0x0360
313#define PESDR1_460EX_L1CLK 0x0361
314#define PESDR1_460EX_L2CLK 0x0362
315#define PESDR1_460EX_L3CLK 0x0363
316#define PESDR1_460EX_PHY_CTL_RST 0x0364
317#define PESDR1_460EX_RSTSTA 0x0365
318#define PESDR1_460EX_OBS 0x0366
319#define PESDR1_460EX_L0ERRC 0x0368
320#define PESDR1_460EX_L1ERRC 0x0369
321#define PESDR1_460EX_L2ERRC 0x036A
322#define PESDR1_460EX_L3ERRC 0x036B
323#define PESDR0_460EX_IHS1 0x036C
324#define PESDR0_460EX_IHS2 0x036D
325
326/*
274 * Of the above, some are common offsets from the base 327 * Of the above, some are common offsets from the base
275 */ 328 */
276#define PESDRn_UTLSET1 0x00 329#define PESDRn_UTLSET1 0x00
@@ -353,6 +406,12 @@
353#define PECFG_POM2LAL 0x390 406#define PECFG_POM2LAL 0x390
354#define PECFG_POM2LAH 0x394 407#define PECFG_POM2LAH 0x394
355 408
409/* SDR Bit Mappings */
410#define PESDRx_RCSSET_HLDPLB 0x10000000
411#define PESDRx_RCSSET_RSTGU 0x01000000
412#define PESDRx_RCSSET_RDY 0x00100000
413#define PESDRx_RCSSET_RSTDL 0x00010000
414#define PESDRx_RCSSET_RSTPYN 0x00001000
356 415
357enum 416enum
358{ 417{
diff --git a/arch/powerpc/sysdev/ppc4xx_soc.c b/arch/powerpc/sysdev/ppc4xx_soc.c
new file mode 100644
index 000000000000..5b32adc9a9b2
--- /dev/null
+++ b/arch/powerpc/sysdev/ppc4xx_soc.c
@@ -0,0 +1,200 @@
1/*
2 * IBM/AMCC PPC4xx SoC setup code
3 *
4 * Copyright 2008 DENX Software Engineering, Stefan Roese <sr@denx.de>
5 *
6 * L2 cache routines cloned from arch/ppc/syslib/ibm440gx_common.c which is:
7 * Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
8 * Copyright (c) 2003 - 2006 Zultys Technologies
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 */
15
16#include <linux/stddef.h>
17#include <linux/kernel.h>
18#include <linux/init.h>
19#include <linux/errno.h>
20#include <linux/interrupt.h>
21#include <linux/irq.h>
22#include <linux/of_platform.h>
23
24#include <asm/dcr.h>
25#include <asm/dcr-regs.h>
26#include <asm/reg.h>
27
28static u32 dcrbase_l2c;
29
30/*
31 * L2-cache
32 */
33
34/* Issue L2C diagnostic command */
35static inline u32 l2c_diag(u32 addr)
36{
37 mtdcr(dcrbase_l2c + DCRN_L2C0_ADDR, addr);
38 mtdcr(dcrbase_l2c + DCRN_L2C0_CMD, L2C_CMD_DIAG);
39 while (!(mfdcr(dcrbase_l2c + DCRN_L2C0_SR) & L2C_SR_CC))
40 ;
41
42 return mfdcr(dcrbase_l2c + DCRN_L2C0_DATA);
43}
44
45static irqreturn_t l2c_error_handler(int irq, void *dev)
46{
47 u32 sr = mfdcr(dcrbase_l2c + DCRN_L2C0_SR);
48
49 if (sr & L2C_SR_CPE) {
50 /* Read cache trapped address */
51 u32 addr = l2c_diag(0x42000000);
52 printk(KERN_EMERG "L2C: Cache Parity Error, addr[16:26] = 0x%08x\n",
53 addr);
54 }
55 if (sr & L2C_SR_TPE) {
56 /* Read tag trapped address */
57 u32 addr = l2c_diag(0x82000000) >> 16;
58 printk(KERN_EMERG "L2C: Tag Parity Error, addr[16:26] = 0x%08x\n",
59 addr);
60 }
61
62 /* Clear parity errors */
63 if (sr & (L2C_SR_CPE | L2C_SR_TPE)){
64 mtdcr(dcrbase_l2c + DCRN_L2C0_ADDR, 0);
65 mtdcr(dcrbase_l2c + DCRN_L2C0_CMD, L2C_CMD_CCP | L2C_CMD_CTE);
66 } else {
67 printk(KERN_EMERG "L2C: LRU error\n");
68 }
69
70 return IRQ_HANDLED;
71}
72
73static int __init ppc4xx_l2c_probe(void)
74{
75 struct device_node *np;
76 u32 r;
77 unsigned long flags;
78 int irq;
79 const u32 *dcrreg;
80 u32 dcrbase_isram;
81 int len;
82 const u32 *prop;
83 u32 l2_size;
84
85 np = of_find_compatible_node(NULL, NULL, "ibm,l2-cache");
86 if (!np)
87 return 0;
88
89 /* Get l2 cache size */
90 prop = of_get_property(np, "cache-size", NULL);
91 if (prop == NULL) {
92 printk(KERN_ERR "%s: Can't get cache-size!\n", np->full_name);
93 of_node_put(np);
94 return -ENODEV;
95 }
96 l2_size = prop[0];
97
98 /* Map DCRs */
99 dcrreg = of_get_property(np, "dcr-reg", &len);
100 if (!dcrreg || (len != 4 * sizeof(u32))) {
101 printk(KERN_ERR "%s: Can't get DCR register base !",
102 np->full_name);
103 of_node_put(np);
104 return -ENODEV;
105 }
106 dcrbase_isram = dcrreg[0];
107 dcrbase_l2c = dcrreg[2];
108
109 /* Get and map irq number from device tree */
110 irq = irq_of_parse_and_map(np, 0);
111 if (irq == NO_IRQ) {
112 printk(KERN_ERR "irq_of_parse_and_map failed\n");
113 of_node_put(np);
114 return -ENODEV;
115 }
116
117 /* Install error handler */
118 if (request_irq(irq, l2c_error_handler, IRQF_DISABLED, "L2C", 0) < 0) {
119 printk(KERN_ERR "Cannot install L2C error handler"
120 ", cache is not enabled\n");
121 of_node_put(np);
122 return -ENODEV;
123 }
124
125 local_irq_save(flags);
126 asm volatile ("sync" ::: "memory");
127
128 /* Disable SRAM */
129 mtdcr(dcrbase_isram + DCRN_SRAM0_DPC,
130 mfdcr(dcrbase_isram + DCRN_SRAM0_DPC) & ~SRAM_DPC_ENABLE);
131 mtdcr(dcrbase_isram + DCRN_SRAM0_SB0CR,
132 mfdcr(dcrbase_isram + DCRN_SRAM0_SB0CR) & ~SRAM_SBCR_BU_MASK);
133 mtdcr(dcrbase_isram + DCRN_SRAM0_SB1CR,
134 mfdcr(dcrbase_isram + DCRN_SRAM0_SB1CR) & ~SRAM_SBCR_BU_MASK);
135 mtdcr(dcrbase_isram + DCRN_SRAM0_SB2CR,
136 mfdcr(dcrbase_isram + DCRN_SRAM0_SB2CR) & ~SRAM_SBCR_BU_MASK);
137 mtdcr(dcrbase_isram + DCRN_SRAM0_SB3CR,
138 mfdcr(dcrbase_isram + DCRN_SRAM0_SB3CR) & ~SRAM_SBCR_BU_MASK);
139
140 /* Enable L2_MODE without ICU/DCU */
141 r = mfdcr(dcrbase_l2c + DCRN_L2C0_CFG) &
142 ~(L2C_CFG_ICU | L2C_CFG_DCU | L2C_CFG_SS_MASK);
143 r |= L2C_CFG_L2M | L2C_CFG_SS_256;
144 mtdcr(dcrbase_l2c + DCRN_L2C0_CFG, r);
145
146 mtdcr(dcrbase_l2c + DCRN_L2C0_ADDR, 0);
147
148 /* Hardware Clear Command */
149 mtdcr(dcrbase_l2c + DCRN_L2C0_CMD, L2C_CMD_HCC);
150 while (!(mfdcr(dcrbase_l2c + DCRN_L2C0_SR) & L2C_SR_CC))
151 ;
152
153 /* Clear Cache Parity and Tag Errors */
154 mtdcr(dcrbase_l2c + DCRN_L2C0_CMD, L2C_CMD_CCP | L2C_CMD_CTE);
155
156 /* Enable 64G snoop region starting at 0 */
157 r = mfdcr(dcrbase_l2c + DCRN_L2C0_SNP0) &
158 ~(L2C_SNP_BA_MASK | L2C_SNP_SSR_MASK);
159 r |= L2C_SNP_SSR_32G | L2C_SNP_ESR;
160 mtdcr(dcrbase_l2c + DCRN_L2C0_SNP0, r);
161
162 r = mfdcr(dcrbase_l2c + DCRN_L2C0_SNP1) &
163 ~(L2C_SNP_BA_MASK | L2C_SNP_SSR_MASK);
164 r |= 0x80000000 | L2C_SNP_SSR_32G | L2C_SNP_ESR;
165 mtdcr(dcrbase_l2c + DCRN_L2C0_SNP1, r);
166
167 asm volatile ("sync" ::: "memory");
168
169 /* Enable ICU/DCU ports */
170 r = mfdcr(dcrbase_l2c + DCRN_L2C0_CFG);
171 r &= ~(L2C_CFG_DCW_MASK | L2C_CFG_PMUX_MASK | L2C_CFG_PMIM
172 | L2C_CFG_TPEI | L2C_CFG_CPEI | L2C_CFG_NAM | L2C_CFG_NBRM);
173 r |= L2C_CFG_ICU | L2C_CFG_DCU | L2C_CFG_TPC | L2C_CFG_CPC | L2C_CFG_FRAN
174 | L2C_CFG_CPIM | L2C_CFG_TPIM | L2C_CFG_LIM | L2C_CFG_SMCM;
175
176 /* Check for 460EX/GT special handling */
177 if (of_device_is_compatible(np, "ibm,l2-cache-460ex"))
178 r |= L2C_CFG_RDBW;
179
180 mtdcr(dcrbase_l2c + DCRN_L2C0_CFG, r);
181
182 asm volatile ("sync; isync" ::: "memory");
183 local_irq_restore(flags);
184
185 printk(KERN_INFO "%dk L2-cache enabled\n", l2_size >> 10);
186
187 of_node_put(np);
188 return 0;
189}
190arch_initcall(ppc4xx_l2c_probe);
191
192/*
193 * At present, this routine just applies a system reset.
194 */
195void ppc4xx_reset_system(char *cmd)
196{
197 mtspr(SPRN_DBCR0, mfspr(SPRN_DBCR0) | DBCR0_RST_SYSTEM);
198 while (1)
199 ; /* Just in case the reset doesn't work */
200}
diff --git a/arch/powerpc/sysdev/qe_lib/qe.c b/arch/powerpc/sysdev/qe_lib/qe.c
index cc81fd1141b0..cff550eec7e8 100644
--- a/arch/powerpc/sysdev/qe_lib/qe.c
+++ b/arch/powerpc/sysdev/qe_lib/qe.c
@@ -55,7 +55,7 @@ struct qe_snum {
55/* We allocate this here because it is used almost exclusively for 55/* We allocate this here because it is used almost exclusively for
56 * the communication processor devices. 56 * the communication processor devices.
57 */ 57 */
58struct qe_immap *qe_immr = NULL; 58struct qe_immap __iomem *qe_immr;
59EXPORT_SYMBOL(qe_immr); 59EXPORT_SYMBOL(qe_immr);
60 60
61static struct qe_snum snums[QE_NUM_OF_SNUM]; /* Dynamically allocated SNUMs */ 61static struct qe_snum snums[QE_NUM_OF_SNUM]; /* Dynamically allocated SNUMs */
@@ -156,7 +156,7 @@ EXPORT_SYMBOL(qe_issue_cmd);
156 */ 156 */
157static unsigned int brg_clk = 0; 157static unsigned int brg_clk = 0;
158 158
159unsigned int get_brg_clk(void) 159unsigned int qe_get_brg_clk(void)
160{ 160{
161 struct device_node *qe; 161 struct device_node *qe;
162 unsigned int size; 162 unsigned int size;
@@ -180,6 +180,7 @@ unsigned int get_brg_clk(void)
180 180
181 return brg_clk; 181 return brg_clk;
182} 182}
183EXPORT_SYMBOL(qe_get_brg_clk);
183 184
184/* Program the BRG to the given sampling rate and multiplier 185/* Program the BRG to the given sampling rate and multiplier
185 * 186 *
@@ -197,7 +198,7 @@ int qe_setbrg(enum qe_clock brg, unsigned int rate, unsigned int multiplier)
197 if ((brg < QE_BRG1) || (brg > QE_BRG16)) 198 if ((brg < QE_BRG1) || (brg > QE_BRG16))
198 return -EINVAL; 199 return -EINVAL;
199 200
200 divisor = get_brg_clk() / (rate * multiplier); 201 divisor = qe_get_brg_clk() / (rate * multiplier);
201 202
202 if (divisor > QE_BRGC_DIVISOR_MAX + 1) { 203 if (divisor > QE_BRGC_DIVISOR_MAX + 1) {
203 div16 = QE_BRGC_DIV16; 204 div16 = QE_BRGC_DIV16;
@@ -415,12 +416,6 @@ void qe_muram_dump(void)
415} 416}
416EXPORT_SYMBOL(qe_muram_dump); 417EXPORT_SYMBOL(qe_muram_dump);
417 418
418void *qe_muram_addr(unsigned long offset)
419{
420 return (void *)&qe_immr->muram[offset];
421}
422EXPORT_SYMBOL(qe_muram_addr);
423
424/* The maximum number of RISCs we support */ 419/* The maximum number of RISCs we support */
425#define MAX_QE_RISC 2 420#define MAX_QE_RISC 2
426 421
diff --git a/arch/powerpc/sysdev/qe_lib/qe_io.c b/arch/powerpc/sysdev/qe_lib/qe_io.c
index e53ea4d374a0..93916a48afec 100644
--- a/arch/powerpc/sysdev/qe_lib/qe_io.c
+++ b/arch/powerpc/sysdev/qe_lib/qe_io.c
@@ -22,6 +22,7 @@
22#include <linux/ioport.h> 22#include <linux/ioport.h>
23 23
24#include <asm/io.h> 24#include <asm/io.h>
25#include <asm/qe.h>
25#include <asm/prom.h> 26#include <asm/prom.h>
26#include <sysdev/fsl_soc.h> 27#include <sysdev/fsl_soc.h>
27 28
@@ -41,7 +42,7 @@ struct port_regs {
41#endif 42#endif
42}; 43};
43 44
44static struct port_regs *par_io = NULL; 45static struct port_regs __iomem *par_io;
45static int num_par_io_ports = 0; 46static int num_par_io_ports = 0;
46 47
47int par_io_init(struct device_node *np) 48int par_io_init(struct device_node *np)
@@ -165,7 +166,7 @@ int par_io_of_config(struct device_node *np)
165 } 166 }
166 167
167 ph = of_get_property(np, "pio-handle", NULL); 168 ph = of_get_property(np, "pio-handle", NULL);
168 if (ph == 0) { 169 if (ph == NULL) {
169 printk(KERN_ERR "pio-handle not available \n"); 170 printk(KERN_ERR "pio-handle not available \n");
170 return -1; 171 return -1;
171 } 172 }
@@ -200,7 +201,7 @@ static void dump_par_io(void)
200{ 201{
201 unsigned int i; 202 unsigned int i;
202 203
203 printk(KERN_INFO "%s: par_io=%p\n", __FUNCTION__, par_io); 204 printk(KERN_INFO "%s: par_io=%p\n", __func__, par_io);
204 for (i = 0; i < num_par_io_ports; i++) { 205 for (i = 0; i < num_par_io_ports; i++) {
205 printk(KERN_INFO " cpodr[%u]=%08x\n", i, 206 printk(KERN_INFO " cpodr[%u]=%08x\n", i,
206 in_be32(&par_io[i].cpodr)); 207 in_be32(&par_io[i].cpodr));
diff --git a/arch/powerpc/sysdev/qe_lib/ucc_fast.c b/arch/powerpc/sysdev/qe_lib/ucc_fast.c
index 3223acbc39e5..bcf88e6ce962 100644
--- a/arch/powerpc/sysdev/qe_lib/ucc_fast.c
+++ b/arch/powerpc/sysdev/qe_lib/ucc_fast.c
@@ -148,57 +148,57 @@ int ucc_fast_init(struct ucc_fast_info * uf_info, struct ucc_fast_private ** ucc
148 148
149 /* check if the UCC port number is in range. */ 149 /* check if the UCC port number is in range. */
150 if ((uf_info->ucc_num < 0) || (uf_info->ucc_num > UCC_MAX_NUM - 1)) { 150 if ((uf_info->ucc_num < 0) || (uf_info->ucc_num > UCC_MAX_NUM - 1)) {
151 printk(KERN_ERR "%s: illegal UCC number\n", __FUNCTION__); 151 printk(KERN_ERR "%s: illegal UCC number\n", __func__);
152 return -EINVAL; 152 return -EINVAL;
153 } 153 }
154 154
155 /* Check that 'max_rx_buf_length' is properly aligned (4). */ 155 /* Check that 'max_rx_buf_length' is properly aligned (4). */
156 if (uf_info->max_rx_buf_length & (UCC_FAST_MRBLR_ALIGNMENT - 1)) { 156 if (uf_info->max_rx_buf_length & (UCC_FAST_MRBLR_ALIGNMENT - 1)) {
157 printk(KERN_ERR "%s: max_rx_buf_length not aligned\n", 157 printk(KERN_ERR "%s: max_rx_buf_length not aligned\n",
158 __FUNCTION__); 158 __func__);
159 return -EINVAL; 159 return -EINVAL;
160 } 160 }
161 161
162 /* Validate Virtual Fifo register values */ 162 /* Validate Virtual Fifo register values */
163 if (uf_info->urfs < UCC_FAST_URFS_MIN_VAL) { 163 if (uf_info->urfs < UCC_FAST_URFS_MIN_VAL) {
164 printk(KERN_ERR "%s: urfs is too small\n", __FUNCTION__); 164 printk(KERN_ERR "%s: urfs is too small\n", __func__);
165 return -EINVAL; 165 return -EINVAL;
166 } 166 }
167 167
168 if (uf_info->urfs & (UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT - 1)) { 168 if (uf_info->urfs & (UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT - 1)) {
169 printk(KERN_ERR "%s: urfs is not aligned\n", __FUNCTION__); 169 printk(KERN_ERR "%s: urfs is not aligned\n", __func__);
170 return -EINVAL; 170 return -EINVAL;
171 } 171 }
172 172
173 if (uf_info->urfet & (UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT - 1)) { 173 if (uf_info->urfet & (UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT - 1)) {
174 printk(KERN_ERR "%s: urfet is not aligned.\n", __FUNCTION__); 174 printk(KERN_ERR "%s: urfet is not aligned.\n", __func__);
175 return -EINVAL; 175 return -EINVAL;
176 } 176 }
177 177
178 if (uf_info->urfset & (UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT - 1)) { 178 if (uf_info->urfset & (UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT - 1)) {
179 printk(KERN_ERR "%s: urfset is not aligned\n", __FUNCTION__); 179 printk(KERN_ERR "%s: urfset is not aligned\n", __func__);
180 return -EINVAL; 180 return -EINVAL;
181 } 181 }
182 182
183 if (uf_info->utfs & (UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT - 1)) { 183 if (uf_info->utfs & (UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT - 1)) {
184 printk(KERN_ERR "%s: utfs is not aligned\n", __FUNCTION__); 184 printk(KERN_ERR "%s: utfs is not aligned\n", __func__);
185 return -EINVAL; 185 return -EINVAL;
186 } 186 }
187 187
188 if (uf_info->utfet & (UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT - 1)) { 188 if (uf_info->utfet & (UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT - 1)) {
189 printk(KERN_ERR "%s: utfet is not aligned\n", __FUNCTION__); 189 printk(KERN_ERR "%s: utfet is not aligned\n", __func__);
190 return -EINVAL; 190 return -EINVAL;
191 } 191 }
192 192
193 if (uf_info->utftt & (UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT - 1)) { 193 if (uf_info->utftt & (UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT - 1)) {
194 printk(KERN_ERR "%s: utftt is not aligned\n", __FUNCTION__); 194 printk(KERN_ERR "%s: utftt is not aligned\n", __func__);
195 return -EINVAL; 195 return -EINVAL;
196 } 196 }
197 197
198 uccf = kzalloc(sizeof(struct ucc_fast_private), GFP_KERNEL); 198 uccf = kzalloc(sizeof(struct ucc_fast_private), GFP_KERNEL);
199 if (!uccf) { 199 if (!uccf) {
200 printk(KERN_ERR "%s: Cannot allocate private data\n", 200 printk(KERN_ERR "%s: Cannot allocate private data\n",
201 __FUNCTION__); 201 __func__);
202 return -ENOMEM; 202 return -ENOMEM;
203 } 203 }
204 204
@@ -207,7 +207,7 @@ int ucc_fast_init(struct ucc_fast_info * uf_info, struct ucc_fast_private ** ucc
207 /* Set the PHY base address */ 207 /* Set the PHY base address */
208 uccf->uf_regs = ioremap(uf_info->regs, sizeof(struct ucc_fast)); 208 uccf->uf_regs = ioremap(uf_info->regs, sizeof(struct ucc_fast));
209 if (uccf->uf_regs == NULL) { 209 if (uccf->uf_regs == NULL) {
210 printk(KERN_ERR "%s: Cannot map UCC registers\n", __FUNCTION__); 210 printk(KERN_ERR "%s: Cannot map UCC registers\n", __func__);
211 return -ENOMEM; 211 return -ENOMEM;
212 } 212 }
213 213
@@ -230,7 +230,7 @@ int ucc_fast_init(struct ucc_fast_info * uf_info, struct ucc_fast_private ** ucc
230 /* Set UCC to fast type */ 230 /* Set UCC to fast type */
231 ret = ucc_set_type(uf_info->ucc_num, UCC_SPEED_TYPE_FAST); 231 ret = ucc_set_type(uf_info->ucc_num, UCC_SPEED_TYPE_FAST);
232 if (ret) { 232 if (ret) {
233 printk(KERN_ERR "%s: cannot set UCC type\n", __FUNCTION__); 233 printk(KERN_ERR "%s: cannot set UCC type\n", __func__);
234 ucc_fast_free(uccf); 234 ucc_fast_free(uccf);
235 return ret; 235 return ret;
236 } 236 }
@@ -270,7 +270,7 @@ int ucc_fast_init(struct ucc_fast_info * uf_info, struct ucc_fast_private ** ucc
270 qe_muram_alloc(uf_info->utfs, UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT); 270 qe_muram_alloc(uf_info->utfs, UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT);
271 if (IS_ERR_VALUE(uccf->ucc_fast_tx_virtual_fifo_base_offset)) { 271 if (IS_ERR_VALUE(uccf->ucc_fast_tx_virtual_fifo_base_offset)) {
272 printk(KERN_ERR "%s: cannot allocate MURAM for TX FIFO\n", 272 printk(KERN_ERR "%s: cannot allocate MURAM for TX FIFO\n",
273 __FUNCTION__); 273 __func__);
274 uccf->ucc_fast_tx_virtual_fifo_base_offset = 0; 274 uccf->ucc_fast_tx_virtual_fifo_base_offset = 0;
275 ucc_fast_free(uccf); 275 ucc_fast_free(uccf);
276 return -ENOMEM; 276 return -ENOMEM;
@@ -283,7 +283,7 @@ int ucc_fast_init(struct ucc_fast_info * uf_info, struct ucc_fast_private ** ucc
283 UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT); 283 UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT);
284 if (IS_ERR_VALUE(uccf->ucc_fast_rx_virtual_fifo_base_offset)) { 284 if (IS_ERR_VALUE(uccf->ucc_fast_rx_virtual_fifo_base_offset)) {
285 printk(KERN_ERR "%s: cannot allocate MURAM for RX FIFO\n", 285 printk(KERN_ERR "%s: cannot allocate MURAM for RX FIFO\n",
286 __FUNCTION__); 286 __func__);
287 uccf->ucc_fast_rx_virtual_fifo_base_offset = 0; 287 uccf->ucc_fast_rx_virtual_fifo_base_offset = 0;
288 ucc_fast_free(uccf); 288 ucc_fast_free(uccf);
289 return -ENOMEM; 289 return -ENOMEM;
@@ -314,7 +314,7 @@ int ucc_fast_init(struct ucc_fast_info * uf_info, struct ucc_fast_private ** ucc
314 ucc_set_qe_mux_rxtx(uf_info->ucc_num, uf_info->rx_clock, 314 ucc_set_qe_mux_rxtx(uf_info->ucc_num, uf_info->rx_clock,
315 COMM_DIR_RX)) { 315 COMM_DIR_RX)) {
316 printk(KERN_ERR "%s: illegal value for RX clock\n", 316 printk(KERN_ERR "%s: illegal value for RX clock\n",
317 __FUNCTION__); 317 __func__);
318 ucc_fast_free(uccf); 318 ucc_fast_free(uccf);
319 return -EINVAL; 319 return -EINVAL;
320 } 320 }
@@ -323,7 +323,7 @@ int ucc_fast_init(struct ucc_fast_info * uf_info, struct ucc_fast_private ** ucc
323 ucc_set_qe_mux_rxtx(uf_info->ucc_num, uf_info->tx_clock, 323 ucc_set_qe_mux_rxtx(uf_info->ucc_num, uf_info->tx_clock,
324 COMM_DIR_TX)) { 324 COMM_DIR_TX)) {
325 printk(KERN_ERR "%s: illegal value for TX clock\n", 325 printk(KERN_ERR "%s: illegal value for TX clock\n",
326 __FUNCTION__); 326 __func__);
327 ucc_fast_free(uccf); 327 ucc_fast_free(uccf);
328 return -EINVAL; 328 return -EINVAL;
329 } 329 }
diff --git a/arch/powerpc/sysdev/qe_lib/ucc_slow.c b/arch/powerpc/sysdev/qe_lib/ucc_slow.c
index b2870b208ddb..a578bc77b9d5 100644
--- a/arch/powerpc/sysdev/qe_lib/ucc_slow.c
+++ b/arch/powerpc/sysdev/qe_lib/ucc_slow.c
@@ -142,7 +142,7 @@ int ucc_slow_init(struct ucc_slow_info * us_info, struct ucc_slow_private ** ucc
142 142
143 /* check if the UCC port number is in range. */ 143 /* check if the UCC port number is in range. */
144 if ((us_info->ucc_num < 0) || (us_info->ucc_num > UCC_MAX_NUM - 1)) { 144 if ((us_info->ucc_num < 0) || (us_info->ucc_num > UCC_MAX_NUM - 1)) {
145 printk(KERN_ERR "%s: illegal UCC number\n", __FUNCTION__); 145 printk(KERN_ERR "%s: illegal UCC number\n", __func__);
146 return -EINVAL; 146 return -EINVAL;
147 } 147 }
148 148
@@ -161,7 +161,7 @@ int ucc_slow_init(struct ucc_slow_info * us_info, struct ucc_slow_private ** ucc
161 uccs = kzalloc(sizeof(struct ucc_slow_private), GFP_KERNEL); 161 uccs = kzalloc(sizeof(struct ucc_slow_private), GFP_KERNEL);
162 if (!uccs) { 162 if (!uccs) {
163 printk(KERN_ERR "%s: Cannot allocate private data\n", 163 printk(KERN_ERR "%s: Cannot allocate private data\n",
164 __FUNCTION__); 164 __func__);
165 return -ENOMEM; 165 return -ENOMEM;
166 } 166 }
167 167
@@ -170,7 +170,7 @@ int ucc_slow_init(struct ucc_slow_info * us_info, struct ucc_slow_private ** ucc
170 /* Set the PHY base address */ 170 /* Set the PHY base address */
171 uccs->us_regs = ioremap(us_info->regs, sizeof(struct ucc_slow)); 171 uccs->us_regs = ioremap(us_info->regs, sizeof(struct ucc_slow));
172 if (uccs->us_regs == NULL) { 172 if (uccs->us_regs == NULL) {
173 printk(KERN_ERR "%s: Cannot map UCC registers\n", __FUNCTION__); 173 printk(KERN_ERR "%s: Cannot map UCC registers\n", __func__);
174 return -ENOMEM; 174 return -ENOMEM;
175 } 175 }
176 176
@@ -189,7 +189,7 @@ int ucc_slow_init(struct ucc_slow_info * us_info, struct ucc_slow_private ** ucc
189 uccs->us_pram_offset = 189 uccs->us_pram_offset =
190 qe_muram_alloc(UCC_SLOW_PRAM_SIZE, ALIGNMENT_OF_UCC_SLOW_PRAM); 190 qe_muram_alloc(UCC_SLOW_PRAM_SIZE, ALIGNMENT_OF_UCC_SLOW_PRAM);
191 if (IS_ERR_VALUE(uccs->us_pram_offset)) { 191 if (IS_ERR_VALUE(uccs->us_pram_offset)) {
192 printk(KERN_ERR "%s: cannot allocate MURAM for PRAM", __FUNCTION__); 192 printk(KERN_ERR "%s: cannot allocate MURAM for PRAM", __func__);
193 ucc_slow_free(uccs); 193 ucc_slow_free(uccs);
194 return -ENOMEM; 194 return -ENOMEM;
195 } 195 }
@@ -202,7 +202,7 @@ int ucc_slow_init(struct ucc_slow_info * us_info, struct ucc_slow_private ** ucc
202 /* Set UCC to slow type */ 202 /* Set UCC to slow type */
203 ret = ucc_set_type(us_info->ucc_num, UCC_SPEED_TYPE_SLOW); 203 ret = ucc_set_type(us_info->ucc_num, UCC_SPEED_TYPE_SLOW);
204 if (ret) { 204 if (ret) {
205 printk(KERN_ERR "%s: cannot set UCC type", __FUNCTION__); 205 printk(KERN_ERR "%s: cannot set UCC type", __func__);
206 ucc_slow_free(uccs); 206 ucc_slow_free(uccs);
207 return ret; 207 return ret;
208 } 208 }
@@ -216,7 +216,7 @@ int ucc_slow_init(struct ucc_slow_info * us_info, struct ucc_slow_private ** ucc
216 qe_muram_alloc(us_info->rx_bd_ring_len * sizeof(struct qe_bd), 216 qe_muram_alloc(us_info->rx_bd_ring_len * sizeof(struct qe_bd),
217 QE_ALIGNMENT_OF_BD); 217 QE_ALIGNMENT_OF_BD);
218 if (IS_ERR_VALUE(uccs->rx_base_offset)) { 218 if (IS_ERR_VALUE(uccs->rx_base_offset)) {
219 printk(KERN_ERR "%s: cannot allocate %u RX BDs\n", __FUNCTION__, 219 printk(KERN_ERR "%s: cannot allocate %u RX BDs\n", __func__,
220 us_info->rx_bd_ring_len); 220 us_info->rx_bd_ring_len);
221 uccs->rx_base_offset = 0; 221 uccs->rx_base_offset = 0;
222 ucc_slow_free(uccs); 222 ucc_slow_free(uccs);
@@ -227,7 +227,7 @@ int ucc_slow_init(struct ucc_slow_info * us_info, struct ucc_slow_private ** ucc
227 qe_muram_alloc(us_info->tx_bd_ring_len * sizeof(struct qe_bd), 227 qe_muram_alloc(us_info->tx_bd_ring_len * sizeof(struct qe_bd),
228 QE_ALIGNMENT_OF_BD); 228 QE_ALIGNMENT_OF_BD);
229 if (IS_ERR_VALUE(uccs->tx_base_offset)) { 229 if (IS_ERR_VALUE(uccs->tx_base_offset)) {
230 printk(KERN_ERR "%s: cannot allocate TX BDs", __FUNCTION__); 230 printk(KERN_ERR "%s: cannot allocate TX BDs", __func__);
231 uccs->tx_base_offset = 0; 231 uccs->tx_base_offset = 0;
232 ucc_slow_free(uccs); 232 ucc_slow_free(uccs);
233 return -ENOMEM; 233 return -ENOMEM;
@@ -317,7 +317,7 @@ int ucc_slow_init(struct ucc_slow_info * us_info, struct ucc_slow_private ** ucc
317 if (ucc_set_qe_mux_rxtx(us_info->ucc_num, us_info->rx_clock, 317 if (ucc_set_qe_mux_rxtx(us_info->ucc_num, us_info->rx_clock,
318 COMM_DIR_RX)) { 318 COMM_DIR_RX)) {
319 printk(KERN_ERR "%s: illegal value for RX clock\n", 319 printk(KERN_ERR "%s: illegal value for RX clock\n",
320 __FUNCTION__); 320 __func__);
321 ucc_slow_free(uccs); 321 ucc_slow_free(uccs);
322 return -EINVAL; 322 return -EINVAL;
323 } 323 }
@@ -325,7 +325,7 @@ int ucc_slow_init(struct ucc_slow_info * us_info, struct ucc_slow_private ** ucc
325 if (ucc_set_qe_mux_rxtx(us_info->ucc_num, us_info->tx_clock, 325 if (ucc_set_qe_mux_rxtx(us_info->ucc_num, us_info->tx_clock,
326 COMM_DIR_TX)) { 326 COMM_DIR_TX)) {
327 printk(KERN_ERR "%s: illegal value for TX clock\n", 327 printk(KERN_ERR "%s: illegal value for TX clock\n",
328 __FUNCTION__); 328 __func__);
329 ucc_slow_free(uccs); 329 ucc_slow_free(uccs);
330 return -EINVAL; 330 return -EINVAL;
331 } 331 }
diff --git a/arch/powerpc/sysdev/rtc_cmos_setup.c b/arch/powerpc/sysdev/rtc_cmos_setup.c
index 0c9ac7ee08fb..c09ddc0dbeb3 100644
--- a/arch/powerpc/sysdev/rtc_cmos_setup.c
+++ b/arch/powerpc/sysdev/rtc_cmos_setup.c
@@ -56,3 +56,5 @@ static int __init add_rtc(void)
56 return 0; 56 return 0;
57} 57}
58fs_initcall(add_rtc); 58fs_initcall(add_rtc);
59
60MODULE_LICENSE("GPL");
diff --git a/arch/powerpc/sysdev/tsi108_dev.c b/arch/powerpc/sysdev/tsi108_dev.c
index be2808a292f7..d4d15aaf18fa 100644
--- a/arch/powerpc/sysdev/tsi108_dev.c
+++ b/arch/powerpc/sysdev/tsi108_dev.c
@@ -84,7 +84,7 @@ static int __init tsi108_eth_of_init(void)
84 84
85 ret = of_address_to_resource(np, 0, &r[0]); 85 ret = of_address_to_resource(np, 0, &r[0]);
86 DBG("%s: name:start->end = %s:0x%lx-> 0x%lx\n", 86 DBG("%s: name:start->end = %s:0x%lx-> 0x%lx\n",
87 __FUNCTION__,r[0].name, r[0].start, r[0].end); 87 __func__,r[0].name, r[0].start, r[0].end);
88 if (ret) 88 if (ret)
89 goto err; 89 goto err;
90 90
@@ -93,7 +93,7 @@ static int __init tsi108_eth_of_init(void)
93 r[1].end = irq_of_parse_and_map(np, 0); 93 r[1].end = irq_of_parse_and_map(np, 0);
94 r[1].flags = IORESOURCE_IRQ; 94 r[1].flags = IORESOURCE_IRQ;
95 DBG("%s: name:start->end = %s:0x%lx-> 0x%lx\n", 95 DBG("%s: name:start->end = %s:0x%lx-> 0x%lx\n",
96 __FUNCTION__,r[1].name, r[1].start, r[1].end); 96 __func__,r[1].name, r[1].start, r[1].end);
97 97
98 tsi_eth_dev = 98 tsi_eth_dev =
99 platform_device_register_simple("tsi-ethernet", i++, &r[0], 99 platform_device_register_simple("tsi-ethernet", i++, &r[0],
diff --git a/arch/powerpc/sysdev/tsi108_pci.c b/arch/powerpc/sysdev/tsi108_pci.c
index 31d3d33d91fc..ac1a72dc21e5 100644
--- a/arch/powerpc/sysdev/tsi108_pci.c
+++ b/arch/powerpc/sysdev/tsi108_pci.c
@@ -207,7 +207,7 @@ int __init tsi108_setup_pci(struct device_node *dev, u32 cfg_phys, int primary)
207 /* PCI Config mapping */ 207 /* PCI Config mapping */
208 tsi108_pci_cfg_base = (u32)ioremap(cfg_phys, TSI108_PCI_CFG_SIZE); 208 tsi108_pci_cfg_base = (u32)ioremap(cfg_phys, TSI108_PCI_CFG_SIZE);
209 tsi108_pci_cfg_phys = cfg_phys; 209 tsi108_pci_cfg_phys = cfg_phys;
210 DBG("TSI_PCI: %s tsi108_pci_cfg_base=0x%x\n", __FUNCTION__, 210 DBG("TSI_PCI: %s tsi108_pci_cfg_base=0x%x\n", __func__,
211 tsi108_pci_cfg_base); 211 tsi108_pci_cfg_base);
212 212
213 /* Fetch host bridge registers address */ 213 /* Fetch host bridge registers address */
@@ -395,7 +395,7 @@ static int pci_irq_host_xlate(struct irq_host *h, struct device_node *ct,
395static int pci_irq_host_map(struct irq_host *h, unsigned int virq, 395static int pci_irq_host_map(struct irq_host *h, unsigned int virq,
396 irq_hw_number_t hw) 396 irq_hw_number_t hw)
397{ unsigned int irq; 397{ unsigned int irq;
398 DBG("%s(%d, 0x%lx)\n", __FUNCTION__, virq, hw); 398 DBG("%s(%d, 0x%lx)\n", __func__, virq, hw);
399 if ((virq >= 1) && (virq <= 4)){ 399 if ((virq >= 1) && (virq <= 4)){
400 irq = virq + IRQ_PCI_INTAD_BASE - 1; 400 irq = virq + IRQ_PCI_INTAD_BASE - 1;
401 get_irq_desc(irq)->status |= IRQ_LEVEL; 401 get_irq_desc(irq)->status |= IRQ_LEVEL;
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-11 04:33:01 -0500