3 files changed, 196 insertions, 18 deletions

diff --git a/arch/powerpc/sysdev/Makefile b/arch/powerpc/sysdev/Makefile
index b33b28a6fe12..2d1c87dd5d14 100644
--- a/arch/powerpc/sysdev/Makefile
+++ b/arch/powerpc/sysdev/Makefile
@@ -34,6 +34,7 @@ obj-$(CONFIG_IPIC)		+= ipic.o
 obj-$(CONFIG_4xx)               += uic.o
 obj-$(CONFIG_4xx_SOC)           += ppc4xx_soc.o
 obj-$(CONFIG_XILINX_VIRTEX)     += xilinx_intc.o
+obj-$(CONFIG_XILINX_PCI)        += xilinx_pci.o
 obj-$(CONFIG_OF_RTC)            += of_rtc.o
 ifeq ($(CONFIG_PCI),y)
 obj-$(CONFIG_4xx)               += ppc4xx_pci.o
diff --git a/arch/powerpc/sysdev/xilinx_intc.c b/arch/powerpc/sysdev/xilinx_intc.c
index c658b413c9b4..3ee1fd37bbfc 100644
--- a/arch/powerpc/sysdev/xilinx_intc.c
+++ b/arch/powerpc/sysdev/xilinx_intc.c
@@ -25,6 +25,7 @@
 #include <linux/of.h>
 #include <asm/io.h>
 #include <asm/processor.h>
+#include <asm/i8259.h>
 #include <asm/irq.h>
 
 /*
@@ -191,20 +192,14 @@ struct irq_host * __init
 xilinx_intc_init(struct device_node *np)
 {
         struct irq_host * irq;
-        struct resource res;
         void * regs;
-        int rc;
 
         /* Find and map the intc registers */
-        rc = of_address_to_resource(np, 0, &res);
-        if (rc) {
-                printk(KERN_ERR __FILE__ ": of_address_to_resource() failed\n");
+        regs = of_iomap(np, 0);
+        if (!regs) {
+                pr_err("xilinx_intc: could not map registers\n");
                 return NULL;
         }
-        regs = ioremap(res.start, 32);
-
-        printk(KERN_INFO "Xilinx intc at 0x%08llx mapped to 0x%p\n",
-                (unsigned long long) res.start, regs);
 
         /* Setup interrupt controller */
         out_be32(regs + XINTC_IER, 0); /* disable all irqs */
@@ -217,6 +212,7 @@ xilinx_intc_init(struct device_node *np)
         if (!irq)
                 panic(__FILE__ ": Cannot allocate IRQ host\n");
         irq->host_data = regs;
+
         return irq;
 }
 
@@ -227,23 +223,70 @@ int xilinx_intc_get_irq(void)
         return irq_linear_revmap(master_irqhost, in_be32(regs + XINTC_IVR));
 }
 
+#if defined(CONFIG_PPC_I8259)
+/*
+ * Support code for cascading to 8259 interrupt controllers
+ */
+static void xilinx_i8259_cascade(unsigned int irq, struct irq_desc *desc)
+{
+        unsigned int cascade_irq = i8259_irq();
+        if (cascade_irq)
+                generic_handle_irq(cascade_irq);
+
+        /* Let xilinx_intc end the interrupt */
+        desc->chip->ack(irq);
+        desc->chip->unmask(irq);
+}
+
+static void __init xilinx_i8259_setup_cascade(void)
+{
+        struct device_node *cascade_node;
+        int cascade_irq;
+
+        /* Initialize i8259 controller */
+        cascade_node = of_find_compatible_node(NULL, NULL, "chrp,iic");
+        if (!cascade_node)
+                return;
+
+        cascade_irq = irq_of_parse_and_map(cascade_node, 0);
+        if (!cascade_irq) {
+                pr_err("virtex_ml510: Failed to map cascade interrupt\n");
+                goto out;
+        }
+
+        i8259_init(cascade_node, 0);
+        set_irq_chained_handler(cascade_irq, xilinx_i8259_cascade);
+
+        /* Program irq 7 (usb/audio), 14/15 (ide) to level sensitive */
+        /* This looks like a dirty hack to me --gcl */
+        outb(0xc0, 0x4d0);
+        outb(0xc0, 0x4d1);
+
+ out:
+        of_node_put(cascade_node);
+}
+#else
+static inline void xilinx_i8259_setup_cascade(void) { return; }
+#endif /* defined(CONFIG_PPC_I8259) */
+
+static struct of_device_id xilinx_intc_match[] __initconst = {
+        { .compatible = "xlnx,opb-intc-1.00.c", },
+        { .compatible = "xlnx,xps-intc-1.00.a", },
+        {}
+};
+
+/*
+ * Initialize master Xilinx interrupt controller
+ */
 void __init xilinx_intc_init_tree(void)
 {
         struct device_node *np;
 
         /* find top level interrupt controller */
-        for_each_compatible_node(np, NULL, "xlnx,opb-intc-1.00.c") {
+        for_each_matching_node(np, xilinx_intc_match) {
                 if (!of_get_property(np, "interrupts", NULL))
                         break;
         }
-        if (!np) {
-                for_each_compatible_node(np, NULL, "xlnx,xps-intc-1.00.a") {
-                        if (!of_get_property(np, "interrupts", NULL))
-                                break;
-                }
-        }
-
-        /* xilinx interrupt controller needs to be top level */
         BUG_ON(!np);
 
         master_irqhost = xilinx_intc_init(np);
@@ -251,4 +294,6 @@ void __init xilinx_intc_init_tree(void)
 
         irq_set_default_host(master_irqhost);
         of_node_put(np);
+
+        xilinx_i8259_setup_cascade();
 }
diff --git a/arch/powerpc/sysdev/xilinx_pci.c b/arch/powerpc/sysdev/xilinx_pci.c
new file mode 100644
index 000000000000..1453b0eed220
--- /dev/null
+++ b/arch/powerpc/sysdev/xilinx_pci.c
@@ -0,0 +1,132 @@
+/*
+ * PCI support for Xilinx plbv46_pci soft-core which can be used on
+ * Xilinx Virtex ML410 / ML510 boards.
+ *
+ * Copyright 2009 Roderick Colenbrander
+ * Copyright 2009 Secret Lab Technologies Ltd.
+ *
+ * The pci bridge fixup code was copied from ppc4xx_pci.c and was written
+ * by Benjamin Herrenschmidt.
+ * Copyright 2007 Ben. Herrenschmidt <benh@kernel.crashing.org>, IBM Corp.
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+#include <linux/ioport.h>
+#include <linux/of.h>
+#include <linux/pci.h>
+#include <mm/mmu_decl.h>
+#include <asm/io.h>
+#include <asm/xilinx_pci.h>
+
+#define XPLB_PCI_ADDR 0x10c
+#define XPLB_PCI_DATA 0x110
+#define XPLB_PCI_BUS  0x114
+
+#define PCI_HOST_ENABLE_CMD PCI_COMMAND_SERR | PCI_COMMAND_PARITY | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY
+
+static struct of_device_id xilinx_pci_match[] = {
+        { .compatible = "xlnx,plbv46-pci-1.03.a", },
+        {}
+};
+
+/**
+ * xilinx_pci_fixup_bridge - Block Xilinx PHB configuration.
+ */
+static void xilinx_pci_fixup_bridge(struct pci_dev *dev)
+{
+        struct pci_controller *hose;
+        int i;
+
+        if (dev->devfn || dev->bus->self)
+                return;
+
+        hose = pci_bus_to_host(dev->bus);
+        if (!hose)
+                return;
+
+        if (!of_match_node(xilinx_pci_match, hose->dn))
+                return;
+
+        /* Hide the PCI host BARs from the kernel as their content doesn't
+         * fit well in the resource management
+         */
+        for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
+                dev->resource[i].start = 0;
+                dev->resource[i].end = 0;
+                dev->resource[i].flags = 0;
+        }
+
+        dev_info(&dev->dev, "Hiding Xilinx plb-pci host bridge resources %s\n",
+                 pci_name(dev));
+}
+DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, xilinx_pci_fixup_bridge);
+
+/**
+ * xilinx_pci_exclude_device - Don't do config access for non-root bus
+ *
+ * This is a hack.  Config access to any bus other than bus 0 does not
+ * currently work on the ML510 so we prevent it here.
+ */
+static int
+xilinx_pci_exclude_device(struct pci_controller *hose, u_char bus, u8 devfn)
+{
+        return (bus != 0);
+}
+
+/**
+ * xilinx_pci_init - Find and register a Xilinx PCI host bridge
+ */
+void __init xilinx_pci_init(void)
+{
+        struct pci_controller *hose;
+        struct resource r;
+        void __iomem *pci_reg;
+        struct device_node *pci_node;
+
+        pci_node = of_find_matching_node(NULL, xilinx_pci_match);
+        if(!pci_node)
+                return;
+
+        if (of_address_to_resource(pci_node, 0, &r)) {
+                pr_err("xilinx-pci: cannot resolve base address\n");
+                return;
+        }
+
+        hose = pcibios_alloc_controller(pci_node);
+        if (!hose) {
+                pr_err("xilinx-pci: pcibios_alloc_controller() failed\n");
+                return;
+        }
+
+        /* Setup config space */
+        setup_indirect_pci(hose, r.start + XPLB_PCI_ADDR,
+                           r.start + XPLB_PCI_DATA,
+                           PPC_INDIRECT_TYPE_SET_CFG_TYPE);
+
+        /* According to the xilinx plbv46_pci documentation the soft-core starts
+         * a self-init when the bus master enable bit is set. Without this bit
+         * set the pci bus can't be scanned.
+         */
+        early_write_config_word(hose, 0, 0, PCI_COMMAND, PCI_HOST_ENABLE_CMD);
+
+        /* Set the max latency timer to 255 */
+        early_write_config_byte(hose, 0, 0, PCI_LATENCY_TIMER, 0xff);
+
+        /* Set the max bus number to 255 */
+        pci_reg = of_iomap(pci_node, 0);
+        out_8(pci_reg + XPLB_PCI_BUS, 0xff);
+        iounmap(pci_reg);
+
+        /* Nothing past the root bridge is working right now.  By default
+         * exclude config access to anything except bus 0 */
+        if (!ppc_md.pci_exclude_device)
+                ppc_md.pci_exclude_device = xilinx_pci_exclude_device;
+
+        /* Register the host bridge with the linux kernel! */
+        pci_process_bridge_OF_ranges(hose, pci_node, 1);
+
+        pr_info("xilinx-pci: Registered PCI host bridge\n");
+}