4 files changed, 394 insertions, 159 deletions

diff --git a/arch/powerpc/sysdev/Makefile b/arch/powerpc/sysdev/Makefile
index cebfae242602..e5e999ea891a 100644
--- a/arch/powerpc/sysdev/Makefile
+++ b/arch/powerpc/sysdev/Makefile
@@ -9,11 +9,11 @@ obj-$(CONFIG_BOOKE)		+= dcr.o
 obj-$(CONFIG_40x)               += dcr.o
 obj-$(CONFIG_U3_DART)           += dart_iommu.o
 obj-$(CONFIG_MMIO_NVRAM)        += mmio_nvram.o
-obj-$(CONFIG_PPC_83xx)          += ipic.o
 obj-$(CONFIG_FSL_SOC)           += fsl_soc.o
 obj-$(CONFIG_PPC_TODC)          += todc.o
 obj-$(CONFIG_TSI108_BRIDGE)     += tsi108_pci.o tsi108_dev.o
 
 ifeq ($(CONFIG_PPC_MERGE),y)
 obj-$(CONFIG_PPC_I8259)         += i8259.o
- endif
+obj-$(CONFIG_PPC_83xx)          += ipic.o
+endif
diff --git a/arch/powerpc/sysdev/ipic.c b/arch/powerpc/sysdev/ipic.c
index 46801f5ec03f..70e707785d49 100644
--- a/arch/powerpc/sysdev/ipic.c
+++ b/arch/powerpc/sysdev/ipic.c
@@ -19,15 +19,18 @@
 #include <linux/sched.h>
 #include <linux/signal.h>
 #include <linux/sysdev.h>
+#include <linux/device.h>
+#include <linux/bootmem.h>
+#include <linux/spinlock.h>
 #include <asm/irq.h>
 #include <asm/io.h>
+#include <asm/prom.h>
 #include <asm/ipic.h>
-#include <asm/mpc83xx.h>
 
 #include "ipic.h"
 
-static struct ipic p_ipic;
 static struct ipic * primary_ipic;
+static DEFINE_SPINLOCK(ipic_lock);
 
 static struct ipic_info ipic_info[] = {
         [9] = {
@@ -373,74 +376,220 @@ static inline void ipic_write(volatile u32 __iomem *base, unsigned int reg, u32
         out_be32(base + (reg >> 2), value);
 }
 
-static inline struct ipic * ipic_from_irq(unsigned int irq)
+static inline struct ipic * ipic_from_irq(unsigned int virq)
 {
         return primary_ipic;
 }
 
-static void ipic_enable_irq(unsigned int irq)
+#define ipic_irq_to_hw(virq)    ((unsigned int)irq_map[virq].hwirq)
+
+static void ipic_unmask_irq(unsigned int virq)
 {
-        struct ipic *ipic = ipic_from_irq(irq);
-        unsigned int src = irq - ipic->irq_offset;
+        struct ipic *ipic = ipic_from_irq(virq);
+        unsigned int src = ipic_irq_to_hw(virq);
+        unsigned long flags;
         u32 temp;
 
+        spin_lock_irqsave(&ipic_lock, flags);
+
         temp = ipic_read(ipic->regs, ipic_info[src].mask);
         temp |= (1 << (31 - ipic_info[src].bit));
         ipic_write(ipic->regs, ipic_info[src].mask, temp);
+
+        spin_unlock_irqrestore(&ipic_lock, flags);
 }
 
-static void ipic_disable_irq(unsigned int irq)
+static void ipic_mask_irq(unsigned int virq)
 {
-        struct ipic *ipic = ipic_from_irq(irq);
-        unsigned int src = irq - ipic->irq_offset;
+        struct ipic *ipic = ipic_from_irq(virq);
+        unsigned int src = ipic_irq_to_hw(virq);
+        unsigned long flags;
         u32 temp;
 
+        spin_lock_irqsave(&ipic_lock, flags);
+
         temp = ipic_read(ipic->regs, ipic_info[src].mask);
         temp &= ~(1 << (31 - ipic_info[src].bit));
         ipic_write(ipic->regs, ipic_info[src].mask, temp);
+
+        spin_unlock_irqrestore(&ipic_lock, flags);
 }
 
-static void ipic_disable_irq_and_ack(unsigned int irq)
+static void ipic_ack_irq(unsigned int virq)
 {
-        struct ipic *ipic = ipic_from_irq(irq);
-        unsigned int src = irq - ipic->irq_offset;
+        struct ipic *ipic = ipic_from_irq(virq);
+        unsigned int src = ipic_irq_to_hw(virq);
+        unsigned long flags;
         u32 temp;
 
-        ipic_disable_irq(irq);
+        spin_lock_irqsave(&ipic_lock, flags);
 
         temp = ipic_read(ipic->regs, ipic_info[src].pend);
         temp |= (1 << (31 - ipic_info[src].bit));
         ipic_write(ipic->regs, ipic_info[src].pend, temp);
+
+        spin_unlock_irqrestore(&ipic_lock, flags);
 }
 
-static void ipic_end_irq(unsigned int irq)
+static void ipic_mask_irq_and_ack(unsigned int virq)
 {
-        if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
-                ipic_enable_irq(irq);
+        struct ipic *ipic = ipic_from_irq(virq);
+        unsigned int src = ipic_irq_to_hw(virq);
+        unsigned long flags;
+        u32 temp;
+
+        spin_lock_irqsave(&ipic_lock, flags);
+
+        temp = ipic_read(ipic->regs, ipic_info[src].mask);
+        temp &= ~(1 << (31 - ipic_info[src].bit));
+        ipic_write(ipic->regs, ipic_info[src].mask, temp);
+
+        temp = ipic_read(ipic->regs, ipic_info[src].pend);
+        temp |= (1 << (31 - ipic_info[src].bit));
+        ipic_write(ipic->regs, ipic_info[src].pend, temp);
+
+        spin_unlock_irqrestore(&ipic_lock, flags);
 }
 
-struct hw_interrupt_type ipic = {
-        .typename = " IPIC  ",
-        .enable = ipic_enable_irq,
-        .disable = ipic_disable_irq,
-        .ack = ipic_disable_irq_and_ack,
-        .end = ipic_end_irq,
+static int ipic_set_irq_type(unsigned int virq, unsigned int flow_type)
+{
+        struct ipic *ipic = ipic_from_irq(virq);
+        unsigned int src = ipic_irq_to_hw(virq);
+        struct irq_desc *desc = get_irq_desc(virq);
+        unsigned int vold, vnew, edibit;
+
+        if (flow_type == IRQ_TYPE_NONE)
+                flow_type = IRQ_TYPE_LEVEL_LOW;
+
+        /* ipic supports only low assertion and high-to-low change senses
+         */
+        if (!(flow_type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_EDGE_FALLING))) {
+                printk(KERN_ERR "ipic: sense type 0x%x not supported\n",
+                        flow_type);
+                return -EINVAL;
+        }
+
+        desc->status &= ~(IRQ_TYPE_SENSE_MASK | IRQ_LEVEL);
+        desc->status |= flow_type & IRQ_TYPE_SENSE_MASK;
+        if (flow_type & IRQ_TYPE_LEVEL_LOW)  {
+                desc->status |= IRQ_LEVEL;
+                set_irq_handler(virq, handle_level_irq);
+        } else {
+                set_irq_handler(virq, handle_edge_irq);
+        }
+
+        /* only EXT IRQ senses are programmable on ipic
+         * internal IRQ senses are LEVEL_LOW
+         */
+        if (src == IPIC_IRQ_EXT0)
+                edibit = 15;
+        else
+                if (src >= IPIC_IRQ_EXT1 && src <= IPIC_IRQ_EXT7)
+                        edibit = (14 - (src - IPIC_IRQ_EXT1));
+                else
+                        return (flow_type & IRQ_TYPE_LEVEL_LOW) ? 0 : -EINVAL;
+
+        vold = ipic_read(ipic->regs, IPIC_SECNR);
+        if ((flow_type & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_FALLING) {
+                vnew = vold | (1 << edibit);
+        } else {
+                vnew = vold & ~(1 << edibit);
+        }
+        if (vold != vnew)
+                ipic_write(ipic->regs, IPIC_SECNR, vnew);
+        return 0;
+}
+
+static struct irq_chip ipic_irq_chip = {
+        .typename       = " IPIC  ",
+        .unmask         = ipic_unmask_irq,
+        .mask           = ipic_mask_irq,
+        .mask_ack       = ipic_mask_irq_and_ack,
+        .ack            = ipic_ack_irq,
+        .set_type       = ipic_set_irq_type,
+};
+
+static int ipic_host_match(struct irq_host *h, struct device_node *node)
+{
+        struct ipic *ipic = h->host_data;
+
+        /* Exact match, unless ipic node is NULL */
+        return ipic->of_node == NULL || ipic->of_node == node;
+}
+
+static int ipic_host_map(struct irq_host *h, unsigned int virq,
+                         irq_hw_number_t hw)
+{
+        struct ipic *ipic = h->host_data;
+        struct irq_chip *chip;
+
+        /* Default chip */
+        chip = &ipic->hc_irq;
+
+        set_irq_chip_data(virq, ipic);
+        set_irq_chip_and_handler(virq, chip, handle_level_irq);
+
+        /* Set default irq type */
+        set_irq_type(virq, IRQ_TYPE_NONE);
+
+        return 0;
+}
+
+static int ipic_host_xlate(struct irq_host *h, struct device_node *ct,
+                           u32 *intspec, unsigned int intsize,
+                           irq_hw_number_t *out_hwirq, unsigned int *out_flags)
+
+{
+        /* interrupt sense values coming from the device tree equal either
+         * LEVEL_LOW (low assertion) or EDGE_FALLING (high-to-low change)
+         */
+        *out_hwirq = intspec[0];
+        if (intsize > 1)
+                *out_flags = intspec[1];
+        else
+                *out_flags = IRQ_TYPE_NONE;
+        return 0;
+}
+
+static struct irq_host_ops ipic_host_ops = {
+        .match  = ipic_host_match,
+        .map    = ipic_host_map,
+        .xlate  = ipic_host_xlate,
 };
 
-void __init ipic_init(phys_addr_t phys_addr,
-                unsigned int flags,
-                unsigned int irq_offset,
-                unsigned char *senses,
-                unsigned int senses_count)
+void __init ipic_init(struct device_node *node,
+                unsigned int flags)
 {
-        u32 i, temp = 0;
+        struct ipic     *ipic;
+        struct resource res;
+        u32 temp = 0, ret;
+
+        ipic = alloc_bootmem(sizeof(struct ipic));
+        if (ipic == NULL)
+                return;
+
+        memset(ipic, 0, sizeof(struct ipic));
+        ipic->of_node = node ? of_node_get(node) : NULL;
+
+        ipic->irqhost = irq_alloc_host(IRQ_HOST_MAP_LINEAR,
+                                       NR_IPIC_INTS,
+                                       &ipic_host_ops, 0);
+        if (ipic->irqhost == NULL) {
+                of_node_put(node);
+                return;
+        }
+
+        ret = of_address_to_resource(node, 0, &res);
+        if (ret)
+                return;
 
-        primary_ipic = &p_ipic;
-        primary_ipic->regs = ioremap(phys_addr, MPC83xx_IPIC_SIZE);
+        ipic->regs = ioremap(res.start, res.end - res.start + 1);
 
-        primary_ipic->irq_offset = irq_offset;
+        ipic->irqhost->host_data = ipic;
+        ipic->hc_irq = ipic_irq_chip;
 
-        ipic_write(primary_ipic->regs, IPIC_SICNR, 0x0);
+        /* init hw */
+        ipic_write(ipic->regs, IPIC_SICNR, 0x0);
 
         /* default priority scheme is grouped. If spread mode is required
          * configure SICFR accordingly */
@@ -453,49 +602,35 @@ void __init ipic_init(phys_addr_t phys_addr,
         if (flags & IPIC_SPREADMODE_MIX_B)
                 temp |= SICFR_MPSB;
 
-        ipic_write(primary_ipic->regs, IPIC_SICNR, temp);
+        ipic_write(ipic->regs, IPIC_SICNR, temp);
 
         /* handle MCP route */
         temp = 0;
         if (flags & IPIC_DISABLE_MCP_OUT)
                 temp = SERCR_MCPR;
-        ipic_write(primary_ipic->regs, IPIC_SERCR, temp);
+        ipic_write(ipic->regs, IPIC_SERCR, temp);
 
         /* handle routing of IRQ0 to MCP */
-        temp = ipic_read(primary_ipic->regs, IPIC_SEMSR);
+        temp = ipic_read(ipic->regs, IPIC_SEMSR);
 
         if (flags & IPIC_IRQ0_MCP)
                 temp |= SEMSR_SIRQ0;
         else
                 temp &= ~SEMSR_SIRQ0;
 
-        ipic_write(primary_ipic->regs, IPIC_SEMSR, temp);
+        ipic_write(ipic->regs, IPIC_SEMSR, temp);
 
-        for (i = 0 ; i < NR_IPIC_INTS ; i++) {
-                irq_desc[i+irq_offset].chip = &ipic;
-                irq_desc[i+irq_offset].status = IRQ_LEVEL;
-        }
+        primary_ipic = ipic;
+        irq_set_default_host(primary_ipic->irqhost);
 
-        temp = 0;
-        for (i = 0 ; i < senses_count ; i++) {
-                if ((senses[i] & IRQ_SENSE_MASK) == IRQ_SENSE_EDGE) {
-                        temp |= 1 << (15 - i);
-                        if (i != 0)
-                                irq_desc[i + irq_offset + MPC83xx_IRQ_EXT1 - 1].status = 0;
-                        else
-                                irq_desc[irq_offset + MPC83xx_IRQ_EXT0].status = 0;
-                }
-        }
-        ipic_write(primary_ipic->regs, IPIC_SECNR, temp);
-
-        printk ("IPIC (%d IRQ sources, %d External IRQs) at %p\n", NR_IPIC_INTS,
-                        senses_count, primary_ipic->regs);
+        printk ("IPIC (%d IRQ sources) at %p\n", NR_IPIC_INTS,
+                        primary_ipic->regs);
 }
 
-int ipic_set_priority(unsigned int irq, unsigned int priority)
+int ipic_set_priority(unsigned int virq, unsigned int priority)
 {
-        struct ipic *ipic = ipic_from_irq(irq);
-        unsigned int src = irq - ipic->irq_offset;
+        struct ipic *ipic = ipic_from_irq(virq);
+        unsigned int src = ipic_irq_to_hw(virq);
         u32 temp;
 
         if (priority > 7)
@@ -520,10 +655,10 @@ int ipic_set_priority(unsigned int irq, unsigned int priority)
         return 0;
 }
 
-void ipic_set_highest_priority(unsigned int irq)
+void ipic_set_highest_priority(unsigned int virq)
 {
-        struct ipic *ipic = ipic_from_irq(irq);
-        unsigned int src = irq - ipic->irq_offset;
+        struct ipic *ipic = ipic_from_irq(virq);
+        unsigned int src = ipic_irq_to_hw(virq);
         u32 temp;
 
         temp = ipic_read(ipic->regs, IPIC_SICFR);
@@ -537,37 +672,10 @@ void ipic_set_highest_priority(unsigned int irq)
 
 void ipic_set_default_priority(void)
 {
-        ipic_set_priority(MPC83xx_IRQ_TSEC1_TX, 0);
-        ipic_set_priority(MPC83xx_IRQ_TSEC1_RX, 1);
-        ipic_set_priority(MPC83xx_IRQ_TSEC1_ERROR, 2);
-        ipic_set_priority(MPC83xx_IRQ_TSEC2_TX, 3);
-        ipic_set_priority(MPC83xx_IRQ_TSEC2_RX, 4);
-        ipic_set_priority(MPC83xx_IRQ_TSEC2_ERROR, 5);
-        ipic_set_priority(MPC83xx_IRQ_USB2_DR, 6);
-        ipic_set_priority(MPC83xx_IRQ_USB2_MPH, 7);
-
-        ipic_set_priority(MPC83xx_IRQ_UART1, 0);
-        ipic_set_priority(MPC83xx_IRQ_UART2, 1);
-        ipic_set_priority(MPC83xx_IRQ_SEC2, 2);
-        ipic_set_priority(MPC83xx_IRQ_IIC1, 5);
-        ipic_set_priority(MPC83xx_IRQ_IIC2, 6);
-        ipic_set_priority(MPC83xx_IRQ_SPI, 7);
-        ipic_set_priority(MPC83xx_IRQ_RTC_SEC, 0);
-        ipic_set_priority(MPC83xx_IRQ_PIT, 1);
-        ipic_set_priority(MPC83xx_IRQ_PCI1, 2);
-        ipic_set_priority(MPC83xx_IRQ_PCI2, 3);
-        ipic_set_priority(MPC83xx_IRQ_EXT0, 4);
-        ipic_set_priority(MPC83xx_IRQ_EXT1, 5);
-        ipic_set_priority(MPC83xx_IRQ_EXT2, 6);
-        ipic_set_priority(MPC83xx_IRQ_EXT3, 7);
-        ipic_set_priority(MPC83xx_IRQ_RTC_ALR, 0);
-        ipic_set_priority(MPC83xx_IRQ_MU, 1);
-        ipic_set_priority(MPC83xx_IRQ_SBA, 2);
-        ipic_set_priority(MPC83xx_IRQ_DMA, 3);
-        ipic_set_priority(MPC83xx_IRQ_EXT4, 4);
-        ipic_set_priority(MPC83xx_IRQ_EXT5, 5);
-        ipic_set_priority(MPC83xx_IRQ_EXT6, 6);
-        ipic_set_priority(MPC83xx_IRQ_EXT7, 7);
+        ipic_write(primary_ipic->regs, IPIC_SIPRR_A, IPIC_SIPRR_A_DEFAULT);
+        ipic_write(primary_ipic->regs, IPIC_SIPRR_D, IPIC_SIPRR_D_DEFAULT);
+        ipic_write(primary_ipic->regs, IPIC_SMPRR_A, IPIC_SMPRR_A_DEFAULT);
+        ipic_write(primary_ipic->regs, IPIC_SMPRR_B, IPIC_SMPRR_B_DEFAULT);
 }
 
 void ipic_enable_mcp(enum ipic_mcp_irq mcp_irq)
@@ -600,17 +708,20 @@ void ipic_clear_mcp_status(u32 mask)
         ipic_write(primary_ipic->regs, IPIC_SERMR, mask);
 }
 
-/* Return an interrupt vector or -1 if no interrupt is pending. */
-int ipic_get_irq(struct pt_regs *regs)
+/* Return an interrupt vector or NO_IRQ if no interrupt is pending. */
+unsigned int ipic_get_irq(struct pt_regs *regs)
 {
         int irq;
 
-        irq = ipic_read(primary_ipic->regs, IPIC_SIVCR) & 0x7f;
+        BUG_ON(primary_ipic == NULL);
+
+#define IPIC_SIVCR_VECTOR_MASK  0x7f
+        irq = ipic_read(primary_ipic->regs, IPIC_SIVCR) & IPIC_SIVCR_VECTOR_MASK;
 
         if (irq == 0)    /* 0 --> no irq is pending */
-                irq = -1;
+                return NO_IRQ;
 
-        return irq;
+        return irq_linear_revmap(primary_ipic->irqhost, irq);
 }
 
 static struct sysdev_class ipic_sysclass = {
diff --git a/arch/powerpc/sysdev/ipic.h b/arch/powerpc/sysdev/ipic.h
index a60c9d18bb7f..c28e589877eb 100644
--- a/arch/powerpc/sysdev/ipic.h
+++ b/arch/powerpc/sysdev/ipic.h
@@ -15,7 +15,18 @@
 
 #include <asm/ipic.h>
 
-#define MPC83xx_IPIC_SIZE       (0x00100)
+#define NR_IPIC_INTS 128
+
+/* External IRQS */
+#define IPIC_IRQ_EXT0 48
+#define IPIC_IRQ_EXT1 17
+#define IPIC_IRQ_EXT7 23
+
+/* Default Priority Registers */
+#define IPIC_SIPRR_A_DEFAULT 0x05309770
+#define IPIC_SIPRR_D_DEFAULT 0x05309770
+#define IPIC_SMPRR_A_DEFAULT 0x05309770
+#define IPIC_SMPRR_B_DEFAULT 0x05309770
 
 /* System Global Interrupt Configuration Register */
 #define SICFR_IPSA      0x00010000
@@ -31,7 +42,15 @@
 
 struct ipic {
         volatile u32 __iomem    *regs;
-        unsigned int            irq_offset;
+
+        /* The remapper for this IPIC */
+        struct irq_host         *irqhost;
+
+        /* The "linux" controller struct */
+        struct irq_chip         hc_irq;
+
+        /* The device node of the interrupt controller */
+        struct device_node      *of_node;
 };
 
 struct ipic_info {
diff --git a/arch/powerpc/sysdev/mpic.c b/arch/powerpc/sysdev/mpic.c
index 6e0281afa6c3..b604926401f5 100644
--- a/arch/powerpc/sysdev/mpic.c
+++ b/arch/powerpc/sysdev/mpic.c
@@ -54,6 +54,94 @@ static DEFINE_SPINLOCK(mpic_lock);
 #endif
 #endif
 
+#ifdef CONFIG_MPIC_WEIRD
+static u32 mpic_infos[][MPIC_IDX_END] = {
+        [0] = { /* Original OpenPIC compatible MPIC */
+                MPIC_GREG_BASE,
+                MPIC_GREG_FEATURE_0,
+                MPIC_GREG_GLOBAL_CONF_0,
+                MPIC_GREG_VENDOR_ID,
+                MPIC_GREG_IPI_VECTOR_PRI_0,
+                MPIC_GREG_IPI_STRIDE,
+                MPIC_GREG_SPURIOUS,
+                MPIC_GREG_TIMER_FREQ,
+
+                MPIC_TIMER_BASE,
+                MPIC_TIMER_STRIDE,
+                MPIC_TIMER_CURRENT_CNT,
+                MPIC_TIMER_BASE_CNT,
+                MPIC_TIMER_VECTOR_PRI,
+                MPIC_TIMER_DESTINATION,
+
+                MPIC_CPU_BASE,
+                MPIC_CPU_STRIDE,
+                MPIC_CPU_IPI_DISPATCH_0,
+                MPIC_CPU_IPI_DISPATCH_STRIDE,
+                MPIC_CPU_CURRENT_TASK_PRI,
+                MPIC_CPU_WHOAMI,
+                MPIC_CPU_INTACK,
+                MPIC_CPU_EOI,
+
+                MPIC_IRQ_BASE,
+                MPIC_IRQ_STRIDE,
+                MPIC_IRQ_VECTOR_PRI,
+                MPIC_VECPRI_VECTOR_MASK,
+                MPIC_VECPRI_POLARITY_POSITIVE,
+                MPIC_VECPRI_POLARITY_NEGATIVE,
+                MPIC_VECPRI_SENSE_LEVEL,
+                MPIC_VECPRI_SENSE_EDGE,
+                MPIC_VECPRI_POLARITY_MASK,
+                MPIC_VECPRI_SENSE_MASK,
+                MPIC_IRQ_DESTINATION
+        },
+        [1] = { /* Tsi108/109 PIC */
+                TSI108_GREG_BASE,
+                TSI108_GREG_FEATURE_0,
+                TSI108_GREG_GLOBAL_CONF_0,
+                TSI108_GREG_VENDOR_ID,
+                TSI108_GREG_IPI_VECTOR_PRI_0,
+                TSI108_GREG_IPI_STRIDE,
+                TSI108_GREG_SPURIOUS,
+                TSI108_GREG_TIMER_FREQ,
+
+                TSI108_TIMER_BASE,
+                TSI108_TIMER_STRIDE,
+                TSI108_TIMER_CURRENT_CNT,
+                TSI108_TIMER_BASE_CNT,
+                TSI108_TIMER_VECTOR_PRI,
+                TSI108_TIMER_DESTINATION,
+
+                TSI108_CPU_BASE,
+                TSI108_CPU_STRIDE,
+                TSI108_CPU_IPI_DISPATCH_0,
+                TSI108_CPU_IPI_DISPATCH_STRIDE,
+                TSI108_CPU_CURRENT_TASK_PRI,
+                TSI108_CPU_WHOAMI,
+                TSI108_CPU_INTACK,
+                TSI108_CPU_EOI,
+
+                TSI108_IRQ_BASE,
+                TSI108_IRQ_STRIDE,
+                TSI108_IRQ_VECTOR_PRI,
+                TSI108_VECPRI_VECTOR_MASK,
+                TSI108_VECPRI_POLARITY_POSITIVE,
+                TSI108_VECPRI_POLARITY_NEGATIVE,
+                TSI108_VECPRI_SENSE_LEVEL,
+                TSI108_VECPRI_SENSE_EDGE,
+                TSI108_VECPRI_POLARITY_MASK,
+                TSI108_VECPRI_SENSE_MASK,
+                TSI108_IRQ_DESTINATION
+        },
+};
+
+#define MPIC_INFO(name) mpic->hw_set[MPIC_IDX_##name]
+
+#else /* CONFIG_MPIC_WEIRD */
+
+#define MPIC_INFO(name) MPIC_##name
+
+#endif /* CONFIG_MPIC_WEIRD */
+
 /*
  * Register accessor functions
  */
@@ -80,7 +168,8 @@ static inline void _mpic_write(unsigned int be, volatile u32 __iomem *base,
 static inline u32 _mpic_ipi_read(struct mpic *mpic, unsigned int ipi)
 {
         unsigned int be = (mpic->flags & MPIC_BIG_ENDIAN) != 0;
-        unsigned int offset = MPIC_GREG_IPI_VECTOR_PRI_0 + (ipi * 0x10);
+        unsigned int offset = MPIC_INFO(GREG_IPI_VECTOR_PRI_0) +
+                              (ipi * MPIC_INFO(GREG_IPI_STRIDE));
 
         if (mpic->flags & MPIC_BROKEN_IPI)
                 be = !be;
@@ -89,7 +178,8 @@ static inline u32 _mpic_ipi_read(struct mpic *mpic, unsigned int ipi)
 
 static inline void _mpic_ipi_write(struct mpic *mpic, unsigned int ipi, u32 value)
 {
-        unsigned int offset = MPIC_GREG_IPI_VECTOR_PRI_0 + (ipi * 0x10);
+        unsigned int offset = MPIC_INFO(GREG_IPI_VECTOR_PRI_0) +
+                              (ipi * MPIC_INFO(GREG_IPI_STRIDE));
 
         _mpic_write(mpic->flags & MPIC_BIG_ENDIAN, mpic->gregs, offset, value);
 }
@@ -120,7 +210,7 @@ static inline u32 _mpic_irq_read(struct mpic *mpic, unsigned int src_no, unsigne
         unsigned int    idx = src_no & mpic->isu_mask;
 
         return _mpic_read(mpic->flags & MPIC_BIG_ENDIAN, mpic->isus[isu],
-                          reg + (idx * MPIC_IRQ_STRIDE));
+                          reg + (idx * MPIC_INFO(IRQ_STRIDE)));
 }
 
 static inline void _mpic_irq_write(struct mpic *mpic, unsigned int src_no,
@@ -130,7 +220,7 @@ static inline void _mpic_irq_write(struct mpic *mpic, unsigned int src_no,
         unsigned int    idx = src_no & mpic->isu_mask;
 
         _mpic_write(mpic->flags & MPIC_BIG_ENDIAN, mpic->isus[isu],
-                    reg + (idx * MPIC_IRQ_STRIDE), value);
+                    reg + (idx * MPIC_INFO(IRQ_STRIDE)), value);
 }
 
 #define mpic_read(b,r)          _mpic_read(mpic->flags & MPIC_BIG_ENDIAN,(b),(r))
@@ -156,8 +246,8 @@ static void __init mpic_test_broken_ipi(struct mpic *mpic)
 {
         u32 r;
 
-        mpic_write(mpic->gregs, MPIC_GREG_IPI_VECTOR_PRI_0, MPIC_VECPRI_MASK);
-        r = mpic_read(mpic->gregs, MPIC_GREG_IPI_VECTOR_PRI_0);
+        mpic_write(mpic->gregs, MPIC_INFO(GREG_IPI_VECTOR_PRI_0), MPIC_VECPRI_MASK);
+        r = mpic_read(mpic->gregs, MPIC_INFO(GREG_IPI_VECTOR_PRI_0));
 
         if (r == le32_to_cpu(MPIC_VECPRI_MASK)) {
                 printk(KERN_INFO "mpic: Detected reversed IPI registers\n");
@@ -394,8 +484,8 @@ static inline struct mpic * mpic_from_irq(unsigned int irq)
 /* Send an EOI */
 static inline void mpic_eoi(struct mpic *mpic)
 {
-        mpic_cpu_write(MPIC_CPU_EOI, 0);
-        (void)mpic_cpu_read(MPIC_CPU_WHOAMI);
+        mpic_cpu_write(MPIC_INFO(CPU_EOI), 0);
+        (void)mpic_cpu_read(MPIC_INFO(CPU_WHOAMI));
 }
 
 #ifdef CONFIG_SMP
@@ -419,8 +509,8 @@ static void mpic_unmask_irq(unsigned int irq)
 
         DBG("%p: %s: enable_irq: %d (src %d)\n", mpic, mpic->name, irq, src);
 
-        mpic_irq_write(src, MPIC_IRQ_VECTOR_PRI,
-                       mpic_irq_read(src, MPIC_IRQ_VECTOR_PRI) &
+        mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI),
+                       mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) &
                        ~MPIC_VECPRI_MASK);
         /* make sure mask gets to controller before we return to user */
         do {
@@ -428,7 +518,7 @@ static void mpic_unmask_irq(unsigned int irq)
                         printk(KERN_ERR "mpic_enable_irq timeout\n");
                         break;
                 }
-        } while(mpic_irq_read(src, MPIC_IRQ_VECTOR_PRI) & MPIC_VECPRI_MASK);
+        } while(mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) & MPIC_VECPRI_MASK);
 }
 
 static void mpic_mask_irq(unsigned int irq)
@@ -439,8 +529,8 @@ static void mpic_mask_irq(unsigned int irq)
 
         DBG("%s: disable_irq: %d (src %d)\n", mpic->name, irq, src);
 
-        mpic_irq_write(src, MPIC_IRQ_VECTOR_PRI,
-                       mpic_irq_read(src, MPIC_IRQ_VECTOR_PRI) |
+        mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI),
+                       mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) |
                        MPIC_VECPRI_MASK);
 
         /* make sure mask gets to controller before we return to user */
@@ -449,7 +539,7 @@ static void mpic_mask_irq(unsigned int irq)
                         printk(KERN_ERR "mpic_enable_irq timeout\n");
                         break;
                 }
-        } while(!(mpic_irq_read(src, MPIC_IRQ_VECTOR_PRI) & MPIC_VECPRI_MASK));
+        } while(!(mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) & MPIC_VECPRI_MASK));
 }
 
 static void mpic_end_irq(unsigned int irq)
@@ -560,24 +650,28 @@ static void mpic_set_affinity(unsigned int irq, cpumask_t cpumask)
 
         cpus_and(tmp, cpumask, cpu_online_map);
 
-        mpic_irq_write(src, MPIC_IRQ_DESTINATION,
+        mpic_irq_write(src, MPIC_INFO(IRQ_DESTINATION),
                        mpic_physmask(cpus_addr(tmp)[0]));       
 }
 
-static unsigned int mpic_type_to_vecpri(unsigned int type)
+static unsigned int mpic_type_to_vecpri(struct mpic *mpic, unsigned int type)
 {
         /* Now convert sense value */
         switch(type & IRQ_TYPE_SENSE_MASK) {
         case IRQ_TYPE_EDGE_RISING:
-                return MPIC_VECPRI_SENSE_EDGE | MPIC_VECPRI_POLARITY_POSITIVE;
+                return MPIC_INFO(VECPRI_SENSE_EDGE) |
+                       MPIC_INFO(VECPRI_POLARITY_POSITIVE);
         case IRQ_TYPE_EDGE_FALLING:
         case IRQ_TYPE_EDGE_BOTH:
-                return MPIC_VECPRI_SENSE_EDGE | MPIC_VECPRI_POLARITY_NEGATIVE;
+                return MPIC_INFO(VECPRI_SENSE_EDGE) |
+                       MPIC_INFO(VECPRI_POLARITY_NEGATIVE);
         case IRQ_TYPE_LEVEL_HIGH:
-                return MPIC_VECPRI_SENSE_LEVEL | MPIC_VECPRI_POLARITY_POSITIVE;
+                return MPIC_INFO(VECPRI_SENSE_LEVEL) |
+                       MPIC_INFO(VECPRI_POLARITY_POSITIVE);
         case IRQ_TYPE_LEVEL_LOW:
         default:
-                return MPIC_VECPRI_SENSE_LEVEL | MPIC_VECPRI_POLARITY_NEGATIVE;
+                return MPIC_INFO(VECPRI_SENSE_LEVEL) |
+                       MPIC_INFO(VECPRI_POLARITY_NEGATIVE);
         }
 }
 
@@ -609,13 +703,14 @@ static int mpic_set_irq_type(unsigned int virq, unsigned int flow_type)
                 vecpri = MPIC_VECPRI_POLARITY_POSITIVE |
                         MPIC_VECPRI_SENSE_EDGE;
         else
-                vecpri = mpic_type_to_vecpri(flow_type);
+                vecpri = mpic_type_to_vecpri(mpic, flow_type);
 
-        vold = mpic_irq_read(src, MPIC_IRQ_VECTOR_PRI);
-        vnew = vold & ~(MPIC_VECPRI_POLARITY_MASK | MPIC_VECPRI_SENSE_MASK);
+        vold = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI));
+        vnew = vold & ~(MPIC_INFO(VECPRI_POLARITY_MASK) |
+                        MPIC_INFO(VECPRI_SENSE_MASK));
         vnew |= vecpri;
         if (vold != vnew)
-                mpic_irq_write(src, MPIC_IRQ_VECTOR_PRI, vnew);
+                mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI), vnew);
 
         return 0;
 }
@@ -798,17 +893,22 @@ struct mpic * __init mpic_alloc(struct device_node *node,
         mpic->irq_count = irq_count;
         mpic->num_sources = 0; /* so far */
 
+#ifdef CONFIG_MPIC_WEIRD
+        mpic->hw_set = mpic_infos[MPIC_GET_REGSET(flags)];
+#endif
+
         /* Map the global registers */
-        mpic->gregs = ioremap(phys_addr + MPIC_GREG_BASE, 0x1000);
-        mpic->tmregs = mpic->gregs + ((MPIC_TIMER_BASE - MPIC_GREG_BASE) >> 2);
+        mpic->gregs = ioremap(phys_addr + MPIC_INFO(GREG_BASE), 0x1000);
+        mpic->tmregs = mpic->gregs +
+                       ((MPIC_INFO(TIMER_BASE) - MPIC_INFO(GREG_BASE)) >> 2);
         BUG_ON(mpic->gregs == NULL);
 
         /* Reset */
         if (flags & MPIC_WANTS_RESET) {
-                mpic_write(mpic->gregs, MPIC_GREG_GLOBAL_CONF_0,
-                           mpic_read(mpic->gregs, MPIC_GREG_GLOBAL_CONF_0)
+                mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
+                           mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
                            | MPIC_GREG_GCONF_RESET);
-                while( mpic_read(mpic->gregs, MPIC_GREG_GLOBAL_CONF_0)
+                while( mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
                        & MPIC_GREG_GCONF_RESET)
                         mb();
         }
@@ -817,7 +917,7 @@ struct mpic * __init mpic_alloc(struct device_node *node,
          * MPICs, num sources as well. On ISU MPICs, sources are counted
          * as ISUs are added
          */
-        reg = mpic_read(mpic->gregs, MPIC_GREG_FEATURE_0);
+        reg = mpic_read(mpic->gregs, MPIC_INFO(GREG_FEATURE_0));
         mpic->num_cpus = ((reg & MPIC_GREG_FEATURE_LAST_CPU_MASK)
                           >> MPIC_GREG_FEATURE_LAST_CPU_SHIFT) + 1;
         if (isu_size == 0)
@@ -826,16 +926,16 @@ struct mpic * __init mpic_alloc(struct device_node *node,
 
         /* Map the per-CPU registers */
         for (i = 0; i < mpic->num_cpus; i++) {
-                mpic->cpuregs[i] = ioremap(phys_addr + MPIC_CPU_BASE +
-                                           i * MPIC_CPU_STRIDE, 0x1000);
+                mpic->cpuregs[i] = ioremap(phys_addr + MPIC_INFO(CPU_BASE) +
+                                           i * MPIC_INFO(CPU_STRIDE), 0x1000);
                 BUG_ON(mpic->cpuregs[i] == NULL);
         }
 
         /* Initialize main ISU if none provided */
         if (mpic->isu_size == 0) {
                 mpic->isu_size = mpic->num_sources;
-                mpic->isus[0] = ioremap(phys_addr + MPIC_IRQ_BASE,
-                                        MPIC_IRQ_STRIDE * mpic->isu_size);
+                mpic->isus[0] = ioremap(phys_addr + MPIC_INFO(IRQ_BASE),
+                                        MPIC_INFO(IRQ_STRIDE) * mpic->isu_size);
                 BUG_ON(mpic->isus[0] == NULL);
         }
         mpic->isu_shift = 1 + __ilog2(mpic->isu_size - 1);
@@ -879,7 +979,8 @@ void __init mpic_assign_isu(struct mpic *mpic, unsigned int isu_num,
 
         BUG_ON(isu_num >= MPIC_MAX_ISU);
 
-        mpic->isus[isu_num] = ioremap(phys_addr, MPIC_IRQ_STRIDE * mpic->isu_size);
+        mpic->isus[isu_num] = ioremap(phys_addr,
+                                      MPIC_INFO(IRQ_STRIDE) * mpic->isu_size);
         if ((isu_first + mpic->isu_size) > mpic->num_sources)
                 mpic->num_sources = isu_first + mpic->isu_size;
 }
@@ -904,14 +1005,16 @@ void __init mpic_init(struct mpic *mpic)
         printk(KERN_INFO "mpic: Initializing for %d sources\n", mpic->num_sources);
 
         /* Set current processor priority to max */
-        mpic_cpu_write(MPIC_CPU_CURRENT_TASK_PRI, 0xf);
+        mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0xf);
 
         /* Initialize timers: just disable them all */
         for (i = 0; i < 4; i++) {
                 mpic_write(mpic->tmregs,
-                           i * MPIC_TIMER_STRIDE + MPIC_TIMER_DESTINATION, 0);
+                           i * MPIC_INFO(TIMER_STRIDE) +
+                           MPIC_INFO(TIMER_DESTINATION), 0);
                 mpic_write(mpic->tmregs,
-                           i * MPIC_TIMER_STRIDE + MPIC_TIMER_VECTOR_PRI,
+                           i * MPIC_INFO(TIMER_STRIDE) +
+                           MPIC_INFO(TIMER_VECTOR_PRI),
                            MPIC_VECPRI_MASK |
                            (MPIC_VEC_TIMER_0 + i));
         }
@@ -940,21 +1043,22 @@ void __init mpic_init(struct mpic *mpic)
                         (8 << MPIC_VECPRI_PRIORITY_SHIFT);
                 
                 /* init hw */
-                mpic_irq_write(i, MPIC_IRQ_VECTOR_PRI, vecpri);
-                mpic_irq_write(i, MPIC_IRQ_DESTINATION,
+                mpic_irq_write(i, MPIC_INFO(IRQ_VECTOR_PRI), vecpri);
+                mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION),
                                1 << hard_smp_processor_id());
         }
         
         /* Init spurrious vector */
-        mpic_write(mpic->gregs, MPIC_GREG_SPURIOUS, MPIC_VEC_SPURRIOUS);
+        mpic_write(mpic->gregs, MPIC_INFO(GREG_SPURIOUS), MPIC_VEC_SPURRIOUS);
 
-        /* Disable 8259 passthrough */
-        mpic_write(mpic->gregs, MPIC_GREG_GLOBAL_CONF_0,
-                   mpic_read(mpic->gregs, MPIC_GREG_GLOBAL_CONF_0)
-                   | MPIC_GREG_GCONF_8259_PTHROU_DIS);
+        /* Disable 8259 passthrough, if supported */
+        if (!(mpic->flags & MPIC_NO_PTHROU_DIS))
+                mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
+                           mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
+                           | MPIC_GREG_GCONF_8259_PTHROU_DIS);
 
         /* Set current processor priority to 0 */
-        mpic_cpu_write(MPIC_CPU_CURRENT_TASK_PRI, 0);
+        mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0);
 }
 
 void __init mpic_set_clk_ratio(struct mpic *mpic, u32 clock_ratio)
@@ -997,9 +1101,9 @@ void mpic_irq_set_priority(unsigned int irq, unsigned int pri)
                 mpic_ipi_write(src - MPIC_VEC_IPI_0,
                                reg | (pri << MPIC_VECPRI_PRIORITY_SHIFT));
         } else {
-                reg = mpic_irq_read(src, MPIC_IRQ_VECTOR_PRI)
+                reg = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI))
                         & ~MPIC_VECPRI_PRIORITY_MASK;
-                mpic_irq_write(src, MPIC_IRQ_VECTOR_PRI,
+                mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI),
                                reg | (pri << MPIC_VECPRI_PRIORITY_SHIFT));
         }
         spin_unlock_irqrestore(&mpic_lock, flags);
@@ -1017,7 +1121,7 @@ unsigned int mpic_irq_get_priority(unsigned int irq)
         if (is_ipi)
                 reg = mpic_ipi_read(src = MPIC_VEC_IPI_0);
         else
-                reg = mpic_irq_read(src, MPIC_IRQ_VECTOR_PRI);
+                reg = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI));
         spin_unlock_irqrestore(&mpic_lock, flags);
         return (reg & MPIC_VECPRI_PRIORITY_MASK) >> MPIC_VECPRI_PRIORITY_SHIFT;
 }
@@ -1043,12 +1147,12 @@ void mpic_setup_this_cpu(void)
          */
         if (distribute_irqs) {
                 for (i = 0; i < mpic->num_sources ; i++)
-                        mpic_irq_write(i, MPIC_IRQ_DESTINATION,
-                                mpic_irq_read(i, MPIC_IRQ_DESTINATION) | msk);
+                        mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION),
+                                mpic_irq_read(i, MPIC_INFO(IRQ_DESTINATION)) | msk);
         }
 
         /* Set current processor priority to 0 */
-        mpic_cpu_write(MPIC_CPU_CURRENT_TASK_PRI, 0);
+        mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0);
 
         spin_unlock_irqrestore(&mpic_lock, flags);
 #endif /* CONFIG_SMP */
@@ -1058,7 +1162,7 @@ int mpic_cpu_get_priority(void)
 {
         struct mpic *mpic = mpic_primary;
 
-        return mpic_cpu_read(MPIC_CPU_CURRENT_TASK_PRI);
+        return mpic_cpu_read(MPIC_INFO(CPU_CURRENT_TASK_PRI));
 }
 
 void mpic_cpu_set_priority(int prio)
@@ -1066,7 +1170,7 @@ void mpic_cpu_set_priority(int prio)
         struct mpic *mpic = mpic_primary;
 
         prio &= MPIC_CPU_TASKPRI_MASK;
-        mpic_cpu_write(MPIC_CPU_CURRENT_TASK_PRI, prio);
+        mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), prio);
 }
 
 /*
@@ -1088,11 +1192,11 @@ void mpic_teardown_this_cpu(int secondary)
 
         /* let the mpic know we don't want intrs.  */
         for (i = 0; i < mpic->num_sources ; i++)
-                mpic_irq_write(i, MPIC_IRQ_DESTINATION,
-                        mpic_irq_read(i, MPIC_IRQ_DESTINATION) & ~msk);
+                mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION),
+                        mpic_irq_read(i, MPIC_INFO(IRQ_DESTINATION)) & ~msk);
 
         /* Set current processor priority to max */
-        mpic_cpu_write(MPIC_CPU_CURRENT_TASK_PRI, 0xf);
+        mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0xf);
 
         spin_unlock_irqrestore(&mpic_lock, flags);
 }
@@ -1108,7 +1212,8 @@ void mpic_send_ipi(unsigned int ipi_no, unsigned int cpu_mask)
         DBG("%s: send_ipi(ipi_no: %d)\n", mpic->name, ipi_no);
 #endif
 
-        mpic_cpu_write(MPIC_CPU_IPI_DISPATCH_0 + ipi_no * 0x10,
+        mpic_cpu_write(MPIC_INFO(CPU_IPI_DISPATCH_0) +
+                       ipi_no * MPIC_INFO(CPU_IPI_DISPATCH_STRIDE),
                        mpic_physmask(cpu_mask & cpus_addr(cpu_online_map)[0]));
 }
 
@@ -1116,7 +1221,7 @@ unsigned int mpic_get_one_irq(struct mpic *mpic, struct pt_regs *regs)
 {
         u32 src;
 
-        src = mpic_cpu_read(MPIC_CPU_INTACK) & MPIC_VECPRI_VECTOR_MASK;
+        src = mpic_cpu_read(MPIC_INFO(CPU_INTACK)) & MPIC_INFO(VECPRI_VECTOR_MASK);
 #ifdef DEBUG_LOW
         DBG("%s: get_one_irq(): %d\n", mpic->name, src);
 #endif