diff options
Diffstat (limited to 'arch/powerpc/sysdev')
-rw-r--r-- | arch/powerpc/sysdev/mpic.c | 34 | ||||
-rw-r--r-- | arch/powerpc/sysdev/qe_lib/qe.c | 9 |
2 files changed, 24 insertions, 19 deletions
diff --git a/arch/powerpc/sysdev/mpic.c b/arch/powerpc/sysdev/mpic.c index 9c3af5045495..d46de1f0f3ee 100644 --- a/arch/powerpc/sysdev/mpic.c +++ b/arch/powerpc/sysdev/mpic.c | |||
@@ -279,28 +279,29 @@ static void _mpic_map_mmio(struct mpic *mpic, phys_addr_t phys_addr, | |||
279 | } | 279 | } |
280 | 280 | ||
281 | #ifdef CONFIG_PPC_DCR | 281 | #ifdef CONFIG_PPC_DCR |
282 | static void _mpic_map_dcr(struct mpic *mpic, struct mpic_reg_bank *rb, | 282 | static void _mpic_map_dcr(struct mpic *mpic, struct device_node *node, |
283 | struct mpic_reg_bank *rb, | ||
283 | unsigned int offset, unsigned int size) | 284 | unsigned int offset, unsigned int size) |
284 | { | 285 | { |
285 | const u32 *dbasep; | 286 | const u32 *dbasep; |
286 | 287 | ||
287 | dbasep = of_get_property(mpic->irqhost->of_node, "dcr-reg", NULL); | 288 | dbasep = of_get_property(node, "dcr-reg", NULL); |
288 | 289 | ||
289 | rb->dhost = dcr_map(mpic->irqhost->of_node, *dbasep + offset, size); | 290 | rb->dhost = dcr_map(node, *dbasep + offset, size); |
290 | BUG_ON(!DCR_MAP_OK(rb->dhost)); | 291 | BUG_ON(!DCR_MAP_OK(rb->dhost)); |
291 | } | 292 | } |
292 | 293 | ||
293 | static inline void mpic_map(struct mpic *mpic, phys_addr_t phys_addr, | 294 | static inline void mpic_map(struct mpic *mpic, struct device_node *node, |
294 | struct mpic_reg_bank *rb, unsigned int offset, | 295 | phys_addr_t phys_addr, struct mpic_reg_bank *rb, |
295 | unsigned int size) | 296 | unsigned int offset, unsigned int size) |
296 | { | 297 | { |
297 | if (mpic->flags & MPIC_USES_DCR) | 298 | if (mpic->flags & MPIC_USES_DCR) |
298 | _mpic_map_dcr(mpic, rb, offset, size); | 299 | _mpic_map_dcr(mpic, node, rb, offset, size); |
299 | else | 300 | else |
300 | _mpic_map_mmio(mpic, phys_addr, rb, offset, size); | 301 | _mpic_map_mmio(mpic, phys_addr, rb, offset, size); |
301 | } | 302 | } |
302 | #else /* CONFIG_PPC_DCR */ | 303 | #else /* CONFIG_PPC_DCR */ |
303 | #define mpic_map(m,p,b,o,s) _mpic_map_mmio(m,p,b,o,s) | 304 | #define mpic_map(m,n,p,b,o,s) _mpic_map_mmio(m,p,b,o,s) |
304 | #endif /* !CONFIG_PPC_DCR */ | 305 | #endif /* !CONFIG_PPC_DCR */ |
305 | 306 | ||
306 | 307 | ||
@@ -1052,11 +1053,10 @@ struct mpic * __init mpic_alloc(struct device_node *node, | |||
1052 | int intvec_top; | 1053 | int intvec_top; |
1053 | u64 paddr = phys_addr; | 1054 | u64 paddr = phys_addr; |
1054 | 1055 | ||
1055 | mpic = alloc_bootmem(sizeof(struct mpic)); | 1056 | mpic = kzalloc(sizeof(struct mpic), GFP_KERNEL); |
1056 | if (mpic == NULL) | 1057 | if (mpic == NULL) |
1057 | return NULL; | 1058 | return NULL; |
1058 | 1059 | ||
1059 | memset(mpic, 0, sizeof(struct mpic)); | ||
1060 | mpic->name = name; | 1060 | mpic->name = name; |
1061 | 1061 | ||
1062 | mpic->hc_irq = mpic_irq_chip; | 1062 | mpic->hc_irq = mpic_irq_chip; |
@@ -1152,8 +1152,8 @@ struct mpic * __init mpic_alloc(struct device_node *node, | |||
1152 | } | 1152 | } |
1153 | 1153 | ||
1154 | /* Map the global registers */ | 1154 | /* Map the global registers */ |
1155 | mpic_map(mpic, paddr, &mpic->gregs, MPIC_INFO(GREG_BASE), 0x1000); | 1155 | mpic_map(mpic, node, paddr, &mpic->gregs, MPIC_INFO(GREG_BASE), 0x1000); |
1156 | mpic_map(mpic, paddr, &mpic->tmregs, MPIC_INFO(TIMER_BASE), 0x1000); | 1156 | mpic_map(mpic, node, paddr, &mpic->tmregs, MPIC_INFO(TIMER_BASE), 0x1000); |
1157 | 1157 | ||
1158 | /* Reset */ | 1158 | /* Reset */ |
1159 | if (flags & MPIC_WANTS_RESET) { | 1159 | if (flags & MPIC_WANTS_RESET) { |
@@ -1194,7 +1194,7 @@ struct mpic * __init mpic_alloc(struct device_node *node, | |||
1194 | 1194 | ||
1195 | /* Map the per-CPU registers */ | 1195 | /* Map the per-CPU registers */ |
1196 | for (i = 0; i < mpic->num_cpus; i++) { | 1196 | for (i = 0; i < mpic->num_cpus; i++) { |
1197 | mpic_map(mpic, paddr, &mpic->cpuregs[i], | 1197 | mpic_map(mpic, node, paddr, &mpic->cpuregs[i], |
1198 | MPIC_INFO(CPU_BASE) + i * MPIC_INFO(CPU_STRIDE), | 1198 | MPIC_INFO(CPU_BASE) + i * MPIC_INFO(CPU_STRIDE), |
1199 | 0x1000); | 1199 | 0x1000); |
1200 | } | 1200 | } |
@@ -1202,7 +1202,7 @@ struct mpic * __init mpic_alloc(struct device_node *node, | |||
1202 | /* Initialize main ISU if none provided */ | 1202 | /* Initialize main ISU if none provided */ |
1203 | if (mpic->isu_size == 0) { | 1203 | if (mpic->isu_size == 0) { |
1204 | mpic->isu_size = mpic->num_sources; | 1204 | mpic->isu_size = mpic->num_sources; |
1205 | mpic_map(mpic, paddr, &mpic->isus[0], | 1205 | mpic_map(mpic, node, paddr, &mpic->isus[0], |
1206 | MPIC_INFO(IRQ_BASE), MPIC_INFO(IRQ_STRIDE) * mpic->isu_size); | 1206 | MPIC_INFO(IRQ_BASE), MPIC_INFO(IRQ_STRIDE) * mpic->isu_size); |
1207 | } | 1207 | } |
1208 | mpic->isu_shift = 1 + __ilog2(mpic->isu_size - 1); | 1208 | mpic->isu_shift = 1 + __ilog2(mpic->isu_size - 1); |
@@ -1256,8 +1256,10 @@ void __init mpic_assign_isu(struct mpic *mpic, unsigned int isu_num, | |||
1256 | 1256 | ||
1257 | BUG_ON(isu_num >= MPIC_MAX_ISU); | 1257 | BUG_ON(isu_num >= MPIC_MAX_ISU); |
1258 | 1258 | ||
1259 | mpic_map(mpic, paddr, &mpic->isus[isu_num], 0, | 1259 | mpic_map(mpic, mpic->irqhost->of_node, |
1260 | paddr, &mpic->isus[isu_num], 0, | ||
1260 | MPIC_INFO(IRQ_STRIDE) * mpic->isu_size); | 1261 | MPIC_INFO(IRQ_STRIDE) * mpic->isu_size); |
1262 | |||
1261 | if ((isu_first + mpic->isu_size) > mpic->num_sources) | 1263 | if ((isu_first + mpic->isu_size) > mpic->num_sources) |
1262 | mpic->num_sources = isu_first + mpic->isu_size; | 1264 | mpic->num_sources = isu_first + mpic->isu_size; |
1263 | } | 1265 | } |
diff --git a/arch/powerpc/sysdev/qe_lib/qe.c b/arch/powerpc/sysdev/qe_lib/qe.c index b28b0e512d67..237e3654f48c 100644 --- a/arch/powerpc/sysdev/qe_lib/qe.c +++ b/arch/powerpc/sysdev/qe_lib/qe.c | |||
@@ -112,6 +112,7 @@ int qe_issue_cmd(u32 cmd, u32 device, u8 mcn_protocol, u32 cmd_input) | |||
112 | { | 112 | { |
113 | unsigned long flags; | 113 | unsigned long flags; |
114 | u8 mcn_shift = 0, dev_shift = 0; | 114 | u8 mcn_shift = 0, dev_shift = 0; |
115 | u32 ret; | ||
115 | 116 | ||
116 | spin_lock_irqsave(&qe_lock, flags); | 117 | spin_lock_irqsave(&qe_lock, flags); |
117 | if (cmd == QE_RESET) { | 118 | if (cmd == QE_RESET) { |
@@ -139,11 +140,13 @@ int qe_issue_cmd(u32 cmd, u32 device, u8 mcn_protocol, u32 cmd_input) | |||
139 | } | 140 | } |
140 | 141 | ||
141 | /* wait for the QE_CR_FLG to clear */ | 142 | /* wait for the QE_CR_FLG to clear */ |
142 | while(in_be32(&qe_immr->cp.cecr) & QE_CR_FLG) | 143 | ret = spin_event_timeout((in_be32(&qe_immr->cp.cecr) & QE_CR_FLG) == 0, |
143 | cpu_relax(); | 144 | 100, 0); |
145 | /* On timeout (e.g. failure), the expression will be false (ret == 0), | ||
146 | otherwise it will be true (ret == 1). */ | ||
144 | spin_unlock_irqrestore(&qe_lock, flags); | 147 | spin_unlock_irqrestore(&qe_lock, flags); |
145 | 148 | ||
146 | return 0; | 149 | return ret == 1; |
147 | } | 150 | } |
148 | EXPORT_SYMBOL(qe_issue_cmd); | 151 | EXPORT_SYMBOL(qe_issue_cmd); |
149 | 152 | ||