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-rw-r--r--arch/powerpc/sysdev/Makefile1
-rw-r--r--arch/powerpc/sysdev/cpm1.c2
-rw-r--r--arch/powerpc/sysdev/cpm2.c2
-rw-r--r--arch/powerpc/sysdev/dart_iommu.c2
-rw-r--r--arch/powerpc/sysdev/mpic.c32
-rw-r--r--arch/powerpc/sysdev/ppc4xx_pci.c133
-rw-r--r--arch/powerpc/sysdev/ppc4xx_pci.h59
-rw-r--r--arch/powerpc/sysdev/ppc4xx_soc.c200
-rw-r--r--arch/powerpc/sysdev/qe_lib/qe_io.c2
-rw-r--r--arch/powerpc/sysdev/qe_lib/ucc_fast.c32
-rw-r--r--arch/powerpc/sysdev/qe_lib/ucc_slow.c18
-rw-r--r--arch/powerpc/sysdev/tsi108_dev.c4
-rw-r--r--arch/powerpc/sysdev/tsi108_pci.c4
13 files changed, 428 insertions, 63 deletions
diff --git a/arch/powerpc/sysdev/Makefile b/arch/powerpc/sysdev/Makefile
index 15f3e8527d77..851a0be71947 100644
--- a/arch/powerpc/sysdev/Makefile
+++ b/arch/powerpc/sysdev/Makefile
@@ -27,6 +27,7 @@ obj-$(CONFIG_PPC_INDIRECT_PCI) += indirect_pci.o
27obj-$(CONFIG_PPC_I8259) += i8259.o 27obj-$(CONFIG_PPC_I8259) += i8259.o
28obj-$(CONFIG_IPIC) += ipic.o 28obj-$(CONFIG_IPIC) += ipic.o
29obj-$(CONFIG_4xx) += uic.o 29obj-$(CONFIG_4xx) += uic.o
30obj-$(CONFIG_4xx_SOC) += ppc4xx_soc.o
30obj-$(CONFIG_XILINX_VIRTEX) += xilinx_intc.o 31obj-$(CONFIG_XILINX_VIRTEX) += xilinx_intc.o
31obj-$(CONFIG_OF_RTC) += of_rtc.o 32obj-$(CONFIG_OF_RTC) += of_rtc.o
32ifeq ($(CONFIG_PCI),y) 33ifeq ($(CONFIG_PCI),y)
diff --git a/arch/powerpc/sysdev/cpm1.c b/arch/powerpc/sysdev/cpm1.c
index df8bd2b64796..3eceeb5f3ee7 100644
--- a/arch/powerpc/sysdev/cpm1.c
+++ b/arch/powerpc/sysdev/cpm1.c
@@ -257,7 +257,7 @@ int cpm_command(u32 command, u8 opcode)
257 if ((in_be16(&cpmp->cp_cpcr) & CPM_CR_FLG) == 0) 257 if ((in_be16(&cpmp->cp_cpcr) & CPM_CR_FLG) == 0)
258 goto out; 258 goto out;
259 259
260 printk(KERN_ERR "%s(): Not able to issue CPM command\n", __FUNCTION__); 260 printk(KERN_ERR "%s(): Not able to issue CPM command\n", __func__);
261 ret = -EIO; 261 ret = -EIO;
262out: 262out:
263 spin_unlock_irqrestore(&cmd_lock, flags); 263 spin_unlock_irqrestore(&cmd_lock, flags);
diff --git a/arch/powerpc/sysdev/cpm2.c b/arch/powerpc/sysdev/cpm2.c
index dd066bb1d562..fa70ee31349e 100644
--- a/arch/powerpc/sysdev/cpm2.c
+++ b/arch/powerpc/sysdev/cpm2.c
@@ -99,7 +99,7 @@ int cpm_command(u32 command, u8 opcode)
99 if ((in_be32(&cpmp->cp_cpcr) & CPM_CR_FLG) == 0) 99 if ((in_be32(&cpmp->cp_cpcr) & CPM_CR_FLG) == 0)
100 goto out; 100 goto out;
101 101
102 printk(KERN_ERR "%s(): Not able to issue CPM command\n", __FUNCTION__); 102 printk(KERN_ERR "%s(): Not able to issue CPM command\n", __func__);
103 ret = -EIO; 103 ret = -EIO;
104out: 104out:
105 spin_unlock_irqrestore(&cmd_lock, flags); 105 spin_unlock_irqrestore(&cmd_lock, flags);
diff --git a/arch/powerpc/sysdev/dart_iommu.c b/arch/powerpc/sysdev/dart_iommu.c
index e0e24b01e3a6..005c2ecf976f 100644
--- a/arch/powerpc/sysdev/dart_iommu.c
+++ b/arch/powerpc/sysdev/dart_iommu.c
@@ -37,6 +37,7 @@
37#include <linux/dma-mapping.h> 37#include <linux/dma-mapping.h>
38#include <linux/vmalloc.h> 38#include <linux/vmalloc.h>
39#include <linux/suspend.h> 39#include <linux/suspend.h>
40#include <linux/lmb.h>
40#include <asm/io.h> 41#include <asm/io.h>
41#include <asm/prom.h> 42#include <asm/prom.h>
42#include <asm/iommu.h> 43#include <asm/iommu.h>
@@ -44,7 +45,6 @@
44#include <asm/machdep.h> 45#include <asm/machdep.h>
45#include <asm/abs_addr.h> 46#include <asm/abs_addr.h>
46#include <asm/cacheflush.h> 47#include <asm/cacheflush.h>
47#include <asm/lmb.h>
48#include <asm/ppc-pci.h> 48#include <asm/ppc-pci.h>
49 49
50#include "dart.h" 50#include "dart.h"
diff --git a/arch/powerpc/sysdev/mpic.c b/arch/powerpc/sysdev/mpic.c
index 6ffdda244bb1..6131fd2b6619 100644
--- a/arch/powerpc/sysdev/mpic.c
+++ b/arch/powerpc/sysdev/mpic.c
@@ -175,13 +175,16 @@ static inline void _mpic_write(enum mpic_reg_type type,
175 switch(type) { 175 switch(type) {
176#ifdef CONFIG_PPC_DCR 176#ifdef CONFIG_PPC_DCR
177 case mpic_access_dcr: 177 case mpic_access_dcr:
178 return dcr_write(rb->dhost, reg, value); 178 dcr_write(rb->dhost, reg, value);
179 break;
179#endif 180#endif
180 case mpic_access_mmio_be: 181 case mpic_access_mmio_be:
181 return out_be32(rb->base + (reg >> 2), value); 182 out_be32(rb->base + (reg >> 2), value);
183 break;
182 case mpic_access_mmio_le: 184 case mpic_access_mmio_le:
183 default: 185 default:
184 return out_le32(rb->base + (reg >> 2), value); 186 out_le32(rb->base + (reg >> 2), value);
187 break;
185 } 188 }
186} 189}
187 190
@@ -1000,7 +1003,7 @@ struct mpic * __init mpic_alloc(struct device_node *node,
1000 const char *name) 1003 const char *name)
1001{ 1004{
1002 struct mpic *mpic; 1005 struct mpic *mpic;
1003 u32 reg; 1006 u32 greg_feature;
1004 const char *vers; 1007 const char *vers;
1005 int i; 1008 int i;
1006 int intvec_top; 1009 int intvec_top;
@@ -1064,7 +1067,8 @@ struct mpic * __init mpic_alloc(struct device_node *node,
1064 1067
1065 /* Look for protected sources */ 1068 /* Look for protected sources */
1066 if (node) { 1069 if (node) {
1067 unsigned int psize, bits, mapsize; 1070 int psize;
1071 unsigned int bits, mapsize;
1068 const u32 *psrc = 1072 const u32 *psrc =
1069 of_get_property(node, "protected-sources", &psize); 1073 of_get_property(node, "protected-sources", &psize);
1070 if (psrc) { 1074 if (psrc) {
@@ -1107,8 +1111,7 @@ struct mpic * __init mpic_alloc(struct device_node *node,
1107 * in, try to obtain one 1111 * in, try to obtain one
1108 */ 1112 */
1109 if (paddr == 0 && !(mpic->flags & MPIC_USES_DCR)) { 1113 if (paddr == 0 && !(mpic->flags & MPIC_USES_DCR)) {
1110 const u32 *reg; 1114 const u32 *reg = of_get_property(node, "reg", NULL);
1111 reg = of_get_property(node, "reg", NULL);
1112 BUG_ON(reg == NULL); 1115 BUG_ON(reg == NULL);
1113 paddr = of_translate_address(node, reg); 1116 paddr = of_translate_address(node, reg);
1114 BUG_ON(paddr == OF_BAD_ADDR); 1117 BUG_ON(paddr == OF_BAD_ADDR);
@@ -1137,12 +1140,13 @@ struct mpic * __init mpic_alloc(struct device_node *node,
1137 * MPICs, num sources as well. On ISU MPICs, sources are counted 1140 * MPICs, num sources as well. On ISU MPICs, sources are counted
1138 * as ISUs are added 1141 * as ISUs are added
1139 */ 1142 */
1140 reg = mpic_read(mpic->gregs, MPIC_INFO(GREG_FEATURE_0)); 1143 greg_feature = mpic_read(mpic->gregs, MPIC_INFO(GREG_FEATURE_0));
1141 mpic->num_cpus = ((reg & MPIC_GREG_FEATURE_LAST_CPU_MASK) 1144 mpic->num_cpus = ((greg_feature & MPIC_GREG_FEATURE_LAST_CPU_MASK)
1142 >> MPIC_GREG_FEATURE_LAST_CPU_SHIFT) + 1; 1145 >> MPIC_GREG_FEATURE_LAST_CPU_SHIFT) + 1;
1143 if (isu_size == 0) 1146 if (isu_size == 0)
1144 mpic->num_sources = ((reg & MPIC_GREG_FEATURE_LAST_SRC_MASK) 1147 mpic->num_sources =
1145 >> MPIC_GREG_FEATURE_LAST_SRC_SHIFT) + 1; 1148 ((greg_feature & MPIC_GREG_FEATURE_LAST_SRC_MASK)
1149 >> MPIC_GREG_FEATURE_LAST_SRC_SHIFT) + 1;
1146 1150
1147 /* Map the per-CPU registers */ 1151 /* Map the per-CPU registers */
1148 for (i = 0; i < mpic->num_cpus; i++) { 1152 for (i = 0; i < mpic->num_cpus; i++) {
@@ -1161,7 +1165,7 @@ struct mpic * __init mpic_alloc(struct device_node *node,
1161 mpic->isu_mask = (1 << mpic->isu_shift) - 1; 1165 mpic->isu_mask = (1 << mpic->isu_shift) - 1;
1162 1166
1163 /* Display version */ 1167 /* Display version */
1164 switch (reg & MPIC_GREG_FEATURE_VERSION_MASK) { 1168 switch (greg_feature & MPIC_GREG_FEATURE_VERSION_MASK) {
1165 case 1: 1169 case 1:
1166 vers = "1.0"; 1170 vers = "1.0";
1167 break; 1171 break;
@@ -1321,7 +1325,7 @@ void __init mpic_set_serial_int(struct mpic *mpic, int enable)
1321 1325
1322void mpic_irq_set_priority(unsigned int irq, unsigned int pri) 1326void mpic_irq_set_priority(unsigned int irq, unsigned int pri)
1323{ 1327{
1324 int is_ipi; 1328 unsigned int is_ipi;
1325 struct mpic *mpic = mpic_find(irq, &is_ipi); 1329 struct mpic *mpic = mpic_find(irq, &is_ipi);
1326 unsigned int src = mpic_irq_to_hw(irq); 1330 unsigned int src = mpic_irq_to_hw(irq);
1327 unsigned long flags; 1331 unsigned long flags;
@@ -1344,7 +1348,7 @@ void mpic_irq_set_priority(unsigned int irq, unsigned int pri)
1344 1348
1345unsigned int mpic_irq_get_priority(unsigned int irq) 1349unsigned int mpic_irq_get_priority(unsigned int irq)
1346{ 1350{
1347 int is_ipi; 1351 unsigned int is_ipi;
1348 struct mpic *mpic = mpic_find(irq, &is_ipi); 1352 struct mpic *mpic = mpic_find(irq, &is_ipi);
1349 unsigned int src = mpic_irq_to_hw(irq); 1353 unsigned int src = mpic_irq_to_hw(irq);
1350 unsigned long flags; 1354 unsigned long flags;
diff --git a/arch/powerpc/sysdev/ppc4xx_pci.c b/arch/powerpc/sysdev/ppc4xx_pci.c
index 5abfcd157483..1814adbd2236 100644
--- a/arch/powerpc/sysdev/ppc4xx_pci.c
+++ b/arch/powerpc/sysdev/ppc4xx_pci.c
@@ -527,6 +527,7 @@ static void __init ppc4xx_probe_pcix_bridge(struct device_node *np)
527 * 527 *
528 * ibm,plb-pciex-440spe 528 * ibm,plb-pciex-440spe
529 * ibm,plb-pciex-405ex 529 * ibm,plb-pciex-405ex
530 * ibm,plb-pciex-460ex
530 * 531 *
531 * Anything else will be rejected for now as they are all subtly 532 * Anything else will be rejected for now as they are all subtly
532 * different unfortunately. 533 * different unfortunately.
@@ -645,7 +646,7 @@ static int __init ppc440spe_pciex_core_init(struct device_node *np)
645 int time_out = 20; 646 int time_out = 20;
646 647
647 /* Set PLL clock receiver to LVPECL */ 648 /* Set PLL clock receiver to LVPECL */
648 mtdcri(SDR0, PESDR0_PLLLCT1, mfdcri(SDR0, PESDR0_PLLLCT1) | 1 << 28); 649 dcri_clrset(SDR0, PESDR0_PLLLCT1, 0, 1 << 28);
649 650
650 /* Shouldn't we do all the calibration stuff etc... here ? */ 651 /* Shouldn't we do all the calibration stuff etc... here ? */
651 if (ppc440spe_pciex_check_reset(np)) 652 if (ppc440spe_pciex_check_reset(np))
@@ -659,8 +660,7 @@ static int __init ppc440spe_pciex_core_init(struct device_node *np)
659 } 660 }
660 661
661 /* De-assert reset of PCIe PLL, wait for lock */ 662 /* De-assert reset of PCIe PLL, wait for lock */
662 mtdcri(SDR0, PESDR0_PLLLCT1, 663 dcri_clrset(SDR0, PESDR0_PLLLCT1, 1 << 24, 0);
663 mfdcri(SDR0, PESDR0_PLLLCT1) & ~(1 << 24));
664 udelay(3); 664 udelay(3);
665 665
666 while (time_out) { 666 while (time_out) {
@@ -712,9 +712,8 @@ static int ppc440spe_pciex_init_port_hw(struct ppc4xx_pciex_port *port)
712 mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL7SET1, 712 mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL7SET1,
713 0x35000000); 713 0x35000000);
714 } 714 }
715 val = mfdcri(SDR0, port->sdr_base + PESDRn_RCSSET); 715 dcri_clrset(SDR0, port->sdr_base + PESDRn_RCSSET,
716 mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET, 716 (1 << 24) | (1 << 16), 1 << 12);
717 (val & ~(1 << 24 | 1 << 16)) | 1 << 12);
718 717
719 return 0; 718 return 0;
720} 719}
@@ -775,6 +774,115 @@ static struct ppc4xx_pciex_hwops ppc440speB_pcie_hwops __initdata =
775 .setup_utl = ppc440speB_pciex_init_utl, 774 .setup_utl = ppc440speB_pciex_init_utl,
776}; 775};
777 776
777static int __init ppc460ex_pciex_core_init(struct device_node *np)
778{
779 /* Nothing to do, return 2 ports */
780 return 2;
781}
782
783static int ppc460ex_pciex_init_port_hw(struct ppc4xx_pciex_port *port)
784{
785 u32 val;
786 u32 utlset1;
787
788 if (port->endpoint)
789 val = PTYPE_LEGACY_ENDPOINT << 20;
790 else
791 val = PTYPE_ROOT_PORT << 20;
792
793 if (port->index == 0) {
794 val |= LNKW_X1 << 12;
795 utlset1 = 0x20000000;
796 } else {
797 val |= LNKW_X4 << 12;
798 utlset1 = 0x20101101;
799 }
800
801 mtdcri(SDR0, port->sdr_base + PESDRn_DLPSET, val);
802 mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET1, utlset1);
803 mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET2, 0x01210000);
804
805 switch (port->index) {
806 case 0:
807 mtdcri(SDR0, PESDR0_460EX_L0CDRCTL, 0x00003230);
808 mtdcri(SDR0, PESDR0_460EX_L0DRV, 0x00000136);
809 mtdcri(SDR0, PESDR0_460EX_L0CLK, 0x00000006);
810
811 mtdcri(SDR0, PESDR0_460EX_PHY_CTL_RST,0x10000000);
812 break;
813
814 case 1:
815 mtdcri(SDR0, PESDR1_460EX_L0CDRCTL, 0x00003230);
816 mtdcri(SDR0, PESDR1_460EX_L1CDRCTL, 0x00003230);
817 mtdcri(SDR0, PESDR1_460EX_L2CDRCTL, 0x00003230);
818 mtdcri(SDR0, PESDR1_460EX_L3CDRCTL, 0x00003230);
819 mtdcri(SDR0, PESDR1_460EX_L0DRV, 0x00000136);
820 mtdcri(SDR0, PESDR1_460EX_L1DRV, 0x00000136);
821 mtdcri(SDR0, PESDR1_460EX_L2DRV, 0x00000136);
822 mtdcri(SDR0, PESDR1_460EX_L3DRV, 0x00000136);
823 mtdcri(SDR0, PESDR1_460EX_L0CLK, 0x00000006);
824 mtdcri(SDR0, PESDR1_460EX_L1CLK, 0x00000006);
825 mtdcri(SDR0, PESDR1_460EX_L2CLK, 0x00000006);
826 mtdcri(SDR0, PESDR1_460EX_L3CLK, 0x00000006);
827
828 mtdcri(SDR0, PESDR1_460EX_PHY_CTL_RST,0x10000000);
829 break;
830 }
831
832 mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET,
833 mfdcri(SDR0, port->sdr_base + PESDRn_RCSSET) |
834 (PESDRx_RCSSET_RSTGU | PESDRx_RCSSET_RSTPYN));
835
836 /* Poll for PHY reset */
837 /* XXX FIXME add timeout */
838 switch (port->index) {
839 case 0:
840 while (!(mfdcri(SDR0, PESDR0_460EX_RSTSTA) & 0x1))
841 udelay(10);
842 break;
843 case 1:
844 while (!(mfdcri(SDR0, PESDR1_460EX_RSTSTA) & 0x1))
845 udelay(10);
846 break;
847 }
848
849 mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET,
850 (mfdcri(SDR0, port->sdr_base + PESDRn_RCSSET) &
851 ~(PESDRx_RCSSET_RSTGU | PESDRx_RCSSET_RSTDL)) |
852 PESDRx_RCSSET_RSTPYN);
853
854 port->has_ibpre = 1;
855
856 return 0;
857}
858
859static int ppc460ex_pciex_init_utl(struct ppc4xx_pciex_port *port)
860{
861 dcr_write(port->dcrs, DCRO_PEGPL_SPECIAL, 0x0);
862
863 /*
864 * Set buffer allocations and then assert VRB and TXE.
865 */
866 out_be32(port->utl_base + PEUTL_PBCTL, 0x0800000c);
867 out_be32(port->utl_base + PEUTL_OUTTR, 0x08000000);
868 out_be32(port->utl_base + PEUTL_INTR, 0x02000000);
869 out_be32(port->utl_base + PEUTL_OPDBSZ, 0x04000000);
870 out_be32(port->utl_base + PEUTL_PBBSZ, 0x00000000);
871 out_be32(port->utl_base + PEUTL_IPHBSZ, 0x02000000);
872 out_be32(port->utl_base + PEUTL_IPDBSZ, 0x04000000);
873 out_be32(port->utl_base + PEUTL_RCIRQEN,0x00f00000);
874 out_be32(port->utl_base + PEUTL_PCTL, 0x80800066);
875
876 return 0;
877}
878
879static struct ppc4xx_pciex_hwops ppc460ex_pcie_hwops __initdata =
880{
881 .core_init = ppc460ex_pciex_core_init,
882 .port_init_hw = ppc460ex_pciex_init_port_hw,
883 .setup_utl = ppc460ex_pciex_init_utl,
884};
885
778#endif /* CONFIG_44x */ 886#endif /* CONFIG_44x */
779 887
780#ifdef CONFIG_40x 888#ifdef CONFIG_40x
@@ -830,17 +938,9 @@ static int ppc405ex_pciex_init_port_hw(struct ppc4xx_pciex_port *port)
830 * PCIe boards don't show this problem. 938 * PCIe boards don't show this problem.
831 * This has to be re-tested and fixed in a later release! 939 * This has to be re-tested and fixed in a later release!
832 */ 940 */
833#if 0 /* XXX FIXME: Not resetting the PHY will leave all resources
834 * configured as done previously by U-Boot. Then Linux will currently
835 * not reassign them. So the PHY reset is now done always. This will
836 * lead to problems with the Atheros PCIe board again.
837 */
838 val = mfdcri(SDR0, port->sdr_base + PESDRn_LOOP); 941 val = mfdcri(SDR0, port->sdr_base + PESDRn_LOOP);
839 if (!(val & 0x00001000)) 942 if (!(val & 0x00001000))
840 ppc405ex_pcie_phy_reset(port); 943 ppc405ex_pcie_phy_reset(port);
841#else
842 ppc405ex_pcie_phy_reset(port);
843#endif
844 944
845 dcr_write(port->dcrs, DCRO_PEGPL_CFG, 0x10000000); /* guarded on */ 945 dcr_write(port->dcrs, DCRO_PEGPL_CFG, 0x10000000); /* guarded on */
846 946
@@ -896,6 +996,8 @@ static int __init ppc4xx_pciex_check_core_init(struct device_node *np)
896 else 996 else
897 ppc4xx_pciex_hwops = &ppc440speB_pcie_hwops; 997 ppc4xx_pciex_hwops = &ppc440speB_pcie_hwops;
898 } 998 }
999 if (of_device_is_compatible(np, "ibm,plb-pciex-460ex"))
1000 ppc4xx_pciex_hwops = &ppc460ex_pcie_hwops;
899#endif /* CONFIG_44x */ 1001#endif /* CONFIG_44x */
900#ifdef CONFIG_40x 1002#ifdef CONFIG_40x
901 if (of_device_is_compatible(np, "ibm,plb-pciex-405ex")) 1003 if (of_device_is_compatible(np, "ibm,plb-pciex-405ex"))
@@ -1042,8 +1144,7 @@ static int __init ppc4xx_pciex_port_init(struct ppc4xx_pciex_port *port)
1042 port->link = 0; 1144 port->link = 0;
1043 } 1145 }
1044 1146
1045 mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET, 1147 dcri_clrset(SDR0, port->sdr_base + PESDRn_RCSSET, 0, 1 << 20);
1046 mfdcri(SDR0, port->sdr_base + PESDRn_RCSSET) | 1 << 20);
1047 msleep(100); 1148 msleep(100);
1048 1149
1049 return 0; 1150 return 0;
diff --git a/arch/powerpc/sysdev/ppc4xx_pci.h b/arch/powerpc/sysdev/ppc4xx_pci.h
index 1c07908dc6ef..d04e40b306fb 100644
--- a/arch/powerpc/sysdev/ppc4xx_pci.h
+++ b/arch/powerpc/sysdev/ppc4xx_pci.h
@@ -271,6 +271,59 @@
271#define PESDR1_405EX_PHYSTA 0x044C 271#define PESDR1_405EX_PHYSTA 0x044C
272 272
273/* 273/*
274 * 460EX additional DCRs
275 */
276#define PESDR0_460EX_L0BIST 0x0308
277#define PESDR0_460EX_L0BISTSTS 0x0309
278#define PESDR0_460EX_L0CDRCTL 0x030A
279#define PESDR0_460EX_L0DRV 0x030B
280#define PESDR0_460EX_L0REC 0x030C
281#define PESDR0_460EX_L0LPB 0x030D
282#define PESDR0_460EX_L0CLK 0x030E
283#define PESDR0_460EX_PHY_CTL_RST 0x030F
284#define PESDR0_460EX_RSTSTA 0x0310
285#define PESDR0_460EX_OBS 0x0311
286#define PESDR0_460EX_L0ERRC 0x0320
287
288#define PESDR1_460EX_L0BIST 0x0348
289#define PESDR1_460EX_L1BIST 0x0349
290#define PESDR1_460EX_L2BIST 0x034A
291#define PESDR1_460EX_L3BIST 0x034B
292#define PESDR1_460EX_L0BISTSTS 0x034C
293#define PESDR1_460EX_L1BISTSTS 0x034D
294#define PESDR1_460EX_L2BISTSTS 0x034E
295#define PESDR1_460EX_L3BISTSTS 0x034F
296#define PESDR1_460EX_L0CDRCTL 0x0350
297#define PESDR1_460EX_L1CDRCTL 0x0351
298#define PESDR1_460EX_L2CDRCTL 0x0352
299#define PESDR1_460EX_L3CDRCTL 0x0353
300#define PESDR1_460EX_L0DRV 0x0354
301#define PESDR1_460EX_L1DRV 0x0355
302#define PESDR1_460EX_L2DRV 0x0356
303#define PESDR1_460EX_L3DRV 0x0357
304#define PESDR1_460EX_L0REC 0x0358
305#define PESDR1_460EX_L1REC 0x0359
306#define PESDR1_460EX_L2REC 0x035A
307#define PESDR1_460EX_L3REC 0x035B
308#define PESDR1_460EX_L0LPB 0x035C
309#define PESDR1_460EX_L1LPB 0x035D
310#define PESDR1_460EX_L2LPB 0x035E
311#define PESDR1_460EX_L3LPB 0x035F
312#define PESDR1_460EX_L0CLK 0x0360
313#define PESDR1_460EX_L1CLK 0x0361
314#define PESDR1_460EX_L2CLK 0x0362
315#define PESDR1_460EX_L3CLK 0x0363
316#define PESDR1_460EX_PHY_CTL_RST 0x0364
317#define PESDR1_460EX_RSTSTA 0x0365
318#define PESDR1_460EX_OBS 0x0366
319#define PESDR1_460EX_L0ERRC 0x0368
320#define PESDR1_460EX_L1ERRC 0x0369
321#define PESDR1_460EX_L2ERRC 0x036A
322#define PESDR1_460EX_L3ERRC 0x036B
323#define PESDR0_460EX_IHS1 0x036C
324#define PESDR0_460EX_IHS2 0x036D
325
326/*
274 * Of the above, some are common offsets from the base 327 * Of the above, some are common offsets from the base
275 */ 328 */
276#define PESDRn_UTLSET1 0x00 329#define PESDRn_UTLSET1 0x00
@@ -353,6 +406,12 @@
353#define PECFG_POM2LAL 0x390 406#define PECFG_POM2LAL 0x390
354#define PECFG_POM2LAH 0x394 407#define PECFG_POM2LAH 0x394
355 408
409/* SDR Bit Mappings */
410#define PESDRx_RCSSET_HLDPLB 0x10000000
411#define PESDRx_RCSSET_RSTGU 0x01000000
412#define PESDRx_RCSSET_RDY 0x00100000
413#define PESDRx_RCSSET_RSTDL 0x00010000
414#define PESDRx_RCSSET_RSTPYN 0x00001000
356 415
357enum 416enum
358{ 417{
diff --git a/arch/powerpc/sysdev/ppc4xx_soc.c b/arch/powerpc/sysdev/ppc4xx_soc.c
new file mode 100644
index 000000000000..5b32adc9a9b2
--- /dev/null
+++ b/arch/powerpc/sysdev/ppc4xx_soc.c
@@ -0,0 +1,200 @@
1/*
2 * IBM/AMCC PPC4xx SoC setup code
3 *
4 * Copyright 2008 DENX Software Engineering, Stefan Roese <sr@denx.de>
5 *
6 * L2 cache routines cloned from arch/ppc/syslib/ibm440gx_common.c which is:
7 * Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
8 * Copyright (c) 2003 - 2006 Zultys Technologies
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 */
15
16#include <linux/stddef.h>
17#include <linux/kernel.h>
18#include <linux/init.h>
19#include <linux/errno.h>
20#include <linux/interrupt.h>
21#include <linux/irq.h>
22#include <linux/of_platform.h>
23
24#include <asm/dcr.h>
25#include <asm/dcr-regs.h>
26#include <asm/reg.h>
27
28static u32 dcrbase_l2c;
29
30/*
31 * L2-cache
32 */
33
34/* Issue L2C diagnostic command */
35static inline u32 l2c_diag(u32 addr)
36{
37 mtdcr(dcrbase_l2c + DCRN_L2C0_ADDR, addr);
38 mtdcr(dcrbase_l2c + DCRN_L2C0_CMD, L2C_CMD_DIAG);
39 while (!(mfdcr(dcrbase_l2c + DCRN_L2C0_SR) & L2C_SR_CC))
40 ;
41
42 return mfdcr(dcrbase_l2c + DCRN_L2C0_DATA);
43}
44
45static irqreturn_t l2c_error_handler(int irq, void *dev)
46{
47 u32 sr = mfdcr(dcrbase_l2c + DCRN_L2C0_SR);
48
49 if (sr & L2C_SR_CPE) {
50 /* Read cache trapped address */
51 u32 addr = l2c_diag(0x42000000);
52 printk(KERN_EMERG "L2C: Cache Parity Error, addr[16:26] = 0x%08x\n",
53 addr);
54 }
55 if (sr & L2C_SR_TPE) {
56 /* Read tag trapped address */
57 u32 addr = l2c_diag(0x82000000) >> 16;
58 printk(KERN_EMERG "L2C: Tag Parity Error, addr[16:26] = 0x%08x\n",
59 addr);
60 }
61
62 /* Clear parity errors */
63 if (sr & (L2C_SR_CPE | L2C_SR_TPE)){
64 mtdcr(dcrbase_l2c + DCRN_L2C0_ADDR, 0);
65 mtdcr(dcrbase_l2c + DCRN_L2C0_CMD, L2C_CMD_CCP | L2C_CMD_CTE);
66 } else {
67 printk(KERN_EMERG "L2C: LRU error\n");
68 }
69
70 return IRQ_HANDLED;
71}
72
73static int __init ppc4xx_l2c_probe(void)
74{
75 struct device_node *np;
76 u32 r;
77 unsigned long flags;
78 int irq;
79 const u32 *dcrreg;
80 u32 dcrbase_isram;
81 int len;
82 const u32 *prop;
83 u32 l2_size;
84
85 np = of_find_compatible_node(NULL, NULL, "ibm,l2-cache");
86 if (!np)
87 return 0;
88
89 /* Get l2 cache size */
90 prop = of_get_property(np, "cache-size", NULL);
91 if (prop == NULL) {
92 printk(KERN_ERR "%s: Can't get cache-size!\n", np->full_name);
93 of_node_put(np);
94 return -ENODEV;
95 }
96 l2_size = prop[0];
97
98 /* Map DCRs */
99 dcrreg = of_get_property(np, "dcr-reg", &len);
100 if (!dcrreg || (len != 4 * sizeof(u32))) {
101 printk(KERN_ERR "%s: Can't get DCR register base !",
102 np->full_name);
103 of_node_put(np);
104 return -ENODEV;
105 }
106 dcrbase_isram = dcrreg[0];
107 dcrbase_l2c = dcrreg[2];
108
109 /* Get and map irq number from device tree */
110 irq = irq_of_parse_and_map(np, 0);
111 if (irq == NO_IRQ) {
112 printk(KERN_ERR "irq_of_parse_and_map failed\n");
113 of_node_put(np);
114 return -ENODEV;
115 }
116
117 /* Install error handler */
118 if (request_irq(irq, l2c_error_handler, IRQF_DISABLED, "L2C", 0) < 0) {
119 printk(KERN_ERR "Cannot install L2C error handler"
120 ", cache is not enabled\n");
121 of_node_put(np);
122 return -ENODEV;
123 }
124
125 local_irq_save(flags);
126 asm volatile ("sync" ::: "memory");
127
128 /* Disable SRAM */
129 mtdcr(dcrbase_isram + DCRN_SRAM0_DPC,
130 mfdcr(dcrbase_isram + DCRN_SRAM0_DPC) & ~SRAM_DPC_ENABLE);
131 mtdcr(dcrbase_isram + DCRN_SRAM0_SB0CR,
132 mfdcr(dcrbase_isram + DCRN_SRAM0_SB0CR) & ~SRAM_SBCR_BU_MASK);
133 mtdcr(dcrbase_isram + DCRN_SRAM0_SB1CR,
134 mfdcr(dcrbase_isram + DCRN_SRAM0_SB1CR) & ~SRAM_SBCR_BU_MASK);
135 mtdcr(dcrbase_isram + DCRN_SRAM0_SB2CR,
136 mfdcr(dcrbase_isram + DCRN_SRAM0_SB2CR) & ~SRAM_SBCR_BU_MASK);
137 mtdcr(dcrbase_isram + DCRN_SRAM0_SB3CR,
138 mfdcr(dcrbase_isram + DCRN_SRAM0_SB3CR) & ~SRAM_SBCR_BU_MASK);
139
140 /* Enable L2_MODE without ICU/DCU */
141 r = mfdcr(dcrbase_l2c + DCRN_L2C0_CFG) &
142 ~(L2C_CFG_ICU | L2C_CFG_DCU | L2C_CFG_SS_MASK);
143 r |= L2C_CFG_L2M | L2C_CFG_SS_256;
144 mtdcr(dcrbase_l2c + DCRN_L2C0_CFG, r);
145
146 mtdcr(dcrbase_l2c + DCRN_L2C0_ADDR, 0);
147
148 /* Hardware Clear Command */
149 mtdcr(dcrbase_l2c + DCRN_L2C0_CMD, L2C_CMD_HCC);
150 while (!(mfdcr(dcrbase_l2c + DCRN_L2C0_SR) & L2C_SR_CC))
151 ;
152
153 /* Clear Cache Parity and Tag Errors */
154 mtdcr(dcrbase_l2c + DCRN_L2C0_CMD, L2C_CMD_CCP | L2C_CMD_CTE);
155
156 /* Enable 64G snoop region starting at 0 */
157 r = mfdcr(dcrbase_l2c + DCRN_L2C0_SNP0) &
158 ~(L2C_SNP_BA_MASK | L2C_SNP_SSR_MASK);
159 r |= L2C_SNP_SSR_32G | L2C_SNP_ESR;
160 mtdcr(dcrbase_l2c + DCRN_L2C0_SNP0, r);
161
162 r = mfdcr(dcrbase_l2c + DCRN_L2C0_SNP1) &
163 ~(L2C_SNP_BA_MASK | L2C_SNP_SSR_MASK);
164 r |= 0x80000000 | L2C_SNP_SSR_32G | L2C_SNP_ESR;
165 mtdcr(dcrbase_l2c + DCRN_L2C0_SNP1, r);
166
167 asm volatile ("sync" ::: "memory");
168
169 /* Enable ICU/DCU ports */
170 r = mfdcr(dcrbase_l2c + DCRN_L2C0_CFG);
171 r &= ~(L2C_CFG_DCW_MASK | L2C_CFG_PMUX_MASK | L2C_CFG_PMIM
172 | L2C_CFG_TPEI | L2C_CFG_CPEI | L2C_CFG_NAM | L2C_CFG_NBRM);
173 r |= L2C_CFG_ICU | L2C_CFG_DCU | L2C_CFG_TPC | L2C_CFG_CPC | L2C_CFG_FRAN
174 | L2C_CFG_CPIM | L2C_CFG_TPIM | L2C_CFG_LIM | L2C_CFG_SMCM;
175
176 /* Check for 460EX/GT special handling */
177 if (of_device_is_compatible(np, "ibm,l2-cache-460ex"))
178 r |= L2C_CFG_RDBW;
179
180 mtdcr(dcrbase_l2c + DCRN_L2C0_CFG, r);
181
182 asm volatile ("sync; isync" ::: "memory");
183 local_irq_restore(flags);
184
185 printk(KERN_INFO "%dk L2-cache enabled\n", l2_size >> 10);
186
187 of_node_put(np);
188 return 0;
189}
190arch_initcall(ppc4xx_l2c_probe);
191
192/*
193 * At present, this routine just applies a system reset.
194 */
195void ppc4xx_reset_system(char *cmd)
196{
197 mtspr(SPRN_DBCR0, mfspr(SPRN_DBCR0) | DBCR0_RST_SYSTEM);
198 while (1)
199 ; /* Just in case the reset doesn't work */
200}
diff --git a/arch/powerpc/sysdev/qe_lib/qe_io.c b/arch/powerpc/sysdev/qe_lib/qe_io.c
index e53ea4d374a0..736c1fcc9503 100644
--- a/arch/powerpc/sysdev/qe_lib/qe_io.c
+++ b/arch/powerpc/sysdev/qe_lib/qe_io.c
@@ -200,7 +200,7 @@ static void dump_par_io(void)
200{ 200{
201 unsigned int i; 201 unsigned int i;
202 202
203 printk(KERN_INFO "%s: par_io=%p\n", __FUNCTION__, par_io); 203 printk(KERN_INFO "%s: par_io=%p\n", __func__, par_io);
204 for (i = 0; i < num_par_io_ports; i++) { 204 for (i = 0; i < num_par_io_ports; i++) {
205 printk(KERN_INFO " cpodr[%u]=%08x\n", i, 205 printk(KERN_INFO " cpodr[%u]=%08x\n", i,
206 in_be32(&par_io[i].cpodr)); 206 in_be32(&par_io[i].cpodr));
diff --git a/arch/powerpc/sysdev/qe_lib/ucc_fast.c b/arch/powerpc/sysdev/qe_lib/ucc_fast.c
index 3223acbc39e5..bcf88e6ce962 100644
--- a/arch/powerpc/sysdev/qe_lib/ucc_fast.c
+++ b/arch/powerpc/sysdev/qe_lib/ucc_fast.c
@@ -148,57 +148,57 @@ int ucc_fast_init(struct ucc_fast_info * uf_info, struct ucc_fast_private ** ucc
148 148
149 /* check if the UCC port number is in range. */ 149 /* check if the UCC port number is in range. */
150 if ((uf_info->ucc_num < 0) || (uf_info->ucc_num > UCC_MAX_NUM - 1)) { 150 if ((uf_info->ucc_num < 0) || (uf_info->ucc_num > UCC_MAX_NUM - 1)) {
151 printk(KERN_ERR "%s: illegal UCC number\n", __FUNCTION__); 151 printk(KERN_ERR "%s: illegal UCC number\n", __func__);
152 return -EINVAL; 152 return -EINVAL;
153 } 153 }
154 154
155 /* Check that 'max_rx_buf_length' is properly aligned (4). */ 155 /* Check that 'max_rx_buf_length' is properly aligned (4). */
156 if (uf_info->max_rx_buf_length & (UCC_FAST_MRBLR_ALIGNMENT - 1)) { 156 if (uf_info->max_rx_buf_length & (UCC_FAST_MRBLR_ALIGNMENT - 1)) {
157 printk(KERN_ERR "%s: max_rx_buf_length not aligned\n", 157 printk(KERN_ERR "%s: max_rx_buf_length not aligned\n",
158 __FUNCTION__); 158 __func__);
159 return -EINVAL; 159 return -EINVAL;
160 } 160 }
161 161
162 /* Validate Virtual Fifo register values */ 162 /* Validate Virtual Fifo register values */
163 if (uf_info->urfs < UCC_FAST_URFS_MIN_VAL) { 163 if (uf_info->urfs < UCC_FAST_URFS_MIN_VAL) {
164 printk(KERN_ERR "%s: urfs is too small\n", __FUNCTION__); 164 printk(KERN_ERR "%s: urfs is too small\n", __func__);
165 return -EINVAL; 165 return -EINVAL;
166 } 166 }
167 167
168 if (uf_info->urfs & (UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT - 1)) { 168 if (uf_info->urfs & (UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT - 1)) {
169 printk(KERN_ERR "%s: urfs is not aligned\n", __FUNCTION__); 169 printk(KERN_ERR "%s: urfs is not aligned\n", __func__);
170 return -EINVAL; 170 return -EINVAL;
171 } 171 }
172 172
173 if (uf_info->urfet & (UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT - 1)) { 173 if (uf_info->urfet & (UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT - 1)) {
174 printk(KERN_ERR "%s: urfet is not aligned.\n", __FUNCTION__); 174 printk(KERN_ERR "%s: urfet is not aligned.\n", __func__);
175 return -EINVAL; 175 return -EINVAL;
176 } 176 }
177 177
178 if (uf_info->urfset & (UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT - 1)) { 178 if (uf_info->urfset & (UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT - 1)) {
179 printk(KERN_ERR "%s: urfset is not aligned\n", __FUNCTION__); 179 printk(KERN_ERR "%s: urfset is not aligned\n", __func__);
180 return -EINVAL; 180 return -EINVAL;
181 } 181 }
182 182
183 if (uf_info->utfs & (UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT - 1)) { 183 if (uf_info->utfs & (UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT - 1)) {
184 printk(KERN_ERR "%s: utfs is not aligned\n", __FUNCTION__); 184 printk(KERN_ERR "%s: utfs is not aligned\n", __func__);
185 return -EINVAL; 185 return -EINVAL;
186 } 186 }
187 187
188 if (uf_info->utfet & (UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT - 1)) { 188 if (uf_info->utfet & (UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT - 1)) {
189 printk(KERN_ERR "%s: utfet is not aligned\n", __FUNCTION__); 189 printk(KERN_ERR "%s: utfet is not aligned\n", __func__);
190 return -EINVAL; 190 return -EINVAL;
191 } 191 }
192 192
193 if (uf_info->utftt & (UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT - 1)) { 193 if (uf_info->utftt & (UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT - 1)) {
194 printk(KERN_ERR "%s: utftt is not aligned\n", __FUNCTION__); 194 printk(KERN_ERR "%s: utftt is not aligned\n", __func__);
195 return -EINVAL; 195 return -EINVAL;
196 } 196 }
197 197
198 uccf = kzalloc(sizeof(struct ucc_fast_private), GFP_KERNEL); 198 uccf = kzalloc(sizeof(struct ucc_fast_private), GFP_KERNEL);
199 if (!uccf) { 199 if (!uccf) {
200 printk(KERN_ERR "%s: Cannot allocate private data\n", 200 printk(KERN_ERR "%s: Cannot allocate private data\n",
201 __FUNCTION__); 201 __func__);
202 return -ENOMEM; 202 return -ENOMEM;
203 } 203 }
204 204
@@ -207,7 +207,7 @@ int ucc_fast_init(struct ucc_fast_info * uf_info, struct ucc_fast_private ** ucc
207 /* Set the PHY base address */ 207 /* Set the PHY base address */
208 uccf->uf_regs = ioremap(uf_info->regs, sizeof(struct ucc_fast)); 208 uccf->uf_regs = ioremap(uf_info->regs, sizeof(struct ucc_fast));
209 if (uccf->uf_regs == NULL) { 209 if (uccf->uf_regs == NULL) {
210 printk(KERN_ERR "%s: Cannot map UCC registers\n", __FUNCTION__); 210 printk(KERN_ERR "%s: Cannot map UCC registers\n", __func__);
211 return -ENOMEM; 211 return -ENOMEM;
212 } 212 }
213 213
@@ -230,7 +230,7 @@ int ucc_fast_init(struct ucc_fast_info * uf_info, struct ucc_fast_private ** ucc
230 /* Set UCC to fast type */ 230 /* Set UCC to fast type */
231 ret = ucc_set_type(uf_info->ucc_num, UCC_SPEED_TYPE_FAST); 231 ret = ucc_set_type(uf_info->ucc_num, UCC_SPEED_TYPE_FAST);
232 if (ret) { 232 if (ret) {
233 printk(KERN_ERR "%s: cannot set UCC type\n", __FUNCTION__); 233 printk(KERN_ERR "%s: cannot set UCC type\n", __func__);
234 ucc_fast_free(uccf); 234 ucc_fast_free(uccf);
235 return ret; 235 return ret;
236 } 236 }
@@ -270,7 +270,7 @@ int ucc_fast_init(struct ucc_fast_info * uf_info, struct ucc_fast_private ** ucc
270 qe_muram_alloc(uf_info->utfs, UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT); 270 qe_muram_alloc(uf_info->utfs, UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT);
271 if (IS_ERR_VALUE(uccf->ucc_fast_tx_virtual_fifo_base_offset)) { 271 if (IS_ERR_VALUE(uccf->ucc_fast_tx_virtual_fifo_base_offset)) {
272 printk(KERN_ERR "%s: cannot allocate MURAM for TX FIFO\n", 272 printk(KERN_ERR "%s: cannot allocate MURAM for TX FIFO\n",
273 __FUNCTION__); 273 __func__);
274 uccf->ucc_fast_tx_virtual_fifo_base_offset = 0; 274 uccf->ucc_fast_tx_virtual_fifo_base_offset = 0;
275 ucc_fast_free(uccf); 275 ucc_fast_free(uccf);
276 return -ENOMEM; 276 return -ENOMEM;
@@ -283,7 +283,7 @@ int ucc_fast_init(struct ucc_fast_info * uf_info, struct ucc_fast_private ** ucc
283 UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT); 283 UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT);
284 if (IS_ERR_VALUE(uccf->ucc_fast_rx_virtual_fifo_base_offset)) { 284 if (IS_ERR_VALUE(uccf->ucc_fast_rx_virtual_fifo_base_offset)) {
285 printk(KERN_ERR "%s: cannot allocate MURAM for RX FIFO\n", 285 printk(KERN_ERR "%s: cannot allocate MURAM for RX FIFO\n",
286 __FUNCTION__); 286 __func__);
287 uccf->ucc_fast_rx_virtual_fifo_base_offset = 0; 287 uccf->ucc_fast_rx_virtual_fifo_base_offset = 0;
288 ucc_fast_free(uccf); 288 ucc_fast_free(uccf);
289 return -ENOMEM; 289 return -ENOMEM;
@@ -314,7 +314,7 @@ int ucc_fast_init(struct ucc_fast_info * uf_info, struct ucc_fast_private ** ucc
314 ucc_set_qe_mux_rxtx(uf_info->ucc_num, uf_info->rx_clock, 314 ucc_set_qe_mux_rxtx(uf_info->ucc_num, uf_info->rx_clock,
315 COMM_DIR_RX)) { 315 COMM_DIR_RX)) {
316 printk(KERN_ERR "%s: illegal value for RX clock\n", 316 printk(KERN_ERR "%s: illegal value for RX clock\n",
317 __FUNCTION__); 317 __func__);
318 ucc_fast_free(uccf); 318 ucc_fast_free(uccf);
319 return -EINVAL; 319 return -EINVAL;
320 } 320 }
@@ -323,7 +323,7 @@ int ucc_fast_init(struct ucc_fast_info * uf_info, struct ucc_fast_private ** ucc
323 ucc_set_qe_mux_rxtx(uf_info->ucc_num, uf_info->tx_clock, 323 ucc_set_qe_mux_rxtx(uf_info->ucc_num, uf_info->tx_clock,
324 COMM_DIR_TX)) { 324 COMM_DIR_TX)) {
325 printk(KERN_ERR "%s: illegal value for TX clock\n", 325 printk(KERN_ERR "%s: illegal value for TX clock\n",
326 __FUNCTION__); 326 __func__);
327 ucc_fast_free(uccf); 327 ucc_fast_free(uccf);
328 return -EINVAL; 328 return -EINVAL;
329 } 329 }
diff --git a/arch/powerpc/sysdev/qe_lib/ucc_slow.c b/arch/powerpc/sysdev/qe_lib/ucc_slow.c
index b2870b208ddb..a578bc77b9d5 100644
--- a/arch/powerpc/sysdev/qe_lib/ucc_slow.c
+++ b/arch/powerpc/sysdev/qe_lib/ucc_slow.c
@@ -142,7 +142,7 @@ int ucc_slow_init(struct ucc_slow_info * us_info, struct ucc_slow_private ** ucc
142 142
143 /* check if the UCC port number is in range. */ 143 /* check if the UCC port number is in range. */
144 if ((us_info->ucc_num < 0) || (us_info->ucc_num > UCC_MAX_NUM - 1)) { 144 if ((us_info->ucc_num < 0) || (us_info->ucc_num > UCC_MAX_NUM - 1)) {
145 printk(KERN_ERR "%s: illegal UCC number\n", __FUNCTION__); 145 printk(KERN_ERR "%s: illegal UCC number\n", __func__);
146 return -EINVAL; 146 return -EINVAL;
147 } 147 }
148 148
@@ -161,7 +161,7 @@ int ucc_slow_init(struct ucc_slow_info * us_info, struct ucc_slow_private ** ucc
161 uccs = kzalloc(sizeof(struct ucc_slow_private), GFP_KERNEL); 161 uccs = kzalloc(sizeof(struct ucc_slow_private), GFP_KERNEL);
162 if (!uccs) { 162 if (!uccs) {
163 printk(KERN_ERR "%s: Cannot allocate private data\n", 163 printk(KERN_ERR "%s: Cannot allocate private data\n",
164 __FUNCTION__); 164 __func__);
165 return -ENOMEM; 165 return -ENOMEM;
166 } 166 }
167 167
@@ -170,7 +170,7 @@ int ucc_slow_init(struct ucc_slow_info * us_info, struct ucc_slow_private ** ucc
170 /* Set the PHY base address */ 170 /* Set the PHY base address */
171 uccs->us_regs = ioremap(us_info->regs, sizeof(struct ucc_slow)); 171 uccs->us_regs = ioremap(us_info->regs, sizeof(struct ucc_slow));
172 if (uccs->us_regs == NULL) { 172 if (uccs->us_regs == NULL) {
173 printk(KERN_ERR "%s: Cannot map UCC registers\n", __FUNCTION__); 173 printk(KERN_ERR "%s: Cannot map UCC registers\n", __func__);
174 return -ENOMEM; 174 return -ENOMEM;
175 } 175 }
176 176
@@ -189,7 +189,7 @@ int ucc_slow_init(struct ucc_slow_info * us_info, struct ucc_slow_private ** ucc
189 uccs->us_pram_offset = 189 uccs->us_pram_offset =
190 qe_muram_alloc(UCC_SLOW_PRAM_SIZE, ALIGNMENT_OF_UCC_SLOW_PRAM); 190 qe_muram_alloc(UCC_SLOW_PRAM_SIZE, ALIGNMENT_OF_UCC_SLOW_PRAM);
191 if (IS_ERR_VALUE(uccs->us_pram_offset)) { 191 if (IS_ERR_VALUE(uccs->us_pram_offset)) {
192 printk(KERN_ERR "%s: cannot allocate MURAM for PRAM", __FUNCTION__); 192 printk(KERN_ERR "%s: cannot allocate MURAM for PRAM", __func__);
193 ucc_slow_free(uccs); 193 ucc_slow_free(uccs);
194 return -ENOMEM; 194 return -ENOMEM;
195 } 195 }
@@ -202,7 +202,7 @@ int ucc_slow_init(struct ucc_slow_info * us_info, struct ucc_slow_private ** ucc
202 /* Set UCC to slow type */ 202 /* Set UCC to slow type */
203 ret = ucc_set_type(us_info->ucc_num, UCC_SPEED_TYPE_SLOW); 203 ret = ucc_set_type(us_info->ucc_num, UCC_SPEED_TYPE_SLOW);
204 if (ret) { 204 if (ret) {
205 printk(KERN_ERR "%s: cannot set UCC type", __FUNCTION__); 205 printk(KERN_ERR "%s: cannot set UCC type", __func__);
206 ucc_slow_free(uccs); 206 ucc_slow_free(uccs);
207 return ret; 207 return ret;
208 } 208 }
@@ -216,7 +216,7 @@ int ucc_slow_init(struct ucc_slow_info * us_info, struct ucc_slow_private ** ucc
216 qe_muram_alloc(us_info->rx_bd_ring_len * sizeof(struct qe_bd), 216 qe_muram_alloc(us_info->rx_bd_ring_len * sizeof(struct qe_bd),
217 QE_ALIGNMENT_OF_BD); 217 QE_ALIGNMENT_OF_BD);
218 if (IS_ERR_VALUE(uccs->rx_base_offset)) { 218 if (IS_ERR_VALUE(uccs->rx_base_offset)) {
219 printk(KERN_ERR "%s: cannot allocate %u RX BDs\n", __FUNCTION__, 219 printk(KERN_ERR "%s: cannot allocate %u RX BDs\n", __func__,
220 us_info->rx_bd_ring_len); 220 us_info->rx_bd_ring_len);
221 uccs->rx_base_offset = 0; 221 uccs->rx_base_offset = 0;
222 ucc_slow_free(uccs); 222 ucc_slow_free(uccs);
@@ -227,7 +227,7 @@ int ucc_slow_init(struct ucc_slow_info * us_info, struct ucc_slow_private ** ucc
227 qe_muram_alloc(us_info->tx_bd_ring_len * sizeof(struct qe_bd), 227 qe_muram_alloc(us_info->tx_bd_ring_len * sizeof(struct qe_bd),
228 QE_ALIGNMENT_OF_BD); 228 QE_ALIGNMENT_OF_BD);
229 if (IS_ERR_VALUE(uccs->tx_base_offset)) { 229 if (IS_ERR_VALUE(uccs->tx_base_offset)) {
230 printk(KERN_ERR "%s: cannot allocate TX BDs", __FUNCTION__); 230 printk(KERN_ERR "%s: cannot allocate TX BDs", __func__);
231 uccs->tx_base_offset = 0; 231 uccs->tx_base_offset = 0;
232 ucc_slow_free(uccs); 232 ucc_slow_free(uccs);
233 return -ENOMEM; 233 return -ENOMEM;
@@ -317,7 +317,7 @@ int ucc_slow_init(struct ucc_slow_info * us_info, struct ucc_slow_private ** ucc
317 if (ucc_set_qe_mux_rxtx(us_info->ucc_num, us_info->rx_clock, 317 if (ucc_set_qe_mux_rxtx(us_info->ucc_num, us_info->rx_clock,
318 COMM_DIR_RX)) { 318 COMM_DIR_RX)) {
319 printk(KERN_ERR "%s: illegal value for RX clock\n", 319 printk(KERN_ERR "%s: illegal value for RX clock\n",
320 __FUNCTION__); 320 __func__);
321 ucc_slow_free(uccs); 321 ucc_slow_free(uccs);
322 return -EINVAL; 322 return -EINVAL;
323 } 323 }
@@ -325,7 +325,7 @@ int ucc_slow_init(struct ucc_slow_info * us_info, struct ucc_slow_private ** ucc
325 if (ucc_set_qe_mux_rxtx(us_info->ucc_num, us_info->tx_clock, 325 if (ucc_set_qe_mux_rxtx(us_info->ucc_num, us_info->tx_clock,
326 COMM_DIR_TX)) { 326 COMM_DIR_TX)) {
327 printk(KERN_ERR "%s: illegal value for TX clock\n", 327 printk(KERN_ERR "%s: illegal value for TX clock\n",
328 __FUNCTION__); 328 __func__);
329 ucc_slow_free(uccs); 329 ucc_slow_free(uccs);
330 return -EINVAL; 330 return -EINVAL;
331 } 331 }
diff --git a/arch/powerpc/sysdev/tsi108_dev.c b/arch/powerpc/sysdev/tsi108_dev.c
index be2808a292f7..d4d15aaf18fa 100644
--- a/arch/powerpc/sysdev/tsi108_dev.c
+++ b/arch/powerpc/sysdev/tsi108_dev.c
@@ -84,7 +84,7 @@ static int __init tsi108_eth_of_init(void)
84 84
85 ret = of_address_to_resource(np, 0, &r[0]); 85 ret = of_address_to_resource(np, 0, &r[0]);
86 DBG("%s: name:start->end = %s:0x%lx-> 0x%lx\n", 86 DBG("%s: name:start->end = %s:0x%lx-> 0x%lx\n",
87 __FUNCTION__,r[0].name, r[0].start, r[0].end); 87 __func__,r[0].name, r[0].start, r[0].end);
88 if (ret) 88 if (ret)
89 goto err; 89 goto err;
90 90
@@ -93,7 +93,7 @@ static int __init tsi108_eth_of_init(void)
93 r[1].end = irq_of_parse_and_map(np, 0); 93 r[1].end = irq_of_parse_and_map(np, 0);
94 r[1].flags = IORESOURCE_IRQ; 94 r[1].flags = IORESOURCE_IRQ;
95 DBG("%s: name:start->end = %s:0x%lx-> 0x%lx\n", 95 DBG("%s: name:start->end = %s:0x%lx-> 0x%lx\n",
96 __FUNCTION__,r[1].name, r[1].start, r[1].end); 96 __func__,r[1].name, r[1].start, r[1].end);
97 97
98 tsi_eth_dev = 98 tsi_eth_dev =
99 platform_device_register_simple("tsi-ethernet", i++, &r[0], 99 platform_device_register_simple("tsi-ethernet", i++, &r[0],
diff --git a/arch/powerpc/sysdev/tsi108_pci.c b/arch/powerpc/sysdev/tsi108_pci.c
index 31d3d33d91fc..ac1a72dc21e5 100644
--- a/arch/powerpc/sysdev/tsi108_pci.c
+++ b/arch/powerpc/sysdev/tsi108_pci.c
@@ -207,7 +207,7 @@ int __init tsi108_setup_pci(struct device_node *dev, u32 cfg_phys, int primary)
207 /* PCI Config mapping */ 207 /* PCI Config mapping */
208 tsi108_pci_cfg_base = (u32)ioremap(cfg_phys, TSI108_PCI_CFG_SIZE); 208 tsi108_pci_cfg_base = (u32)ioremap(cfg_phys, TSI108_PCI_CFG_SIZE);
209 tsi108_pci_cfg_phys = cfg_phys; 209 tsi108_pci_cfg_phys = cfg_phys;
210 DBG("TSI_PCI: %s tsi108_pci_cfg_base=0x%x\n", __FUNCTION__, 210 DBG("TSI_PCI: %s tsi108_pci_cfg_base=0x%x\n", __func__,
211 tsi108_pci_cfg_base); 211 tsi108_pci_cfg_base);
212 212
213 /* Fetch host bridge registers address */ 213 /* Fetch host bridge registers address */
@@ -395,7 +395,7 @@ static int pci_irq_host_xlate(struct irq_host *h, struct device_node *ct,
395static int pci_irq_host_map(struct irq_host *h, unsigned int virq, 395static int pci_irq_host_map(struct irq_host *h, unsigned int virq,
396 irq_hw_number_t hw) 396 irq_hw_number_t hw)
397{ unsigned int irq; 397{ unsigned int irq;
398 DBG("%s(%d, 0x%lx)\n", __FUNCTION__, virq, hw); 398 DBG("%s(%d, 0x%lx)\n", __func__, virq, hw);
399 if ((virq >= 1) && (virq <= 4)){ 399 if ((virq >= 1) && (virq <= 4)){
400 irq = virq + IRQ_PCI_INTAD_BASE - 1; 400 irq = virq + IRQ_PCI_INTAD_BASE - 1;
401 get_irq_desc(irq)->status |= IRQ_LEVEL; 401 get_irq_desc(irq)->status |= IRQ_LEVEL;
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-25 15:36:22 -0500