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-rw-r--r--arch/powerpc/sysdev/Makefile3
-rw-r--r--arch/powerpc/sysdev/fsl_pci.c150
-rw-r--r--arch/powerpc/sysdev/fsl_rio.c932
-rw-r--r--arch/powerpc/sysdev/fsl_rio.h20
-rw-r--r--arch/powerpc/sysdev/fsl_soc.c103
-rw-r--r--arch/powerpc/sysdev/ipic.c62
-rw-r--r--arch/powerpc/sysdev/mpic.c4
-rw-r--r--arch/powerpc/sysdev/qe_lib/Kconfig2
-rw-r--r--arch/powerpc/sysdev/qe_lib/qe.c247
-rw-r--r--arch/powerpc/sysdev/qe_lib/ucc_slow.c10
10 files changed, 1414 insertions, 119 deletions
diff --git a/arch/powerpc/sysdev/Makefile b/arch/powerpc/sysdev/Makefile
index 9a20ef4f0ea4..f17e7b885f60 100644
--- a/arch/powerpc/sysdev/Makefile
+++ b/arch/powerpc/sysdev/Makefile
@@ -12,6 +12,7 @@ obj-$(CONFIG_U3_DART) += dart_iommu.o
12obj-$(CONFIG_MMIO_NVRAM) += mmio_nvram.o 12obj-$(CONFIG_MMIO_NVRAM) += mmio_nvram.o
13obj-$(CONFIG_FSL_SOC) += fsl_soc.o 13obj-$(CONFIG_FSL_SOC) += fsl_soc.o
14obj-$(CONFIG_FSL_PCI) += fsl_pci.o 14obj-$(CONFIG_FSL_PCI) += fsl_pci.o
15obj-$(CONFIG_RAPIDIO) += fsl_rio.o
15obj-$(CONFIG_TSI108_BRIDGE) += tsi108_pci.o tsi108_dev.o 16obj-$(CONFIG_TSI108_BRIDGE) += tsi108_pci.o tsi108_dev.o
16obj-$(CONFIG_QUICC_ENGINE) += qe_lib/ 17obj-$(CONFIG_QUICC_ENGINE) += qe_lib/
17obj-$(CONFIG_PPC_BESTCOMM) += bestcomm/ 18obj-$(CONFIG_PPC_BESTCOMM) += bestcomm/
@@ -24,7 +25,7 @@ obj-$(CONFIG_AXON_RAM) += axonram.o
24ifeq ($(CONFIG_PPC_MERGE),y) 25ifeq ($(CONFIG_PPC_MERGE),y)
25obj-$(CONFIG_PPC_INDIRECT_PCI) += indirect_pci.o 26obj-$(CONFIG_PPC_INDIRECT_PCI) += indirect_pci.o
26obj-$(CONFIG_PPC_I8259) += i8259.o 27obj-$(CONFIG_PPC_I8259) += i8259.o
27obj-$(CONFIG_PPC_83xx) += ipic.o 28obj-$(CONFIG_IPIC) += ipic.o
28obj-$(CONFIG_4xx) += uic.o 29obj-$(CONFIG_4xx) += uic.o
29obj-$(CONFIG_XILINX_VIRTEX) += xilinx_intc.o 30obj-$(CONFIG_XILINX_VIRTEX) += xilinx_intc.o
30ifeq ($(CONFIG_PCI),y) 31ifeq ($(CONFIG_PCI),y)
diff --git a/arch/powerpc/sysdev/fsl_pci.c b/arch/powerpc/sysdev/fsl_pci.c
index 4b1d5120c122..bf13c2174a4e 100644
--- a/arch/powerpc/sysdev/fsl_pci.c
+++ b/arch/powerpc/sysdev/fsl_pci.c
@@ -33,8 +33,8 @@ void __init setup_pci_atmu(struct pci_controller *hose, struct resource *rsrc)
33 struct ccsr_pci __iomem *pci; 33 struct ccsr_pci __iomem *pci;
34 int i; 34 int i;
35 35
36 pr_debug("PCI memory map start 0x%x, size 0x%x\n", rsrc->start, 36 pr_debug("PCI memory map start 0x%016llx, size 0x%016llx\n",
37 rsrc->end - rsrc->start + 1); 37 (u64)rsrc->start, (u64)rsrc->end - (u64)rsrc->start + 1);
38 pci = ioremap(rsrc->start, rsrc->end - rsrc->start + 1); 38 pci = ioremap(rsrc->start, rsrc->end - rsrc->start + 1);
39 39
40 /* Disable all windows (except powar0 since its ignored) */ 40 /* Disable all windows (except powar0 since its ignored) */
@@ -46,17 +46,17 @@ void __init setup_pci_atmu(struct pci_controller *hose, struct resource *rsrc)
46 /* Setup outbound MEM window */ 46 /* Setup outbound MEM window */
47 for(i = 0; i < 3; i++) 47 for(i = 0; i < 3; i++)
48 if (hose->mem_resources[i].flags & IORESOURCE_MEM){ 48 if (hose->mem_resources[i].flags & IORESOURCE_MEM){
49 pr_debug("PCI MEM resource start 0x%08x, size 0x%08x.\n", 49 resource_size_t pci_addr_start =
50 hose->mem_resources[i].start, 50 hose->mem_resources[i].start -
51 hose->mem_resources[i].end 51 hose->pci_mem_offset;
52 - hose->mem_resources[i].start + 1); 52 pr_debug("PCI MEM resource start 0x%016llx, size 0x%016llx.\n",
53 out_be32(&pci->pow[i+1].potar, 53 (u64)hose->mem_resources[i].start,
54 (hose->mem_resources[i].start >> 12) 54 (u64)hose->mem_resources[i].end
55 & 0x000fffff); 55 - (u64)hose->mem_resources[i].start + 1);
56 out_be32(&pci->pow[i+1].potar, (pci_addr_start >> 12));
56 out_be32(&pci->pow[i+1].potear, 0); 57 out_be32(&pci->pow[i+1].potear, 0);
57 out_be32(&pci->pow[i+1].powbar, 58 out_be32(&pci->pow[i+1].powbar,
58 (hose->mem_resources[i].start >> 12) 59 (hose->mem_resources[i].start >> 12));
59 & 0x000fffff);
60 /* Enable, Mem R/W */ 60 /* Enable, Mem R/W */
61 out_be32(&pci->pow[i+1].powar, 0x80044000 61 out_be32(&pci->pow[i+1].powar, 0x80044000
62 | (__ilog2(hose->mem_resources[i].end 62 | (__ilog2(hose->mem_resources[i].end
@@ -65,15 +65,14 @@ void __init setup_pci_atmu(struct pci_controller *hose, struct resource *rsrc)
65 65
66 /* Setup outbound IO window */ 66 /* Setup outbound IO window */
67 if (hose->io_resource.flags & IORESOURCE_IO){ 67 if (hose->io_resource.flags & IORESOURCE_IO){
68 pr_debug("PCI IO resource start 0x%08x, size 0x%08x, phy base 0x%08x.\n", 68 pr_debug("PCI IO resource start 0x%016llx, size 0x%016llx, "
69 hose->io_resource.start, 69 "phy base 0x%016llx.\n",
70 hose->io_resource.end - hose->io_resource.start + 1, 70 (u64)hose->io_resource.start,
71 hose->io_base_phys); 71 (u64)hose->io_resource.end - (u64)hose->io_resource.start + 1,
72 out_be32(&pci->pow[i+1].potar, (hose->io_resource.start >> 12) 72 (u64)hose->io_base_phys);
73 & 0x000fffff); 73 out_be32(&pci->pow[i+1].potar, (hose->io_resource.start >> 12));
74 out_be32(&pci->pow[i+1].potear, 0); 74 out_be32(&pci->pow[i+1].potear, 0);
75 out_be32(&pci->pow[i+1].powbar, (hose->io_base_phys >> 12) 75 out_be32(&pci->pow[i+1].powbar, (hose->io_base_phys >> 12));
76 & 0x000fffff);
77 /* Enable, IO R/W */ 76 /* Enable, IO R/W */
78 out_be32(&pci->pow[i+1].powar, 0x80088000 77 out_be32(&pci->pow[i+1].powar, 0x80088000
79 | (__ilog2(hose->io_resource.end 78 | (__ilog2(hose->io_resource.end
@@ -107,55 +106,17 @@ void __init setup_pci_cmd(struct pci_controller *hose)
107 } 106 }
108} 107}
109 108
110static void __init quirk_fsl_pcie_transparent(struct pci_dev *dev) 109static int fsl_pcie_bus_fixup;
111{
112 struct resource *res;
113 int i, res_idx = PCI_BRIDGE_RESOURCES;
114 struct pci_controller *hose;
115 110
111static void __init quirk_fsl_pcie_header(struct pci_dev *dev)
112{
116 /* if we aren't a PCIe don't bother */ 113 /* if we aren't a PCIe don't bother */
117 if (!pci_find_capability(dev, PCI_CAP_ID_EXP)) 114 if (!pci_find_capability(dev, PCI_CAP_ID_EXP))
118 return ; 115 return ;
119 116
120 /* 117 dev->class = PCI_CLASS_BRIDGE_PCI << 8;
121 * Make the bridge be transparent. 118 fsl_pcie_bus_fixup = 1;
122 */ 119 return ;
123 dev->transparent = 1;
124
125 hose = pci_bus_to_host(dev->bus);
126 if (!hose) {
127 printk(KERN_ERR "Can't find hose for bus %d\n",
128 dev->bus->number);
129 return;
130 }
131
132 /* Clear out any of the virtual P2P bridge registers */
133 pci_write_config_word(dev, PCI_IO_BASE_UPPER16, 0);
134 pci_write_config_word(dev, PCI_IO_LIMIT_UPPER16, 0);
135 pci_write_config_byte(dev, PCI_IO_BASE, 0x10);
136 pci_write_config_byte(dev, PCI_IO_LIMIT, 0);
137 pci_write_config_word(dev, PCI_MEMORY_BASE, 0x10);
138 pci_write_config_word(dev, PCI_MEMORY_LIMIT, 0);
139 pci_write_config_word(dev, PCI_PREF_BASE_UPPER32, 0x0);
140 pci_write_config_word(dev, PCI_PREF_LIMIT_UPPER32, 0x0);
141 pci_write_config_word(dev, PCI_PREF_MEMORY_BASE, 0x10);
142 pci_write_config_word(dev, PCI_PREF_MEMORY_LIMIT, 0);
143
144 if (hose->io_resource.flags) {
145 res = &dev->resource[res_idx++];
146 res->start = hose->io_resource.start;
147 res->end = hose->io_resource.end;
148 res->flags = hose->io_resource.flags;
149 update_bridge_resource(dev, res);
150 }
151
152 for (i = 0; i < 3; i++) {
153 res = &dev->resource[res_idx + i];
154 res->start = hose->mem_resources[i].start;
155 res->end = hose->mem_resources[i].end;
156 res->flags = hose->mem_resources[i].flags;
157 update_bridge_resource(dev, res);
158 }
159} 120}
160 121
161int __init fsl_pcie_check_link(struct pci_controller *hose) 122int __init fsl_pcie_check_link(struct pci_controller *hose)
@@ -172,11 +133,24 @@ void fsl_pcibios_fixup_bus(struct pci_bus *bus)
172 struct pci_controller *hose = (struct pci_controller *) bus->sysdata; 133 struct pci_controller *hose = (struct pci_controller *) bus->sysdata;
173 int i; 134 int i;
174 135
175 /* deal with bogus pci_bus when we don't have anything connected on PCIe */ 136 if ((bus->parent == hose->bus) &&
176 if (hose->indirect_type & PPC_INDIRECT_TYPE_NO_PCIE_LINK) { 137 ((fsl_pcie_bus_fixup &&
177 if (bus->parent) { 138 early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) ||
178 for (i = 0; i < 4; ++i) 139 (hose->indirect_type & PPC_INDIRECT_TYPE_NO_PCIE_LINK)))
179 bus->resource[i] = bus->parent->resource[i]; 140 {
141 for (i = 0; i < 4; ++i) {
142 struct resource *res = bus->resource[i];
143 struct resource *par = bus->parent->resource[i];
144 if (res) {
145 res->start = 0;
146 res->end = 0;
147 res->flags = 0;
148 }
149 if (res && par) {
150 res->start = par->start;
151 res->end = par->end;
152 res->flags = par->flags;
153 }
180 } 154 }
181 } 155 }
182} 156}
@@ -240,23 +214,23 @@ int __init fsl_add_bridge(struct device_node *dev, int is_primary)
240 return 0; 214 return 0;
241} 215}
242 216
243DECLARE_PCI_FIXUP_EARLY(0x1957, PCI_DEVICE_ID_MPC8548E, quirk_fsl_pcie_transparent); 217DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8548E, quirk_fsl_pcie_header);
244DECLARE_PCI_FIXUP_EARLY(0x1957, PCI_DEVICE_ID_MPC8548, quirk_fsl_pcie_transparent); 218DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8548, quirk_fsl_pcie_header);
245DECLARE_PCI_FIXUP_EARLY(0x1957, PCI_DEVICE_ID_MPC8543E, quirk_fsl_pcie_transparent); 219DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8543E, quirk_fsl_pcie_header);
246DECLARE_PCI_FIXUP_EARLY(0x1957, PCI_DEVICE_ID_MPC8543, quirk_fsl_pcie_transparent); 220DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8543, quirk_fsl_pcie_header);
247DECLARE_PCI_FIXUP_EARLY(0x1957, PCI_DEVICE_ID_MPC8547E, quirk_fsl_pcie_transparent); 221DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8547E, quirk_fsl_pcie_header);
248DECLARE_PCI_FIXUP_EARLY(0x1957, PCI_DEVICE_ID_MPC8545E, quirk_fsl_pcie_transparent); 222DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8545E, quirk_fsl_pcie_header);
249DECLARE_PCI_FIXUP_EARLY(0x1957, PCI_DEVICE_ID_MPC8545, quirk_fsl_pcie_transparent); 223DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8545, quirk_fsl_pcie_header);
250DECLARE_PCI_FIXUP_EARLY(0x1957, PCI_DEVICE_ID_MPC8568E, quirk_fsl_pcie_transparent); 224DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8568E, quirk_fsl_pcie_header);
251DECLARE_PCI_FIXUP_EARLY(0x1957, PCI_DEVICE_ID_MPC8568, quirk_fsl_pcie_transparent); 225DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8568, quirk_fsl_pcie_header);
252DECLARE_PCI_FIXUP_EARLY(0x1957, PCI_DEVICE_ID_MPC8567E, quirk_fsl_pcie_transparent); 226DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8567E, quirk_fsl_pcie_header);
253DECLARE_PCI_FIXUP_EARLY(0x1957, PCI_DEVICE_ID_MPC8567, quirk_fsl_pcie_transparent); 227DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8567, quirk_fsl_pcie_header);
254DECLARE_PCI_FIXUP_EARLY(0x1957, PCI_DEVICE_ID_MPC8533E, quirk_fsl_pcie_transparent); 228DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8533E, quirk_fsl_pcie_header);
255DECLARE_PCI_FIXUP_EARLY(0x1957, PCI_DEVICE_ID_MPC8533, quirk_fsl_pcie_transparent); 229DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8533, quirk_fsl_pcie_header);
256DECLARE_PCI_FIXUP_EARLY(0x1957, PCI_DEVICE_ID_MPC8544E, quirk_fsl_pcie_transparent); 230DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8544E, quirk_fsl_pcie_header);
257DECLARE_PCI_FIXUP_EARLY(0x1957, PCI_DEVICE_ID_MPC8544, quirk_fsl_pcie_transparent); 231DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8544, quirk_fsl_pcie_header);
258DECLARE_PCI_FIXUP_EARLY(0x1957, PCI_DEVICE_ID_MPC8572E, quirk_fsl_pcie_transparent); 232DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8572E, quirk_fsl_pcie_header);
259DECLARE_PCI_FIXUP_EARLY(0x1957, PCI_DEVICE_ID_MPC8572, quirk_fsl_pcie_transparent); 233DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8572, quirk_fsl_pcie_header);
260DECLARE_PCI_FIXUP_EARLY(0x1957, PCI_DEVICE_ID_MPC8641, quirk_fsl_pcie_transparent); 234DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8641, quirk_fsl_pcie_header);
261DECLARE_PCI_FIXUP_EARLY(0x1957, PCI_DEVICE_ID_MPC8641D, quirk_fsl_pcie_transparent); 235DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8641D, quirk_fsl_pcie_header);
262DECLARE_PCI_FIXUP_EARLY(0x1957, PCI_DEVICE_ID_MPC8610, quirk_fsl_pcie_transparent); 236DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8610, quirk_fsl_pcie_header);
diff --git a/arch/powerpc/sysdev/fsl_rio.c b/arch/powerpc/sysdev/fsl_rio.c
new file mode 100644
index 000000000000..af2425e4655f
--- /dev/null
+++ b/arch/powerpc/sysdev/fsl_rio.c
@@ -0,0 +1,932 @@
1/*
2 * MPC85xx RapidIO support
3 *
4 * Copyright 2005 MontaVista Software, Inc.
5 * Matt Porter <mporter@kernel.crashing.org>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 */
12
13#include <linux/init.h>
14#include <linux/module.h>
15#include <linux/types.h>
16#include <linux/dma-mapping.h>
17#include <linux/interrupt.h>
18#include <linux/rio.h>
19#include <linux/rio_drv.h>
20
21#include <asm/io.h>
22
23#define RIO_REGS_BASE (CCSRBAR + 0xc0000)
24#define RIO_ATMU_REGS_OFFSET 0x10c00
25#define RIO_MSG_REGS_OFFSET 0x11000
26#define RIO_MAINT_WIN_SIZE 0x400000
27#define RIO_DBELL_WIN_SIZE 0x1000
28
29#define RIO_MSG_OMR_MUI 0x00000002
30#define RIO_MSG_OSR_TE 0x00000080
31#define RIO_MSG_OSR_QOI 0x00000020
32#define RIO_MSG_OSR_QFI 0x00000010
33#define RIO_MSG_OSR_MUB 0x00000004
34#define RIO_MSG_OSR_EOMI 0x00000002
35#define RIO_MSG_OSR_QEI 0x00000001
36
37#define RIO_MSG_IMR_MI 0x00000002
38#define RIO_MSG_ISR_TE 0x00000080
39#define RIO_MSG_ISR_QFI 0x00000010
40#define RIO_MSG_ISR_DIQI 0x00000001
41
42#define RIO_MSG_DESC_SIZE 32
43#define RIO_MSG_BUFFER_SIZE 4096
44#define RIO_MIN_TX_RING_SIZE 2
45#define RIO_MAX_TX_RING_SIZE 2048
46#define RIO_MIN_RX_RING_SIZE 2
47#define RIO_MAX_RX_RING_SIZE 2048
48
49#define DOORBELL_DMR_DI 0x00000002
50#define DOORBELL_DSR_TE 0x00000080
51#define DOORBELL_DSR_QFI 0x00000010
52#define DOORBELL_DSR_DIQI 0x00000001
53#define DOORBELL_TID_OFFSET 0x03
54#define DOORBELL_SID_OFFSET 0x05
55#define DOORBELL_INFO_OFFSET 0x06
56
57#define DOORBELL_MESSAGE_SIZE 0x08
58#define DBELL_SID(x) (*(u8 *)(x + DOORBELL_SID_OFFSET))
59#define DBELL_TID(x) (*(u8 *)(x + DOORBELL_TID_OFFSET))
60#define DBELL_INF(x) (*(u16 *)(x + DOORBELL_INFO_OFFSET))
61
62struct rio_atmu_regs {
63 u32 rowtar;
64 u32 pad1;
65 u32 rowbar;
66 u32 pad2;
67 u32 rowar;
68 u32 pad3[3];
69};
70
71struct rio_msg_regs {
72 u32 omr;
73 u32 osr;
74 u32 pad1;
75 u32 odqdpar;
76 u32 pad2;
77 u32 osar;
78 u32 odpr;
79 u32 odatr;
80 u32 odcr;
81 u32 pad3;
82 u32 odqepar;
83 u32 pad4[13];
84 u32 imr;
85 u32 isr;
86 u32 pad5;
87 u32 ifqdpar;
88 u32 pad6;
89 u32 ifqepar;
90 u32 pad7[250];
91 u32 dmr;
92 u32 dsr;
93 u32 pad8;
94 u32 dqdpar;
95 u32 pad9;
96 u32 dqepar;
97 u32 pad10[26];
98 u32 pwmr;
99 u32 pwsr;
100 u32 pad11;
101 u32 pwqbar;
102};
103
104struct rio_tx_desc {
105 u32 res1;
106 u32 saddr;
107 u32 dport;
108 u32 dattr;
109 u32 res2;
110 u32 res3;
111 u32 dwcnt;
112 u32 res4;
113};
114
115static u32 regs_win;
116static struct rio_atmu_regs *atmu_regs;
117static struct rio_atmu_regs *maint_atmu_regs;
118static struct rio_atmu_regs *dbell_atmu_regs;
119static u32 dbell_win;
120static u32 maint_win;
121static struct rio_msg_regs *msg_regs;
122
123static struct rio_dbell_ring {
124 void *virt;
125 dma_addr_t phys;
126} dbell_ring;
127
128static struct rio_msg_tx_ring {
129 void *virt;
130 dma_addr_t phys;
131 void *virt_buffer[RIO_MAX_TX_RING_SIZE];
132 dma_addr_t phys_buffer[RIO_MAX_TX_RING_SIZE];
133 int tx_slot;
134 int size;
135 void *dev_id;
136} msg_tx_ring;
137
138static struct rio_msg_rx_ring {
139 void *virt;
140 dma_addr_t phys;
141 void *virt_buffer[RIO_MAX_RX_RING_SIZE];
142 int rx_slot;
143 int size;
144 void *dev_id;
145} msg_rx_ring;
146
147/**
148 * mpc85xx_rio_doorbell_send - Send a MPC85xx doorbell message
149 * @index: ID of RapidIO interface
150 * @destid: Destination ID of target device
151 * @data: 16-bit info field of RapidIO doorbell message
152 *
153 * Sends a MPC85xx doorbell message. Returns %0 on success or
154 * %-EINVAL on failure.
155 */
156static int mpc85xx_rio_doorbell_send(int index, u16 destid, u16 data)
157{
158 pr_debug("mpc85xx_doorbell_send: index %d destid %4.4x data %4.4x\n",
159 index, destid, data);
160 out_be32((void *)&dbell_atmu_regs->rowtar, destid << 22);
161 out_be16((void *)(dbell_win), data);
162
163 return 0;
164}
165
166/**
167 * mpc85xx_local_config_read - Generate a MPC85xx local config space read
168 * @index: ID of RapdiIO interface
169 * @offset: Offset into configuration space
170 * @len: Length (in bytes) of the maintenance transaction
171 * @data: Value to be read into
172 *
173 * Generates a MPC85xx local configuration space read. Returns %0 on
174 * success or %-EINVAL on failure.
175 */
176static int mpc85xx_local_config_read(int index, u32 offset, int len, u32 * data)
177{
178 pr_debug("mpc85xx_local_config_read: index %d offset %8.8x\n", index,
179 offset);
180 *data = in_be32((void *)(regs_win + offset));
181
182 return 0;
183}
184
185/**
186 * mpc85xx_local_config_write - Generate a MPC85xx local config space write
187 * @index: ID of RapdiIO interface
188 * @offset: Offset into configuration space
189 * @len: Length (in bytes) of the maintenance transaction
190 * @data: Value to be written
191 *
192 * Generates a MPC85xx local configuration space write. Returns %0 on
193 * success or %-EINVAL on failure.
194 */
195static int mpc85xx_local_config_write(int index, u32 offset, int len, u32 data)
196{
197 pr_debug
198 ("mpc85xx_local_config_write: index %d offset %8.8x data %8.8x\n",
199 index, offset, data);
200 out_be32((void *)(regs_win + offset), data);
201
202 return 0;
203}
204
205/**
206 * mpc85xx_rio_config_read - Generate a MPC85xx read maintenance transaction
207 * @index: ID of RapdiIO interface
208 * @destid: Destination ID of transaction
209 * @hopcount: Number of hops to target device
210 * @offset: Offset into configuration space
211 * @len: Length (in bytes) of the maintenance transaction
212 * @val: Location to be read into
213 *
214 * Generates a MPC85xx read maintenance transaction. Returns %0 on
215 * success or %-EINVAL on failure.
216 */
217static int
218mpc85xx_rio_config_read(int index, u16 destid, u8 hopcount, u32 offset, int len,
219 u32 * val)
220{
221 u8 *data;
222
223 pr_debug
224 ("mpc85xx_rio_config_read: index %d destid %d hopcount %d offset %8.8x len %d\n",
225 index, destid, hopcount, offset, len);
226 out_be32((void *)&maint_atmu_regs->rowtar,
227 (destid << 22) | (hopcount << 12) | ((offset & ~0x3) >> 9));
228
229 data = (u8 *) maint_win + offset;
230 switch (len) {
231 case 1:
232 *val = in_8((u8 *) data);
233 break;
234 case 2:
235 *val = in_be16((u16 *) data);
236 break;
237 default:
238 *val = in_be32((u32 *) data);
239 break;
240 }
241
242 return 0;
243}
244
245/**
246 * mpc85xx_rio_config_write - Generate a MPC85xx write maintenance transaction
247 * @index: ID of RapdiIO interface
248 * @destid: Destination ID of transaction
249 * @hopcount: Number of hops to target device
250 * @offset: Offset into configuration space
251 * @len: Length (in bytes) of the maintenance transaction
252 * @val: Value to be written
253 *
254 * Generates an MPC85xx write maintenance transaction. Returns %0 on
255 * success or %-EINVAL on failure.
256 */
257static int
258mpc85xx_rio_config_write(int index, u16 destid, u8 hopcount, u32 offset,
259 int len, u32 val)
260{
261 u8 *data;
262 pr_debug
263 ("mpc85xx_rio_config_write: index %d destid %d hopcount %d offset %8.8x len %d val %8.8x\n",
264 index, destid, hopcount, offset, len, val);
265 out_be32((void *)&maint_atmu_regs->rowtar,
266 (destid << 22) | (hopcount << 12) | ((offset & ~0x3) >> 9));
267
268 data = (u8 *) maint_win + offset;
269 switch (len) {
270 case 1:
271 out_8((u8 *) data, val);
272 break;
273 case 2:
274 out_be16((u16 *) data, val);
275 break;
276 default:
277 out_be32((u32 *) data, val);
278 break;
279 }
280
281 return 0;
282}
283
284/**
285 * rio_hw_add_outb_message - Add message to the MPC85xx outbound message queue
286 * @mport: Master port with outbound message queue
287 * @rdev: Target of outbound message
288 * @mbox: Outbound mailbox
289 * @buffer: Message to add to outbound queue
290 * @len: Length of message
291 *
292 * Adds the @buffer message to the MPC85xx outbound message queue. Returns
293 * %0 on success or %-EINVAL on failure.
294 */
295int
296rio_hw_add_outb_message(struct rio_mport *mport, struct rio_dev *rdev, int mbox,
297 void *buffer, size_t len)
298{
299 u32 omr;
300 struct rio_tx_desc *desc =
301 (struct rio_tx_desc *)msg_tx_ring.virt + msg_tx_ring.tx_slot;
302 int ret = 0;
303
304 pr_debug
305 ("RIO: rio_hw_add_outb_message(): destid %4.4x mbox %d buffer %8.8x len %8.8x\n",
306 rdev->destid, mbox, (int)buffer, len);
307
308 if ((len < 8) || (len > RIO_MAX_MSG_SIZE)) {
309 ret = -EINVAL;
310 goto out;
311 }
312
313 /* Copy and clear rest of buffer */
314 memcpy(msg_tx_ring.virt_buffer[msg_tx_ring.tx_slot], buffer, len);
315 if (len < (RIO_MAX_MSG_SIZE - 4))
316 memset((void *)((u32) msg_tx_ring.
317 virt_buffer[msg_tx_ring.tx_slot] + len), 0,
318 RIO_MAX_MSG_SIZE - len);
319
320 /* Set mbox field for message */
321 desc->dport = mbox & 0x3;
322
323 /* Enable EOMI interrupt, set priority, and set destid */
324 desc->dattr = 0x28000000 | (rdev->destid << 2);
325
326 /* Set transfer size aligned to next power of 2 (in double words) */
327 desc->dwcnt = is_power_of_2(len) ? len : 1 << get_bitmask_order(len);
328
329 /* Set snooping and source buffer address */
330 desc->saddr = 0x00000004 | msg_tx_ring.phys_buffer[msg_tx_ring.tx_slot];
331
332 /* Increment enqueue pointer */
333 omr = in_be32((void *)&msg_regs->omr);
334 out_be32((void *)&msg_regs->omr, omr | RIO_MSG_OMR_MUI);
335
336 /* Go to next descriptor */
337 if (++msg_tx_ring.tx_slot == msg_tx_ring.size)
338 msg_tx_ring.tx_slot = 0;
339
340 out:
341 return ret;
342}
343
344EXPORT_SYMBOL_GPL(rio_hw_add_outb_message);
345
346/**
347 * mpc85xx_rio_tx_handler - MPC85xx outbound message interrupt handler
348 * @irq: Linux interrupt number
349 * @dev_instance: Pointer to interrupt-specific data
350 *
351 * Handles outbound message interrupts. Executes a register outbound
352 * mailbox event handler and acks the interrupt occurrence.
353 */
354static irqreturn_t
355mpc85xx_rio_tx_handler(int irq, void *dev_instance)
356{
357 int osr;
358 struct rio_mport *port = (struct rio_mport *)dev_instance;
359
360 osr = in_be32((void *)&msg_regs->osr);
361
362 if (osr & RIO_MSG_OSR_TE) {
363 pr_info("RIO: outbound message transmission error\n");
364 out_be32((void *)&msg_regs->osr, RIO_MSG_OSR_TE);
365 goto out;
366 }
367
368 if (osr & RIO_MSG_OSR_QOI) {
369 pr_info("RIO: outbound message queue overflow\n");
370 out_be32((void *)&msg_regs->osr, RIO_MSG_OSR_QOI);
371 goto out;
372 }
373
374 if (osr & RIO_MSG_OSR_EOMI) {
375 u32 dqp = in_be32((void *)&msg_regs->odqdpar);
376 int slot = (dqp - msg_tx_ring.phys) >> 5;
377 port->outb_msg[0].mcback(port, msg_tx_ring.dev_id, -1, slot);
378
379 /* Ack the end-of-message interrupt */
380 out_be32((void *)&msg_regs->osr, RIO_MSG_OSR_EOMI);
381 }
382
383 out:
384 return IRQ_HANDLED;
385}
386
387/**
388 * rio_open_outb_mbox - Initialize MPC85xx outbound mailbox
389 * @mport: Master port implementing the outbound message unit
390 * @dev_id: Device specific pointer to pass on event
391 * @mbox: Mailbox to open
392 * @entries: Number of entries in the outbound mailbox ring
393 *
394 * Initializes buffer ring, request the outbound message interrupt,
395 * and enables the outbound message unit. Returns %0 on success and
396 * %-EINVAL or %-ENOMEM on failure.
397 */
398int rio_open_outb_mbox(struct rio_mport *mport, void *dev_id, int mbox, int entries)
399{
400 int i, j, rc = 0;
401
402 if ((entries < RIO_MIN_TX_RING_SIZE) ||
403 (entries > RIO_MAX_TX_RING_SIZE) || (!is_power_of_2(entries))) {
404 rc = -EINVAL;
405 goto out;
406 }
407
408 /* Initialize shadow copy ring */
409 msg_tx_ring.dev_id = dev_id;
410 msg_tx_ring.size = entries;
411
412 for (i = 0; i < msg_tx_ring.size; i++) {
413 if (!
414 (msg_tx_ring.virt_buffer[i] =
415 dma_alloc_coherent(NULL, RIO_MSG_BUFFER_SIZE,
416 &msg_tx_ring.phys_buffer[i],
417 GFP_KERNEL))) {
418 rc = -ENOMEM;
419 for (j = 0; j < msg_tx_ring.size; j++)
420 if (msg_tx_ring.virt_buffer[j])
421 dma_free_coherent(NULL,
422 RIO_MSG_BUFFER_SIZE,
423 msg_tx_ring.
424 virt_buffer[j],
425 msg_tx_ring.
426 phys_buffer[j]);
427 goto out;
428 }
429 }
430
431 /* Initialize outbound message descriptor ring */
432 if (!(msg_tx_ring.virt = dma_alloc_coherent(NULL,
433 msg_tx_ring.size *
434 RIO_MSG_DESC_SIZE,
435 &msg_tx_ring.phys,
436 GFP_KERNEL))) {
437 rc = -ENOMEM;
438 goto out_dma;
439 }
440 memset(msg_tx_ring.virt, 0, msg_tx_ring.size * RIO_MSG_DESC_SIZE);
441 msg_tx_ring.tx_slot = 0;
442
443 /* Point dequeue/enqueue pointers at first entry in ring */
444 out_be32((void *)&msg_regs->odqdpar, msg_tx_ring.phys);
445 out_be32((void *)&msg_regs->odqepar, msg_tx_ring.phys);
446
447 /* Configure for snooping */
448 out_be32((void *)&msg_regs->osar, 0x00000004);
449
450 /* Clear interrupt status */
451 out_be32((void *)&msg_regs->osr, 0x000000b3);
452
453 /* Hook up outbound message handler */
454 if ((rc =
455 request_irq(MPC85xx_IRQ_RIO_TX, mpc85xx_rio_tx_handler, 0,
456 "msg_tx", (void *)mport)) < 0)
457 goto out_irq;
458
459 /*
460 * Configure outbound message unit
461 * Snooping
462 * Interrupts (all enabled, except QEIE)
463 * Chaining mode
464 * Disable
465 */
466 out_be32((void *)&msg_regs->omr, 0x00100220);
467
468 /* Set number of entries */
469 out_be32((void *)&msg_regs->omr,
470 in_be32((void *)&msg_regs->omr) |
471 ((get_bitmask_order(entries) - 2) << 12));
472
473 /* Now enable the unit */
474 out_be32((void *)&msg_regs->omr, in_be32((void *)&msg_regs->omr) | 0x1);
475
476 out:
477 return rc;
478
479 out_irq:
480 dma_free_coherent(NULL, msg_tx_ring.size * RIO_MSG_DESC_SIZE,
481 msg_tx_ring.virt, msg_tx_ring.phys);
482
483 out_dma:
484 for (i = 0; i < msg_tx_ring.size; i++)
485 dma_free_coherent(NULL, RIO_MSG_BUFFER_SIZE,
486 msg_tx_ring.virt_buffer[i],
487 msg_tx_ring.phys_buffer[i]);
488
489 return rc;
490}
491
492/**
493 * rio_close_outb_mbox - Shut down MPC85xx outbound mailbox
494 * @mport: Master port implementing the outbound message unit
495 * @mbox: Mailbox to close
496 *
497 * Disables the outbound message unit, free all buffers, and
498 * frees the outbound message interrupt.
499 */
500void rio_close_outb_mbox(struct rio_mport *mport, int mbox)
501{
502 /* Disable inbound message unit */
503 out_be32((void *)&msg_regs->omr, 0);
504
505 /* Free ring */
506 dma_free_coherent(NULL, msg_tx_ring.size * RIO_MSG_DESC_SIZE,
507 msg_tx_ring.virt, msg_tx_ring.phys);
508
509 /* Free interrupt */
510 free_irq(MPC85xx_IRQ_RIO_TX, (void *)mport);
511}
512
513/**
514 * mpc85xx_rio_rx_handler - MPC85xx inbound message interrupt handler
515 * @irq: Linux interrupt number
516 * @dev_instance: Pointer to interrupt-specific data
517 *
518 * Handles inbound message interrupts. Executes a registered inbound
519 * mailbox event handler and acks the interrupt occurrence.
520 */
521static irqreturn_t
522mpc85xx_rio_rx_handler(int irq, void *dev_instance)
523{
524 int isr;
525 struct rio_mport *port = (struct rio_mport *)dev_instance;
526
527 isr = in_be32((void *)&msg_regs->isr);
528
529 if (isr & RIO_MSG_ISR_TE) {
530 pr_info("RIO: inbound message reception error\n");
531 out_be32((void *)&msg_regs->isr, RIO_MSG_ISR_TE);
532 goto out;
533 }
534
535 /* XXX Need to check/dispatch until queue empty */
536 if (isr & RIO_MSG_ISR_DIQI) {
537 /*
538 * We implement *only* mailbox 0, but can receive messages
539 * for any mailbox/letter to that mailbox destination. So,
540 * make the callback with an unknown/invalid mailbox number
541 * argument.
542 */
543 port->inb_msg[0].mcback(port, msg_rx_ring.dev_id, -1, -1);
544
545 /* Ack the queueing interrupt */
546 out_be32((void *)&msg_regs->isr, RIO_MSG_ISR_DIQI);
547 }
548
549 out:
550 return IRQ_HANDLED;
551}
552
553/**
554 * rio_open_inb_mbox - Initialize MPC85xx inbound mailbox
555 * @mport: Master port implementing the inbound message unit
556 * @dev_id: Device specific pointer to pass on event
557 * @mbox: Mailbox to open
558 * @entries: Number of entries in the inbound mailbox ring
559 *
560 * Initializes buffer ring, request the inbound message interrupt,
561 * and enables the inbound message unit. Returns %0 on success
562 * and %-EINVAL or %-ENOMEM on failure.
563 */
564int rio_open_inb_mbox(struct rio_mport *mport, void *dev_id, int mbox, int entries)
565{
566 int i, rc = 0;
567
568 if ((entries < RIO_MIN_RX_RING_SIZE) ||
569 (entries > RIO_MAX_RX_RING_SIZE) || (!is_power_of_2(entries))) {
570 rc = -EINVAL;
571 goto out;
572 }
573
574 /* Initialize client buffer ring */
575 msg_rx_ring.dev_id = dev_id;
576 msg_rx_ring.size = entries;
577 msg_rx_ring.rx_slot = 0;
578 for (i = 0; i < msg_rx_ring.size; i++)
579 msg_rx_ring.virt_buffer[i] = NULL;
580
581 /* Initialize inbound message ring */
582 if (!(msg_rx_ring.virt = dma_alloc_coherent(NULL,
583 msg_rx_ring.size *
584 RIO_MAX_MSG_SIZE,
585 &msg_rx_ring.phys,
586 GFP_KERNEL))) {
587 rc = -ENOMEM;
588 goto out;
589 }
590
591 /* Point dequeue/enqueue pointers at first entry in ring */
592 out_be32((void *)&msg_regs->ifqdpar, (u32) msg_rx_ring.phys);
593 out_be32((void *)&msg_regs->ifqepar, (u32) msg_rx_ring.phys);
594
595 /* Clear interrupt status */
596 out_be32((void *)&msg_regs->isr, 0x00000091);
597
598 /* Hook up inbound message handler */
599 if ((rc =
600 request_irq(MPC85xx_IRQ_RIO_RX, mpc85xx_rio_rx_handler, 0,
601 "msg_rx", (void *)mport)) < 0) {
602 dma_free_coherent(NULL, RIO_MSG_BUFFER_SIZE,
603 msg_tx_ring.virt_buffer[i],
604 msg_tx_ring.phys_buffer[i]);
605 goto out;
606 }
607
608 /*
609 * Configure inbound message unit:
610 * Snooping
611 * 4KB max message size
612 * Unmask all interrupt sources
613 * Disable
614 */
615 out_be32((void *)&msg_regs->imr, 0x001b0060);
616
617 /* Set number of queue entries */
618 out_be32((void *)&msg_regs->imr,
619 in_be32((void *)&msg_regs->imr) |
620 ((get_bitmask_order(entries) - 2) << 12));
621
622 /* Now enable the unit */
623 out_be32((void *)&msg_regs->imr, in_be32((void *)&msg_regs->imr) | 0x1);
624
625 out:
626 return rc;
627}
628
629/**
630 * rio_close_inb_mbox - Shut down MPC85xx inbound mailbox
631 * @mport: Master port implementing the inbound message unit
632 * @mbox: Mailbox to close
633 *
634 * Disables the inbound message unit, free all buffers, and
635 * frees the inbound message interrupt.
636 */
637void rio_close_inb_mbox(struct rio_mport *mport, int mbox)
638{
639 /* Disable inbound message unit */
640 out_be32((void *)&msg_regs->imr, 0);
641
642 /* Free ring */
643 dma_free_coherent(NULL, msg_rx_ring.size * RIO_MAX_MSG_SIZE,
644 msg_rx_ring.virt, msg_rx_ring.phys);
645
646 /* Free interrupt */
647 free_irq(MPC85xx_IRQ_RIO_RX, (void *)mport);
648}
649
650/**
651 * rio_hw_add_inb_buffer - Add buffer to the MPC85xx inbound message queue
652 * @mport: Master port implementing the inbound message unit
653 * @mbox: Inbound mailbox number
654 * @buf: Buffer to add to inbound queue
655 *
656 * Adds the @buf buffer to the MPC85xx inbound message queue. Returns
657 * %0 on success or %-EINVAL on failure.
658 */
659int rio_hw_add_inb_buffer(struct rio_mport *mport, int mbox, void *buf)
660{
661 int rc = 0;
662
663 pr_debug("RIO: rio_hw_add_inb_buffer(), msg_rx_ring.rx_slot %d\n",
664 msg_rx_ring.rx_slot);
665
666 if (msg_rx_ring.virt_buffer[msg_rx_ring.rx_slot]) {
667 printk(KERN_ERR
668 "RIO: error adding inbound buffer %d, buffer exists\n",
669 msg_rx_ring.rx_slot);
670 rc = -EINVAL;
671 goto out;
672 }
673
674 msg_rx_ring.virt_buffer[msg_rx_ring.rx_slot] = buf;
675 if (++msg_rx_ring.rx_slot == msg_rx_ring.size)
676 msg_rx_ring.rx_slot = 0;
677
678 out:
679 return rc;
680}
681
682EXPORT_SYMBOL_GPL(rio_hw_add_inb_buffer);
683
684/**
685 * rio_hw_get_inb_message - Fetch inbound message from the MPC85xx message unit
686 * @mport: Master port implementing the inbound message unit
687 * @mbox: Inbound mailbox number
688 *
689 * Gets the next available inbound message from the inbound message queue.
690 * A pointer to the message is returned on success or NULL on failure.
691 */
692void *rio_hw_get_inb_message(struct rio_mport *mport, int mbox)
693{
694 u32 imr;
695 u32 phys_buf, virt_buf;
696 void *buf = NULL;
697 int buf_idx;
698
699 phys_buf = in_be32((void *)&msg_regs->ifqdpar);
700
701 /* If no more messages, then bail out */
702 if (phys_buf == in_be32((void *)&msg_regs->ifqepar))
703 goto out2;
704
705 virt_buf = (u32) msg_rx_ring.virt + (phys_buf - msg_rx_ring.phys);
706 buf_idx = (phys_buf - msg_rx_ring.phys) / RIO_MAX_MSG_SIZE;
707 buf = msg_rx_ring.virt_buffer[buf_idx];
708
709 if (!buf) {
710 printk(KERN_ERR
711 "RIO: inbound message copy failed, no buffers\n");
712 goto out1;
713 }
714
715 /* Copy max message size, caller is expected to allocate that big */
716 memcpy(buf, (void *)virt_buf, RIO_MAX_MSG_SIZE);
717
718 /* Clear the available buffer */
719 msg_rx_ring.virt_buffer[buf_idx] = NULL;
720
721 out1:
722 imr = in_be32((void *)&msg_regs->imr);
723 out_be32((void *)&msg_regs->imr, imr | RIO_MSG_IMR_MI);
724
725 out2:
726 return buf;
727}
728
729EXPORT_SYMBOL_GPL(rio_hw_get_inb_message);
730
731/**
732 * mpc85xx_rio_dbell_handler - MPC85xx doorbell interrupt handler
733 * @irq: Linux interrupt number
734 * @dev_instance: Pointer to interrupt-specific data
735 *
736 * Handles doorbell interrupts. Parses a list of registered
737 * doorbell event handlers and executes a matching event handler.
738 */
739static irqreturn_t
740mpc85xx_rio_dbell_handler(int irq, void *dev_instance)
741{
742 int dsr;
743 struct rio_mport *port = (struct rio_mport *)dev_instance;
744
745 dsr = in_be32((void *)&msg_regs->dsr);
746
747 if (dsr & DOORBELL_DSR_TE) {
748 pr_info("RIO: doorbell reception error\n");
749 out_be32((void *)&msg_regs->dsr, DOORBELL_DSR_TE);
750 goto out;
751 }
752
753 if (dsr & DOORBELL_DSR_QFI) {
754 pr_info("RIO: doorbell queue full\n");
755 out_be32((void *)&msg_regs->dsr, DOORBELL_DSR_QFI);
756 goto out;
757 }
758
759 /* XXX Need to check/dispatch until queue empty */
760 if (dsr & DOORBELL_DSR_DIQI) {
761 u32 dmsg =
762 (u32) dbell_ring.virt +
763 (in_be32((void *)&msg_regs->dqdpar) & 0xfff);
764 u32 dmr;
765 struct rio_dbell *dbell;
766 int found = 0;
767
768 pr_debug
769 ("RIO: processing doorbell, sid %2.2x tid %2.2x info %4.4x\n",
770 DBELL_SID(dmsg), DBELL_TID(dmsg), DBELL_INF(dmsg));
771
772 list_for_each_entry(dbell, &port->dbells, node) {
773 if ((dbell->res->start <= DBELL_INF(dmsg)) &&
774 (dbell->res->end >= DBELL_INF(dmsg))) {
775 found = 1;
776 break;
777 }
778 }
779 if (found) {
780 dbell->dinb(port, dbell->dev_id, DBELL_SID(dmsg), DBELL_TID(dmsg),
781 DBELL_INF(dmsg));
782 } else {
783 pr_debug
784 ("RIO: spurious doorbell, sid %2.2x tid %2.2x info %4.4x\n",
785 DBELL_SID(dmsg), DBELL_TID(dmsg), DBELL_INF(dmsg));
786 }
787 dmr = in_be32((void *)&msg_regs->dmr);
788 out_be32((void *)&msg_regs->dmr, dmr | DOORBELL_DMR_DI);
789 out_be32((void *)&msg_regs->dsr, DOORBELL_DSR_DIQI);
790 }
791
792 out:
793 return IRQ_HANDLED;
794}
795
796/**
797 * mpc85xx_rio_doorbell_init - MPC85xx doorbell interface init
798 * @mport: Master port implementing the inbound doorbell unit
799 *
800 * Initializes doorbell unit hardware and inbound DMA buffer
801 * ring. Called from mpc85xx_rio_setup(). Returns %0 on success
802 * or %-ENOMEM on failure.
803 */
804static int mpc85xx_rio_doorbell_init(struct rio_mport *mport)
805{
806 int rc = 0;
807
808 /* Map outbound doorbell window immediately after maintenance window */
809 if (!(dbell_win =
810 (u32) ioremap(mport->iores.start + RIO_MAINT_WIN_SIZE,
811 RIO_DBELL_WIN_SIZE))) {
812 printk(KERN_ERR
813 "RIO: unable to map outbound doorbell window\n");
814 rc = -ENOMEM;
815 goto out;
816 }
817
818 /* Initialize inbound doorbells */
819 if (!(dbell_ring.virt = dma_alloc_coherent(NULL,
820 512 * DOORBELL_MESSAGE_SIZE,
821 &dbell_ring.phys,
822 GFP_KERNEL))) {
823 printk(KERN_ERR "RIO: unable allocate inbound doorbell ring\n");
824 rc = -ENOMEM;
825 iounmap((void *)dbell_win);
826 goto out;
827 }
828
829 /* Point dequeue/enqueue pointers at first entry in ring */
830 out_be32((void *)&msg_regs->dqdpar, (u32) dbell_ring.phys);
831 out_be32((void *)&msg_regs->dqepar, (u32) dbell_ring.phys);
832
833 /* Clear interrupt status */
834 out_be32((void *)&msg_regs->dsr, 0x00000091);
835
836 /* Hook up doorbell handler */
837 if ((rc =
838 request_irq(MPC85xx_IRQ_RIO_BELL, mpc85xx_rio_dbell_handler, 0,
839 "dbell_rx", (void *)mport) < 0)) {
840 iounmap((void *)dbell_win);
841 dma_free_coherent(NULL, 512 * DOORBELL_MESSAGE_SIZE,
842 dbell_ring.virt, dbell_ring.phys);
843 printk(KERN_ERR
844 "MPC85xx RIO: unable to request inbound doorbell irq");
845 goto out;
846 }
847
848 /* Configure doorbells for snooping, 512 entries, and enable */
849 out_be32((void *)&msg_regs->dmr, 0x00108161);
850
851 out:
852 return rc;
853}
854
855static char *cmdline = NULL;
856
857static int mpc85xx_rio_get_hdid(int index)
858{
859 /* XXX Need to parse multiple entries in some format */
860 if (!cmdline)
861 return -1;
862
863 return simple_strtol(cmdline, NULL, 0);
864}
865
866static int mpc85xx_rio_get_cmdline(char *s)
867{
868 if (!s)
869 return 0;
870
871 cmdline = s;
872 return 1;
873}
874
875__setup("riohdid=", mpc85xx_rio_get_cmdline);
876
877/**
878 * mpc85xx_rio_setup - Setup MPC85xx RapidIO interface
879 * @law_start: Starting physical address of RapidIO LAW
880 * @law_size: Size of RapidIO LAW
881 *
882 * Initializes MPC85xx RapidIO hardware interface, configures
883 * master port with system-specific info, and registers the
884 * master port with the RapidIO subsystem.
885 */
886void mpc85xx_rio_setup(int law_start, int law_size)
887{
888 struct rio_ops *ops;
889 struct rio_mport *port;
890
891 ops = kmalloc(sizeof(struct rio_ops), GFP_KERNEL);
892 ops->lcread = mpc85xx_local_config_read;
893 ops->lcwrite = mpc85xx_local_config_write;
894 ops->cread = mpc85xx_rio_config_read;
895 ops->cwrite = mpc85xx_rio_config_write;
896 ops->dsend = mpc85xx_rio_doorbell_send;
897
898 port = kmalloc(sizeof(struct rio_mport), GFP_KERNEL);
899 port->id = 0;
900 port->index = 0;
901 INIT_LIST_HEAD(&port->dbells);
902 port->iores.start = law_start;
903 port->iores.end = law_start + law_size;
904 port->iores.flags = IORESOURCE_MEM;
905
906 rio_init_dbell_res(&port->riores[RIO_DOORBELL_RESOURCE], 0, 0xffff);
907 rio_init_mbox_res(&port->riores[RIO_INB_MBOX_RESOURCE], 0, 0);
908 rio_init_mbox_res(&port->riores[RIO_OUTB_MBOX_RESOURCE], 0, 0);
909 strcpy(port->name, "RIO0 mport");
910
911 port->ops = ops;
912 port->host_deviceid = mpc85xx_rio_get_hdid(port->id);
913
914 rio_register_mport(port);
915
916 regs_win = (u32) ioremap(RIO_REGS_BASE, 0x20000);
917 atmu_regs = (struct rio_atmu_regs *)(regs_win + RIO_ATMU_REGS_OFFSET);
918 maint_atmu_regs = atmu_regs + 1;
919 dbell_atmu_regs = atmu_regs + 2;
920 msg_regs = (struct rio_msg_regs *)(regs_win + RIO_MSG_REGS_OFFSET);
921
922 /* Configure maintenance transaction window */
923 out_be32((void *)&maint_atmu_regs->rowbar, 0x000c0000);
924 out_be32((void *)&maint_atmu_regs->rowar, 0x80077015);
925
926 maint_win = (u32) ioremap(law_start, RIO_MAINT_WIN_SIZE);
927
928 /* Configure outbound doorbell window */
929 out_be32((void *)&dbell_atmu_regs->rowbar, 0x000c0400);
930 out_be32((void *)&dbell_atmu_regs->rowar, 0x8004200b);
931 mpc85xx_rio_doorbell_init(port);
932}
diff --git a/arch/powerpc/sysdev/fsl_rio.h b/arch/powerpc/sysdev/fsl_rio.h
new file mode 100644
index 000000000000..6d3ff30b1579
--- /dev/null
+++ b/arch/powerpc/sysdev/fsl_rio.h
@@ -0,0 +1,20 @@
1/*
2 * MPC85xx RapidIO definitions
3 *
4 * Copyright 2005 MontaVista Software, Inc.
5 * Matt Porter <mporter@kernel.crashing.org>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 */
12
13#ifndef __PPC_SYSLIB_PPC85XX_RIO_H
14#define __PPC_SYSLIB_PPC85XX_RIO_H
15
16#include <linux/init.h>
17
18extern void mpc85xx_rio_setup(int law_start, int law_size);
19
20#endif /* __PPC_SYSLIB_PPC85XX_RIO_H */
diff --git a/arch/powerpc/sysdev/fsl_soc.c b/arch/powerpc/sysdev/fsl_soc.c
index 217bcc2e8f86..f2c0988a03b8 100644
--- a/arch/powerpc/sysdev/fsl_soc.c
+++ b/arch/powerpc/sysdev/fsl_soc.c
@@ -24,6 +24,7 @@
24#include <linux/platform_device.h> 24#include <linux/platform_device.h>
25#include <linux/of_platform.h> 25#include <linux/of_platform.h>
26#include <linux/phy.h> 26#include <linux/phy.h>
27#include <linux/phy_fixed.h>
27#include <linux/spi/spi.h> 28#include <linux/spi/spi.h>
28#include <linux/fsl_devices.h> 29#include <linux/fsl_devices.h>
29#include <linux/fs_enet_pd.h> 30#include <linux/fs_enet_pd.h>
@@ -54,10 +55,18 @@ phys_addr_t get_immrbase(void)
54 soc = of_find_node_by_type(NULL, "soc"); 55 soc = of_find_node_by_type(NULL, "soc");
55 if (soc) { 56 if (soc) {
56 int size; 57 int size;
57 const void *prop = of_get_property(soc, "reg", &size); 58 u32 naddr;
59 const u32 *prop = of_get_property(soc, "#address-cells", &size);
58 60
61 if (prop && size == 4)
62 naddr = *prop;
63 else
64 naddr = 2;
65
66 prop = of_get_property(soc, "ranges", &size);
59 if (prop) 67 if (prop)
60 immrbase = of_translate_address(soc, prop); 68 immrbase = of_translate_address(soc, prop + naddr);
69
61 of_node_put(soc); 70 of_node_put(soc);
62 } 71 }
63 72
@@ -130,6 +139,37 @@ u32 get_baudrate(void)
130EXPORT_SYMBOL(get_baudrate); 139EXPORT_SYMBOL(get_baudrate);
131#endif /* CONFIG_CPM2 */ 140#endif /* CONFIG_CPM2 */
132 141
142#ifdef CONFIG_FIXED_PHY
143static int __init of_add_fixed_phys(void)
144{
145 int ret;
146 struct device_node *np;
147 u32 *fixed_link;
148 struct fixed_phy_status status = {};
149
150 for_each_node_by_name(np, "ethernet") {
151 fixed_link = (u32 *)of_get_property(np, "fixed-link", NULL);
152 if (!fixed_link)
153 continue;
154
155 status.link = 1;
156 status.duplex = fixed_link[1];
157 status.speed = fixed_link[2];
158 status.pause = fixed_link[3];
159 status.asym_pause = fixed_link[4];
160
161 ret = fixed_phy_add(PHY_POLL, fixed_link[0], &status);
162 if (ret) {
163 of_node_put(np);
164 return ret;
165 }
166 }
167
168 return 0;
169}
170arch_initcall(of_add_fixed_phys);
171#endif /* CONFIG_FIXED_PHY */
172
133static int __init gfar_mdio_of_init(void) 173static int __init gfar_mdio_of_init(void)
134{ 174{
135 struct device_node *np = NULL; 175 struct device_node *np = NULL;
@@ -198,7 +238,6 @@ static const char *gfar_tx_intr = "tx";
198static const char *gfar_rx_intr = "rx"; 238static const char *gfar_rx_intr = "rx";
199static const char *gfar_err_intr = "error"; 239static const char *gfar_err_intr = "error";
200 240
201
202static int __init gfar_of_init(void) 241static int __init gfar_of_init(void)
203{ 242{
204 struct device_node *np; 243 struct device_node *np;
@@ -282,29 +321,43 @@ static int __init gfar_of_init(void)
282 gfar_data.interface = PHY_INTERFACE_MODE_MII; 321 gfar_data.interface = PHY_INTERFACE_MODE_MII;
283 322
284 ph = of_get_property(np, "phy-handle", NULL); 323 ph = of_get_property(np, "phy-handle", NULL);
285 phy = of_find_node_by_phandle(*ph); 324 if (ph == NULL) {
325 u32 *fixed_link;
286 326
287 if (phy == NULL) { 327 fixed_link = (u32 *)of_get_property(np, "fixed-link",
288 ret = -ENODEV; 328 NULL);
289 goto unreg; 329 if (!fixed_link) {
290 } 330 ret = -ENODEV;
331 goto unreg;
332 }
291 333
292 mdio = of_get_parent(phy); 334 gfar_data.bus_id = 0;
335 gfar_data.phy_id = fixed_link[0];
336 } else {
337 phy = of_find_node_by_phandle(*ph);
338
339 if (phy == NULL) {
340 ret = -ENODEV;
341 goto unreg;
342 }
343
344 mdio = of_get_parent(phy);
345
346 id = of_get_property(phy, "reg", NULL);
347 ret = of_address_to_resource(mdio, 0, &res);
348 if (ret) {
349 of_node_put(phy);
350 of_node_put(mdio);
351 goto unreg;
352 }
353
354 gfar_data.phy_id = *id;
355 gfar_data.bus_id = res.start;
293 356
294 id = of_get_property(phy, "reg", NULL);
295 ret = of_address_to_resource(mdio, 0, &res);
296 if (ret) {
297 of_node_put(phy); 357 of_node_put(phy);
298 of_node_put(mdio); 358 of_node_put(mdio);
299 goto unreg;
300 } 359 }
301 360
302 gfar_data.phy_id = *id;
303 gfar_data.bus_id = res.start;
304
305 of_node_put(phy);
306 of_node_put(mdio);
307
308 ret = 361 ret =
309 platform_device_add_data(gfar_dev, &gfar_data, 362 platform_device_add_data(gfar_dev, &gfar_data,
310 sizeof(struct 363 sizeof(struct
@@ -531,14 +584,12 @@ static enum fsl_usb2_phy_modes determine_usb_phy(const char *phy_type)
531static int __init fsl_usb_of_init(void) 584static int __init fsl_usb_of_init(void)
532{ 585{
533 struct device_node *np; 586 struct device_node *np;
534 unsigned int i; 587 unsigned int i = 0;
535 struct platform_device *usb_dev_mph = NULL, *usb_dev_dr_host = NULL, 588 struct platform_device *usb_dev_mph = NULL, *usb_dev_dr_host = NULL,
536 *usb_dev_dr_client = NULL; 589 *usb_dev_dr_client = NULL;
537 int ret; 590 int ret;
538 591
539 for (np = NULL, i = 0; 592 for_each_compatible_node(np, NULL, "fsl-usb2-mph") {
540 (np = of_find_compatible_node(np, "usb", "fsl-usb2-mph")) != NULL;
541 i++) {
542 struct resource r[2]; 593 struct resource r[2];
543 struct fsl_usb2_platform_data usb_data; 594 struct fsl_usb2_platform_data usb_data;
544 const unsigned char *prop = NULL; 595 const unsigned char *prop = NULL;
@@ -581,11 +632,10 @@ static int __init fsl_usb_of_init(void)
581 fsl_usb2_platform_data)); 632 fsl_usb2_platform_data));
582 if (ret) 633 if (ret)
583 goto unreg_mph; 634 goto unreg_mph;
635 i++;
584 } 636 }
585 637
586 for (np = NULL; 638 for_each_compatible_node(np, NULL, "fsl-usb2-dr") {
587 (np = of_find_compatible_node(np, "usb", "fsl-usb2-dr")) != NULL;
588 i++) {
589 struct resource r[2]; 639 struct resource r[2];
590 struct fsl_usb2_platform_data usb_data; 640 struct fsl_usb2_platform_data usb_data;
591 const unsigned char *prop = NULL; 641 const unsigned char *prop = NULL;
@@ -657,6 +707,7 @@ static int __init fsl_usb_of_init(void)
657 fsl_usb2_platform_data)))) 707 fsl_usb2_platform_data))))
658 goto unreg_dr; 708 goto unreg_dr;
659 } 709 }
710 i++;
660 } 711 }
661 return 0; 712 return 0;
662 713
diff --git a/arch/powerpc/sysdev/ipic.c b/arch/powerpc/sysdev/ipic.c
index 7274750fd9c6..4c016da68426 100644
--- a/arch/powerpc/sysdev/ipic.c
+++ b/arch/powerpc/sysdev/ipic.c
@@ -48,6 +48,13 @@ static struct ipic_info ipic_info[] = {
48 .bit = 17, 48 .bit = 17,
49 .prio_mask = 1, 49 .prio_mask = 1,
50 }, 50 },
51 [3] = {
52 .mask = IPIC_SIMSR_H,
53 .prio = IPIC_SIPRR_C,
54 .force = IPIC_SIFCR_H,
55 .bit = 18,
56 .prio_mask = 2,
57 },
51 [4] = { 58 [4] = {
52 .mask = IPIC_SIMSR_H, 59 .mask = IPIC_SIMSR_H,
53 .prio = IPIC_SIPRR_C, 60 .prio = IPIC_SIPRR_C,
@@ -55,6 +62,34 @@ static struct ipic_info ipic_info[] = {
55 .bit = 19, 62 .bit = 19,
56 .prio_mask = 3, 63 .prio_mask = 3,
57 }, 64 },
65 [5] = {
66 .mask = IPIC_SIMSR_H,
67 .prio = IPIC_SIPRR_C,
68 .force = IPIC_SIFCR_H,
69 .bit = 20,
70 .prio_mask = 4,
71 },
72 [6] = {
73 .mask = IPIC_SIMSR_H,
74 .prio = IPIC_SIPRR_C,
75 .force = IPIC_SIFCR_H,
76 .bit = 21,
77 .prio_mask = 5,
78 },
79 [7] = {
80 .mask = IPIC_SIMSR_H,
81 .prio = IPIC_SIPRR_C,
82 .force = IPIC_SIFCR_H,
83 .bit = 22,
84 .prio_mask = 6,
85 },
86 [8] = {
87 .mask = IPIC_SIMSR_H,
88 .prio = IPIC_SIPRR_C,
89 .force = IPIC_SIFCR_H,
90 .bit = 23,
91 .prio_mask = 7,
92 },
58 [9] = { 93 [9] = {
59 .mask = IPIC_SIMSR_H, 94 .mask = IPIC_SIMSR_H,
60 .prio = IPIC_SIPRR_D, 95 .prio = IPIC_SIPRR_D,
@@ -223,6 +258,20 @@ static struct ipic_info ipic_info[] = {
223 .bit = 7, 258 .bit = 7,
224 .prio_mask = 7, 259 .prio_mask = 7,
225 }, 260 },
261 [40] = {
262 .mask = IPIC_SIMSR_H,
263 .prio = IPIC_SIPRR_B,
264 .force = IPIC_SIFCR_H,
265 .bit = 8,
266 .prio_mask = 0,
267 },
268 [41] = {
269 .mask = IPIC_SIMSR_H,
270 .prio = IPIC_SIPRR_B,
271 .force = IPIC_SIFCR_H,
272 .bit = 9,
273 .prio_mask = 1,
274 },
226 [42] = { 275 [42] = {
227 .mask = IPIC_SIMSR_H, 276 .mask = IPIC_SIMSR_H,
228 .prio = IPIC_SIPRR_B, 277 .prio = IPIC_SIPRR_B,
@@ -230,6 +279,13 @@ static struct ipic_info ipic_info[] = {
230 .bit = 10, 279 .bit = 10,
231 .prio_mask = 2, 280 .prio_mask = 2,
232 }, 281 },
282 [43] = {
283 .mask = IPIC_SIMSR_H,
284 .prio = IPIC_SIPRR_B,
285 .force = IPIC_SIFCR_H,
286 .bit = 11,
287 .prio_mask = 3,
288 },
233 [44] = { 289 [44] = {
234 .mask = IPIC_SIMSR_H, 290 .mask = IPIC_SIMSR_H,
235 .prio = IPIC_SIPRR_B, 291 .prio = IPIC_SIPRR_B,
@@ -387,6 +443,12 @@ static struct ipic_info ipic_info[] = {
387 .force = IPIC_SIFCR_L, 443 .force = IPIC_SIFCR_L,
388 .bit = 18, 444 .bit = 18,
389 }, 445 },
446 [83] = {
447 .mask = IPIC_SIMSR_L,
448 .prio = 0,
449 .force = IPIC_SIFCR_L,
450 .bit = 19,
451 },
390 [84] = { 452 [84] = {
391 .mask = IPIC_SIMSR_L, 453 .mask = IPIC_SIMSR_L,
392 .prio = 0, 454 .prio = 0,
diff --git a/arch/powerpc/sysdev/mpic.c b/arch/powerpc/sysdev/mpic.c
index f88ff09c4711..0da7069c7c62 100644
--- a/arch/powerpc/sysdev/mpic.c
+++ b/arch/powerpc/sysdev/mpic.c
@@ -267,7 +267,7 @@ static inline void _mpic_irq_write(struct mpic *mpic, unsigned int src_no,
267 */ 267 */
268 268
269 269
270static void _mpic_map_mmio(struct mpic *mpic, unsigned long phys_addr, 270static void _mpic_map_mmio(struct mpic *mpic, phys_addr_t phys_addr,
271 struct mpic_reg_bank *rb, unsigned int offset, 271 struct mpic_reg_bank *rb, unsigned int offset,
272 unsigned int size) 272 unsigned int size)
273{ 273{
@@ -287,7 +287,7 @@ static void _mpic_map_dcr(struct mpic *mpic, struct mpic_reg_bank *rb,
287 BUG_ON(!DCR_MAP_OK(rb->dhost)); 287 BUG_ON(!DCR_MAP_OK(rb->dhost));
288} 288}
289 289
290static inline void mpic_map(struct mpic *mpic, unsigned long phys_addr, 290static inline void mpic_map(struct mpic *mpic, phys_addr_t phys_addr,
291 struct mpic_reg_bank *rb, unsigned int offset, 291 struct mpic_reg_bank *rb, unsigned int offset,
292 unsigned int size) 292 unsigned int size)
293{ 293{
diff --git a/arch/powerpc/sysdev/qe_lib/Kconfig b/arch/powerpc/sysdev/qe_lib/Kconfig
index f611d344a126..adc66212a419 100644
--- a/arch/powerpc/sysdev/qe_lib/Kconfig
+++ b/arch/powerpc/sysdev/qe_lib/Kconfig
@@ -4,7 +4,7 @@
4 4
5config UCC_SLOW 5config UCC_SLOW
6 bool 6 bool
7 default n 7 default y if SERIAL_QE
8 help 8 help
9 This option provides qe_lib support to UCC slow 9 This option provides qe_lib support to UCC slow
10 protocols: UART, BISYNC, QMC 10 protocols: UART, BISYNC, QMC
diff --git a/arch/powerpc/sysdev/qe_lib/qe.c b/arch/powerpc/sysdev/qe_lib/qe.c
index 21e01061aca9..3925eae9b0f5 100644
--- a/arch/powerpc/sysdev/qe_lib/qe.c
+++ b/arch/powerpc/sysdev/qe_lib/qe.c
@@ -25,6 +25,7 @@
25#include <linux/module.h> 25#include <linux/module.h>
26#include <linux/delay.h> 26#include <linux/delay.h>
27#include <linux/ioport.h> 27#include <linux/ioport.h>
28#include <linux/crc32.h>
28#include <asm/irq.h> 29#include <asm/irq.h>
29#include <asm/page.h> 30#include <asm/page.h>
30#include <asm/pgtable.h> 31#include <asm/pgtable.h>
@@ -394,3 +395,249 @@ void *qe_muram_addr(unsigned long offset)
394 return (void *)&qe_immr->muram[offset]; 395 return (void *)&qe_immr->muram[offset];
395} 396}
396EXPORT_SYMBOL(qe_muram_addr); 397EXPORT_SYMBOL(qe_muram_addr);
398
399/* The maximum number of RISCs we support */
400#define MAX_QE_RISC 2
401
402/* Firmware information stored here for qe_get_firmware_info() */
403static struct qe_firmware_info qe_firmware_info;
404
405/*
406 * Set to 1 if QE firmware has been uploaded, and therefore
407 * qe_firmware_info contains valid data.
408 */
409static int qe_firmware_uploaded;
410
411/*
412 * Upload a QE microcode
413 *
414 * This function is a worker function for qe_upload_firmware(). It does
415 * the actual uploading of the microcode.
416 */
417static void qe_upload_microcode(const void *base,
418 const struct qe_microcode *ucode)
419{
420 const __be32 *code = base + be32_to_cpu(ucode->code_offset);
421 unsigned int i;
422
423 if (ucode->major || ucode->minor || ucode->revision)
424 printk(KERN_INFO "qe-firmware: "
425 "uploading microcode '%s' version %u.%u.%u\n",
426 ucode->id, ucode->major, ucode->minor, ucode->revision);
427 else
428 printk(KERN_INFO "qe-firmware: "
429 "uploading microcode '%s'\n", ucode->id);
430
431 /* Use auto-increment */
432 out_be32(&qe_immr->iram.iadd, be32_to_cpu(ucode->iram_offset) |
433 QE_IRAM_IADD_AIE | QE_IRAM_IADD_BADDR);
434
435 for (i = 0; i < be32_to_cpu(ucode->count); i++)
436 out_be32(&qe_immr->iram.idata, be32_to_cpu(code[i]));
437}
438
439/*
440 * Upload a microcode to the I-RAM at a specific address.
441 *
442 * See Documentation/powerpc/qe-firmware.txt for information on QE microcode
443 * uploading.
444 *
445 * Currently, only version 1 is supported, so the 'version' field must be
446 * set to 1.
447 *
448 * The SOC model and revision are not validated, they are only displayed for
449 * informational purposes.
450 *
451 * 'calc_size' is the calculated size, in bytes, of the firmware structure and
452 * all of the microcode structures, minus the CRC.
453 *
454 * 'length' is the size that the structure says it is, including the CRC.
455 */
456int qe_upload_firmware(const struct qe_firmware *firmware)
457{
458 unsigned int i;
459 unsigned int j;
460 u32 crc;
461 size_t calc_size = sizeof(struct qe_firmware);
462 size_t length;
463 const struct qe_header *hdr;
464
465 if (!firmware) {
466 printk(KERN_ERR "qe-firmware: invalid pointer\n");
467 return -EINVAL;
468 }
469
470 hdr = &firmware->header;
471 length = be32_to_cpu(hdr->length);
472
473 /* Check the magic */
474 if ((hdr->magic[0] != 'Q') || (hdr->magic[1] != 'E') ||
475 (hdr->magic[2] != 'F')) {
476 printk(KERN_ERR "qe-firmware: not a microcode\n");
477 return -EPERM;
478 }
479
480 /* Check the version */
481 if (hdr->version != 1) {
482 printk(KERN_ERR "qe-firmware: unsupported version\n");
483 return -EPERM;
484 }
485
486 /* Validate some of the fields */
487 if ((firmware->count < 1) || (firmware->count >= MAX_QE_RISC)) {
488 printk(KERN_ERR "qe-firmware: invalid data\n");
489 return -EINVAL;
490 }
491
492 /* Validate the length and check if there's a CRC */
493 calc_size += (firmware->count - 1) * sizeof(struct qe_microcode);
494
495 for (i = 0; i < firmware->count; i++)
496 /*
497 * For situations where the second RISC uses the same microcode
498 * as the first, the 'code_offset' and 'count' fields will be
499 * zero, so it's okay to add those.
500 */
501 calc_size += sizeof(__be32) *
502 be32_to_cpu(firmware->microcode[i].count);
503
504 /* Validate the length */
505 if (length != calc_size + sizeof(__be32)) {
506 printk(KERN_ERR "qe-firmware: invalid length\n");
507 return -EPERM;
508 }
509
510 /* Validate the CRC */
511 crc = be32_to_cpu(*(__be32 *)((void *)firmware + calc_size));
512 if (crc != crc32(0, firmware, calc_size)) {
513 printk(KERN_ERR "qe-firmware: firmware CRC is invalid\n");
514 return -EIO;
515 }
516
517 /*
518 * If the microcode calls for it, split the I-RAM.
519 */
520 if (!firmware->split)
521 setbits16(&qe_immr->cp.cercr, QE_CP_CERCR_CIR);
522
523 if (firmware->soc.model)
524 printk(KERN_INFO
525 "qe-firmware: firmware '%s' for %u V%u.%u\n",
526 firmware->id, be16_to_cpu(firmware->soc.model),
527 firmware->soc.major, firmware->soc.minor);
528 else
529 printk(KERN_INFO "qe-firmware: firmware '%s'\n",
530 firmware->id);
531
532 /*
533 * The QE only supports one microcode per RISC, so clear out all the
534 * saved microcode information and put in the new.
535 */
536 memset(&qe_firmware_info, 0, sizeof(qe_firmware_info));
537 strcpy(qe_firmware_info.id, firmware->id);
538 qe_firmware_info.extended_modes = firmware->extended_modes;
539 memcpy(qe_firmware_info.vtraps, firmware->vtraps,
540 sizeof(firmware->vtraps));
541
542 /* Loop through each microcode. */
543 for (i = 0; i < firmware->count; i++) {
544 const struct qe_microcode *ucode = &firmware->microcode[i];
545
546 /* Upload a microcode if it's present */
547 if (ucode->code_offset)
548 qe_upload_microcode(firmware, ucode);
549
550 /* Program the traps for this processor */
551 for (j = 0; j < 16; j++) {
552 u32 trap = be32_to_cpu(ucode->traps[j]);
553
554 if (trap)
555 out_be32(&qe_immr->rsp[i].tibcr[j], trap);
556 }
557
558 /* Enable traps */
559 out_be32(&qe_immr->rsp[i].eccr, be32_to_cpu(ucode->eccr));
560 }
561
562 qe_firmware_uploaded = 1;
563
564 return 0;
565}
566EXPORT_SYMBOL(qe_upload_firmware);
567
568/*
569 * Get info on the currently-loaded firmware
570 *
571 * This function also checks the device tree to see if the boot loader has
572 * uploaded a firmware already.
573 */
574struct qe_firmware_info *qe_get_firmware_info(void)
575{
576 static int initialized;
577 struct property *prop;
578 struct device_node *qe;
579 struct device_node *fw = NULL;
580 const char *sprop;
581 unsigned int i;
582
583 /*
584 * If we haven't checked yet, and a driver hasn't uploaded a firmware
585 * yet, then check the device tree for information.
586 */
587 if (initialized || qe_firmware_uploaded)
588 return NULL;
589
590 initialized = 1;
591
592 /*
593 * Newer device trees have an "fsl,qe" compatible property for the QE
594 * node, but we still need to support older device trees.
595 */
596 qe = of_find_compatible_node(NULL, NULL, "fsl,qe");
597 if (!qe) {
598 qe = of_find_node_by_type(NULL, "qe");
599 if (!qe)
600 return NULL;
601 }
602
603 /* Find the 'firmware' child node */
604 for_each_child_of_node(qe, fw) {
605 if (strcmp(fw->name, "firmware") == 0)
606 break;
607 }
608
609 of_node_put(qe);
610
611 /* Did we find the 'firmware' node? */
612 if (!fw)
613 return NULL;
614
615 qe_firmware_uploaded = 1;
616
617 /* Copy the data into qe_firmware_info*/
618 sprop = of_get_property(fw, "id", NULL);
619 if (sprop)
620 strncpy(qe_firmware_info.id, sprop,
621 sizeof(qe_firmware_info.id) - 1);
622
623 prop = of_find_property(fw, "extended-modes", NULL);
624 if (prop && (prop->length == sizeof(u64))) {
625 const u64 *iprop = prop->value;
626
627 qe_firmware_info.extended_modes = *iprop;
628 }
629
630 prop = of_find_property(fw, "virtual-traps", NULL);
631 if (prop && (prop->length == 32)) {
632 const u32 *iprop = prop->value;
633
634 for (i = 0; i < ARRAY_SIZE(qe_firmware_info.vtraps); i++)
635 qe_firmware_info.vtraps[i] = iprop[i];
636 }
637
638 of_node_put(fw);
639
640 return &qe_firmware_info;
641}
642EXPORT_SYMBOL(qe_get_firmware_info);
643
diff --git a/arch/powerpc/sysdev/qe_lib/ucc_slow.c b/arch/powerpc/sysdev/qe_lib/ucc_slow.c
index 0174b3aeef8f..b2870b208ddb 100644
--- a/arch/powerpc/sysdev/qe_lib/ucc_slow.c
+++ b/arch/powerpc/sysdev/qe_lib/ucc_slow.c
@@ -19,6 +19,7 @@
19#include <linux/stddef.h> 19#include <linux/stddef.h>
20#include <linux/interrupt.h> 20#include <linux/interrupt.h>
21#include <linux/err.h> 21#include <linux/err.h>
22#include <linux/module.h>
22 23
23#include <asm/io.h> 24#include <asm/io.h>
24#include <asm/immap_qe.h> 25#include <asm/immap_qe.h>
@@ -41,6 +42,7 @@ u32 ucc_slow_get_qe_cr_subblock(int uccs_num)
41 default: return QE_CR_SUBBLOCK_INVALID; 42 default: return QE_CR_SUBBLOCK_INVALID;
42 } 43 }
43} 44}
45EXPORT_SYMBOL(ucc_slow_get_qe_cr_subblock);
44 46
45void ucc_slow_poll_transmitter_now(struct ucc_slow_private * uccs) 47void ucc_slow_poll_transmitter_now(struct ucc_slow_private * uccs)
46{ 48{
@@ -56,6 +58,7 @@ void ucc_slow_graceful_stop_tx(struct ucc_slow_private * uccs)
56 qe_issue_cmd(QE_GRACEFUL_STOP_TX, id, 58 qe_issue_cmd(QE_GRACEFUL_STOP_TX, id,
57 QE_CR_PROTOCOL_UNSPECIFIED, 0); 59 QE_CR_PROTOCOL_UNSPECIFIED, 0);
58} 60}
61EXPORT_SYMBOL(ucc_slow_graceful_stop_tx);
59 62
60void ucc_slow_stop_tx(struct ucc_slow_private * uccs) 63void ucc_slow_stop_tx(struct ucc_slow_private * uccs)
61{ 64{
@@ -65,6 +68,7 @@ void ucc_slow_stop_tx(struct ucc_slow_private * uccs)
65 id = ucc_slow_get_qe_cr_subblock(us_info->ucc_num); 68 id = ucc_slow_get_qe_cr_subblock(us_info->ucc_num);
66 qe_issue_cmd(QE_STOP_TX, id, QE_CR_PROTOCOL_UNSPECIFIED, 0); 69 qe_issue_cmd(QE_STOP_TX, id, QE_CR_PROTOCOL_UNSPECIFIED, 0);
67} 70}
71EXPORT_SYMBOL(ucc_slow_stop_tx);
68 72
69void ucc_slow_restart_tx(struct ucc_slow_private * uccs) 73void ucc_slow_restart_tx(struct ucc_slow_private * uccs)
70{ 74{
@@ -74,6 +78,7 @@ void ucc_slow_restart_tx(struct ucc_slow_private * uccs)
74 id = ucc_slow_get_qe_cr_subblock(us_info->ucc_num); 78 id = ucc_slow_get_qe_cr_subblock(us_info->ucc_num);
75 qe_issue_cmd(QE_RESTART_TX, id, QE_CR_PROTOCOL_UNSPECIFIED, 0); 79 qe_issue_cmd(QE_RESTART_TX, id, QE_CR_PROTOCOL_UNSPECIFIED, 0);
76} 80}
81EXPORT_SYMBOL(ucc_slow_restart_tx);
77 82
78void ucc_slow_enable(struct ucc_slow_private * uccs, enum comm_dir mode) 83void ucc_slow_enable(struct ucc_slow_private * uccs, enum comm_dir mode)
79{ 84{
@@ -94,6 +99,7 @@ void ucc_slow_enable(struct ucc_slow_private * uccs, enum comm_dir mode)
94 } 99 }
95 out_be32(&us_regs->gumr_l, gumr_l); 100 out_be32(&us_regs->gumr_l, gumr_l);
96} 101}
102EXPORT_SYMBOL(ucc_slow_enable);
97 103
98void ucc_slow_disable(struct ucc_slow_private * uccs, enum comm_dir mode) 104void ucc_slow_disable(struct ucc_slow_private * uccs, enum comm_dir mode)
99{ 105{
@@ -114,6 +120,7 @@ void ucc_slow_disable(struct ucc_slow_private * uccs, enum comm_dir mode)
114 } 120 }
115 out_be32(&us_regs->gumr_l, gumr_l); 121 out_be32(&us_regs->gumr_l, gumr_l);
116} 122}
123EXPORT_SYMBOL(ucc_slow_disable);
117 124
118/* Initialize the UCC for Slow operations 125/* Initialize the UCC for Slow operations
119 * 126 *
@@ -347,6 +354,7 @@ int ucc_slow_init(struct ucc_slow_info * us_info, struct ucc_slow_private ** ucc
347 *uccs_ret = uccs; 354 *uccs_ret = uccs;
348 return 0; 355 return 0;
349} 356}
357EXPORT_SYMBOL(ucc_slow_init);
350 358
351void ucc_slow_free(struct ucc_slow_private * uccs) 359void ucc_slow_free(struct ucc_slow_private * uccs)
352{ 360{
@@ -366,5 +374,5 @@ void ucc_slow_free(struct ucc_slow_private * uccs)
366 374
367 kfree(uccs); 375 kfree(uccs);
368} 376}
369 377EXPORT_SYMBOL(ucc_slow_free);
370 378
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-30 09:23:44 -0500