1 files changed, 242 insertions, 0 deletions

diff --git a/arch/powerpc/sysdev/ppc4xx_pci.h b/arch/powerpc/sysdev/ppc4xx_pci.h
index 8b787bfdc8a5..43e51ce5c477 100644
--- a/arch/powerpc/sysdev/ppc4xx_pci.h
+++ b/arch/powerpc/sysdev/ppc4xx_pci.h
@@ -121,5 +121,247 @@
 #define PCIL0_PTM2MS            0x38
 #define PCIL0_PTM2LA            0x3c
 
+/*
+ * 4xx PCIe bridge register definitions
+ */
+
+/* DCR offsets */
+#define DCRO_PEGPL_CFGBAH               0x00
+#define DCRO_PEGPL_CFGBAL               0x01
+#define DCRO_PEGPL_CFGMSK               0x02
+#define DCRO_PEGPL_MSGBAH               0x03
+#define DCRO_PEGPL_MSGBAL               0x04
+#define DCRO_PEGPL_MSGMSK               0x05
+#define DCRO_PEGPL_OMR1BAH              0x06
+#define DCRO_PEGPL_OMR1BAL              0x07
+#define DCRO_PEGPL_OMR1MSKH             0x08
+#define DCRO_PEGPL_OMR1MSKL             0x09
+#define DCRO_PEGPL_OMR2BAH              0x0a
+#define DCRO_PEGPL_OMR2BAL              0x0b
+#define DCRO_PEGPL_OMR2MSKH             0x0c
+#define DCRO_PEGPL_OMR2MSKL             0x0d
+#define DCRO_PEGPL_OMR3BAH              0x0e
+#define DCRO_PEGPL_OMR3BAL              0x0f
+#define DCRO_PEGPL_OMR3MSKH             0x10
+#define DCRO_PEGPL_OMR3MSKL             0x11
+#define DCRO_PEGPL_REGBAH               0x12
+#define DCRO_PEGPL_REGBAL               0x13
+#define DCRO_PEGPL_REGMSK               0x14
+#define DCRO_PEGPL_SPECIAL              0x15
+#define DCRO_PEGPL_CFG                  0x16
+#define DCRO_PEGPL_ESR                  0x17
+#define DCRO_PEGPL_EARH                 0x18
+#define DCRO_PEGPL_EARL                 0x19
+#define DCRO_PEGPL_EATR                 0x1a
+
+/* DMER mask */
+#define GPL_DMER_MASK_DISA      0x02000000
+
+/*
+ * System DCRs (SDRs)
+ */
+#define PESDR0_PLLLCT1                  0x03a0
+#define PESDR0_PLLLCT2                  0x03a1
+#define PESDR0_PLLLCT3                  0x03a2
+
+/*
+ * 440SPe additional DCRs
+ */
+#define PESDR0_440SPE_UTLSET1           0x0300
+#define PESDR0_440SPE_UTLSET2           0x0301
+#define PESDR0_440SPE_DLPSET            0x0302
+#define PESDR0_440SPE_LOOP              0x0303
+#define PESDR0_440SPE_RCSSET            0x0304
+#define PESDR0_440SPE_RCSSTS            0x0305
+#define PESDR0_440SPE_HSSL0SET1         0x0306
+#define PESDR0_440SPE_HSSL0SET2         0x0307
+#define PESDR0_440SPE_HSSL0STS          0x0308
+#define PESDR0_440SPE_HSSL1SET1         0x0309
+#define PESDR0_440SPE_HSSL1SET2         0x030a
+#define PESDR0_440SPE_HSSL1STS          0x030b
+#define PESDR0_440SPE_HSSL2SET1         0x030c
+#define PESDR0_440SPE_HSSL2SET2         0x030d
+#define PESDR0_440SPE_HSSL2STS          0x030e
+#define PESDR0_440SPE_HSSL3SET1         0x030f
+#define PESDR0_440SPE_HSSL3SET2         0x0310
+#define PESDR0_440SPE_HSSL3STS          0x0311
+#define PESDR0_440SPE_HSSL4SET1         0x0312
+#define PESDR0_440SPE_HSSL4SET2         0x0313
+#define PESDR0_440SPE_HSSL4STS          0x0314
+#define PESDR0_440SPE_HSSL5SET1         0x0315
+#define PESDR0_440SPE_HSSL5SET2         0x0316
+#define PESDR0_440SPE_HSSL5STS          0x0317
+#define PESDR0_440SPE_HSSL6SET1         0x0318
+#define PESDR0_440SPE_HSSL6SET2         0x0319
+#define PESDR0_440SPE_HSSL6STS          0x031a
+#define PESDR0_440SPE_HSSL7SET1         0x031b
+#define PESDR0_440SPE_HSSL7SET2         0x031c
+#define PESDR0_440SPE_HSSL7STS          0x031d
+#define PESDR0_440SPE_HSSCTLSET         0x031e
+#define PESDR0_440SPE_LANE_ABCD         0x031f
+#define PESDR0_440SPE_LANE_EFGH         0x0320
+
+#define PESDR1_440SPE_UTLSET1           0x0340
+#define PESDR1_440SPE_UTLSET2           0x0341
+#define PESDR1_440SPE_DLPSET            0x0342
+#define PESDR1_440SPE_LOOP              0x0343
+#define PESDR1_440SPE_RCSSET            0x0344
+#define PESDR1_440SPE_RCSSTS            0x0345
+#define PESDR1_440SPE_HSSL0SET1         0x0346
+#define PESDR1_440SPE_HSSL0SET2         0x0347
+#define PESDR1_440SPE_HSSL0STS          0x0348
+#define PESDR1_440SPE_HSSL1SET1         0x0349
+#define PESDR1_440SPE_HSSL1SET2         0x034a
+#define PESDR1_440SPE_HSSL1STS          0x034b
+#define PESDR1_440SPE_HSSL2SET1         0x034c
+#define PESDR1_440SPE_HSSL2SET2         0x034d
+#define PESDR1_440SPE_HSSL2STS          0x034e
+#define PESDR1_440SPE_HSSL3SET1         0x034f
+#define PESDR1_440SPE_HSSL3SET2         0x0350
+#define PESDR1_440SPE_HSSL3STS          0x0351
+#define PESDR1_440SPE_HSSCTLSET         0x0352
+#define PESDR1_440SPE_LANE_ABCD         0x0353
+
+#define PESDR2_440SPE_UTLSET1           0x0370
+#define PESDR2_440SPE_UTLSET2           0x0371
+#define PESDR2_440SPE_DLPSET            0x0372
+#define PESDR2_440SPE_LOOP              0x0373
+#define PESDR2_440SPE_RCSSET            0x0374
+#define PESDR2_440SPE_RCSSTS            0x0375
+#define PESDR2_440SPE_HSSL0SET1         0x0376
+#define PESDR2_440SPE_HSSL0SET2         0x0377
+#define PESDR2_440SPE_HSSL0STS          0x0378
+#define PESDR2_440SPE_HSSL1SET1         0x0379
+#define PESDR2_440SPE_HSSL1SET2         0x037a
+#define PESDR2_440SPE_HSSL1STS          0x037b
+#define PESDR2_440SPE_HSSL2SET1         0x037c
+#define PESDR2_440SPE_HSSL2SET2         0x037d
+#define PESDR2_440SPE_HSSL2STS          0x037e
+#define PESDR2_440SPE_HSSL3SET1         0x037f
+#define PESDR2_440SPE_HSSL3SET2         0x0380
+#define PESDR2_440SPE_HSSL3STS          0x0381
+#define PESDR2_440SPE_HSSCTLSET         0x0382
+#define PESDR2_440SPE_LANE_ABCD         0x0383
+
+/*
+ * 405EX additional DCRs
+ */
+#define PESDR0_405EX_UTLSET1            0x0400
+#define PESDR0_405EX_UTLSET2            0x0401
+#define PESDR0_405EX_DLPSET             0x0402
+#define PESDR0_405EX_LOOP               0x0403
+#define PESDR0_405EX_RCSSET             0x0404
+#define PESDR0_405EX_RCSSTS             0x0405
+#define PESDR0_405EX_PHYSET1            0x0406
+#define PESDR0_405EX_PHYSET2            0x0407
+#define PESDR0_405EX_BIST               0x0408
+#define PESDR0_405EX_LPB                0x040B
+#define PESDR0_405EX_PHYSTA             0x040C
+
+#define PESDR1_405EX_UTLSET1            0x0440
+#define PESDR1_405EX_UTLSET2            0x0441
+#define PESDR1_405EX_DLPSET             0x0442
+#define PESDR1_405EX_LOOP               0x0443
+#define PESDR1_405EX_RCSSET             0x0444
+#define PESDR1_405EX_RCSSTS             0x0445
+#define PESDR1_405EX_PHYSET1            0x0446
+#define PESDR1_405EX_PHYSET2            0x0447
+#define PESDR1_405EX_BIST               0x0448
+#define PESDR1_405EX_LPB                0x044B
+#define PESDR1_405EX_PHYSTA             0x044C
+
+/*
+ * Of the above, some are common offsets from the base
+ */
+#define PESDRn_UTLSET1                  0x00
+#define PESDRn_UTLSET2                  0x01
+#define PESDRn_DLPSET                   0x02
+#define PESDRn_LOOP                     0x03
+#define PESDRn_RCSSET                   0x04
+#define PESDRn_RCSSTS                   0x05
+
+/* 440spe only */
+#define PESDRn_440SPE_HSSL0SET1         0x06
+#define PESDRn_440SPE_HSSL0SET2         0x07
+#define PESDRn_440SPE_HSSL0STS          0x08
+#define PESDRn_440SPE_HSSL1SET1         0x09
+#define PESDRn_440SPE_HSSL1SET2         0x0a
+#define PESDRn_440SPE_HSSL1STS          0x0b
+#define PESDRn_440SPE_HSSL2SET1         0x0c
+#define PESDRn_440SPE_HSSL2SET2         0x0d
+#define PESDRn_440SPE_HSSL2STS          0x0e
+#define PESDRn_440SPE_HSSL3SET1         0x0f
+#define PESDRn_440SPE_HSSL3SET2         0x10
+#define PESDRn_440SPE_HSSL3STS          0x11
+
+/* 440spe port 0 only */
+#define PESDRn_440SPE_HSSL4SET1         0x12
+#define PESDRn_440SPE_HSSL4SET2         0x13
+#define PESDRn_440SPE_HSSL4STS          0x14
+#define PESDRn_440SPE_HSSL5SET1         0x15
+#define PESDRn_440SPE_HSSL5SET2         0x16
+#define PESDRn_440SPE_HSSL5STS          0x17
+#define PESDRn_440SPE_HSSL6SET1         0x18
+#define PESDRn_440SPE_HSSL6SET2         0x19
+#define PESDRn_440SPE_HSSL6STS          0x1a
+#define PESDRn_440SPE_HSSL7SET1         0x1b
+#define PESDRn_440SPE_HSSL7SET2         0x1c
+#define PESDRn_440SPE_HSSL7STS          0x1d
+
+/* 405ex only */
+#define PESDRn_405EX_PHYSET1            0x06
+#define PESDRn_405EX_PHYSET2            0x07
+#define PESDRn_405EX_PHYSTA             0x0c
+
+/*
+ * UTL register offsets
+ */
+#define PEUTL_PBCTL             0x00
+#define PEUTL_PBBSZ             0x20
+#define PEUTL_OPDBSZ            0x68
+#define PEUTL_IPHBSZ            0x70
+#define PEUTL_IPDBSZ            0x78
+#define PEUTL_OUTTR             0x90
+#define PEUTL_INTR              0x98
+#define PEUTL_PCTL              0xa0
+#define PEUTL_RCSTA             0xB0
+#define PEUTL_RCIRQEN           0xb8
+
+/*
+ * Config space register offsets
+ */
+#define PECFG_BAR0LMPA          0x210
+#define PECFG_BAR0HMPA          0x214
+#define PECFG_BAR1MPA           0x218
+#define PECFG_BAR2LMPA          0x220
+#define PECFG_BAR2HMPA          0x224
+
+#define PECFG_PIMEN             0x33c
+#define PECFG_PIM0LAL           0x340
+#define PECFG_PIM0LAH           0x344
+#define PECFG_PIM1LAL           0x348
+#define PECFG_PIM1LAH           0x34c
+#define PECFG_PIM01SAL          0x350
+#define PECFG_PIM01SAH          0x354
+
+#define PECFG_POM0LAL           0x380
+#define PECFG_POM0LAH           0x384
+#define PECFG_POM1LAL           0x388
+#define PECFG_POM1LAH           0x38c
+#define PECFG_POM2LAL           0x390
+#define PECFG_POM2LAH           0x394
+
+
+enum
+{
+        PTYPE_ENDPOINT          = 0x0,
+        PTYPE_LEGACY_ENDPOINT   = 0x1,
+        PTYPE_ROOT_PORT         = 0x4,
+
+        LNKW_X1                 = 0x1,
+        LNKW_X4                 = 0x4,
+        LNKW_X8                 = 0x8
+};
+
 
 #endif /* __PPC4XX_PCI_H__ */