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Diffstat (limited to 'arch/powerpc/sysdev/ppc4xx_pci.c')
-rw-r--r--arch/powerpc/sysdev/ppc4xx_pci.c32
1 files changed, 19 insertions, 13 deletions
diff --git a/arch/powerpc/sysdev/ppc4xx_pci.c b/arch/powerpc/sysdev/ppc4xx_pci.c
index e8a76d9539db..d3e4d61030b5 100644
--- a/arch/powerpc/sysdev/ppc4xx_pci.c
+++ b/arch/powerpc/sysdev/ppc4xx_pci.c
@@ -30,14 +30,12 @@
30#include <asm/machdep.h> 30#include <asm/machdep.h>
31#include <asm/dcr.h> 31#include <asm/dcr.h>
32#include <asm/dcr-regs.h> 32#include <asm/dcr-regs.h>
33#include <mm/mmu_decl.h>
33 34
34#include "ppc4xx_pci.h" 35#include "ppc4xx_pci.h"
35 36
36static int dma_offset_set; 37static int dma_offset_set;
37 38
38/* Move that to a useable header */
39extern unsigned long total_memory;
40
41#define U64_TO_U32_LOW(val) ((u32)((val) & 0x00000000ffffffffULL)) 39#define U64_TO_U32_LOW(val) ((u32)((val) & 0x00000000ffffffffULL))
42#define U64_TO_U32_HIGH(val) ((u32)((val) >> 32)) 40#define U64_TO_U32_HIGH(val) ((u32)((val) >> 32))
43 41
@@ -102,7 +100,8 @@ static int __init ppc4xx_parse_dma_ranges(struct pci_controller *hose,
102 100
103 /* Default */ 101 /* Default */
104 res->start = 0; 102 res->start = 0;
105 res->end = size = 0x80000000; 103 size = 0x80000000;
104 res->end = size - 1;
106 res->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH; 105 res->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH;
107 106
108 /* Get dma-ranges property */ 107 /* Get dma-ranges property */
@@ -163,13 +162,13 @@ static int __init ppc4xx_parse_dma_ranges(struct pci_controller *hose,
163 */ 162 */
164 if (size < total_memory) { 163 if (size < total_memory) {
165 printk(KERN_ERR "%s: dma-ranges too small " 164 printk(KERN_ERR "%s: dma-ranges too small "
166 "(size=%llx total_memory=%lx)\n", 165 "(size=%llx total_memory=%llx)\n",
167 hose->dn->full_name, size, total_memory); 166 hose->dn->full_name, size, (u64)total_memory);
168 return -ENXIO; 167 return -ENXIO;
169 } 168 }
170 169
171 /* Check we are a power of 2 size and that base is a multiple of size*/ 170 /* Check we are a power of 2 size and that base is a multiple of size*/
172 if (!is_power_of_2(size) || 171 if ((size & (size - 1)) != 0 ||
173 (res->start & (size - 1)) != 0) { 172 (res->start & (size - 1)) != 0) {
174 printk(KERN_ERR "%s: dma-ranges unaligned\n", 173 printk(KERN_ERR "%s: dma-ranges unaligned\n",
175 hose->dn->full_name); 174 hose->dn->full_name);
@@ -273,9 +272,16 @@ static void __init ppc4xx_probe_pci_bridge(struct device_node *np)
273 const int *bus_range; 272 const int *bus_range;
274 int primary = 0; 273 int primary = 0;
275 274
275 /* Check if device is enabled */
276 if (!of_device_is_available(np)) {
277 printk(KERN_INFO "%s: Port disabled via device-tree\n",
278 np->full_name);
279 return;
280 }
281
276 /* Fetch config space registers address */ 282 /* Fetch config space registers address */
277 if (of_address_to_resource(np, 0, &rsrc_cfg)) { 283 if (of_address_to_resource(np, 0, &rsrc_cfg)) {
278 printk(KERN_ERR "%s:Can't get PCI config register base !", 284 printk(KERN_ERR "%s: Can't get PCI config register base !",
279 np->full_name); 285 np->full_name);
280 return; 286 return;
281 } 287 }
@@ -806,7 +812,7 @@ static int ppc460ex_pciex_init_port_hw(struct ppc4xx_pciex_port *port)
806 switch (port->index) { 812 switch (port->index) {
807 case 0: 813 case 0:
808 mtdcri(SDR0, PESDR0_460EX_L0CDRCTL, 0x00003230); 814 mtdcri(SDR0, PESDR0_460EX_L0CDRCTL, 0x00003230);
809 mtdcri(SDR0, PESDR0_460EX_L0DRV, 0x00000136); 815 mtdcri(SDR0, PESDR0_460EX_L0DRV, 0x00000130);
810 mtdcri(SDR0, PESDR0_460EX_L0CLK, 0x00000006); 816 mtdcri(SDR0, PESDR0_460EX_L0CLK, 0x00000006);
811 817
812 mtdcri(SDR0, PESDR0_460EX_PHY_CTL_RST,0x10000000); 818 mtdcri(SDR0, PESDR0_460EX_PHY_CTL_RST,0x10000000);
@@ -817,10 +823,10 @@ static int ppc460ex_pciex_init_port_hw(struct ppc4xx_pciex_port *port)
817 mtdcri(SDR0, PESDR1_460EX_L1CDRCTL, 0x00003230); 823 mtdcri(SDR0, PESDR1_460EX_L1CDRCTL, 0x00003230);
818 mtdcri(SDR0, PESDR1_460EX_L2CDRCTL, 0x00003230); 824 mtdcri(SDR0, PESDR1_460EX_L2CDRCTL, 0x00003230);
819 mtdcri(SDR0, PESDR1_460EX_L3CDRCTL, 0x00003230); 825 mtdcri(SDR0, PESDR1_460EX_L3CDRCTL, 0x00003230);
820 mtdcri(SDR0, PESDR1_460EX_L0DRV, 0x00000136); 826 mtdcri(SDR0, PESDR1_460EX_L0DRV, 0x00000130);
821 mtdcri(SDR0, PESDR1_460EX_L1DRV, 0x00000136); 827 mtdcri(SDR0, PESDR1_460EX_L1DRV, 0x00000130);
822 mtdcri(SDR0, PESDR1_460EX_L2DRV, 0x00000136); 828 mtdcri(SDR0, PESDR1_460EX_L2DRV, 0x00000130);
823 mtdcri(SDR0, PESDR1_460EX_L3DRV, 0x00000136); 829 mtdcri(SDR0, PESDR1_460EX_L3DRV, 0x00000130);
824 mtdcri(SDR0, PESDR1_460EX_L0CLK, 0x00000006); 830 mtdcri(SDR0, PESDR1_460EX_L0CLK, 0x00000006);
825 mtdcri(SDR0, PESDR1_460EX_L1CLK, 0x00000006); 831 mtdcri(SDR0, PESDR1_460EX_L1CLK, 0x00000006);
826 mtdcri(SDR0, PESDR1_460EX_L2CLK, 0x00000006); 832 mtdcri(SDR0, PESDR1_460EX_L2CLK, 0x00000006);