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path: root/arch/powerpc/sysdev/ppc4xx_pci.c
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Diffstat (limited to 'arch/powerpc/sysdev/ppc4xx_pci.c')
-rw-r--r--arch/powerpc/sysdev/ppc4xx_pci.c48
1 files changed, 25 insertions, 23 deletions
diff --git a/arch/powerpc/sysdev/ppc4xx_pci.c b/arch/powerpc/sysdev/ppc4xx_pci.c
index fb368dfde5d4..d3e4d61030b5 100644
--- a/arch/powerpc/sysdev/ppc4xx_pci.c
+++ b/arch/powerpc/sysdev/ppc4xx_pci.c
@@ -30,24 +30,19 @@
30#include <asm/machdep.h> 30#include <asm/machdep.h>
31#include <asm/dcr.h> 31#include <asm/dcr.h>
32#include <asm/dcr-regs.h> 32#include <asm/dcr-regs.h>
33#include <mm/mmu_decl.h>
33 34
34#include "ppc4xx_pci.h" 35#include "ppc4xx_pci.h"
35 36
36static int dma_offset_set; 37static int dma_offset_set;
37 38
38/* Move that to a useable header */
39extern unsigned long total_memory;
40
41#define U64_TO_U32_LOW(val) ((u32)((val) & 0x00000000ffffffffULL)) 39#define U64_TO_U32_LOW(val) ((u32)((val) & 0x00000000ffffffffULL))
42#define U64_TO_U32_HIGH(val) ((u32)((val) >> 32)) 40#define U64_TO_U32_HIGH(val) ((u32)((val) >> 32))
43 41
44#ifdef CONFIG_RESOURCES_64BIT 42#define RES_TO_U32_LOW(val) \
45#define RES_TO_U32_LOW(val) U64_TO_U32_LOW(val) 43 ((sizeof(resource_size_t) > sizeof(u32)) ? U64_TO_U32_LOW(val) : (val))
46#define RES_TO_U32_HIGH(val) U64_TO_U32_HIGH(val) 44#define RES_TO_U32_HIGH(val) \
47#else 45 ((sizeof(resource_size_t) > sizeof(u32)) ? U64_TO_U32_HIGH(val) : (0))
48#define RES_TO_U32_LOW(val) (val)
49#define RES_TO_U32_HIGH(val) (0)
50#endif
51 46
52static inline int ppc440spe_revA(void) 47static inline int ppc440spe_revA(void)
53{ 48{
@@ -105,7 +100,8 @@ static int __init ppc4xx_parse_dma_ranges(struct pci_controller *hose,
105 100
106 /* Default */ 101 /* Default */
107 res->start = 0; 102 res->start = 0;
108 res->end = size = 0x80000000; 103 size = 0x80000000;
104 res->end = size - 1;
109 res->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH; 105 res->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH;
110 106
111 /* Get dma-ranges property */ 107 /* Get dma-ranges property */
@@ -145,12 +141,11 @@ static int __init ppc4xx_parse_dma_ranges(struct pci_controller *hose,
145 141
146 /* Use that */ 142 /* Use that */
147 res->start = pci_addr; 143 res->start = pci_addr;
148#ifndef CONFIG_RESOURCES_64BIT
149 /* Beware of 32 bits resources */ 144 /* Beware of 32 bits resources */
150 if ((pci_addr + size) > 0x100000000ull) 145 if (sizeof(resource_size_t) == sizeof(u32) &&
146 (pci_addr + size) > 0x100000000ull)
151 res->end = 0xffffffff; 147 res->end = 0xffffffff;
152 else 148 else
153#endif
154 res->end = res->start + size - 1; 149 res->end = res->start + size - 1;
155 break; 150 break;
156 } 151 }
@@ -167,13 +162,13 @@ static int __init ppc4xx_parse_dma_ranges(struct pci_controller *hose,
167 */ 162 */
168 if (size < total_memory) { 163 if (size < total_memory) {
169 printk(KERN_ERR "%s: dma-ranges too small " 164 printk(KERN_ERR "%s: dma-ranges too small "
170 "(size=%llx total_memory=%lx)\n", 165 "(size=%llx total_memory=%llx)\n",
171 hose->dn->full_name, size, total_memory); 166 hose->dn->full_name, size, (u64)total_memory);
172 return -ENXIO; 167 return -ENXIO;
173 } 168 }
174 169
175 /* Check we are a power of 2 size and that base is a multiple of size*/ 170 /* Check we are a power of 2 size and that base is a multiple of size*/
176 if (!is_power_of_2(size) || 171 if ((size & (size - 1)) != 0 ||
177 (res->start & (size - 1)) != 0) { 172 (res->start & (size - 1)) != 0) {
178 printk(KERN_ERR "%s: dma-ranges unaligned\n", 173 printk(KERN_ERR "%s: dma-ranges unaligned\n",
179 hose->dn->full_name); 174 hose->dn->full_name);
@@ -277,9 +272,16 @@ static void __init ppc4xx_probe_pci_bridge(struct device_node *np)
277 const int *bus_range; 272 const int *bus_range;
278 int primary = 0; 273 int primary = 0;
279 274
275 /* Check if device is enabled */
276 if (!of_device_is_available(np)) {
277 printk(KERN_INFO "%s: Port disabled via device-tree\n",
278 np->full_name);
279 return;
280 }
281
280 /* Fetch config space registers address */ 282 /* Fetch config space registers address */
281 if (of_address_to_resource(np, 0, &rsrc_cfg)) { 283 if (of_address_to_resource(np, 0, &rsrc_cfg)) {
282 printk(KERN_ERR "%s:Can't get PCI config register base !", 284 printk(KERN_ERR "%s: Can't get PCI config register base !",
283 np->full_name); 285 np->full_name);
284 return; 286 return;
285 } 287 }
@@ -810,7 +812,7 @@ static int ppc460ex_pciex_init_port_hw(struct ppc4xx_pciex_port *port)
810 switch (port->index) { 812 switch (port->index) {
811 case 0: 813 case 0:
812 mtdcri(SDR0, PESDR0_460EX_L0CDRCTL, 0x00003230); 814 mtdcri(SDR0, PESDR0_460EX_L0CDRCTL, 0x00003230);
813 mtdcri(SDR0, PESDR0_460EX_L0DRV, 0x00000136); 815 mtdcri(SDR0, PESDR0_460EX_L0DRV, 0x00000130);
814 mtdcri(SDR0, PESDR0_460EX_L0CLK, 0x00000006); 816 mtdcri(SDR0, PESDR0_460EX_L0CLK, 0x00000006);
815 817
816 mtdcri(SDR0, PESDR0_460EX_PHY_CTL_RST,0x10000000); 818 mtdcri(SDR0, PESDR0_460EX_PHY_CTL_RST,0x10000000);
@@ -821,10 +823,10 @@ static int ppc460ex_pciex_init_port_hw(struct ppc4xx_pciex_port *port)
821 mtdcri(SDR0, PESDR1_460EX_L1CDRCTL, 0x00003230); 823 mtdcri(SDR0, PESDR1_460EX_L1CDRCTL, 0x00003230);
822 mtdcri(SDR0, PESDR1_460EX_L2CDRCTL, 0x00003230); 824 mtdcri(SDR0, PESDR1_460EX_L2CDRCTL, 0x00003230);
823 mtdcri(SDR0, PESDR1_460EX_L3CDRCTL, 0x00003230); 825 mtdcri(SDR0, PESDR1_460EX_L3CDRCTL, 0x00003230);
824 mtdcri(SDR0, PESDR1_460EX_L0DRV, 0x00000136); 826 mtdcri(SDR0, PESDR1_460EX_L0DRV, 0x00000130);
825 mtdcri(SDR0, PESDR1_460EX_L1DRV, 0x00000136); 827 mtdcri(SDR0, PESDR1_460EX_L1DRV, 0x00000130);
826 mtdcri(SDR0, PESDR1_460EX_L2DRV, 0x00000136); 828 mtdcri(SDR0, PESDR1_460EX_L2DRV, 0x00000130);
827 mtdcri(SDR0, PESDR1_460EX_L3DRV, 0x00000136); 829 mtdcri(SDR0, PESDR1_460EX_L3DRV, 0x00000130);
828 mtdcri(SDR0, PESDR1_460EX_L0CLK, 0x00000006); 830 mtdcri(SDR0, PESDR1_460EX_L0CLK, 0x00000006);
829 mtdcri(SDR0, PESDR1_460EX_L1CLK, 0x00000006); 831 mtdcri(SDR0, PESDR1_460EX_L1CLK, 0x00000006);
830 mtdcri(SDR0, PESDR1_460EX_L2CLK, 0x00000006); 832 mtdcri(SDR0, PESDR1_460EX_L2CLK, 0x00000006);