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-rw-r--r--arch/powerpc/sysdev/mpic.c223
1 files changed, 164 insertions, 59 deletions
diff --git a/arch/powerpc/sysdev/mpic.c b/arch/powerpc/sysdev/mpic.c
index 6e0281afa6c3..b604926401f5 100644
--- a/arch/powerpc/sysdev/mpic.c
+++ b/arch/powerpc/sysdev/mpic.c
@@ -54,6 +54,94 @@ static DEFINE_SPINLOCK(mpic_lock);
54#endif 54#endif
55#endif 55#endif
56 56
57#ifdef CONFIG_MPIC_WEIRD
58static u32 mpic_infos[][MPIC_IDX_END] = {
59 [0] = { /* Original OpenPIC compatible MPIC */
60 MPIC_GREG_BASE,
61 MPIC_GREG_FEATURE_0,
62 MPIC_GREG_GLOBAL_CONF_0,
63 MPIC_GREG_VENDOR_ID,
64 MPIC_GREG_IPI_VECTOR_PRI_0,
65 MPIC_GREG_IPI_STRIDE,
66 MPIC_GREG_SPURIOUS,
67 MPIC_GREG_TIMER_FREQ,
68
69 MPIC_TIMER_BASE,
70 MPIC_TIMER_STRIDE,
71 MPIC_TIMER_CURRENT_CNT,
72 MPIC_TIMER_BASE_CNT,
73 MPIC_TIMER_VECTOR_PRI,
74 MPIC_TIMER_DESTINATION,
75
76 MPIC_CPU_BASE,
77 MPIC_CPU_STRIDE,
78 MPIC_CPU_IPI_DISPATCH_0,
79 MPIC_CPU_IPI_DISPATCH_STRIDE,
80 MPIC_CPU_CURRENT_TASK_PRI,
81 MPIC_CPU_WHOAMI,
82 MPIC_CPU_INTACK,
83 MPIC_CPU_EOI,
84
85 MPIC_IRQ_BASE,
86 MPIC_IRQ_STRIDE,
87 MPIC_IRQ_VECTOR_PRI,
88 MPIC_VECPRI_VECTOR_MASK,
89 MPIC_VECPRI_POLARITY_POSITIVE,
90 MPIC_VECPRI_POLARITY_NEGATIVE,
91 MPIC_VECPRI_SENSE_LEVEL,
92 MPIC_VECPRI_SENSE_EDGE,
93 MPIC_VECPRI_POLARITY_MASK,
94 MPIC_VECPRI_SENSE_MASK,
95 MPIC_IRQ_DESTINATION
96 },
97 [1] = { /* Tsi108/109 PIC */
98 TSI108_GREG_BASE,
99 TSI108_GREG_FEATURE_0,
100 TSI108_GREG_GLOBAL_CONF_0,
101 TSI108_GREG_VENDOR_ID,
102 TSI108_GREG_IPI_VECTOR_PRI_0,
103 TSI108_GREG_IPI_STRIDE,
104 TSI108_GREG_SPURIOUS,
105 TSI108_GREG_TIMER_FREQ,
106
107 TSI108_TIMER_BASE,
108 TSI108_TIMER_STRIDE,
109 TSI108_TIMER_CURRENT_CNT,
110 TSI108_TIMER_BASE_CNT,
111 TSI108_TIMER_VECTOR_PRI,
112 TSI108_TIMER_DESTINATION,
113
114 TSI108_CPU_BASE,
115 TSI108_CPU_STRIDE,
116 TSI108_CPU_IPI_DISPATCH_0,
117 TSI108_CPU_IPI_DISPATCH_STRIDE,
118 TSI108_CPU_CURRENT_TASK_PRI,
119 TSI108_CPU_WHOAMI,
120 TSI108_CPU_INTACK,
121 TSI108_CPU_EOI,
122
123 TSI108_IRQ_BASE,
124 TSI108_IRQ_STRIDE,
125 TSI108_IRQ_VECTOR_PRI,
126 TSI108_VECPRI_VECTOR_MASK,
127 TSI108_VECPRI_POLARITY_POSITIVE,
128 TSI108_VECPRI_POLARITY_NEGATIVE,
129 TSI108_VECPRI_SENSE_LEVEL,
130 TSI108_VECPRI_SENSE_EDGE,
131 TSI108_VECPRI_POLARITY_MASK,
132 TSI108_VECPRI_SENSE_MASK,
133 TSI108_IRQ_DESTINATION
134 },
135};
136
137#define MPIC_INFO(name) mpic->hw_set[MPIC_IDX_##name]
138
139#else /* CONFIG_MPIC_WEIRD */
140
141#define MPIC_INFO(name) MPIC_##name
142
143#endif /* CONFIG_MPIC_WEIRD */
144
57/* 145/*
58 * Register accessor functions 146 * Register accessor functions
59 */ 147 */
@@ -80,7 +168,8 @@ static inline void _mpic_write(unsigned int be, volatile u32 __iomem *base,
80static inline u32 _mpic_ipi_read(struct mpic *mpic, unsigned int ipi) 168static inline u32 _mpic_ipi_read(struct mpic *mpic, unsigned int ipi)
81{ 169{
82 unsigned int be = (mpic->flags & MPIC_BIG_ENDIAN) != 0; 170 unsigned int be = (mpic->flags & MPIC_BIG_ENDIAN) != 0;
83 unsigned int offset = MPIC_GREG_IPI_VECTOR_PRI_0 + (ipi * 0x10); 171 unsigned int offset = MPIC_INFO(GREG_IPI_VECTOR_PRI_0) +
172 (ipi * MPIC_INFO(GREG_IPI_STRIDE));
84 173
85 if (mpic->flags & MPIC_BROKEN_IPI) 174 if (mpic->flags & MPIC_BROKEN_IPI)
86 be = !be; 175 be = !be;
@@ -89,7 +178,8 @@ static inline u32 _mpic_ipi_read(struct mpic *mpic, unsigned int ipi)
89 178
90static inline void _mpic_ipi_write(struct mpic *mpic, unsigned int ipi, u32 value) 179static inline void _mpic_ipi_write(struct mpic *mpic, unsigned int ipi, u32 value)
91{ 180{
92 unsigned int offset = MPIC_GREG_IPI_VECTOR_PRI_0 + (ipi * 0x10); 181 unsigned int offset = MPIC_INFO(GREG_IPI_VECTOR_PRI_0) +
182 (ipi * MPIC_INFO(GREG_IPI_STRIDE));
93 183
94 _mpic_write(mpic->flags & MPIC_BIG_ENDIAN, mpic->gregs, offset, value); 184 _mpic_write(mpic->flags & MPIC_BIG_ENDIAN, mpic->gregs, offset, value);
95} 185}
@@ -120,7 +210,7 @@ static inline u32 _mpic_irq_read(struct mpic *mpic, unsigned int src_no, unsigne
120 unsigned int idx = src_no & mpic->isu_mask; 210 unsigned int idx = src_no & mpic->isu_mask;
121 211
122 return _mpic_read(mpic->flags & MPIC_BIG_ENDIAN, mpic->isus[isu], 212 return _mpic_read(mpic->flags & MPIC_BIG_ENDIAN, mpic->isus[isu],
123 reg + (idx * MPIC_IRQ_STRIDE)); 213 reg + (idx * MPIC_INFO(IRQ_STRIDE)));
124} 214}
125 215
126static inline void _mpic_irq_write(struct mpic *mpic, unsigned int src_no, 216static inline void _mpic_irq_write(struct mpic *mpic, unsigned int src_no,
@@ -130,7 +220,7 @@ static inline void _mpic_irq_write(struct mpic *mpic, unsigned int src_no,
130 unsigned int idx = src_no & mpic->isu_mask; 220 unsigned int idx = src_no & mpic->isu_mask;
131 221
132 _mpic_write(mpic->flags & MPIC_BIG_ENDIAN, mpic->isus[isu], 222 _mpic_write(mpic->flags & MPIC_BIG_ENDIAN, mpic->isus[isu],
133 reg + (idx * MPIC_IRQ_STRIDE), value); 223 reg + (idx * MPIC_INFO(IRQ_STRIDE)), value);
134} 224}
135 225
136#define mpic_read(b,r) _mpic_read(mpic->flags & MPIC_BIG_ENDIAN,(b),(r)) 226#define mpic_read(b,r) _mpic_read(mpic->flags & MPIC_BIG_ENDIAN,(b),(r))
@@ -156,8 +246,8 @@ static void __init mpic_test_broken_ipi(struct mpic *mpic)
156{ 246{
157 u32 r; 247 u32 r;
158 248
159 mpic_write(mpic->gregs, MPIC_GREG_IPI_VECTOR_PRI_0, MPIC_VECPRI_MASK); 249 mpic_write(mpic->gregs, MPIC_INFO(GREG_IPI_VECTOR_PRI_0), MPIC_VECPRI_MASK);
160 r = mpic_read(mpic->gregs, MPIC_GREG_IPI_VECTOR_PRI_0); 250 r = mpic_read(mpic->gregs, MPIC_INFO(GREG_IPI_VECTOR_PRI_0));
161 251
162 if (r == le32_to_cpu(MPIC_VECPRI_MASK)) { 252 if (r == le32_to_cpu(MPIC_VECPRI_MASK)) {
163 printk(KERN_INFO "mpic: Detected reversed IPI registers\n"); 253 printk(KERN_INFO "mpic: Detected reversed IPI registers\n");
@@ -394,8 +484,8 @@ static inline struct mpic * mpic_from_irq(unsigned int irq)
394/* Send an EOI */ 484/* Send an EOI */
395static inline void mpic_eoi(struct mpic *mpic) 485static inline void mpic_eoi(struct mpic *mpic)
396{ 486{
397 mpic_cpu_write(MPIC_CPU_EOI, 0); 487 mpic_cpu_write(MPIC_INFO(CPU_EOI), 0);
398 (void)mpic_cpu_read(MPIC_CPU_WHOAMI); 488 (void)mpic_cpu_read(MPIC_INFO(CPU_WHOAMI));
399} 489}
400 490
401#ifdef CONFIG_SMP 491#ifdef CONFIG_SMP
@@ -419,8 +509,8 @@ static void mpic_unmask_irq(unsigned int irq)
419 509
420 DBG("%p: %s: enable_irq: %d (src %d)\n", mpic, mpic->name, irq, src); 510 DBG("%p: %s: enable_irq: %d (src %d)\n", mpic, mpic->name, irq, src);
421 511
422 mpic_irq_write(src, MPIC_IRQ_VECTOR_PRI, 512 mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI),
423 mpic_irq_read(src, MPIC_IRQ_VECTOR_PRI) & 513 mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) &
424 ~MPIC_VECPRI_MASK); 514 ~MPIC_VECPRI_MASK);
425 /* make sure mask gets to controller before we return to user */ 515 /* make sure mask gets to controller before we return to user */
426 do { 516 do {
@@ -428,7 +518,7 @@ static void mpic_unmask_irq(unsigned int irq)
428 printk(KERN_ERR "mpic_enable_irq timeout\n"); 518 printk(KERN_ERR "mpic_enable_irq timeout\n");
429 break; 519 break;
430 } 520 }
431 } while(mpic_irq_read(src, MPIC_IRQ_VECTOR_PRI) & MPIC_VECPRI_MASK); 521 } while(mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) & MPIC_VECPRI_MASK);
432} 522}
433 523
434static void mpic_mask_irq(unsigned int irq) 524static void mpic_mask_irq(unsigned int irq)
@@ -439,8 +529,8 @@ static void mpic_mask_irq(unsigned int irq)
439 529
440 DBG("%s: disable_irq: %d (src %d)\n", mpic->name, irq, src); 530 DBG("%s: disable_irq: %d (src %d)\n", mpic->name, irq, src);
441 531
442 mpic_irq_write(src, MPIC_IRQ_VECTOR_PRI, 532 mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI),
443 mpic_irq_read(src, MPIC_IRQ_VECTOR_PRI) | 533 mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) |
444 MPIC_VECPRI_MASK); 534 MPIC_VECPRI_MASK);
445 535
446 /* make sure mask gets to controller before we return to user */ 536 /* make sure mask gets to controller before we return to user */
@@ -449,7 +539,7 @@ static void mpic_mask_irq(unsigned int irq)
449 printk(KERN_ERR "mpic_enable_irq timeout\n"); 539 printk(KERN_ERR "mpic_enable_irq timeout\n");
450 break; 540 break;
451 } 541 }
452 } while(!(mpic_irq_read(src, MPIC_IRQ_VECTOR_PRI) & MPIC_VECPRI_MASK)); 542 } while(!(mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) & MPIC_VECPRI_MASK));
453} 543}
454 544
455static void mpic_end_irq(unsigned int irq) 545static void mpic_end_irq(unsigned int irq)
@@ -560,24 +650,28 @@ static void mpic_set_affinity(unsigned int irq, cpumask_t cpumask)
560 650
561 cpus_and(tmp, cpumask, cpu_online_map); 651 cpus_and(tmp, cpumask, cpu_online_map);
562 652
563 mpic_irq_write(src, MPIC_IRQ_DESTINATION, 653 mpic_irq_write(src, MPIC_INFO(IRQ_DESTINATION),
564 mpic_physmask(cpus_addr(tmp)[0])); 654 mpic_physmask(cpus_addr(tmp)[0]));
565} 655}
566 656
567static unsigned int mpic_type_to_vecpri(unsigned int type) 657static unsigned int mpic_type_to_vecpri(struct mpic *mpic, unsigned int type)
568{ 658{
569 /* Now convert sense value */ 659 /* Now convert sense value */
570 switch(type & IRQ_TYPE_SENSE_MASK) { 660 switch(type & IRQ_TYPE_SENSE_MASK) {
571 case IRQ_TYPE_EDGE_RISING: 661 case IRQ_TYPE_EDGE_RISING:
572 return MPIC_VECPRI_SENSE_EDGE | MPIC_VECPRI_POLARITY_POSITIVE; 662 return MPIC_INFO(VECPRI_SENSE_EDGE) |
663 MPIC_INFO(VECPRI_POLARITY_POSITIVE);
573 case IRQ_TYPE_EDGE_FALLING: 664 case IRQ_TYPE_EDGE_FALLING:
574 case IRQ_TYPE_EDGE_BOTH: 665 case IRQ_TYPE_EDGE_BOTH:
575 return MPIC_VECPRI_SENSE_EDGE | MPIC_VECPRI_POLARITY_NEGATIVE; 666 return MPIC_INFO(VECPRI_SENSE_EDGE) |
667 MPIC_INFO(VECPRI_POLARITY_NEGATIVE);
576 case IRQ_TYPE_LEVEL_HIGH: 668 case IRQ_TYPE_LEVEL_HIGH:
577 return MPIC_VECPRI_SENSE_LEVEL | MPIC_VECPRI_POLARITY_POSITIVE; 669 return MPIC_INFO(VECPRI_SENSE_LEVEL) |
670 MPIC_INFO(VECPRI_POLARITY_POSITIVE);
578 case IRQ_TYPE_LEVEL_LOW: 671 case IRQ_TYPE_LEVEL_LOW:
579 default: 672 default:
580 return MPIC_VECPRI_SENSE_LEVEL | MPIC_VECPRI_POLARITY_NEGATIVE; 673 return MPIC_INFO(VECPRI_SENSE_LEVEL) |
674 MPIC_INFO(VECPRI_POLARITY_NEGATIVE);
581 } 675 }
582} 676}
583 677
@@ -609,13 +703,14 @@ static int mpic_set_irq_type(unsigned int virq, unsigned int flow_type)
609 vecpri = MPIC_VECPRI_POLARITY_POSITIVE | 703 vecpri = MPIC_VECPRI_POLARITY_POSITIVE |
610 MPIC_VECPRI_SENSE_EDGE; 704 MPIC_VECPRI_SENSE_EDGE;
611 else 705 else
612 vecpri = mpic_type_to_vecpri(flow_type); 706 vecpri = mpic_type_to_vecpri(mpic, flow_type);
613 707
614 vold = mpic_irq_read(src, MPIC_IRQ_VECTOR_PRI); 708 vold = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI));
615 vnew = vold & ~(MPIC_VECPRI_POLARITY_MASK | MPIC_VECPRI_SENSE_MASK); 709 vnew = vold & ~(MPIC_INFO(VECPRI_POLARITY_MASK) |
710 MPIC_INFO(VECPRI_SENSE_MASK));
616 vnew |= vecpri; 711 vnew |= vecpri;
617 if (vold != vnew) 712 if (vold != vnew)
618 mpic_irq_write(src, MPIC_IRQ_VECTOR_PRI, vnew); 713 mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI), vnew);
619 714
620 return 0; 715 return 0;
621} 716}
@@ -798,17 +893,22 @@ struct mpic * __init mpic_alloc(struct device_node *node,
798 mpic->irq_count = irq_count; 893 mpic->irq_count = irq_count;
799 mpic->num_sources = 0; /* so far */ 894 mpic->num_sources = 0; /* so far */
800 895
896#ifdef CONFIG_MPIC_WEIRD
897 mpic->hw_set = mpic_infos[MPIC_GET_REGSET(flags)];
898#endif
899
801 /* Map the global registers */ 900 /* Map the global registers */
802 mpic->gregs = ioremap(phys_addr + MPIC_GREG_BASE, 0x1000); 901 mpic->gregs = ioremap(phys_addr + MPIC_INFO(GREG_BASE), 0x1000);
803 mpic->tmregs = mpic->gregs + ((MPIC_TIMER_BASE - MPIC_GREG_BASE) >> 2); 902 mpic->tmregs = mpic->gregs +
903 ((MPIC_INFO(TIMER_BASE) - MPIC_INFO(GREG_BASE)) >> 2);
804 BUG_ON(mpic->gregs == NULL); 904 BUG_ON(mpic->gregs == NULL);
805 905
806 /* Reset */ 906 /* Reset */
807 if (flags & MPIC_WANTS_RESET) { 907 if (flags & MPIC_WANTS_RESET) {
808 mpic_write(mpic->gregs, MPIC_GREG_GLOBAL_CONF_0, 908 mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
809 mpic_read(mpic->gregs, MPIC_GREG_GLOBAL_CONF_0) 909 mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
810 | MPIC_GREG_GCONF_RESET); 910 | MPIC_GREG_GCONF_RESET);
811 while( mpic_read(mpic->gregs, MPIC_GREG_GLOBAL_CONF_0) 911 while( mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
812 & MPIC_GREG_GCONF_RESET) 912 & MPIC_GREG_GCONF_RESET)
813 mb(); 913 mb();
814 } 914 }
@@ -817,7 +917,7 @@ struct mpic * __init mpic_alloc(struct device_node *node,
817 * MPICs, num sources as well. On ISU MPICs, sources are counted 917 * MPICs, num sources as well. On ISU MPICs, sources are counted
818 * as ISUs are added 918 * as ISUs are added
819 */ 919 */
820 reg = mpic_read(mpic->gregs, MPIC_GREG_FEATURE_0); 920 reg = mpic_read(mpic->gregs, MPIC_INFO(GREG_FEATURE_0));
821 mpic->num_cpus = ((reg & MPIC_GREG_FEATURE_LAST_CPU_MASK) 921 mpic->num_cpus = ((reg & MPIC_GREG_FEATURE_LAST_CPU_MASK)
822 >> MPIC_GREG_FEATURE_LAST_CPU_SHIFT) + 1; 922 >> MPIC_GREG_FEATURE_LAST_CPU_SHIFT) + 1;
823 if (isu_size == 0) 923 if (isu_size == 0)
@@ -826,16 +926,16 @@ struct mpic * __init mpic_alloc(struct device_node *node,
826 926
827 /* Map the per-CPU registers */ 927 /* Map the per-CPU registers */
828 for (i = 0; i < mpic->num_cpus; i++) { 928 for (i = 0; i < mpic->num_cpus; i++) {
829 mpic->cpuregs[i] = ioremap(phys_addr + MPIC_CPU_BASE + 929 mpic->cpuregs[i] = ioremap(phys_addr + MPIC_INFO(CPU_BASE) +
830 i * MPIC_CPU_STRIDE, 0x1000); 930 i * MPIC_INFO(CPU_STRIDE), 0x1000);
831 BUG_ON(mpic->cpuregs[i] == NULL); 931 BUG_ON(mpic->cpuregs[i] == NULL);
832 } 932 }
833 933
834 /* Initialize main ISU if none provided */ 934 /* Initialize main ISU if none provided */
835 if (mpic->isu_size == 0) { 935 if (mpic->isu_size == 0) {
836 mpic->isu_size = mpic->num_sources; 936 mpic->isu_size = mpic->num_sources;
837 mpic->isus[0] = ioremap(phys_addr + MPIC_IRQ_BASE, 937 mpic->isus[0] = ioremap(phys_addr + MPIC_INFO(IRQ_BASE),
838 MPIC_IRQ_STRIDE * mpic->isu_size); 938 MPIC_INFO(IRQ_STRIDE) * mpic->isu_size);
839 BUG_ON(mpic->isus[0] == NULL); 939 BUG_ON(mpic->isus[0] == NULL);
840 } 940 }
841 mpic->isu_shift = 1 + __ilog2(mpic->isu_size - 1); 941 mpic->isu_shift = 1 + __ilog2(mpic->isu_size - 1);
@@ -879,7 +979,8 @@ void __init mpic_assign_isu(struct mpic *mpic, unsigned int isu_num,
879 979
880 BUG_ON(isu_num >= MPIC_MAX_ISU); 980 BUG_ON(isu_num >= MPIC_MAX_ISU);
881 981
882 mpic->isus[isu_num] = ioremap(phys_addr, MPIC_IRQ_STRIDE * mpic->isu_size); 982 mpic->isus[isu_num] = ioremap(phys_addr,
983 MPIC_INFO(IRQ_STRIDE) * mpic->isu_size);
883 if ((isu_first + mpic->isu_size) > mpic->num_sources) 984 if ((isu_first + mpic->isu_size) > mpic->num_sources)
884 mpic->num_sources = isu_first + mpic->isu_size; 985 mpic->num_sources = isu_first + mpic->isu_size;
885} 986}
@@ -904,14 +1005,16 @@ void __init mpic_init(struct mpic *mpic)
904 printk(KERN_INFO "mpic: Initializing for %d sources\n", mpic->num_sources); 1005 printk(KERN_INFO "mpic: Initializing for %d sources\n", mpic->num_sources);
905 1006
906 /* Set current processor priority to max */ 1007 /* Set current processor priority to max */
907 mpic_cpu_write(MPIC_CPU_CURRENT_TASK_PRI, 0xf); 1008 mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0xf);
908 1009
909 /* Initialize timers: just disable them all */ 1010 /* Initialize timers: just disable them all */
910 for (i = 0; i < 4; i++) { 1011 for (i = 0; i < 4; i++) {
911 mpic_write(mpic->tmregs, 1012 mpic_write(mpic->tmregs,
912 i * MPIC_TIMER_STRIDE + MPIC_TIMER_DESTINATION, 0); 1013 i * MPIC_INFO(TIMER_STRIDE) +
1014 MPIC_INFO(TIMER_DESTINATION), 0);
913 mpic_write(mpic->tmregs, 1015 mpic_write(mpic->tmregs,
914 i * MPIC_TIMER_STRIDE + MPIC_TIMER_VECTOR_PRI, 1016 i * MPIC_INFO(TIMER_STRIDE) +
1017 MPIC_INFO(TIMER_VECTOR_PRI),
915 MPIC_VECPRI_MASK | 1018 MPIC_VECPRI_MASK |
916 (MPIC_VEC_TIMER_0 + i)); 1019 (MPIC_VEC_TIMER_0 + i));
917 } 1020 }
@@ -940,21 +1043,22 @@ void __init mpic_init(struct mpic *mpic)
940 (8 << MPIC_VECPRI_PRIORITY_SHIFT); 1043 (8 << MPIC_VECPRI_PRIORITY_SHIFT);
941 1044
942 /* init hw */ 1045 /* init hw */
943 mpic_irq_write(i, MPIC_IRQ_VECTOR_PRI, vecpri); 1046 mpic_irq_write(i, MPIC_INFO(IRQ_VECTOR_PRI), vecpri);
944 mpic_irq_write(i, MPIC_IRQ_DESTINATION, 1047 mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION),
945 1 << hard_smp_processor_id()); 1048 1 << hard_smp_processor_id());
946 } 1049 }
947 1050
948 /* Init spurrious vector */ 1051 /* Init spurrious vector */
949 mpic_write(mpic->gregs, MPIC_GREG_SPURIOUS, MPIC_VEC_SPURRIOUS); 1052 mpic_write(mpic->gregs, MPIC_INFO(GREG_SPURIOUS), MPIC_VEC_SPURRIOUS);
950 1053
951 /* Disable 8259 passthrough */ 1054 /* Disable 8259 passthrough, if supported */
952 mpic_write(mpic->gregs, MPIC_GREG_GLOBAL_CONF_0, 1055 if (!(mpic->flags & MPIC_NO_PTHROU_DIS))
953 mpic_read(mpic->gregs, MPIC_GREG_GLOBAL_CONF_0) 1056 mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
954 | MPIC_GREG_GCONF_8259_PTHROU_DIS); 1057 mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
1058 | MPIC_GREG_GCONF_8259_PTHROU_DIS);
955 1059
956 /* Set current processor priority to 0 */ 1060 /* Set current processor priority to 0 */
957 mpic_cpu_write(MPIC_CPU_CURRENT_TASK_PRI, 0); 1061 mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0);
958} 1062}
959 1063
960void __init mpic_set_clk_ratio(struct mpic *mpic, u32 clock_ratio) 1064void __init mpic_set_clk_ratio(struct mpic *mpic, u32 clock_ratio)
@@ -997,9 +1101,9 @@ void mpic_irq_set_priority(unsigned int irq, unsigned int pri)
997 mpic_ipi_write(src - MPIC_VEC_IPI_0, 1101 mpic_ipi_write(src - MPIC_VEC_IPI_0,
998 reg | (pri << MPIC_VECPRI_PRIORITY_SHIFT)); 1102 reg | (pri << MPIC_VECPRI_PRIORITY_SHIFT));
999 } else { 1103 } else {
1000 reg = mpic_irq_read(src, MPIC_IRQ_VECTOR_PRI) 1104 reg = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI))
1001 & ~MPIC_VECPRI_PRIORITY_MASK; 1105 & ~MPIC_VECPRI_PRIORITY_MASK;
1002 mpic_irq_write(src, MPIC_IRQ_VECTOR_PRI, 1106 mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI),
1003 reg | (pri << MPIC_VECPRI_PRIORITY_SHIFT)); 1107 reg | (pri << MPIC_VECPRI_PRIORITY_SHIFT));
1004 } 1108 }
1005 spin_unlock_irqrestore(&mpic_lock, flags); 1109 spin_unlock_irqrestore(&mpic_lock, flags);
@@ -1017,7 +1121,7 @@ unsigned int mpic_irq_get_priority(unsigned int irq)
1017 if (is_ipi) 1121 if (is_ipi)
1018 reg = mpic_ipi_read(src = MPIC_VEC_IPI_0); 1122 reg = mpic_ipi_read(src = MPIC_VEC_IPI_0);
1019 else 1123 else
1020 reg = mpic_irq_read(src, MPIC_IRQ_VECTOR_PRI); 1124 reg = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI));
1021 spin_unlock_irqrestore(&mpic_lock, flags); 1125 spin_unlock_irqrestore(&mpic_lock, flags);
1022 return (reg & MPIC_VECPRI_PRIORITY_MASK) >> MPIC_VECPRI_PRIORITY_SHIFT; 1126 return (reg & MPIC_VECPRI_PRIORITY_MASK) >> MPIC_VECPRI_PRIORITY_SHIFT;
1023} 1127}
@@ -1043,12 +1147,12 @@ void mpic_setup_this_cpu(void)
1043 */ 1147 */
1044 if (distribute_irqs) { 1148 if (distribute_irqs) {
1045 for (i = 0; i < mpic->num_sources ; i++) 1149 for (i = 0; i < mpic->num_sources ; i++)
1046 mpic_irq_write(i, MPIC_IRQ_DESTINATION, 1150 mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION),
1047 mpic_irq_read(i, MPIC_IRQ_DESTINATION) | msk); 1151 mpic_irq_read(i, MPIC_INFO(IRQ_DESTINATION)) | msk);
1048 } 1152 }
1049 1153
1050 /* Set current processor priority to 0 */ 1154 /* Set current processor priority to 0 */
1051 mpic_cpu_write(MPIC_CPU_CURRENT_TASK_PRI, 0); 1155 mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0);
1052 1156
1053 spin_unlock_irqrestore(&mpic_lock, flags); 1157 spin_unlock_irqrestore(&mpic_lock, flags);
1054#endif /* CONFIG_SMP */ 1158#endif /* CONFIG_SMP */
@@ -1058,7 +1162,7 @@ int mpic_cpu_get_priority(void)
1058{ 1162{
1059 struct mpic *mpic = mpic_primary; 1163 struct mpic *mpic = mpic_primary;
1060 1164
1061 return mpic_cpu_read(MPIC_CPU_CURRENT_TASK_PRI); 1165 return mpic_cpu_read(MPIC_INFO(CPU_CURRENT_TASK_PRI));
1062} 1166}
1063 1167
1064void mpic_cpu_set_priority(int prio) 1168void mpic_cpu_set_priority(int prio)
@@ -1066,7 +1170,7 @@ void mpic_cpu_set_priority(int prio)
1066 struct mpic *mpic = mpic_primary; 1170 struct mpic *mpic = mpic_primary;
1067 1171
1068 prio &= MPIC_CPU_TASKPRI_MASK; 1172 prio &= MPIC_CPU_TASKPRI_MASK;
1069 mpic_cpu_write(MPIC_CPU_CURRENT_TASK_PRI, prio); 1173 mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), prio);
1070} 1174}
1071 1175
1072/* 1176/*
@@ -1088,11 +1192,11 @@ void mpic_teardown_this_cpu(int secondary)
1088 1192
1089 /* let the mpic know we don't want intrs. */ 1193 /* let the mpic know we don't want intrs. */
1090 for (i = 0; i < mpic->num_sources ; i++) 1194 for (i = 0; i < mpic->num_sources ; i++)
1091 mpic_irq_write(i, MPIC_IRQ_DESTINATION, 1195 mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION),
1092 mpic_irq_read(i, MPIC_IRQ_DESTINATION) & ~msk); 1196 mpic_irq_read(i, MPIC_INFO(IRQ_DESTINATION)) & ~msk);
1093 1197
1094 /* Set current processor priority to max */ 1198 /* Set current processor priority to max */
1095 mpic_cpu_write(MPIC_CPU_CURRENT_TASK_PRI, 0xf); 1199 mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0xf);
1096 1200
1097 spin_unlock_irqrestore(&mpic_lock, flags); 1201 spin_unlock_irqrestore(&mpic_lock, flags);
1098} 1202}
@@ -1108,7 +1212,8 @@ void mpic_send_ipi(unsigned int ipi_no, unsigned int cpu_mask)
1108 DBG("%s: send_ipi(ipi_no: %d)\n", mpic->name, ipi_no); 1212 DBG("%s: send_ipi(ipi_no: %d)\n", mpic->name, ipi_no);
1109#endif 1213#endif
1110 1214
1111 mpic_cpu_write(MPIC_CPU_IPI_DISPATCH_0 + ipi_no * 0x10, 1215 mpic_cpu_write(MPIC_INFO(CPU_IPI_DISPATCH_0) +
1216 ipi_no * MPIC_INFO(CPU_IPI_DISPATCH_STRIDE),
1112 mpic_physmask(cpu_mask & cpus_addr(cpu_online_map)[0])); 1217 mpic_physmask(cpu_mask & cpus_addr(cpu_online_map)[0]));
1113} 1218}
1114 1219
@@ -1116,7 +1221,7 @@ unsigned int mpic_get_one_irq(struct mpic *mpic, struct pt_regs *regs)
1116{ 1221{
1117 u32 src; 1222 u32 src;
1118 1223
1119 src = mpic_cpu_read(MPIC_CPU_INTACK) & MPIC_VECPRI_VECTOR_MASK; 1224 src = mpic_cpu_read(MPIC_INFO(CPU_INTACK)) & MPIC_INFO(VECPRI_VECTOR_MASK);
1120#ifdef DEBUG_LOW 1225#ifdef DEBUG_LOW
1121 DBG("%s: get_one_irq(): %d\n", mpic->name, src); 1226 DBG("%s: get_one_irq(): %d\n", mpic->name, src);
1122#endif 1227#endif
generated by cgit v1.2.2 (git 2.25.0) at 2025-10-27 17:36:24 -0400