diff options
Diffstat (limited to 'arch/powerpc/sysdev/fsl_pci.h')
-rw-r--r-- | arch/powerpc/sysdev/fsl_pci.h | 88 |
1 files changed, 88 insertions, 0 deletions
diff --git a/arch/powerpc/sysdev/fsl_pci.h b/arch/powerpc/sysdev/fsl_pci.h new file mode 100644 index 000000000000..37b04ad26571 --- /dev/null +++ b/arch/powerpc/sysdev/fsl_pci.h | |||
@@ -0,0 +1,88 @@ | |||
1 | /* | ||
2 | * MPC85xx/86xx PCI Express structure define | ||
3 | * | ||
4 | * Copyright 2007 Freescale Semiconductor, Inc | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify it | ||
7 | * under the terms of the GNU General Public License as published by the | ||
8 | * Free Software Foundation; either version 2 of the License, or (at your | ||
9 | * option) any later version. | ||
10 | * | ||
11 | */ | ||
12 | |||
13 | #ifdef __KERNEL__ | ||
14 | #ifndef __POWERPC_FSL_PCI_H | ||
15 | #define __POWERPC_FSL_PCI_H | ||
16 | |||
17 | #define PCIE_LTSSM 0x0404 /* PCIE Link Training and Status */ | ||
18 | #define PCIE_LTSSM_L0 0x16 /* L0 state */ | ||
19 | #define PIWAR_2G 0xa0f5501e /* Enable, Prefetch, Local Mem, Snoop R/W, 2G */ | ||
20 | |||
21 | /* PCI/PCI Express outbound window reg */ | ||
22 | struct pci_outbound_window_regs { | ||
23 | __be32 potar; /* 0x.0 - Outbound translation address register */ | ||
24 | __be32 potear; /* 0x.4 - Outbound translation extended address register */ | ||
25 | __be32 powbar; /* 0x.8 - Outbound window base address register */ | ||
26 | u8 res1[4]; | ||
27 | __be32 powar; /* 0x.10 - Outbound window attributes register */ | ||
28 | u8 res2[12]; | ||
29 | }; | ||
30 | |||
31 | /* PCI/PCI Express inbound window reg */ | ||
32 | struct pci_inbound_window_regs { | ||
33 | __be32 pitar; /* 0x.0 - Inbound translation address register */ | ||
34 | u8 res1[4]; | ||
35 | __be32 piwbar; /* 0x.8 - Inbound window base address register */ | ||
36 | __be32 piwbear; /* 0x.c - Inbound window base extended address register */ | ||
37 | __be32 piwar; /* 0x.10 - Inbound window attributes register */ | ||
38 | u8 res2[12]; | ||
39 | }; | ||
40 | |||
41 | /* PCI/PCI Express IO block registers for 85xx/86xx */ | ||
42 | struct ccsr_pci { | ||
43 | __be32 config_addr; /* 0x.000 - PCI/PCIE Configuration Address Register */ | ||
44 | __be32 config_data; /* 0x.004 - PCI/PCIE Configuration Data Register */ | ||
45 | __be32 int_ack; /* 0x.008 - PCI Interrupt Acknowledge Register */ | ||
46 | __be32 pex_otb_cpl_tor; /* 0x.00c - PCIE Outbound completion timeout register */ | ||
47 | __be32 pex_conf_tor; /* 0x.010 - PCIE configuration timeout register */ | ||
48 | u8 res2[12]; | ||
49 | __be32 pex_pme_mes_dr; /* 0x.020 - PCIE PME and message detect register */ | ||
50 | __be32 pex_pme_mes_disr; /* 0x.024 - PCIE PME and message disable register */ | ||
51 | __be32 pex_pme_mes_ier; /* 0x.028 - PCIE PME and message interrupt enable register */ | ||
52 | __be32 pex_pmcr; /* 0x.02c - PCIE power management command register */ | ||
53 | u8 res3[3024]; | ||
54 | |||
55 | /* PCI/PCI Express outbound window 0-4 | ||
56 | * Window 0 is the default window and is the only window enabled upon reset. | ||
57 | * The default outbound register set is used when a transaction misses | ||
58 | * in all of the other outbound windows. | ||
59 | */ | ||
60 | struct pci_outbound_window_regs pow[5]; | ||
61 | |||
62 | u8 res14[256]; | ||
63 | |||
64 | /* PCI/PCI Express inbound window 3-1 | ||
65 | * inbound window 1 supports only a 32-bit base address and does not | ||
66 | * define an inbound window base extended address register. | ||
67 | */ | ||
68 | struct pci_inbound_window_regs piw[3]; | ||
69 | |||
70 | __be32 pex_err_dr; /* 0x.e00 - PCI/PCIE error detect register */ | ||
71 | u8 res21[4]; | ||
72 | __be32 pex_err_en; /* 0x.e08 - PCI/PCIE error interrupt enable register */ | ||
73 | u8 res22[4]; | ||
74 | __be32 pex_err_disr; /* 0x.e10 - PCI/PCIE error disable register */ | ||
75 | u8 res23[12]; | ||
76 | __be32 pex_err_cap_stat; /* 0x.e20 - PCI/PCIE error capture status register */ | ||
77 | u8 res24[4]; | ||
78 | __be32 pex_err_cap_r0; /* 0x.e28 - PCIE error capture register 0 */ | ||
79 | __be32 pex_err_cap_r1; /* 0x.e2c - PCIE error capture register 0 */ | ||
80 | __be32 pex_err_cap_r2; /* 0x.e30 - PCIE error capture register 0 */ | ||
81 | __be32 pex_err_cap_r3; /* 0x.e34 - PCIE error capture register 0 */ | ||
82 | }; | ||
83 | |||
84 | extern int fsl_add_bridge(struct device_node *dev, int is_primary); | ||
85 | extern void fsl_pcibios_fixup_bus(struct pci_bus *bus); | ||
86 | |||
87 | #endif /* __POWERPC_FSL_PCI_H */ | ||
88 | #endif /* __KERNEL__ */ | ||