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Diffstat (limited to 'arch/powerpc/sysdev/fsl_85xx_l2ctlr.c')
-rw-r--r--arch/powerpc/sysdev/fsl_85xx_l2ctlr.c39
1 files changed, 14 insertions, 25 deletions
diff --git a/arch/powerpc/sysdev/fsl_85xx_l2ctlr.c b/arch/powerpc/sysdev/fsl_85xx_l2ctlr.c
index cedabd0f4bfe..68ac3aacb191 100644
--- a/arch/powerpc/sysdev/fsl_85xx_l2ctlr.c
+++ b/arch/powerpc/sysdev/fsl_85xx_l2ctlr.c
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright 2009-2010 Freescale Semiconductor, Inc. 2 * Copyright 2009-2010, 2012 Freescale Semiconductor, Inc.
3 * 3 *
4 * QorIQ (P1/P2) L2 controller init for Cache-SRAM instantiation 4 * QorIQ (P1/P2) L2 controller init for Cache-SRAM instantiation
5 * 5 *
@@ -31,24 +31,21 @@ static char *sram_size;
31static char *sram_offset; 31static char *sram_offset;
32struct mpc85xx_l2ctlr __iomem *l2ctlr; 32struct mpc85xx_l2ctlr __iomem *l2ctlr;
33 33
34static long get_cache_sram_size(void) 34static int get_cache_sram_params(struct sram_parameters *sram_params)
35{ 35{
36 unsigned long val; 36 unsigned long long addr;
37 unsigned int size;
37 38
38 if (!sram_size || (strict_strtoul(sram_size, 0, &val) < 0)) 39 if (!sram_size || (kstrtouint(sram_size, 0, &size) < 0))
39 return -EINVAL; 40 return -EINVAL;
40 41
41 return val; 42 if (!sram_offset || (kstrtoull(sram_offset, 0, &addr) < 0))
42}
43
44static long get_cache_sram_offset(void)
45{
46 unsigned long val;
47
48 if (!sram_offset || (strict_strtoul(sram_offset, 0, &val) < 0))
49 return -EINVAL; 43 return -EINVAL;
50 44
51 return val; 45 sram_params->sram_offset = addr;
46 sram_params->sram_size = size;
47
48 return 0;
52} 49}
53 50
54static int __init get_size_from_cmdline(char *str) 51static int __init get_size_from_cmdline(char *str)
@@ -93,17 +90,9 @@ static int __devinit mpc85xx_l2ctlr_of_probe(struct platform_device *dev)
93 } 90 }
94 l2cache_size = *prop; 91 l2cache_size = *prop;
95 92
96 sram_params.sram_size = get_cache_sram_size(); 93 if (get_cache_sram_params(&sram_params)) {
97 if ((int)sram_params.sram_size <= 0) {
98 dev_err(&dev->dev,
99 "Entire L2 as cache, Aborting Cache-SRAM stuff\n");
100 return -EINVAL;
101 }
102
103 sram_params.sram_offset = get_cache_sram_offset();
104 if ((int64_t)sram_params.sram_offset <= 0) {
105 dev_err(&dev->dev, 94 dev_err(&dev->dev,
106 "Entire L2 as cache, provide a valid sram offset\n"); 95 "Entire L2 as cache, provide valid sram offset and size\n");
107 return -EINVAL; 96 return -EINVAL;
108 } 97 }
109 98
@@ -125,14 +114,14 @@ static int __devinit mpc85xx_l2ctlr_of_probe(struct platform_device *dev)
125 * Write bits[0-17] to srbar0 114 * Write bits[0-17] to srbar0
126 */ 115 */
127 out_be32(&l2ctlr->srbar0, 116 out_be32(&l2ctlr->srbar0,
128 sram_params.sram_offset & L2SRAM_BAR_MSK_LO18); 117 lower_32_bits(sram_params.sram_offset) & L2SRAM_BAR_MSK_LO18);
129 118
130 /* 119 /*
131 * Write bits[18-21] to srbare0 120 * Write bits[18-21] to srbare0
132 */ 121 */
133#ifdef CONFIG_PHYS_64BIT 122#ifdef CONFIG_PHYS_64BIT
134 out_be32(&l2ctlr->srbarea0, 123 out_be32(&l2ctlr->srbarea0,
135 (sram_params.sram_offset >> 32) & L2SRAM_BARE_MSK_HI4); 124 upper_32_bits(sram_params.sram_offset) & L2SRAM_BARE_MSK_HI4);
136#endif 125#endif
137 126
138 clrsetbits_be32(&l2ctlr->ctl, L2CR_L2E, L2CR_L2FI); 127 clrsetbits_be32(&l2ctlr->ctl, L2CR_L2E, L2CR_L2FI);