diff options
Diffstat (limited to 'arch/powerpc/platforms')
-rw-r--r-- | arch/powerpc/platforms/85xx/p1022_ds.c | 211 |
1 files changed, 209 insertions, 2 deletions
diff --git a/arch/powerpc/platforms/85xx/p1022_ds.c b/arch/powerpc/platforms/85xx/p1022_ds.c index 2b390d19a1d1..7eb5c40c069f 100644 --- a/arch/powerpc/platforms/85xx/p1022_ds.c +++ b/arch/powerpc/platforms/85xx/p1022_ds.c | |||
@@ -8,7 +8,6 @@ | |||
8 | * Copyright 2010 Freescale Semiconductor, Inc. | 8 | * Copyright 2010 Freescale Semiconductor, Inc. |
9 | * | 9 | * |
10 | * This file is taken from the Freescale P1022DS BSP, with modifications: | 10 | * This file is taken from the Freescale P1022DS BSP, with modifications: |
11 | * 1) No DIU support (pending rewrite of DIU code) | ||
12 | * 2) No AMP support | 11 | * 2) No AMP support |
13 | * 3) No PCI endpoint support | 12 | * 3) No PCI endpoint support |
14 | * | 13 | * |
@@ -20,12 +19,211 @@ | |||
20 | #include <linux/pci.h> | 19 | #include <linux/pci.h> |
21 | #include <linux/of_platform.h> | 20 | #include <linux/of_platform.h> |
22 | #include <linux/memblock.h> | 21 | #include <linux/memblock.h> |
23 | 22 | #include <asm/div64.h> | |
24 | #include <asm/mpic.h> | 23 | #include <asm/mpic.h> |
25 | #include <asm/swiotlb.h> | 24 | #include <asm/swiotlb.h> |
26 | 25 | ||
27 | #include <sysdev/fsl_soc.h> | 26 | #include <sysdev/fsl_soc.h> |
28 | #include <sysdev/fsl_pci.h> | 27 | #include <sysdev/fsl_pci.h> |
28 | #include <asm/fsl_guts.h> | ||
29 | |||
30 | #if defined(CONFIG_FB_FSL_DIU) || defined(CONFIG_FB_FSL_DIU_MODULE) | ||
31 | |||
32 | /* | ||
33 | * Board-specific initialization of the DIU. This code should probably be | ||
34 | * executed when the DIU is opened, rather than in arch code, but the DIU | ||
35 | * driver does not have a mechanism for this (yet). | ||
36 | * | ||
37 | * This is especially problematic on the P1022DS because the local bus (eLBC) | ||
38 | * and the DIU video signals share the same pins, which means that enabling the | ||
39 | * DIU will disable access to NOR flash. | ||
40 | */ | ||
41 | |||
42 | /* DIU Pixel Clock bits of the CLKDVDR Global Utilities register */ | ||
43 | #define CLKDVDR_PXCKEN 0x80000000 | ||
44 | #define CLKDVDR_PXCKINV 0x10000000 | ||
45 | #define CLKDVDR_PXCKDLY 0x06000000 | ||
46 | #define CLKDVDR_PXCLK_MASK 0x00FF0000 | ||
47 | |||
48 | /* Some ngPIXIS register definitions */ | ||
49 | #define PX_BRDCFG1_DVIEN 0x80 | ||
50 | #define PX_BRDCFG1_DFPEN 0x40 | ||
51 | #define PX_BRDCFG1_BACKLIGHT 0x20 | ||
52 | #define PX_BRDCFG1_DDCEN 0x10 | ||
53 | |||
54 | /* | ||
55 | * DIU Area Descriptor | ||
56 | * | ||
57 | * Note that we need to byte-swap the value before it's written to the AD | ||
58 | * register. So even though the registers don't look like they're in the same | ||
59 | * bit positions as they are on the MPC8610, the same value is written to the | ||
60 | * AD register on the MPC8610 and on the P1022. | ||
61 | */ | ||
62 | #define AD_BYTE_F 0x10000000 | ||
63 | #define AD_ALPHA_C_MASK 0x0E000000 | ||
64 | #define AD_ALPHA_C_SHIFT 25 | ||
65 | #define AD_BLUE_C_MASK 0x01800000 | ||
66 | #define AD_BLUE_C_SHIFT 23 | ||
67 | #define AD_GREEN_C_MASK 0x00600000 | ||
68 | #define AD_GREEN_C_SHIFT 21 | ||
69 | #define AD_RED_C_MASK 0x00180000 | ||
70 | #define AD_RED_C_SHIFT 19 | ||
71 | #define AD_PALETTE 0x00040000 | ||
72 | #define AD_PIXEL_S_MASK 0x00030000 | ||
73 | #define AD_PIXEL_S_SHIFT 16 | ||
74 | #define AD_COMP_3_MASK 0x0000F000 | ||
75 | #define AD_COMP_3_SHIFT 12 | ||
76 | #define AD_COMP_2_MASK 0x00000F00 | ||
77 | #define AD_COMP_2_SHIFT 8 | ||
78 | #define AD_COMP_1_MASK 0x000000F0 | ||
79 | #define AD_COMP_1_SHIFT 4 | ||
80 | #define AD_COMP_0_MASK 0x0000000F | ||
81 | #define AD_COMP_0_SHIFT 0 | ||
82 | |||
83 | #define MAKE_AD(alpha, red, blue, green, size, c0, c1, c2, c3) \ | ||
84 | cpu_to_le32(AD_BYTE_F | (alpha << AD_ALPHA_C_SHIFT) | \ | ||
85 | (blue << AD_BLUE_C_SHIFT) | (green << AD_GREEN_C_SHIFT) | \ | ||
86 | (red << AD_RED_C_SHIFT) | (c3 << AD_COMP_3_SHIFT) | \ | ||
87 | (c2 << AD_COMP_2_SHIFT) | (c1 << AD_COMP_1_SHIFT) | \ | ||
88 | (c0 << AD_COMP_0_SHIFT) | (size << AD_PIXEL_S_SHIFT)) | ||
89 | |||
90 | /** | ||
91 | * p1022ds_get_pixel_format: return the Area Descriptor for a given pixel depth | ||
92 | * | ||
93 | * The Area Descriptor is a 32-bit value that determine which bits in each | ||
94 | * pixel are to be used for each color. | ||
95 | */ | ||
96 | static unsigned int p1022ds_get_pixel_format(unsigned int bits_per_pixel, | ||
97 | int monitor_port) | ||
98 | { | ||
99 | switch (bits_per_pixel) { | ||
100 | case 32: | ||
101 | /* 0x88883316 */ | ||
102 | return MAKE_AD(3, 2, 0, 1, 3, 8, 8, 8, 8); | ||
103 | case 24: | ||
104 | /* 0x88082219 */ | ||
105 | return MAKE_AD(4, 0, 1, 2, 2, 0, 8, 8, 8); | ||
106 | case 16: | ||
107 | /* 0x65053118 */ | ||
108 | return MAKE_AD(4, 2, 1, 0, 1, 5, 6, 5, 0); | ||
109 | default: | ||
110 | pr_err("fsl-diu: unsupported pixel depth %u\n", bits_per_pixel); | ||
111 | return 0; | ||
112 | } | ||
113 | } | ||
114 | |||
115 | /** | ||
116 | * p1022ds_set_gamma_table: update the gamma table, if necessary | ||
117 | * | ||
118 | * On some boards, the gamma table for some ports may need to be modified. | ||
119 | * This is not the case on the P1022DS, so we do nothing. | ||
120 | */ | ||
121 | static void p1022ds_set_gamma_table(int monitor_port, char *gamma_table_base) | ||
122 | { | ||
123 | } | ||
124 | |||
125 | /** | ||
126 | * p1022ds_set_monitor_port: switch the output to a different monitor port | ||
127 | * | ||
128 | */ | ||
129 | static void p1022ds_set_monitor_port(int monitor_port) | ||
130 | { | ||
131 | struct device_node *pixis_node; | ||
132 | u8 __iomem *brdcfg1; | ||
133 | |||
134 | pixis_node = of_find_compatible_node(NULL, NULL, "fsl,p1022ds-pixis"); | ||
135 | if (!pixis_node) { | ||
136 | pr_err("p1022ds: missing ngPIXIS node\n"); | ||
137 | return; | ||
138 | } | ||
139 | |||
140 | brdcfg1 = of_iomap(pixis_node, 0); | ||
141 | if (!brdcfg1) { | ||
142 | pr_err("p1022ds: could not map ngPIXIS registers\n"); | ||
143 | return; | ||
144 | } | ||
145 | brdcfg1 += 9; /* BRDCFG1 is at offset 9 in the ngPIXIS */ | ||
146 | |||
147 | switch (monitor_port) { | ||
148 | case 0: /* DVI */ | ||
149 | /* Enable the DVI port, disable the DFP and the backlight */ | ||
150 | clrsetbits_8(brdcfg1, PX_BRDCFG1_DFPEN | PX_BRDCFG1_BACKLIGHT, | ||
151 | PX_BRDCFG1_DVIEN); | ||
152 | break; | ||
153 | case 1: /* Single link LVDS */ | ||
154 | /* Enable the DFP port, disable the DVI and the backlight */ | ||
155 | clrsetbits_8(brdcfg1, PX_BRDCFG1_DVIEN | PX_BRDCFG1_BACKLIGHT, | ||
156 | PX_BRDCFG1_DFPEN); | ||
157 | break; | ||
158 | default: | ||
159 | pr_err("p1022ds: unsupported monitor port %i\n", monitor_port); | ||
160 | } | ||
161 | } | ||
162 | |||
163 | /** | ||
164 | * p1022ds_set_pixel_clock: program the DIU's clock | ||
165 | * | ||
166 | * @pixclock: the wavelength, in picoseconds, of the clock | ||
167 | */ | ||
168 | void p1022ds_set_pixel_clock(unsigned int pixclock) | ||
169 | { | ||
170 | struct device_node *guts_np = NULL; | ||
171 | struct ccsr_guts_85xx __iomem *guts; | ||
172 | unsigned long freq; | ||
173 | u64 temp; | ||
174 | u32 pxclk; | ||
175 | |||
176 | /* Map the global utilities registers. */ | ||
177 | guts_np = of_find_compatible_node(NULL, NULL, "fsl,p1022-guts"); | ||
178 | if (!guts_np) { | ||
179 | pr_err("p1022ds: missing global utilties device node\n"); | ||
180 | return; | ||
181 | } | ||
182 | |||
183 | guts = of_iomap(guts_np, 0); | ||
184 | of_node_put(guts_np); | ||
185 | if (!guts) { | ||
186 | pr_err("p1022ds: could not map global utilties device\n"); | ||
187 | return; | ||
188 | } | ||
189 | |||
190 | /* Convert pixclock from a wavelength to a frequency */ | ||
191 | temp = 1000000000000ULL; | ||
192 | do_div(temp, pixclock); | ||
193 | freq = temp; | ||
194 | |||
195 | /* pixclk is the ratio of the platform clock to the pixel clock */ | ||
196 | pxclk = DIV_ROUND_CLOSEST(fsl_get_sys_freq(), freq); | ||
197 | |||
198 | /* Disable the pixel clock, and set it to non-inverted and no delay */ | ||
199 | clrbits32(&guts->clkdvdr, | ||
200 | CLKDVDR_PXCKEN | CLKDVDR_PXCKDLY | CLKDVDR_PXCLK_MASK); | ||
201 | |||
202 | /* Enable the clock and set the pxclk */ | ||
203 | setbits32(&guts->clkdvdr, CLKDVDR_PXCKEN | (pxclk << 16)); | ||
204 | } | ||
205 | |||
206 | /** | ||
207 | * p1022ds_show_monitor_port: show the current monitor | ||
208 | * | ||
209 | * This function returns a string indicating whether the current monitor is | ||
210 | * set to DVI or LVDS. | ||
211 | */ | ||
212 | ssize_t p1022ds_show_monitor_port(int monitor_port, char *buf) | ||
213 | { | ||
214 | return sprintf(buf, "%c0 - DVI\n%c1 - Single link LVDS\n", | ||
215 | monitor_port == 0 ? '*' : ' ', monitor_port == 1 ? '*' : ' '); | ||
216 | } | ||
217 | |||
218 | /** | ||
219 | * p1022ds_set_sysfs_monitor_port: set the monitor port for sysfs | ||
220 | */ | ||
221 | int p1022ds_set_sysfs_monitor_port(int val) | ||
222 | { | ||
223 | return val < 2 ? val : 0; | ||
224 | } | ||
225 | |||
226 | #endif | ||
29 | 227 | ||
30 | void __init p1022_ds_pic_init(void) | 228 | void __init p1022_ds_pic_init(void) |
31 | { | 229 | { |
@@ -92,6 +290,15 @@ static void __init p1022_ds_setup_arch(void) | |||
92 | } | 290 | } |
93 | #endif | 291 | #endif |
94 | 292 | ||
293 | #if defined(CONFIG_FB_FSL_DIU) || defined(CONFIG_FB_FSL_DIU_MODULE) | ||
294 | diu_ops.get_pixel_format = p1022ds_get_pixel_format; | ||
295 | diu_ops.set_gamma_table = p1022ds_set_gamma_table; | ||
296 | diu_ops.set_monitor_port = p1022ds_set_monitor_port; | ||
297 | diu_ops.set_pixel_clock = p1022ds_set_pixel_clock; | ||
298 | diu_ops.show_monitor_port = p1022ds_show_monitor_port; | ||
299 | diu_ops.set_sysfs_monitor_port = p1022ds_set_sysfs_monitor_port; | ||
300 | #endif | ||
301 | |||
95 | #ifdef CONFIG_SMP | 302 | #ifdef CONFIG_SMP |
96 | mpc85xx_smp_init(); | 303 | mpc85xx_smp_init(); |
97 | #endif | 304 | #endif |