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-rw-r--r--arch/powerpc/platforms/512x/Kconfig2
-rw-r--r--arch/powerpc/platforms/512x/mpc5121_ads.c10
-rw-r--r--arch/powerpc/platforms/83xx/Kconfig5
-rw-r--r--arch/powerpc/platforms/83xx/mpc837x_mds.c8
-rw-r--r--arch/powerpc/platforms/85xx/Kconfig1
-rw-r--r--arch/powerpc/platforms/86xx/Makefile2
-rw-r--r--arch/powerpc/platforms/86xx/gef_pic.c258
-rw-r--r--arch/powerpc/platforms/86xx/gef_pic.h11
-rw-r--r--arch/powerpc/platforms/86xx/gef_sbc610.c65
-rw-r--r--arch/powerpc/platforms/86xx/mpc8610_hpcd.c1
-rw-r--r--arch/powerpc/platforms/Kconfig12
11 files changed, 364 insertions, 11 deletions
diff --git a/arch/powerpc/platforms/512x/Kconfig b/arch/powerpc/platforms/512x/Kconfig
index c62f893ede19..326852c78b8f 100644
--- a/arch/powerpc/platforms/512x/Kconfig
+++ b/arch/powerpc/platforms/512x/Kconfig
@@ -3,6 +3,8 @@ config PPC_MPC512x
3 select FSL_SOC 3 select FSL_SOC
4 select IPIC 4 select IPIC
5 select PPC_CLOCK 5 select PPC_CLOCK
6 select PPC_PCI_CHOICE
7 select FSL_PCI if PCI
6 8
7config PPC_MPC5121 9config PPC_MPC5121
8 bool 10 bool
diff --git a/arch/powerpc/platforms/512x/mpc5121_ads.c b/arch/powerpc/platforms/512x/mpc5121_ads.c
index 5ebf6939a697..441abc488851 100644
--- a/arch/powerpc/platforms/512x/mpc5121_ads.c
+++ b/arch/powerpc/platforms/512x/mpc5121_ads.c
@@ -22,16 +22,26 @@
22#include <asm/prom.h> 22#include <asm/prom.h>
23#include <asm/time.h> 23#include <asm/time.h>
24 24
25#include <sysdev/fsl_pci.h>
26
25#include "mpc512x.h" 27#include "mpc512x.h"
26#include "mpc5121_ads.h" 28#include "mpc5121_ads.h"
27 29
28static void __init mpc5121_ads_setup_arch(void) 30static void __init mpc5121_ads_setup_arch(void)
29{ 31{
32#ifdef CONFIG_PCI
33 struct device_node *np;
34#endif
30 printk(KERN_INFO "MPC5121 ADS board from Freescale Semiconductor\n"); 35 printk(KERN_INFO "MPC5121 ADS board from Freescale Semiconductor\n");
31 /* 36 /*
32 * cpld regs are needed early 37 * cpld regs are needed early
33 */ 38 */
34 mpc5121_ads_cpld_map(); 39 mpc5121_ads_cpld_map();
40
41#ifdef CONFIG_PCI
42 for_each_compatible_node(np, "pci", "fsl,mpc5121-pci")
43 mpc83xx_add_bridge(np);
44#endif
35} 45}
36 46
37static void __init mpc5121_ads_init_IRQ(void) 47static void __init mpc5121_ads_init_IRQ(void)
diff --git a/arch/powerpc/platforms/83xx/Kconfig b/arch/powerpc/platforms/83xx/Kconfig
index 6159c5d4e5f1..83c664afc897 100644
--- a/arch/powerpc/platforms/83xx/Kconfig
+++ b/arch/powerpc/platforms/83xx/Kconfig
@@ -19,7 +19,6 @@ config MPC831x_RDB
19config MPC832x_MDS 19config MPC832x_MDS
20 bool "Freescale MPC832x MDS" 20 bool "Freescale MPC832x MDS"
21 select DEFAULT_UIMAGE 21 select DEFAULT_UIMAGE
22 select QUICC_ENGINE
23 select PPC_MPC832x 22 select PPC_MPC832x
24 help 23 help
25 This option enables support for the MPC832x MDS evaluation board. 24 This option enables support for the MPC832x MDS evaluation board.
@@ -27,7 +26,6 @@ config MPC832x_MDS
27config MPC832x_RDB 26config MPC832x_RDB
28 bool "Freescale MPC832x RDB" 27 bool "Freescale MPC832x RDB"
29 select DEFAULT_UIMAGE 28 select DEFAULT_UIMAGE
30 select QUICC_ENGINE
31 select PPC_MPC832x 29 select PPC_MPC832x
32 help 30 help
33 This option enables support for the MPC8323 RDB board. 31 This option enables support for the MPC8323 RDB board.
@@ -57,15 +55,12 @@ config MPC834x_ITX
57config MPC836x_MDS 55config MPC836x_MDS
58 bool "Freescale MPC836x MDS" 56 bool "Freescale MPC836x MDS"
59 select DEFAULT_UIMAGE 57 select DEFAULT_UIMAGE
60 select QUICC_ENGINE
61 help 58 help
62 This option enables support for the MPC836x MDS Processor Board. 59 This option enables support for the MPC836x MDS Processor Board.
63 60
64config MPC836x_RDK 61config MPC836x_RDK
65 bool "Freescale/Logic MPC836x RDK" 62 bool "Freescale/Logic MPC836x RDK"
66 select DEFAULT_UIMAGE 63 select DEFAULT_UIMAGE
67 select QUICC_ENGINE
68 select QE_GPIO
69 select FSL_GTM 64 select FSL_GTM
70 select FSL_LBC 65 select FSL_LBC
71 help 66 help
diff --git a/arch/powerpc/platforms/83xx/mpc837x_mds.c b/arch/powerpc/platforms/83xx/mpc837x_mds.c
index be62de23bead..8bb13c807142 100644
--- a/arch/powerpc/platforms/83xx/mpc837x_mds.c
+++ b/arch/powerpc/platforms/83xx/mpc837x_mds.c
@@ -85,8 +85,14 @@ static void __init mpc837x_mds_setup_arch(void)
85 ppc_md.progress("mpc837x_mds_setup_arch()", 0); 85 ppc_md.progress("mpc837x_mds_setup_arch()", 0);
86 86
87#ifdef CONFIG_PCI 87#ifdef CONFIG_PCI
88 for_each_compatible_node(np, "pci", "fsl,mpc8349-pci") 88 for_each_compatible_node(np, "pci", "fsl,mpc8349-pci") {
89 if (!of_device_is_available(np)) {
90 pr_warning("%s: disabled by the firmware.\n",
91 np->full_name);
92 continue;
93 }
89 mpc83xx_add_bridge(np); 94 mpc83xx_add_bridge(np);
95 }
90#endif 96#endif
91 mpc837xmds_usb_cfg(); 97 mpc837xmds_usb_cfg();
92} 98}
diff --git a/arch/powerpc/platforms/85xx/Kconfig b/arch/powerpc/platforms/85xx/Kconfig
index 291675b0097a..b79dc710ed34 100644
--- a/arch/powerpc/platforms/85xx/Kconfig
+++ b/arch/powerpc/platforms/85xx/Kconfig
@@ -33,7 +33,6 @@ config MPC85xx_CDS
33config MPC85xx_MDS 33config MPC85xx_MDS
34 bool "Freescale MPC85xx MDS" 34 bool "Freescale MPC85xx MDS"
35 select DEFAULT_UIMAGE 35 select DEFAULT_UIMAGE
36 select QUICC_ENGINE
37 select PHYLIB 36 select PHYLIB
38 help 37 help
39 This option enables support for the MPC85xx MDS board 38 This option enables support for the MPC85xx MDS board
diff --git a/arch/powerpc/platforms/86xx/Makefile b/arch/powerpc/platforms/86xx/Makefile
index cb9fc8f4360b..4a56ff619afd 100644
--- a/arch/powerpc/platforms/86xx/Makefile
+++ b/arch/powerpc/platforms/86xx/Makefile
@@ -7,4 +7,4 @@ obj-$(CONFIG_SMP) += mpc86xx_smp.o
7obj-$(CONFIG_MPC8641_HPCN) += mpc86xx_hpcn.o 7obj-$(CONFIG_MPC8641_HPCN) += mpc86xx_hpcn.o
8obj-$(CONFIG_SBC8641D) += sbc8641d.o 8obj-$(CONFIG_SBC8641D) += sbc8641d.o
9obj-$(CONFIG_MPC8610_HPCD) += mpc8610_hpcd.o 9obj-$(CONFIG_MPC8610_HPCD) += mpc8610_hpcd.o
10obj-$(CONFIG_GEF_SBC610) += gef_sbc610.o 10obj-$(CONFIG_GEF_SBC610) += gef_sbc610.o gef_pic.o
diff --git a/arch/powerpc/platforms/86xx/gef_pic.c b/arch/powerpc/platforms/86xx/gef_pic.c
new file mode 100644
index 000000000000..50d0a2b63809
--- /dev/null
+++ b/arch/powerpc/platforms/86xx/gef_pic.c
@@ -0,0 +1,258 @@
1/*
2 * Interrupt handling for GE Fanuc's FPGA based PIC
3 *
4 * Author: Martyn Welch <martyn.welch@gefanuc.com>
5 *
6 * 2008 (c) GE Fanuc Intelligent Platforms Embedded Systems, Inc.
7 *
8 * This file is licensed under the terms of the GNU General Public License
9 * version 2. This program is licensed "as is" without any warranty of any
10 * kind, whether express or implied.
11 */
12
13#include <linux/stddef.h>
14#include <linux/kernel.h>
15#include <linux/init.h>
16#include <linux/irq.h>
17#include <linux/interrupt.h>
18#include <linux/spinlock.h>
19
20#include <asm/byteorder.h>
21#include <asm/io.h>
22#include <asm/prom.h>
23#include <asm/irq.h>
24
25#include "gef_pic.h"
26
27#define DEBUG
28#undef DEBUG
29
30#ifdef DEBUG
31#define DBG(fmt...) do { printk(KERN_DEBUG "gef_pic: " fmt); } while (0)
32#else
33#define DBG(fmt...) do { } while (0)
34#endif
35
36#define GEF_PIC_NUM_IRQS 32
37
38/* Interrupt Controller Interface Registers */
39#define GEF_PIC_INTR_STATUS 0x0000
40
41#define GEF_PIC_INTR_MASK(cpu) (0x0010 + (0x4 * cpu))
42#define GEF_PIC_CPU0_INTR_MASK GEF_PIC_INTR_MASK(0)
43#define GEF_PIC_CPU1_INTR_MASK GEF_PIC_INTR_MASK(1)
44
45#define GEF_PIC_MCP_MASK(cpu) (0x0018 + (0x4 * cpu))
46#define GEF_PIC_CPU0_MCP_MASK GEF_PIC_MCP_MASK(0)
47#define GEF_PIC_CPU1_MCP_MASK GEF_PIC_MCP_MASK(1)
48
49#define gef_irq_to_hw(virq) ((unsigned int)irq_map[virq].hwirq)
50
51
52static DEFINE_SPINLOCK(gef_pic_lock);
53
54static void __iomem *gef_pic_irq_reg_base;
55static struct irq_host *gef_pic_irq_host;
56static int gef_pic_cascade_irq;
57
58/*
59 * Interrupt Controller Handling
60 *
61 * The interrupt controller handles interrupts for most on board interrupts,
62 * apart from PCI interrupts. For example on SBC610:
63 *
64 * 17:31 RO Reserved
65 * 16 RO PCI Express Doorbell 3 Status
66 * 15 RO PCI Express Doorbell 2 Status
67 * 14 RO PCI Express Doorbell 1 Status
68 * 13 RO PCI Express Doorbell 0 Status
69 * 12 RO Real Time Clock Interrupt Status
70 * 11 RO Temperature Interrupt Status
71 * 10 RO Temperature Critical Interrupt Status
72 * 9 RO Ethernet PHY1 Interrupt Status
73 * 8 RO Ethernet PHY3 Interrupt Status
74 * 7 RO PEX8548 Interrupt Status
75 * 6 RO Reserved
76 * 5 RO Watchdog 0 Interrupt Status
77 * 4 RO Watchdog 1 Interrupt Status
78 * 3 RO AXIS Message FIFO A Interrupt Status
79 * 2 RO AXIS Message FIFO B Interrupt Status
80 * 1 RO AXIS Message FIFO C Interrupt Status
81 * 0 RO AXIS Message FIFO D Interrupt Status
82 *
83 * Interrupts can be forwarded to one of two output lines. Nothing
84 * clever is done, so if the masks are incorrectly set, a single input
85 * interrupt could generate interrupts on both output lines!
86 *
87 * The dual lines are there to allow the chained interrupts to be easily
88 * passed into two different cores. We currently do not use this functionality
89 * in this driver.
90 *
91 * Controller can also be configured to generate Machine checks (MCP), again on
92 * two lines, to be attached to two different cores. It is suggested that these
93 * should be masked out.
94 */
95
96void gef_pic_cascade(unsigned int irq, struct irq_desc *desc)
97{
98 unsigned int cascade_irq;
99
100 /*
101 * See if we actually have an interrupt, call generic handling code if
102 * we do.
103 */
104 cascade_irq = gef_pic_get_irq();
105
106 if (cascade_irq != NO_IRQ)
107 generic_handle_irq(cascade_irq);
108
109 desc->chip->eoi(irq);
110
111}
112
113static void gef_pic_mask(unsigned int virq)
114{
115 unsigned long flags;
116 unsigned int hwirq;
117 u32 mask;
118
119 hwirq = gef_irq_to_hw(virq);
120
121 spin_lock_irqsave(&gef_pic_lock, flags);
122 mask = in_be32(gef_pic_irq_reg_base + GEF_PIC_INTR_MASK(0));
123 mask &= ~(1 << hwirq);
124 out_be32(gef_pic_irq_reg_base + GEF_PIC_INTR_MASK(0), mask);
125 spin_unlock_irqrestore(&gef_pic_lock, flags);
126}
127
128static void gef_pic_mask_ack(unsigned int virq)
129{
130 /* Don't think we actually have to do anything to ack an interrupt,
131 * we just need to clear down the devices interrupt and it will go away
132 */
133 gef_pic_mask(virq);
134}
135
136static void gef_pic_unmask(unsigned int virq)
137{
138 unsigned long flags;
139 unsigned int hwirq;
140 u32 mask;
141
142 hwirq = gef_irq_to_hw(virq);
143
144 spin_lock_irqsave(&gef_pic_lock, flags);
145 mask = in_be32(gef_pic_irq_reg_base + GEF_PIC_INTR_MASK(0));
146 mask |= (1 << hwirq);
147 out_be32(gef_pic_irq_reg_base + GEF_PIC_INTR_MASK(0), mask);
148 spin_unlock_irqrestore(&gef_pic_lock, flags);
149}
150
151static struct irq_chip gef_pic_chip = {
152 .typename = "gefp",
153 .mask = gef_pic_mask,
154 .mask_ack = gef_pic_mask_ack,
155 .unmask = gef_pic_unmask,
156};
157
158
159/* When an interrupt is being configured, this call allows some flexibilty
160 * in deciding which irq_chip structure is used
161 */
162static int gef_pic_host_map(struct irq_host *h, unsigned int virq,
163 irq_hw_number_t hwirq)
164{
165 /* All interrupts are LEVEL sensitive */
166 get_irq_desc(virq)->status |= IRQ_LEVEL;
167 set_irq_chip_and_handler(virq, &gef_pic_chip, handle_level_irq);
168
169 return 0;
170}
171
172static int gef_pic_host_xlate(struct irq_host *h, struct device_node *ct,
173 u32 *intspec, unsigned int intsize,
174 irq_hw_number_t *out_hwirq, unsigned int *out_flags)
175{
176
177 *out_hwirq = intspec[0];
178 if (intsize > 1)
179 *out_flags = intspec[1];
180 else
181 *out_flags = IRQ_TYPE_LEVEL_HIGH;
182
183 return 0;
184}
185
186static struct irq_host_ops gef_pic_host_ops = {
187 .map = gef_pic_host_map,
188 .xlate = gef_pic_host_xlate,
189};
190
191
192/*
193 * Initialisation of PIC, this should be called in BSP
194 */
195void __init gef_pic_init(struct device_node *np)
196{
197 unsigned long flags;
198
199 /* Map the devices registers into memory */
200 gef_pic_irq_reg_base = of_iomap(np, 0);
201
202 spin_lock_irqsave(&gef_pic_lock, flags);
203
204 /* Initialise everything as masked. */
205 out_be32(gef_pic_irq_reg_base + GEF_PIC_CPU0_INTR_MASK, 0);
206 out_be32(gef_pic_irq_reg_base + GEF_PIC_CPU1_INTR_MASK, 0);
207
208 out_be32(gef_pic_irq_reg_base + GEF_PIC_CPU0_MCP_MASK, 0);
209 out_be32(gef_pic_irq_reg_base + GEF_PIC_CPU1_MCP_MASK, 0);
210
211 spin_unlock_irqrestore(&gef_pic_lock, flags);
212
213 /* Map controller */
214 gef_pic_cascade_irq = irq_of_parse_and_map(np, 0);
215 if (gef_pic_cascade_irq == NO_IRQ) {
216 printk(KERN_ERR "SBC610: failed to map cascade interrupt");
217 return;
218 }
219
220 /* Setup an irq_host structure */
221 gef_pic_irq_host = irq_alloc_host(np, IRQ_HOST_MAP_LINEAR,
222 GEF_PIC_NUM_IRQS,
223 &gef_pic_host_ops, NO_IRQ);
224 if (gef_pic_irq_host == NULL)
225 return;
226
227 /* Chain with parent controller */
228 set_irq_chained_handler(gef_pic_cascade_irq, gef_pic_cascade);
229}
230
231/*
232 * This is called when we receive an interrupt with apparently comes from this
233 * chip - check, returning the highest interrupt generated or return NO_IRQ
234 */
235unsigned int gef_pic_get_irq(void)
236{
237 u32 cause, mask, active;
238 unsigned int virq = NO_IRQ;
239 int hwirq;
240
241 cause = in_be32(gef_pic_irq_reg_base + GEF_PIC_INTR_STATUS);
242
243 mask = in_be32(gef_pic_irq_reg_base + GEF_PIC_INTR_MASK(0));
244
245 active = cause & mask;
246
247 if (active) {
248 for (hwirq = GEF_PIC_NUM_IRQS - 1; hwirq > -1; hwirq--) {
249 if (active & (0x1 << hwirq))
250 break;
251 }
252 virq = irq_linear_revmap(gef_pic_irq_host,
253 (irq_hw_number_t)hwirq);
254 }
255
256 return virq;
257}
258
diff --git a/arch/powerpc/platforms/86xx/gef_pic.h b/arch/powerpc/platforms/86xx/gef_pic.h
new file mode 100644
index 000000000000..6149916da3f4
--- /dev/null
+++ b/arch/powerpc/platforms/86xx/gef_pic.h
@@ -0,0 +1,11 @@
1#ifndef __GEF_PIC_H__
2#define __GEF_PIC_H__
3
4#include <linux/init.h>
5
6void gef_pic_cascade(unsigned int, struct irq_desc *);
7unsigned int gef_pic_get_irq(void);
8void gef_pic_init(struct device_node *);
9
10#endif /* __GEF_PIC_H__ */
11
diff --git a/arch/powerpc/platforms/86xx/gef_sbc610.c b/arch/powerpc/platforms/86xx/gef_sbc610.c
index ee215002b1cf..821c45fac18b 100644
--- a/arch/powerpc/platforms/86xx/gef_sbc610.c
+++ b/arch/powerpc/platforms/86xx/gef_sbc610.c
@@ -39,6 +39,7 @@
39#include <sysdev/fsl_soc.h> 39#include <sysdev/fsl_soc.h>
40 40
41#include "mpc86xx.h" 41#include "mpc86xx.h"
42#include "gef_pic.h"
42 43
43#undef DEBUG 44#undef DEBUG
44 45
@@ -48,8 +49,31 @@
48#define DBG (fmt...) do { } while (0) 49#define DBG (fmt...) do { } while (0)
49#endif 50#endif
50 51
52void __iomem *sbc610_regs;
53
54static void __init gef_sbc610_init_irq(void)
55{
56 struct device_node *cascade_node = NULL;
57
58 mpc86xx_init_irq();
59
60 /*
61 * There is a simple interrupt handler in the main FPGA, this needs
62 * to be cascaded into the MPIC
63 */
64 cascade_node = of_find_compatible_node(NULL, NULL, "gef,fpga-pic");
65 if (!cascade_node) {
66 printk(KERN_WARNING "SBC610: No FPGA PIC\n");
67 return;
68 }
69
70 gef_pic_init(cascade_node);
71 of_node_put(cascade_node);
72}
73
51static void __init gef_sbc610_setup_arch(void) 74static void __init gef_sbc610_setup_arch(void)
52{ 75{
76 struct device_node *regs;
53#ifdef CONFIG_PCI 77#ifdef CONFIG_PCI
54 struct device_node *np; 78 struct device_node *np;
55 79
@@ -63,8 +87,43 @@ static void __init gef_sbc610_setup_arch(void)
63#ifdef CONFIG_SMP 87#ifdef CONFIG_SMP
64 mpc86xx_smp_init(); 88 mpc86xx_smp_init();
65#endif 89#endif
90
91 /* Remap basic board registers */
92 regs = of_find_compatible_node(NULL, NULL, "gef,fpga-regs");
93 if (regs) {
94 sbc610_regs = of_iomap(regs, 0);
95 if (sbc610_regs == NULL)
96 printk(KERN_WARNING "Unable to map board registers\n");
97 of_node_put(regs);
98 }
99}
100
101/* Return the PCB revision */
102static unsigned int gef_sbc610_get_pcb_rev(void)
103{
104 unsigned int reg;
105
106 reg = ioread32(sbc610_regs);
107 return (reg >> 8) & 0xff;
108}
109
110/* Return the board (software) revision */
111static unsigned int gef_sbc610_get_board_rev(void)
112{
113 unsigned int reg;
114
115 reg = ioread32(sbc610_regs);
116 return (reg >> 16) & 0xff;
66} 117}
67 118
119/* Return the FPGA revision */
120static unsigned int gef_sbc610_get_fpga_rev(void)
121{
122 unsigned int reg;
123
124 reg = ioread32(sbc610_regs);
125 return (reg >> 24) & 0xf;
126}
68 127
69static void gef_sbc610_show_cpuinfo(struct seq_file *m) 128static void gef_sbc610_show_cpuinfo(struct seq_file *m)
70{ 129{
@@ -73,6 +132,10 @@ static void gef_sbc610_show_cpuinfo(struct seq_file *m)
73 132
74 seq_printf(m, "Vendor\t\t: GE Fanuc Intelligent Platforms\n"); 133 seq_printf(m, "Vendor\t\t: GE Fanuc Intelligent Platforms\n");
75 134
135 seq_printf(m, "Revision\t: %u%c\n", gef_sbc610_get_pcb_rev(),
136 ('A' + gef_sbc610_get_board_rev() - 1));
137 seq_printf(m, "FPGA Revision\t: %u\n", gef_sbc610_get_fpga_rev());
138
76 seq_printf(m, "SVR\t\t: 0x%x\n", svid); 139 seq_printf(m, "SVR\t\t: 0x%x\n", svid);
77 seq_printf(m, "Memory\t\t: %d MB\n", memsize / (1024 * 1024)); 140 seq_printf(m, "Memory\t\t: %d MB\n", memsize / (1024 * 1024));
78} 141}
@@ -145,7 +208,7 @@ define_machine(gef_sbc610) {
145 .name = "GE Fanuc SBC610", 208 .name = "GE Fanuc SBC610",
146 .probe = gef_sbc610_probe, 209 .probe = gef_sbc610_probe,
147 .setup_arch = gef_sbc610_setup_arch, 210 .setup_arch = gef_sbc610_setup_arch,
148 .init_IRQ = mpc86xx_init_irq, 211 .init_IRQ = gef_sbc610_init_irq,
149 .show_cpuinfo = gef_sbc610_show_cpuinfo, 212 .show_cpuinfo = gef_sbc610_show_cpuinfo,
150 .get_irq = mpic_get_irq, 213 .get_irq = mpic_get_irq,
151 .restart = fsl_rstcr_restart, 214 .restart = fsl_rstcr_restart,
diff --git a/arch/powerpc/platforms/86xx/mpc8610_hpcd.c b/arch/powerpc/platforms/86xx/mpc8610_hpcd.c
index 5eedb710896e..e8d54ac5292c 100644
--- a/arch/powerpc/platforms/86xx/mpc8610_hpcd.c
+++ b/arch/powerpc/platforms/86xx/mpc8610_hpcd.c
@@ -238,7 +238,6 @@ static void __init mpc86xx_hpcd_setup_arch(void)
238 } 238 }
239#endif 239#endif
240#if defined(CONFIG_FB_FSL_DIU) || defined(CONFIG_FB_FSL_DIU_MODULE) 240#if defined(CONFIG_FB_FSL_DIU) || defined(CONFIG_FB_FSL_DIU_MODULE)
241 preallocate_diu_videomemory();
242 diu_ops.get_pixel_format = mpc8610hpcd_get_pixel_format; 241 diu_ops.get_pixel_format = mpc8610hpcd_get_pixel_format;
243 diu_ops.set_gamma_table = mpc8610hpcd_set_gamma_table; 242 diu_ops.set_gamma_table = mpc8610hpcd_set_gamma_table;
244 diu_ops.set_monitor_port = mpc8610hpcd_set_monitor_port; 243 diu_ops.set_monitor_port = mpc8610hpcd_set_monitor_port;
diff --git a/arch/powerpc/platforms/Kconfig b/arch/powerpc/platforms/Kconfig
index 9578c45b04fe..47e956c871fe 100644
--- a/arch/powerpc/platforms/Kconfig
+++ b/arch/powerpc/platforms/Kconfig
@@ -239,7 +239,8 @@ config TAU_AVERAGE
239 If in doubt, say N here. 239 If in doubt, say N here.
240 240
241config QUICC_ENGINE 241config QUICC_ENGINE
242 bool 242 bool "Freescale QUICC Engine (QE) Support"
243 depends on FSL_SOC
243 select PPC_LIB_RHEAP 244 select PPC_LIB_RHEAP
244 select CRC32 245 select CRC32
245 help 246 help
@@ -248,6 +249,15 @@ config QUICC_ENGINE
248 Selecting this option means that you wish to build a kernel 249 Selecting this option means that you wish to build a kernel
249 for a machine with a QE coprocessor. 250 for a machine with a QE coprocessor.
250 251
252config QE_GPIO
253 bool "QE GPIO support"
254 depends on QUICC_ENGINE
255 select GENERIC_GPIO
256 select ARCH_REQUIRE_GPIOLIB
257 help
258 Say Y here if you're going to use hardware that connects to the
259 QE GPIOs.
260
251config CPM2 261config CPM2
252 bool "Enable support for the CPM2 (Communications Processor Module)" 262 bool "Enable support for the CPM2 (Communications Processor Module)"
253 depends on MPC85xx || 8260 263 depends on MPC85xx || 8260