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-rw-r--r--arch/powerpc/platforms/pseries/xics.c949
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diff --git a/arch/powerpc/platforms/pseries/xics.c b/arch/powerpc/platforms/pseries/xics.c
deleted file mode 100644
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--- a/arch/powerpc/platforms/pseries/xics.c
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1/*
2 * arch/powerpc/platforms/pseries/xics.c
3 *
4 * Copyright 2000 IBM Corporation.
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
10 */
11
12#include <linux/types.h>
13#include <linux/threads.h>
14#include <linux/kernel.h>
15#include <linux/irq.h>
16#include <linux/smp.h>
17#include <linux/interrupt.h>
18#include <linux/init.h>
19#include <linux/radix-tree.h>
20#include <linux/cpu.h>
21#include <linux/msi.h>
22#include <linux/of.h>
23#include <linux/percpu.h>
24
25#include <asm/firmware.h>
26#include <asm/io.h>
27#include <asm/pgtable.h>
28#include <asm/smp.h>
29#include <asm/rtas.h>
30#include <asm/hvcall.h>
31#include <asm/machdep.h>
32
33#include "xics.h"
34#include "plpar_wrappers.h"
35
36static struct irq_host *xics_host;
37
38#define XICS_IPI 2
39#define XICS_IRQ_SPURIOUS 0
40
41/* Want a priority other than 0. Various HW issues require this. */
42#define DEFAULT_PRIORITY 5
43
44/*
45 * Mark IPIs as higher priority so we can take them inside interrupts that
46 * arent marked IRQF_DISABLED
47 */
48#define IPI_PRIORITY 4
49
50/* The least favored priority */
51#define LOWEST_PRIORITY 0xFF
52
53/* The number of priorities defined above */
54#define MAX_NUM_PRIORITIES 3
55
56static unsigned int default_server = 0xFF;
57static unsigned int default_distrib_server = 0;
58static unsigned int interrupt_server_size = 8;
59
60/* RTAS service tokens */
61static int ibm_get_xive;
62static int ibm_set_xive;
63static int ibm_int_on;
64static int ibm_int_off;
65
66struct xics_cppr {
67 unsigned char stack[MAX_NUM_PRIORITIES];
68 int index;
69};
70
71static DEFINE_PER_CPU(struct xics_cppr, xics_cppr);
72
73/* Direct hardware low level accessors */
74
75/* The part of the interrupt presentation layer that we care about */
76struct xics_ipl {
77 union {
78 u32 word;
79 u8 bytes[4];
80 } xirr_poll;
81 union {
82 u32 word;
83 u8 bytes[4];
84 } xirr;
85 u32 dummy;
86 union {
87 u32 word;
88 u8 bytes[4];
89 } qirr;
90};
91
92static struct xics_ipl __iomem *xics_per_cpu[NR_CPUS];
93
94static inline unsigned int direct_xirr_info_get(void)
95{
96 int cpu = smp_processor_id();
97
98 return in_be32(&xics_per_cpu[cpu]->xirr.word);
99}
100
101static inline void direct_xirr_info_set(unsigned int value)
102{
103 int cpu = smp_processor_id();
104
105 out_be32(&xics_per_cpu[cpu]->xirr.word, value);
106}
107
108static inline void direct_cppr_info(u8 value)
109{
110 int cpu = smp_processor_id();
111
112 out_8(&xics_per_cpu[cpu]->xirr.bytes[0], value);
113}
114
115static inline void direct_qirr_info(int n_cpu, u8 value)
116{
117 out_8(&xics_per_cpu[n_cpu]->qirr.bytes[0], value);
118}
119
120
121/* LPAR low level accessors */
122
123static inline unsigned int lpar_xirr_info_get(unsigned char cppr)
124{
125 unsigned long lpar_rc;
126 unsigned long return_value;
127
128 lpar_rc = plpar_xirr(&return_value, cppr);
129 if (lpar_rc != H_SUCCESS)
130 panic(" bad return code xirr - rc = %lx\n", lpar_rc);
131 return (unsigned int)return_value;
132}
133
134static inline void lpar_xirr_info_set(unsigned int value)
135{
136 unsigned long lpar_rc;
137
138 lpar_rc = plpar_eoi(value);
139 if (lpar_rc != H_SUCCESS)
140 panic("bad return code EOI - rc = %ld, value=%x\n", lpar_rc,
141 value);
142}
143
144static inline void lpar_cppr_info(u8 value)
145{
146 unsigned long lpar_rc;
147
148 lpar_rc = plpar_cppr(value);
149 if (lpar_rc != H_SUCCESS)
150 panic("bad return code cppr - rc = %lx\n", lpar_rc);
151}
152
153static inline void lpar_qirr_info(int n_cpu , u8 value)
154{
155 unsigned long lpar_rc;
156
157 lpar_rc = plpar_ipi(get_hard_smp_processor_id(n_cpu), value);
158 if (lpar_rc != H_SUCCESS)
159 panic("bad return code qirr - rc = %lx\n", lpar_rc);
160}
161
162
163/* Interface to generic irq subsystem */
164
165#ifdef CONFIG_SMP
166/*
167 * For the moment we only implement delivery to all cpus or one cpu.
168 *
169 * If the requested affinity is cpu_all_mask, we set global affinity.
170 * If not we set it to the first cpu in the mask, even if multiple cpus
171 * are set. This is so things like irqbalance (which set core and package
172 * wide affinities) do the right thing.
173 */
174static int get_irq_server(unsigned int virq, const struct cpumask *cpumask,
175 unsigned int strict_check)
176{
177
178 if (!distribute_irqs)
179 return default_server;
180
181 if (!cpumask_subset(cpu_possible_mask, cpumask)) {
182 int server = cpumask_first_and(cpu_online_mask, cpumask);
183
184 if (server < nr_cpu_ids)
185 return get_hard_smp_processor_id(server);
186
187 if (strict_check)
188 return -1;
189 }
190
191 /*
192 * Workaround issue with some versions of JS20 firmware that
193 * deliver interrupts to cpus which haven't been started. This
194 * happens when using the maxcpus= boot option.
195 */
196 if (cpumask_equal(cpu_online_mask, cpu_present_mask))
197 return default_distrib_server;
198
199 return default_server;
200}
201#else
202#define get_irq_server(virq, cpumask, strict_check) (default_server)
203#endif
204
205static void xics_unmask_irq(struct irq_data *d)
206{
207 unsigned int hwirq;
208 int call_status;
209 int server;
210
211 pr_devel("xics: unmask virq %d\n", d->irq);
212
213 hwirq = (unsigned int)irq_map[d->irq].hwirq;
214 pr_devel(" -> map to hwirq 0x%x\n", hwirq);
215 if (hwirq == XICS_IPI || hwirq == XICS_IRQ_SPURIOUS)
216 return;
217
218 server = get_irq_server(d->irq, d->affinity, 0);
219
220 call_status = rtas_call(ibm_set_xive, 3, 1, NULL, hwirq, server,
221 DEFAULT_PRIORITY);
222 if (call_status != 0) {
223 printk(KERN_ERR
224 "%s: ibm_set_xive irq %u server %x returned %d\n",
225 __func__, hwirq, server, call_status);
226 return;
227 }
228
229 /* Now unmask the interrupt (often a no-op) */
230 call_status = rtas_call(ibm_int_on, 1, 1, NULL, hwirq);
231 if (call_status != 0) {
232 printk(KERN_ERR "%s: ibm_int_on irq=%u returned %d\n",
233 __func__, hwirq, call_status);
234 return;
235 }
236}
237
238static unsigned int xics_startup(struct irq_data *d)
239{
240 /*
241 * The generic MSI code returns with the interrupt disabled on the
242 * card, using the MSI mask bits. Firmware doesn't appear to unmask
243 * at that level, so we do it here by hand.
244 */
245 if (d->msi_desc)
246 unmask_msi_irq(d);
247
248 /* unmask it */
249 xics_unmask_irq(d);
250 return 0;
251}
252
253static void xics_mask_real_irq(unsigned int hwirq)
254{
255 int call_status;
256
257 if (hwirq == XICS_IPI)
258 return;
259
260 call_status = rtas_call(ibm_int_off, 1, 1, NULL, hwirq);
261 if (call_status != 0) {
262 printk(KERN_ERR "%s: ibm_int_off irq=%u returned %d\n",
263 __func__, hwirq, call_status);
264 return;
265 }
266
267 /* Have to set XIVE to 0xff to be able to remove a slot */
268 call_status = rtas_call(ibm_set_xive, 3, 1, NULL, hwirq,
269 default_server, 0xff);
270 if (call_status != 0) {
271 printk(KERN_ERR "%s: ibm_set_xive(0xff) irq=%u returned %d\n",
272 __func__, hwirq, call_status);
273 return;
274 }
275}
276
277static void xics_mask_irq(struct irq_data *d)
278{
279 unsigned int hwirq;
280
281 pr_devel("xics: mask virq %d\n", d->irq);
282
283 hwirq = (unsigned int)irq_map[d->irq].hwirq;
284 if (hwirq == XICS_IPI || hwirq == XICS_IRQ_SPURIOUS)
285 return;
286 xics_mask_real_irq(hwirq);
287}
288
289static void xics_mask_unknown_vec(unsigned int vec)
290{
291 printk(KERN_ERR "Interrupt %u (real) is invalid, disabling it.\n", vec);
292 xics_mask_real_irq(vec);
293}
294
295static inline unsigned int xics_xirr_vector(unsigned int xirr)
296{
297 /*
298 * The top byte is the old cppr, to be restored on EOI.
299 * The remaining 24 bits are the vector.
300 */
301 return xirr & 0x00ffffff;
302}
303
304static void push_cppr(unsigned int vec)
305{
306 struct xics_cppr *os_cppr = &__get_cpu_var(xics_cppr);
307
308 if (WARN_ON(os_cppr->index >= MAX_NUM_PRIORITIES - 1))
309 return;
310
311 if (vec == XICS_IPI)
312 os_cppr->stack[++os_cppr->index] = IPI_PRIORITY;
313 else
314 os_cppr->stack[++os_cppr->index] = DEFAULT_PRIORITY;
315}
316
317static unsigned int xics_get_irq_direct(void)
318{
319 unsigned int xirr = direct_xirr_info_get();
320 unsigned int vec = xics_xirr_vector(xirr);
321 unsigned int irq;
322
323 if (vec == XICS_IRQ_SPURIOUS)
324 return NO_IRQ;
325
326 irq = irq_radix_revmap_lookup(xics_host, vec);
327 if (likely(irq != NO_IRQ)) {
328 push_cppr(vec);
329 return irq;
330 }
331
332 /* We don't have a linux mapping, so have rtas mask it. */
333 xics_mask_unknown_vec(vec);
334
335 /* We might learn about it later, so EOI it */
336 direct_xirr_info_set(xirr);
337 return NO_IRQ;
338}
339
340static unsigned int xics_get_irq_lpar(void)
341{
342 struct xics_cppr *os_cppr = &__get_cpu_var(xics_cppr);
343 unsigned int xirr = lpar_xirr_info_get(os_cppr->stack[os_cppr->index]);
344 unsigned int vec = xics_xirr_vector(xirr);
345 unsigned int irq;
346
347 if (vec == XICS_IRQ_SPURIOUS)
348 return NO_IRQ;
349
350 irq = irq_radix_revmap_lookup(xics_host, vec);
351 if (likely(irq != NO_IRQ)) {
352 push_cppr(vec);
353 return irq;
354 }
355
356 /* We don't have a linux mapping, so have RTAS mask it. */
357 xics_mask_unknown_vec(vec);
358
359 /* We might learn about it later, so EOI it */
360 lpar_xirr_info_set(xirr);
361 return NO_IRQ;
362}
363
364static unsigned char pop_cppr(void)
365{
366 struct xics_cppr *os_cppr = &__get_cpu_var(xics_cppr);
367
368 if (WARN_ON(os_cppr->index < 1))
369 return LOWEST_PRIORITY;
370
371 return os_cppr->stack[--os_cppr->index];
372}
373
374static void xics_eoi_direct(struct irq_data *d)
375{
376 unsigned int hwirq = (unsigned int)irq_map[d->irq].hwirq;
377
378 iosync();
379 direct_xirr_info_set((pop_cppr() << 24) | hwirq);
380}
381
382static void xics_eoi_lpar(struct irq_data *d)
383{
384 unsigned int hwirq = (unsigned int)irq_map[d->irq].hwirq;
385
386 iosync();
387 lpar_xirr_info_set((pop_cppr() << 24) | hwirq);
388}
389
390static int
391xics_set_affinity(struct irq_data *d, const struct cpumask *cpumask, bool force)
392{
393 unsigned int hwirq;
394 int status;
395 int xics_status[2];
396 int irq_server;
397
398 hwirq = (unsigned int)irq_map[d->irq].hwirq;
399 if (hwirq == XICS_IPI || hwirq == XICS_IRQ_SPURIOUS)
400 return -1;
401
402 status = rtas_call(ibm_get_xive, 1, 3, xics_status, hwirq);
403
404 if (status) {
405 printk(KERN_ERR "%s: ibm,get-xive irq=%u returns %d\n",
406 __func__, hwirq, status);
407 return -1;
408 }
409
410 irq_server = get_irq_server(d->irq, cpumask, 1);
411 if (irq_server == -1) {
412 char cpulist[128];
413 cpumask_scnprintf(cpulist, sizeof(cpulist), cpumask);
414 printk(KERN_WARNING
415 "%s: No online cpus in the mask %s for irq %d\n",
416 __func__, cpulist, d->irq);
417 return -1;
418 }
419
420 status = rtas_call(ibm_set_xive, 3, 1, NULL,
421 hwirq, irq_server, xics_status[1]);
422
423 if (status) {
424 printk(KERN_ERR "%s: ibm,set-xive irq=%u returns %d\n",
425 __func__, hwirq, status);
426 return -1;
427 }
428
429 return 0;
430}
431
432static struct irq_chip xics_pic_direct = {
433 .name = "XICS",
434 .irq_startup = xics_startup,
435 .irq_mask = xics_mask_irq,
436 .irq_unmask = xics_unmask_irq,
437 .irq_eoi = xics_eoi_direct,
438 .irq_set_affinity = xics_set_affinity
439};
440
441static struct irq_chip xics_pic_lpar = {
442 .name = "XICS",
443 .irq_startup = xics_startup,
444 .irq_mask = xics_mask_irq,
445 .irq_unmask = xics_unmask_irq,
446 .irq_eoi = xics_eoi_lpar,
447 .irq_set_affinity = xics_set_affinity
448};
449
450
451/* Interface to arch irq controller subsystem layer */
452
453/* Points to the irq_chip we're actually using */
454static struct irq_chip *xics_irq_chip;
455
456static int xics_host_match(struct irq_host *h, struct device_node *node)
457{
458 /* IBM machines have interrupt parents of various funky types for things
459 * like vdevices, events, etc... The trick we use here is to match
460 * everything here except the legacy 8259 which is compatible "chrp,iic"
461 */
462 return !of_device_is_compatible(node, "chrp,iic");
463}
464
465static int xics_host_map(struct irq_host *h, unsigned int virq,
466 irq_hw_number_t hw)
467{
468 pr_devel("xics: map virq %d, hwirq 0x%lx\n", virq, hw);
469
470 /* Insert the interrupt mapping into the radix tree for fast lookup */
471 irq_radix_revmap_insert(xics_host, virq, hw);
472
473 irq_set_status_flags(virq, IRQ_LEVEL);
474 irq_set_chip_and_handler(virq, xics_irq_chip, handle_fasteoi_irq);
475 return 0;
476}
477
478static int xics_host_xlate(struct irq_host *h, struct device_node *ct,
479 const u32 *intspec, unsigned int intsize,
480 irq_hw_number_t *out_hwirq, unsigned int *out_flags)
481
482{
483 /* Current xics implementation translates everything
484 * to level. It is not technically right for MSIs but this
485 * is irrelevant at this point. We might get smarter in the future
486 */
487 *out_hwirq = intspec[0];
488 *out_flags = IRQ_TYPE_LEVEL_LOW;
489
490 return 0;
491}
492
493static struct irq_host_ops xics_host_ops = {
494 .match = xics_host_match,
495 .map = xics_host_map,
496 .xlate = xics_host_xlate,
497};
498
499static void __init xics_init_host(void)
500{
501 if (firmware_has_feature(FW_FEATURE_LPAR))
502 xics_irq_chip = &xics_pic_lpar;
503 else
504 xics_irq_chip = &xics_pic_direct;
505
506 xics_host = irq_alloc_host(NULL, IRQ_HOST_MAP_TREE, 0, &xics_host_ops,
507 XICS_IRQ_SPURIOUS);
508 BUG_ON(xics_host == NULL);
509 irq_set_default_host(xics_host);
510}
511
512
513/* Inter-processor interrupt support */
514
515#ifdef CONFIG_SMP
516/*
517 * XICS only has a single IPI, so encode the messages per CPU
518 */
519static DEFINE_PER_CPU_SHARED_ALIGNED(unsigned long, xics_ipi_message);
520
521static inline void smp_xics_do_message(int cpu, int msg)
522{
523 unsigned long *tgt = &per_cpu(xics_ipi_message, cpu);
524
525 set_bit(msg, tgt);
526 mb();
527 if (firmware_has_feature(FW_FEATURE_LPAR))
528 lpar_qirr_info(cpu, IPI_PRIORITY);
529 else
530 direct_qirr_info(cpu, IPI_PRIORITY);
531}
532
533void smp_xics_message_pass(int target, int msg)
534{
535 unsigned int i;
536
537 if (target < NR_CPUS) {
538 smp_xics_do_message(target, msg);
539 } else {
540 for_each_online_cpu(i) {
541 if (target == MSG_ALL_BUT_SELF
542 && i == smp_processor_id())
543 continue;
544 smp_xics_do_message(i, msg);
545 }
546 }
547}
548
549static irqreturn_t xics_ipi_dispatch(int cpu)
550{
551 unsigned long *tgt = &per_cpu(xics_ipi_message, cpu);
552
553 mb(); /* order mmio clearing qirr */
554 while (*tgt) {
555 if (test_and_clear_bit(PPC_MSG_CALL_FUNCTION, tgt)) {
556 smp_message_recv(PPC_MSG_CALL_FUNCTION);
557 }
558 if (test_and_clear_bit(PPC_MSG_RESCHEDULE, tgt)) {
559 smp_message_recv(PPC_MSG_RESCHEDULE);
560 }
561 if (test_and_clear_bit(PPC_MSG_CALL_FUNC_SINGLE, tgt)) {
562 smp_message_recv(PPC_MSG_CALL_FUNC_SINGLE);
563 }
564#if defined(CONFIG_DEBUGGER) || defined(CONFIG_KEXEC)
565 if (test_and_clear_bit(PPC_MSG_DEBUGGER_BREAK, tgt)) {
566 smp_message_recv(PPC_MSG_DEBUGGER_BREAK);
567 }
568#endif
569 }
570 return IRQ_HANDLED;
571}
572
573static irqreturn_t xics_ipi_action_direct(int irq, void *dev_id)
574{
575 int cpu = smp_processor_id();
576
577 direct_qirr_info(cpu, 0xff);
578
579 return xics_ipi_dispatch(cpu);
580}
581
582static irqreturn_t xics_ipi_action_lpar(int irq, void *dev_id)
583{
584 int cpu = smp_processor_id();
585
586 lpar_qirr_info(cpu, 0xff);
587
588 return xics_ipi_dispatch(cpu);
589}
590
591static void xics_request_ipi(void)
592{
593 unsigned int ipi;
594 int rc;
595
596 ipi = irq_create_mapping(xics_host, XICS_IPI);
597 BUG_ON(ipi == NO_IRQ);
598
599 /*
600 * IPIs are marked IRQF_DISABLED as they must run with irqs
601 * disabled
602 */
603 irq_set_handler(ipi, handle_percpu_irq);
604 if (firmware_has_feature(FW_FEATURE_LPAR))
605 rc = request_irq(ipi, xics_ipi_action_lpar,
606 IRQF_DISABLED|IRQF_PERCPU, "IPI", NULL);
607 else
608 rc = request_irq(ipi, xics_ipi_action_direct,
609 IRQF_DISABLED|IRQF_PERCPU, "IPI", NULL);
610 BUG_ON(rc);
611}
612
613int __init smp_xics_probe(void)
614{
615 xics_request_ipi();
616
617 return cpumask_weight(cpu_possible_mask);
618}
619
620#endif /* CONFIG_SMP */
621
622
623/* Initialization */
624
625static void xics_update_irq_servers(void)
626{
627 int i, j;
628 struct device_node *np;
629 u32 ilen;
630 const u32 *ireg;
631 u32 hcpuid;
632
633 /* Find the server numbers for the boot cpu. */
634 np = of_get_cpu_node(boot_cpuid, NULL);
635 BUG_ON(!np);
636
637 ireg = of_get_property(np, "ibm,ppc-interrupt-gserver#s", &ilen);
638 if (!ireg) {
639 of_node_put(np);
640 return;
641 }
642
643 i = ilen / sizeof(int);
644 hcpuid = get_hard_smp_processor_id(boot_cpuid);
645
646 /* Global interrupt distribution server is specified in the last
647 * entry of "ibm,ppc-interrupt-gserver#s" property. Get the last
648 * entry fom this property for current boot cpu id and use it as
649 * default distribution server
650 */
651 for (j = 0; j < i; j += 2) {
652 if (ireg[j] == hcpuid) {
653 default_server = hcpuid;
654 default_distrib_server = ireg[j+1];
655 }
656 }
657
658 of_node_put(np);
659}
660
661static void __init xics_map_one_cpu(int hw_id, unsigned long addr,
662 unsigned long size)
663{
664 int i;
665
666 /* This may look gross but it's good enough for now, we don't quite
667 * have a hard -> linux processor id matching.
668 */
669 for_each_possible_cpu(i) {
670 if (!cpu_present(i))
671 continue;
672 if (hw_id == get_hard_smp_processor_id(i)) {
673 xics_per_cpu[i] = ioremap(addr, size);
674 return;
675 }
676 }
677}
678
679static void __init xics_init_one_node(struct device_node *np,
680 unsigned int *indx)
681{
682 unsigned int ilen;
683 const u32 *ireg;
684
685 /* This code does the theorically broken assumption that the interrupt
686 * server numbers are the same as the hard CPU numbers.
687 * This happens to be the case so far but we are playing with fire...
688 * should be fixed one of these days. -BenH.
689 */
690 ireg = of_get_property(np, "ibm,interrupt-server-ranges", NULL);
691
692 /* Do that ever happen ? we'll know soon enough... but even good'old
693 * f80 does have that property ..
694 */
695 WARN_ON(ireg == NULL);
696 if (ireg) {
697 /*
698 * set node starting index for this node
699 */
700 *indx = *ireg;
701 }
702 ireg = of_get_property(np, "reg", &ilen);
703 if (!ireg)
704 panic("xics_init_IRQ: can't find interrupt reg property");
705
706 while (ilen >= (4 * sizeof(u32))) {
707 unsigned long addr, size;
708
709 /* XXX Use proper OF parsing code here !!! */
710 addr = (unsigned long)*ireg++ << 32;
711 ilen -= sizeof(u32);
712 addr |= *ireg++;
713 ilen -= sizeof(u32);
714 size = (unsigned long)*ireg++ << 32;
715 ilen -= sizeof(u32);
716 size |= *ireg++;
717 ilen -= sizeof(u32);
718 xics_map_one_cpu(*indx, addr, size);
719 (*indx)++;
720 }
721}
722
723void __init xics_init_IRQ(void)
724{
725 struct device_node *np;
726 u32 indx = 0;
727 int found = 0;
728 const u32 *isize;
729
730 ppc64_boot_msg(0x20, "XICS Init");
731
732 ibm_get_xive = rtas_token("ibm,get-xive");
733 ibm_set_xive = rtas_token("ibm,set-xive");
734 ibm_int_on = rtas_token("ibm,int-on");
735 ibm_int_off = rtas_token("ibm,int-off");
736
737 for_each_node_by_type(np, "PowerPC-External-Interrupt-Presentation") {
738 found = 1;
739 if (firmware_has_feature(FW_FEATURE_LPAR)) {
740 of_node_put(np);
741 break;
742 }
743 xics_init_one_node(np, &indx);
744 }
745 if (found == 0)
746 return;
747
748 /* get the bit size of server numbers */
749 found = 0;
750
751 for_each_compatible_node(np, NULL, "ibm,ppc-xics") {
752 isize = of_get_property(np, "ibm,interrupt-server#-size", NULL);
753
754 if (!isize)
755 continue;
756
757 if (!found) {
758 interrupt_server_size = *isize;
759 found = 1;
760 } else if (*isize != interrupt_server_size) {
761 printk(KERN_WARNING "XICS: "
762 "mismatched ibm,interrupt-server#-size\n");
763 interrupt_server_size = max(*isize,
764 interrupt_server_size);
765 }
766 }
767
768 xics_update_irq_servers();
769 xics_init_host();
770
771 if (firmware_has_feature(FW_FEATURE_LPAR))
772 ppc_md.get_irq = xics_get_irq_lpar;
773 else
774 ppc_md.get_irq = xics_get_irq_direct;
775
776 xics_setup_cpu();
777
778 ppc64_boot_msg(0x21, "XICS Done");
779}
780
781/* Cpu startup, shutdown, and hotplug */
782
783static void xics_set_cpu_priority(unsigned char cppr)
784{
785 struct xics_cppr *os_cppr = &__get_cpu_var(xics_cppr);
786
787 /*
788 * we only really want to set the priority when there's
789 * just one cppr value on the stack
790 */
791 WARN_ON(os_cppr->index != 0);
792
793 os_cppr->stack[0] = cppr;
794
795 if (firmware_has_feature(FW_FEATURE_LPAR))
796 lpar_cppr_info(cppr);
797 else
798 direct_cppr_info(cppr);
799 iosync();
800}
801
802/* Have the calling processor join or leave the specified global queue */
803static void xics_set_cpu_giq(unsigned int gserver, unsigned int join)
804{
805 int index;
806 int status;
807
808 if (!rtas_indicator_present(GLOBAL_INTERRUPT_QUEUE, NULL))
809 return;
810
811 index = (1UL << interrupt_server_size) - 1 - gserver;
812
813 status = rtas_set_indicator_fast(GLOBAL_INTERRUPT_QUEUE, index, join);
814
815 WARN(status < 0, "set-indicator(%d, %d, %u) returned %d\n",
816 GLOBAL_INTERRUPT_QUEUE, index, join, status);
817}
818
819void xics_setup_cpu(void)
820{
821 xics_set_cpu_priority(LOWEST_PRIORITY);
822
823 xics_set_cpu_giq(default_distrib_server, 1);
824}
825
826void xics_teardown_cpu(void)
827{
828 struct xics_cppr *os_cppr = &__get_cpu_var(xics_cppr);
829 int cpu = smp_processor_id();
830
831 /*
832 * we have to reset the cppr index to 0 because we're
833 * not going to return from the IPI
834 */
835 os_cppr->index = 0;
836 xics_set_cpu_priority(0);
837
838 /* Clear any pending IPI request */
839 if (firmware_has_feature(FW_FEATURE_LPAR))
840 lpar_qirr_info(cpu, 0xff);
841 else
842 direct_qirr_info(cpu, 0xff);
843}
844
845void xics_kexec_teardown_cpu(int secondary)
846{
847 xics_teardown_cpu();
848
849 /*
850 * we take the ipi irq but and never return so we
851 * need to EOI the IPI, but want to leave our priority 0
852 *
853 * should we check all the other interrupts too?
854 * should we be flagging idle loop instead?
855 * or creating some task to be scheduled?
856 */
857
858 if (firmware_has_feature(FW_FEATURE_LPAR))
859 lpar_xirr_info_set((0x00 << 24) | XICS_IPI);
860 else
861 direct_xirr_info_set((0x00 << 24) | XICS_IPI);
862
863 /*
864 * Some machines need to have at least one cpu in the GIQ,
865 * so leave the master cpu in the group.
866 */
867 if (secondary)
868 xics_set_cpu_giq(default_distrib_server, 0);
869}
870
871#ifdef CONFIG_HOTPLUG_CPU
872
873/* Interrupts are disabled. */
874void xics_migrate_irqs_away(void)
875{
876 int cpu = smp_processor_id(), hw_cpu = hard_smp_processor_id();
877 int virq;
878
879 /* If we used to be the default server, move to the new "boot_cpuid" */
880 if (hw_cpu == default_server)
881 xics_update_irq_servers();
882
883 /* Reject any interrupt that was queued to us... */
884 xics_set_cpu_priority(0);
885
886 /* Remove ourselves from the global interrupt queue */
887 xics_set_cpu_giq(default_distrib_server, 0);
888
889 /* Allow IPIs again... */
890 xics_set_cpu_priority(DEFAULT_PRIORITY);
891
892 for_each_irq(virq) {
893 struct irq_desc *desc;
894 struct irq_chip *chip;
895 unsigned int hwirq;
896 int xics_status[2];
897 int status;
898 unsigned long flags;
899
900 /* We can't set affinity on ISA interrupts */
901 if (virq < NUM_ISA_INTERRUPTS)
902 continue;
903 if (irq_map[virq].host != xics_host)
904 continue;
905 hwirq = (unsigned int)irq_map[virq].hwirq;
906 /* We need to get IPIs still. */
907 if (hwirq == XICS_IPI || hwirq == XICS_IRQ_SPURIOUS)
908 continue;
909
910 desc = irq_to_desc(virq);
911
912 /* We only need to migrate enabled IRQS */
913 if (desc == NULL || desc->action == NULL)
914 continue;
915
916 chip = irq_desc_get_chip(desc);
917 if (chip == NULL || chip->irq_set_affinity == NULL)
918 continue;
919
920 raw_spin_lock_irqsave(&desc->lock, flags);
921
922 status = rtas_call(ibm_get_xive, 1, 3, xics_status, hwirq);
923 if (status) {
924 printk(KERN_ERR "%s: ibm,get-xive irq=%u returns %d\n",
925 __func__, hwirq, status);
926 goto unlock;
927 }
928
929 /*
930 * We only support delivery to all cpus or to one cpu.
931 * The irq has to be migrated only in the single cpu
932 * case.
933 */
934 if (xics_status[0] != hw_cpu)
935 goto unlock;
936
937 /* This is expected during cpu offline. */
938 if (cpu_online(cpu))
939 printk(KERN_WARNING "IRQ %u affinity broken off cpu %u\n",
940 virq, cpu);
941
942 /* Reset affinity to all cpus */
943 cpumask_setall(desc->irq_data.affinity);
944 chip->irq_set_affinity(&desc->irq_data, cpu_all_mask, true);
945unlock:
946 raw_spin_unlock_irqrestore(&desc->lock, flags);
947 }
948}
949#endif
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