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-rw-r--r--arch/powerpc/platforms/pseries/eeh.c79
1 files changed, 0 insertions, 79 deletions
diff --git a/arch/powerpc/platforms/pseries/eeh.c b/arch/powerpc/platforms/pseries/eeh.c
index 3c8658ea13f2..b5fcecb06731 100644
--- a/arch/powerpc/platforms/pseries/eeh.c
+++ b/arch/powerpc/platforms/pseries/eeh.c
@@ -610,85 +610,6 @@ int eeh_reset_pe(struct eeh_dev *edev)
610 return -1; 610 return -1;
611} 611}
612 612
613/** Save and restore of PCI BARs
614 *
615 * Although firmware will set up BARs during boot, it doesn't
616 * set up device BAR's after a device reset, although it will,
617 * if requested, set up bridge configuration. Thus, we need to
618 * configure the PCI devices ourselves.
619 */
620
621/**
622 * eeh_restore_one_device_bars - Restore the Base Address Registers for one device
623 * @edev: PCI device associated EEH device
624 *
625 * Loads the PCI configuration space base address registers,
626 * the expansion ROM base address, the latency timer, and etc.
627 * from the saved values in the device node.
628 */
629static inline void eeh_restore_one_device_bars(struct eeh_dev *edev)
630{
631 int i;
632 u32 cmd;
633 struct device_node *dn = eeh_dev_to_of_node(edev);
634
635 if (!edev->phb)
636 return;
637
638 for (i=4; i<10; i++) {
639 eeh_ops->write_config(dn, i*4, 4, edev->config_space[i]);
640 }
641
642 /* 12 == Expansion ROM Address */
643 eeh_ops->write_config(dn, 12*4, 4, edev->config_space[12]);
644
645#define BYTE_SWAP(OFF) (8*((OFF)/4)+3-(OFF))
646#define SAVED_BYTE(OFF) (((u8 *)(edev->config_space))[BYTE_SWAP(OFF)])
647
648 eeh_ops->write_config(dn, PCI_CACHE_LINE_SIZE, 1,
649 SAVED_BYTE(PCI_CACHE_LINE_SIZE));
650
651 eeh_ops->write_config(dn, PCI_LATENCY_TIMER, 1,
652 SAVED_BYTE(PCI_LATENCY_TIMER));
653
654 /* max latency, min grant, interrupt pin and line */
655 eeh_ops->write_config(dn, 15*4, 4, edev->config_space[15]);
656
657 /* Restore PERR & SERR bits, some devices require it,
658 * don't touch the other command bits
659 */
660 eeh_ops->read_config(dn, PCI_COMMAND, 4, &cmd);
661 if (edev->config_space[1] & PCI_COMMAND_PARITY)
662 cmd |= PCI_COMMAND_PARITY;
663 else
664 cmd &= ~PCI_COMMAND_PARITY;
665 if (edev->config_space[1] & PCI_COMMAND_SERR)
666 cmd |= PCI_COMMAND_SERR;
667 else
668 cmd &= ~PCI_COMMAND_SERR;
669 eeh_ops->write_config(dn, PCI_COMMAND, 4, cmd);
670}
671
672/**
673 * eeh_restore_bars - Restore the PCI config space info
674 * @edev: EEH device
675 *
676 * This routine performs a recursive walk to the children
677 * of this device as well.
678 */
679void eeh_restore_bars(struct eeh_dev *edev)
680{
681 struct device_node *dn;
682 if (!edev)
683 return;
684
685 if ((edev->mode & EEH_MODE_SUPPORTED) && !IS_BRIDGE(edev->class_code))
686 eeh_restore_one_device_bars(edev);
687
688 for_each_child_of_node(eeh_dev_to_of_node(edev), dn)
689 eeh_restore_bars(of_node_to_eeh_dev(dn));
690}
691
692/** 613/**
693 * eeh_save_bars - Save device bars 614 * eeh_save_bars - Save device bars
694 * @edev: PCI device associated EEH device 615 * @edev: PCI device associated EEH device