diff options
Diffstat (limited to 'arch/powerpc/platforms/powernv/pci-ioda.c')
-rw-r--r-- | arch/powerpc/platforms/powernv/pci-ioda.c | 797 |
1 files changed, 754 insertions, 43 deletions
diff --git a/arch/powerpc/platforms/powernv/pci-ioda.c b/arch/powerpc/platforms/powernv/pci-ioda.c index 6c9ff2b95119..920c252d1f49 100644 --- a/arch/powerpc/platforms/powernv/pci-ioda.c +++ b/arch/powerpc/platforms/powernv/pci-ioda.c | |||
@@ -44,6 +44,9 @@ | |||
44 | #include "powernv.h" | 44 | #include "powernv.h" |
45 | #include "pci.h" | 45 | #include "pci.h" |
46 | 46 | ||
47 | /* 256M DMA window, 4K TCE pages, 8 bytes TCE */ | ||
48 | #define TCE32_TABLE_SIZE ((0x10000000 / 0x1000) * 8) | ||
49 | |||
47 | static void pe_level_printk(const struct pnv_ioda_pe *pe, const char *level, | 50 | static void pe_level_printk(const struct pnv_ioda_pe *pe, const char *level, |
48 | const char *fmt, ...) | 51 | const char *fmt, ...) |
49 | { | 52 | { |
@@ -56,11 +59,18 @@ static void pe_level_printk(const struct pnv_ioda_pe *pe, const char *level, | |||
56 | vaf.fmt = fmt; | 59 | vaf.fmt = fmt; |
57 | vaf.va = &args; | 60 | vaf.va = &args; |
58 | 61 | ||
59 | if (pe->pdev) | 62 | if (pe->flags & PNV_IODA_PE_DEV) |
60 | strlcpy(pfix, dev_name(&pe->pdev->dev), sizeof(pfix)); | 63 | strlcpy(pfix, dev_name(&pe->pdev->dev), sizeof(pfix)); |
61 | else | 64 | else if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL)) |
62 | sprintf(pfix, "%04x:%02x ", | 65 | sprintf(pfix, "%04x:%02x ", |
63 | pci_domain_nr(pe->pbus), pe->pbus->number); | 66 | pci_domain_nr(pe->pbus), pe->pbus->number); |
67 | #ifdef CONFIG_PCI_IOV | ||
68 | else if (pe->flags & PNV_IODA_PE_VF) | ||
69 | sprintf(pfix, "%04x:%02x:%2x.%d", | ||
70 | pci_domain_nr(pe->parent_dev->bus), | ||
71 | (pe->rid & 0xff00) >> 8, | ||
72 | PCI_SLOT(pe->rid), PCI_FUNC(pe->rid)); | ||
73 | #endif /* CONFIG_PCI_IOV*/ | ||
64 | 74 | ||
65 | printk("%spci %s: [PE# %.3d] %pV", | 75 | printk("%spci %s: [PE# %.3d] %pV", |
66 | level, pfix, pe->pe_number, &vaf); | 76 | level, pfix, pe->pe_number, &vaf); |
@@ -591,7 +601,7 @@ static int pnv_ioda_set_peltv(struct pnv_phb *phb, | |||
591 | bool is_add) | 601 | bool is_add) |
592 | { | 602 | { |
593 | struct pnv_ioda_pe *slave; | 603 | struct pnv_ioda_pe *slave; |
594 | struct pci_dev *pdev; | 604 | struct pci_dev *pdev = NULL; |
595 | int ret; | 605 | int ret; |
596 | 606 | ||
597 | /* | 607 | /* |
@@ -630,8 +640,12 @@ static int pnv_ioda_set_peltv(struct pnv_phb *phb, | |||
630 | 640 | ||
631 | if (pe->flags & (PNV_IODA_PE_BUS_ALL | PNV_IODA_PE_BUS)) | 641 | if (pe->flags & (PNV_IODA_PE_BUS_ALL | PNV_IODA_PE_BUS)) |
632 | pdev = pe->pbus->self; | 642 | pdev = pe->pbus->self; |
633 | else | 643 | else if (pe->flags & PNV_IODA_PE_DEV) |
634 | pdev = pe->pdev->bus->self; | 644 | pdev = pe->pdev->bus->self; |
645 | #ifdef CONFIG_PCI_IOV | ||
646 | else if (pe->flags & PNV_IODA_PE_VF) | ||
647 | pdev = pe->parent_dev->bus->self; | ||
648 | #endif /* CONFIG_PCI_IOV */ | ||
635 | while (pdev) { | 649 | while (pdev) { |
636 | struct pci_dn *pdn = pci_get_pdn(pdev); | 650 | struct pci_dn *pdn = pci_get_pdn(pdev); |
637 | struct pnv_ioda_pe *parent; | 651 | struct pnv_ioda_pe *parent; |
@@ -649,6 +663,87 @@ static int pnv_ioda_set_peltv(struct pnv_phb *phb, | |||
649 | return 0; | 663 | return 0; |
650 | } | 664 | } |
651 | 665 | ||
666 | #ifdef CONFIG_PCI_IOV | ||
667 | static int pnv_ioda_deconfigure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe) | ||
668 | { | ||
669 | struct pci_dev *parent; | ||
670 | uint8_t bcomp, dcomp, fcomp; | ||
671 | int64_t rc; | ||
672 | long rid_end, rid; | ||
673 | |||
674 | /* Currently, we just deconfigure VF PE. Bus PE will always there.*/ | ||
675 | if (pe->pbus) { | ||
676 | int count; | ||
677 | |||
678 | dcomp = OPAL_IGNORE_RID_DEVICE_NUMBER; | ||
679 | fcomp = OPAL_IGNORE_RID_FUNCTION_NUMBER; | ||
680 | parent = pe->pbus->self; | ||
681 | if (pe->flags & PNV_IODA_PE_BUS_ALL) | ||
682 | count = pe->pbus->busn_res.end - pe->pbus->busn_res.start + 1; | ||
683 | else | ||
684 | count = 1; | ||
685 | |||
686 | switch(count) { | ||
687 | case 1: bcomp = OpalPciBusAll; break; | ||
688 | case 2: bcomp = OpalPciBus7Bits; break; | ||
689 | case 4: bcomp = OpalPciBus6Bits; break; | ||
690 | case 8: bcomp = OpalPciBus5Bits; break; | ||
691 | case 16: bcomp = OpalPciBus4Bits; break; | ||
692 | case 32: bcomp = OpalPciBus3Bits; break; | ||
693 | default: | ||
694 | dev_err(&pe->pbus->dev, "Number of subordinate buses %d unsupported\n", | ||
695 | count); | ||
696 | /* Do an exact match only */ | ||
697 | bcomp = OpalPciBusAll; | ||
698 | } | ||
699 | rid_end = pe->rid + (count << 8); | ||
700 | } else { | ||
701 | if (pe->flags & PNV_IODA_PE_VF) | ||
702 | parent = pe->parent_dev; | ||
703 | else | ||
704 | parent = pe->pdev->bus->self; | ||
705 | bcomp = OpalPciBusAll; | ||
706 | dcomp = OPAL_COMPARE_RID_DEVICE_NUMBER; | ||
707 | fcomp = OPAL_COMPARE_RID_FUNCTION_NUMBER; | ||
708 | rid_end = pe->rid + 1; | ||
709 | } | ||
710 | |||
711 | /* Clear the reverse map */ | ||
712 | for (rid = pe->rid; rid < rid_end; rid++) | ||
713 | phb->ioda.pe_rmap[rid] = 0; | ||
714 | |||
715 | /* Release from all parents PELT-V */ | ||
716 | while (parent) { | ||
717 | struct pci_dn *pdn = pci_get_pdn(parent); | ||
718 | if (pdn && pdn->pe_number != IODA_INVALID_PE) { | ||
719 | rc = opal_pci_set_peltv(phb->opal_id, pdn->pe_number, | ||
720 | pe->pe_number, OPAL_REMOVE_PE_FROM_DOMAIN); | ||
721 | /* XXX What to do in case of error ? */ | ||
722 | } | ||
723 | parent = parent->bus->self; | ||
724 | } | ||
725 | |||
726 | opal_pci_eeh_freeze_set(phb->opal_id, pe->pe_number, | ||
727 | OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); | ||
728 | |||
729 | /* Disassociate PE in PELT */ | ||
730 | rc = opal_pci_set_peltv(phb->opal_id, pe->pe_number, | ||
731 | pe->pe_number, OPAL_REMOVE_PE_FROM_DOMAIN); | ||
732 | if (rc) | ||
733 | pe_warn(pe, "OPAL error %ld remove self from PELTV\n", rc); | ||
734 | rc = opal_pci_set_pe(phb->opal_id, pe->pe_number, pe->rid, | ||
735 | bcomp, dcomp, fcomp, OPAL_UNMAP_PE); | ||
736 | if (rc) | ||
737 | pe_err(pe, "OPAL error %ld trying to setup PELT table\n", rc); | ||
738 | |||
739 | pe->pbus = NULL; | ||
740 | pe->pdev = NULL; | ||
741 | pe->parent_dev = NULL; | ||
742 | |||
743 | return 0; | ||
744 | } | ||
745 | #endif /* CONFIG_PCI_IOV */ | ||
746 | |||
652 | static int pnv_ioda_configure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe) | 747 | static int pnv_ioda_configure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe) |
653 | { | 748 | { |
654 | struct pci_dev *parent; | 749 | struct pci_dev *parent; |
@@ -675,15 +770,19 @@ static int pnv_ioda_configure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe) | |||
675 | case 16: bcomp = OpalPciBus4Bits; break; | 770 | case 16: bcomp = OpalPciBus4Bits; break; |
676 | case 32: bcomp = OpalPciBus3Bits; break; | 771 | case 32: bcomp = OpalPciBus3Bits; break; |
677 | default: | 772 | default: |
678 | pr_err("%s: Number of subordinate busses %d" | 773 | dev_err(&pe->pbus->dev, "Number of subordinate buses %d unsupported\n", |
679 | " unsupported\n", | 774 | count); |
680 | pci_name(pe->pbus->self), count); | ||
681 | /* Do an exact match only */ | 775 | /* Do an exact match only */ |
682 | bcomp = OpalPciBusAll; | 776 | bcomp = OpalPciBusAll; |
683 | } | 777 | } |
684 | rid_end = pe->rid + (count << 8); | 778 | rid_end = pe->rid + (count << 8); |
685 | } else { | 779 | } else { |
686 | parent = pe->pdev->bus->self; | 780 | #ifdef CONFIG_PCI_IOV |
781 | if (pe->flags & PNV_IODA_PE_VF) | ||
782 | parent = pe->parent_dev; | ||
783 | else | ||
784 | #endif /* CONFIG_PCI_IOV */ | ||
785 | parent = pe->pdev->bus->self; | ||
687 | bcomp = OpalPciBusAll; | 786 | bcomp = OpalPciBusAll; |
688 | dcomp = OPAL_COMPARE_RID_DEVICE_NUMBER; | 787 | dcomp = OPAL_COMPARE_RID_DEVICE_NUMBER; |
689 | fcomp = OPAL_COMPARE_RID_FUNCTION_NUMBER; | 788 | fcomp = OPAL_COMPARE_RID_FUNCTION_NUMBER; |
@@ -774,6 +873,78 @@ static unsigned int pnv_ioda_dma_weight(struct pci_dev *dev) | |||
774 | return 10; | 873 | return 10; |
775 | } | 874 | } |
776 | 875 | ||
876 | #ifdef CONFIG_PCI_IOV | ||
877 | static int pnv_pci_vf_resource_shift(struct pci_dev *dev, int offset) | ||
878 | { | ||
879 | struct pci_dn *pdn = pci_get_pdn(dev); | ||
880 | int i; | ||
881 | struct resource *res, res2; | ||
882 | resource_size_t size; | ||
883 | u16 num_vfs; | ||
884 | |||
885 | if (!dev->is_physfn) | ||
886 | return -EINVAL; | ||
887 | |||
888 | /* | ||
889 | * "offset" is in VFs. The M64 windows are sized so that when they | ||
890 | * are segmented, each segment is the same size as the IOV BAR. | ||
891 | * Each segment is in a separate PE, and the high order bits of the | ||
892 | * address are the PE number. Therefore, each VF's BAR is in a | ||
893 | * separate PE, and changing the IOV BAR start address changes the | ||
894 | * range of PEs the VFs are in. | ||
895 | */ | ||
896 | num_vfs = pdn->num_vfs; | ||
897 | for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { | ||
898 | res = &dev->resource[i + PCI_IOV_RESOURCES]; | ||
899 | if (!res->flags || !res->parent) | ||
900 | continue; | ||
901 | |||
902 | if (!pnv_pci_is_mem_pref_64(res->flags)) | ||
903 | continue; | ||
904 | |||
905 | /* | ||
906 | * The actual IOV BAR range is determined by the start address | ||
907 | * and the actual size for num_vfs VFs BAR. This check is to | ||
908 | * make sure that after shifting, the range will not overlap | ||
909 | * with another device. | ||
910 | */ | ||
911 | size = pci_iov_resource_size(dev, i + PCI_IOV_RESOURCES); | ||
912 | res2.flags = res->flags; | ||
913 | res2.start = res->start + (size * offset); | ||
914 | res2.end = res2.start + (size * num_vfs) - 1; | ||
915 | |||
916 | if (res2.end > res->end) { | ||
917 | dev_err(&dev->dev, "VF BAR%d: %pR would extend past %pR (trying to enable %d VFs shifted by %d)\n", | ||
918 | i, &res2, res, num_vfs, offset); | ||
919 | return -EBUSY; | ||
920 | } | ||
921 | } | ||
922 | |||
923 | /* | ||
924 | * After doing so, there would be a "hole" in the /proc/iomem when | ||
925 | * offset is a positive value. It looks like the device return some | ||
926 | * mmio back to the system, which actually no one could use it. | ||
927 | */ | ||
928 | for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { | ||
929 | res = &dev->resource[i + PCI_IOV_RESOURCES]; | ||
930 | if (!res->flags || !res->parent) | ||
931 | continue; | ||
932 | |||
933 | if (!pnv_pci_is_mem_pref_64(res->flags)) | ||
934 | continue; | ||
935 | |||
936 | size = pci_iov_resource_size(dev, i + PCI_IOV_RESOURCES); | ||
937 | res2 = *res; | ||
938 | res->start += size * offset; | ||
939 | |||
940 | dev_info(&dev->dev, "VF BAR%d: %pR shifted to %pR (enabling %d VFs shifted by %d)\n", | ||
941 | i, &res2, res, num_vfs, offset); | ||
942 | pci_update_resource(dev, i + PCI_IOV_RESOURCES); | ||
943 | } | ||
944 | return 0; | ||
945 | } | ||
946 | #endif /* CONFIG_PCI_IOV */ | ||
947 | |||
777 | #if 0 | 948 | #if 0 |
778 | static struct pnv_ioda_pe *pnv_ioda_setup_dev_PE(struct pci_dev *dev) | 949 | static struct pnv_ioda_pe *pnv_ioda_setup_dev_PE(struct pci_dev *dev) |
779 | { | 950 | { |
@@ -857,7 +1028,6 @@ static void pnv_ioda_setup_same_PE(struct pci_bus *bus, struct pnv_ioda_pe *pe) | |||
857 | pci_name(dev)); | 1028 | pci_name(dev)); |
858 | continue; | 1029 | continue; |
859 | } | 1030 | } |
860 | pdn->pcidev = dev; | ||
861 | pdn->pe_number = pe->pe_number; | 1031 | pdn->pe_number = pe->pe_number; |
862 | pe->dma_weight += pnv_ioda_dma_weight(dev); | 1032 | pe->dma_weight += pnv_ioda_dma_weight(dev); |
863 | if ((pe->flags & PNV_IODA_PE_BUS_ALL) && dev->subordinate) | 1033 | if ((pe->flags & PNV_IODA_PE_BUS_ALL) && dev->subordinate) |
@@ -916,6 +1086,10 @@ static void pnv_ioda_setup_bus_PE(struct pci_bus *bus, int all) | |||
916 | return; | 1086 | return; |
917 | } | 1087 | } |
918 | 1088 | ||
1089 | pe->tce32_table = kzalloc_node(sizeof(struct iommu_table), | ||
1090 | GFP_KERNEL, hose->node); | ||
1091 | pe->tce32_table->data = pe; | ||
1092 | |||
919 | /* Associate it with all child devices */ | 1093 | /* Associate it with all child devices */ |
920 | pnv_ioda_setup_same_PE(bus, pe); | 1094 | pnv_ioda_setup_same_PE(bus, pe); |
921 | 1095 | ||
@@ -974,6 +1148,441 @@ static void pnv_pci_ioda_setup_PEs(void) | |||
974 | } | 1148 | } |
975 | } | 1149 | } |
976 | 1150 | ||
1151 | #ifdef CONFIG_PCI_IOV | ||
1152 | static int pnv_pci_vf_release_m64(struct pci_dev *pdev) | ||
1153 | { | ||
1154 | struct pci_bus *bus; | ||
1155 | struct pci_controller *hose; | ||
1156 | struct pnv_phb *phb; | ||
1157 | struct pci_dn *pdn; | ||
1158 | int i, j; | ||
1159 | |||
1160 | bus = pdev->bus; | ||
1161 | hose = pci_bus_to_host(bus); | ||
1162 | phb = hose->private_data; | ||
1163 | pdn = pci_get_pdn(pdev); | ||
1164 | |||
1165 | for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) | ||
1166 | for (j = 0; j < M64_PER_IOV; j++) { | ||
1167 | if (pdn->m64_wins[i][j] == IODA_INVALID_M64) | ||
1168 | continue; | ||
1169 | opal_pci_phb_mmio_enable(phb->opal_id, | ||
1170 | OPAL_M64_WINDOW_TYPE, pdn->m64_wins[i][j], 0); | ||
1171 | clear_bit(pdn->m64_wins[i][j], &phb->ioda.m64_bar_alloc); | ||
1172 | pdn->m64_wins[i][j] = IODA_INVALID_M64; | ||
1173 | } | ||
1174 | |||
1175 | return 0; | ||
1176 | } | ||
1177 | |||
1178 | static int pnv_pci_vf_assign_m64(struct pci_dev *pdev, u16 num_vfs) | ||
1179 | { | ||
1180 | struct pci_bus *bus; | ||
1181 | struct pci_controller *hose; | ||
1182 | struct pnv_phb *phb; | ||
1183 | struct pci_dn *pdn; | ||
1184 | unsigned int win; | ||
1185 | struct resource *res; | ||
1186 | int i, j; | ||
1187 | int64_t rc; | ||
1188 | int total_vfs; | ||
1189 | resource_size_t size, start; | ||
1190 | int pe_num; | ||
1191 | int vf_groups; | ||
1192 | int vf_per_group; | ||
1193 | |||
1194 | bus = pdev->bus; | ||
1195 | hose = pci_bus_to_host(bus); | ||
1196 | phb = hose->private_data; | ||
1197 | pdn = pci_get_pdn(pdev); | ||
1198 | total_vfs = pci_sriov_get_totalvfs(pdev); | ||
1199 | |||
1200 | /* Initialize the m64_wins to IODA_INVALID_M64 */ | ||
1201 | for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) | ||
1202 | for (j = 0; j < M64_PER_IOV; j++) | ||
1203 | pdn->m64_wins[i][j] = IODA_INVALID_M64; | ||
1204 | |||
1205 | if (pdn->m64_per_iov == M64_PER_IOV) { | ||
1206 | vf_groups = (num_vfs <= M64_PER_IOV) ? num_vfs: M64_PER_IOV; | ||
1207 | vf_per_group = (num_vfs <= M64_PER_IOV)? 1: | ||
1208 | roundup_pow_of_two(num_vfs) / pdn->m64_per_iov; | ||
1209 | } else { | ||
1210 | vf_groups = 1; | ||
1211 | vf_per_group = 1; | ||
1212 | } | ||
1213 | |||
1214 | for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { | ||
1215 | res = &pdev->resource[i + PCI_IOV_RESOURCES]; | ||
1216 | if (!res->flags || !res->parent) | ||
1217 | continue; | ||
1218 | |||
1219 | if (!pnv_pci_is_mem_pref_64(res->flags)) | ||
1220 | continue; | ||
1221 | |||
1222 | for (j = 0; j < vf_groups; j++) { | ||
1223 | do { | ||
1224 | win = find_next_zero_bit(&phb->ioda.m64_bar_alloc, | ||
1225 | phb->ioda.m64_bar_idx + 1, 0); | ||
1226 | |||
1227 | if (win >= phb->ioda.m64_bar_idx + 1) | ||
1228 | goto m64_failed; | ||
1229 | } while (test_and_set_bit(win, &phb->ioda.m64_bar_alloc)); | ||
1230 | |||
1231 | pdn->m64_wins[i][j] = win; | ||
1232 | |||
1233 | if (pdn->m64_per_iov == M64_PER_IOV) { | ||
1234 | size = pci_iov_resource_size(pdev, | ||
1235 | PCI_IOV_RESOURCES + i); | ||
1236 | size = size * vf_per_group; | ||
1237 | start = res->start + size * j; | ||
1238 | } else { | ||
1239 | size = resource_size(res); | ||
1240 | start = res->start; | ||
1241 | } | ||
1242 | |||
1243 | /* Map the M64 here */ | ||
1244 | if (pdn->m64_per_iov == M64_PER_IOV) { | ||
1245 | pe_num = pdn->offset + j; | ||
1246 | rc = opal_pci_map_pe_mmio_window(phb->opal_id, | ||
1247 | pe_num, OPAL_M64_WINDOW_TYPE, | ||
1248 | pdn->m64_wins[i][j], 0); | ||
1249 | } | ||
1250 | |||
1251 | rc = opal_pci_set_phb_mem_window(phb->opal_id, | ||
1252 | OPAL_M64_WINDOW_TYPE, | ||
1253 | pdn->m64_wins[i][j], | ||
1254 | start, | ||
1255 | 0, /* unused */ | ||
1256 | size); | ||
1257 | |||
1258 | |||
1259 | if (rc != OPAL_SUCCESS) { | ||
1260 | dev_err(&pdev->dev, "Failed to map M64 window #%d: %lld\n", | ||
1261 | win, rc); | ||
1262 | goto m64_failed; | ||
1263 | } | ||
1264 | |||
1265 | if (pdn->m64_per_iov == M64_PER_IOV) | ||
1266 | rc = opal_pci_phb_mmio_enable(phb->opal_id, | ||
1267 | OPAL_M64_WINDOW_TYPE, pdn->m64_wins[i][j], 2); | ||
1268 | else | ||
1269 | rc = opal_pci_phb_mmio_enable(phb->opal_id, | ||
1270 | OPAL_M64_WINDOW_TYPE, pdn->m64_wins[i][j], 1); | ||
1271 | |||
1272 | if (rc != OPAL_SUCCESS) { | ||
1273 | dev_err(&pdev->dev, "Failed to enable M64 window #%d: %llx\n", | ||
1274 | win, rc); | ||
1275 | goto m64_failed; | ||
1276 | } | ||
1277 | } | ||
1278 | } | ||
1279 | return 0; | ||
1280 | |||
1281 | m64_failed: | ||
1282 | pnv_pci_vf_release_m64(pdev); | ||
1283 | return -EBUSY; | ||
1284 | } | ||
1285 | |||
1286 | static void pnv_pci_ioda2_release_dma_pe(struct pci_dev *dev, struct pnv_ioda_pe *pe) | ||
1287 | { | ||
1288 | struct pci_bus *bus; | ||
1289 | struct pci_controller *hose; | ||
1290 | struct pnv_phb *phb; | ||
1291 | struct iommu_table *tbl; | ||
1292 | unsigned long addr; | ||
1293 | int64_t rc; | ||
1294 | |||
1295 | bus = dev->bus; | ||
1296 | hose = pci_bus_to_host(bus); | ||
1297 | phb = hose->private_data; | ||
1298 | tbl = pe->tce32_table; | ||
1299 | addr = tbl->it_base; | ||
1300 | |||
1301 | opal_pci_map_pe_dma_window(phb->opal_id, pe->pe_number, | ||
1302 | pe->pe_number << 1, 1, __pa(addr), | ||
1303 | 0, 0x1000); | ||
1304 | |||
1305 | rc = opal_pci_map_pe_dma_window_real(pe->phb->opal_id, | ||
1306 | pe->pe_number, | ||
1307 | (pe->pe_number << 1) + 1, | ||
1308 | pe->tce_bypass_base, | ||
1309 | 0); | ||
1310 | if (rc) | ||
1311 | pe_warn(pe, "OPAL error %ld release DMA window\n", rc); | ||
1312 | |||
1313 | iommu_free_table(tbl, of_node_full_name(dev->dev.of_node)); | ||
1314 | free_pages(addr, get_order(TCE32_TABLE_SIZE)); | ||
1315 | pe->tce32_table = NULL; | ||
1316 | } | ||
1317 | |||
1318 | static void pnv_ioda_release_vf_PE(struct pci_dev *pdev, u16 num_vfs) | ||
1319 | { | ||
1320 | struct pci_bus *bus; | ||
1321 | struct pci_controller *hose; | ||
1322 | struct pnv_phb *phb; | ||
1323 | struct pnv_ioda_pe *pe, *pe_n; | ||
1324 | struct pci_dn *pdn; | ||
1325 | u16 vf_index; | ||
1326 | int64_t rc; | ||
1327 | |||
1328 | bus = pdev->bus; | ||
1329 | hose = pci_bus_to_host(bus); | ||
1330 | phb = hose->private_data; | ||
1331 | pdn = pci_get_pdn(pdev); | ||
1332 | |||
1333 | if (!pdev->is_physfn) | ||
1334 | return; | ||
1335 | |||
1336 | if (pdn->m64_per_iov == M64_PER_IOV && num_vfs > M64_PER_IOV) { | ||
1337 | int vf_group; | ||
1338 | int vf_per_group; | ||
1339 | int vf_index1; | ||
1340 | |||
1341 | vf_per_group = roundup_pow_of_two(num_vfs) / pdn->m64_per_iov; | ||
1342 | |||
1343 | for (vf_group = 0; vf_group < M64_PER_IOV; vf_group++) | ||
1344 | for (vf_index = vf_group * vf_per_group; | ||
1345 | vf_index < (vf_group + 1) * vf_per_group && | ||
1346 | vf_index < num_vfs; | ||
1347 | vf_index++) | ||
1348 | for (vf_index1 = vf_group * vf_per_group; | ||
1349 | vf_index1 < (vf_group + 1) * vf_per_group && | ||
1350 | vf_index1 < num_vfs; | ||
1351 | vf_index1++){ | ||
1352 | |||
1353 | rc = opal_pci_set_peltv(phb->opal_id, | ||
1354 | pdn->offset + vf_index, | ||
1355 | pdn->offset + vf_index1, | ||
1356 | OPAL_REMOVE_PE_FROM_DOMAIN); | ||
1357 | |||
1358 | if (rc) | ||
1359 | dev_warn(&pdev->dev, "%s: Failed to unlink same group PE#%d(%lld)\n", | ||
1360 | __func__, | ||
1361 | pdn->offset + vf_index1, rc); | ||
1362 | } | ||
1363 | } | ||
1364 | |||
1365 | list_for_each_entry_safe(pe, pe_n, &phb->ioda.pe_list, list) { | ||
1366 | if (pe->parent_dev != pdev) | ||
1367 | continue; | ||
1368 | |||
1369 | pnv_pci_ioda2_release_dma_pe(pdev, pe); | ||
1370 | |||
1371 | /* Remove from list */ | ||
1372 | mutex_lock(&phb->ioda.pe_list_mutex); | ||
1373 | list_del(&pe->list); | ||
1374 | mutex_unlock(&phb->ioda.pe_list_mutex); | ||
1375 | |||
1376 | pnv_ioda_deconfigure_pe(phb, pe); | ||
1377 | |||
1378 | pnv_ioda_free_pe(phb, pe->pe_number); | ||
1379 | } | ||
1380 | } | ||
1381 | |||
1382 | void pnv_pci_sriov_disable(struct pci_dev *pdev) | ||
1383 | { | ||
1384 | struct pci_bus *bus; | ||
1385 | struct pci_controller *hose; | ||
1386 | struct pnv_phb *phb; | ||
1387 | struct pci_dn *pdn; | ||
1388 | struct pci_sriov *iov; | ||
1389 | u16 num_vfs; | ||
1390 | |||
1391 | bus = pdev->bus; | ||
1392 | hose = pci_bus_to_host(bus); | ||
1393 | phb = hose->private_data; | ||
1394 | pdn = pci_get_pdn(pdev); | ||
1395 | iov = pdev->sriov; | ||
1396 | num_vfs = pdn->num_vfs; | ||
1397 | |||
1398 | /* Release VF PEs */ | ||
1399 | pnv_ioda_release_vf_PE(pdev, num_vfs); | ||
1400 | |||
1401 | if (phb->type == PNV_PHB_IODA2) { | ||
1402 | if (pdn->m64_per_iov == 1) | ||
1403 | pnv_pci_vf_resource_shift(pdev, -pdn->offset); | ||
1404 | |||
1405 | /* Release M64 windows */ | ||
1406 | pnv_pci_vf_release_m64(pdev); | ||
1407 | |||
1408 | /* Release PE numbers */ | ||
1409 | bitmap_clear(phb->ioda.pe_alloc, pdn->offset, num_vfs); | ||
1410 | pdn->offset = 0; | ||
1411 | } | ||
1412 | } | ||
1413 | |||
1414 | static void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb, | ||
1415 | struct pnv_ioda_pe *pe); | ||
1416 | static void pnv_ioda_setup_vf_PE(struct pci_dev *pdev, u16 num_vfs) | ||
1417 | { | ||
1418 | struct pci_bus *bus; | ||
1419 | struct pci_controller *hose; | ||
1420 | struct pnv_phb *phb; | ||
1421 | struct pnv_ioda_pe *pe; | ||
1422 | int pe_num; | ||
1423 | u16 vf_index; | ||
1424 | struct pci_dn *pdn; | ||
1425 | int64_t rc; | ||
1426 | |||
1427 | bus = pdev->bus; | ||
1428 | hose = pci_bus_to_host(bus); | ||
1429 | phb = hose->private_data; | ||
1430 | pdn = pci_get_pdn(pdev); | ||
1431 | |||
1432 | if (!pdev->is_physfn) | ||
1433 | return; | ||
1434 | |||
1435 | /* Reserve PE for each VF */ | ||
1436 | for (vf_index = 0; vf_index < num_vfs; vf_index++) { | ||
1437 | pe_num = pdn->offset + vf_index; | ||
1438 | |||
1439 | pe = &phb->ioda.pe_array[pe_num]; | ||
1440 | pe->pe_number = pe_num; | ||
1441 | pe->phb = phb; | ||
1442 | pe->flags = PNV_IODA_PE_VF; | ||
1443 | pe->pbus = NULL; | ||
1444 | pe->parent_dev = pdev; | ||
1445 | pe->tce32_seg = -1; | ||
1446 | pe->mve_number = -1; | ||
1447 | pe->rid = (pci_iov_virtfn_bus(pdev, vf_index) << 8) | | ||
1448 | pci_iov_virtfn_devfn(pdev, vf_index); | ||
1449 | |||
1450 | pe_info(pe, "VF %04d:%02d:%02d.%d associated with PE#%d\n", | ||
1451 | hose->global_number, pdev->bus->number, | ||
1452 | PCI_SLOT(pci_iov_virtfn_devfn(pdev, vf_index)), | ||
1453 | PCI_FUNC(pci_iov_virtfn_devfn(pdev, vf_index)), pe_num); | ||
1454 | |||
1455 | if (pnv_ioda_configure_pe(phb, pe)) { | ||
1456 | /* XXX What do we do here ? */ | ||
1457 | if (pe_num) | ||
1458 | pnv_ioda_free_pe(phb, pe_num); | ||
1459 | pe->pdev = NULL; | ||
1460 | continue; | ||
1461 | } | ||
1462 | |||
1463 | pe->tce32_table = kzalloc_node(sizeof(struct iommu_table), | ||
1464 | GFP_KERNEL, hose->node); | ||
1465 | pe->tce32_table->data = pe; | ||
1466 | |||
1467 | /* Put PE to the list */ | ||
1468 | mutex_lock(&phb->ioda.pe_list_mutex); | ||
1469 | list_add_tail(&pe->list, &phb->ioda.pe_list); | ||
1470 | mutex_unlock(&phb->ioda.pe_list_mutex); | ||
1471 | |||
1472 | pnv_pci_ioda2_setup_dma_pe(phb, pe); | ||
1473 | } | ||
1474 | |||
1475 | if (pdn->m64_per_iov == M64_PER_IOV && num_vfs > M64_PER_IOV) { | ||
1476 | int vf_group; | ||
1477 | int vf_per_group; | ||
1478 | int vf_index1; | ||
1479 | |||
1480 | vf_per_group = roundup_pow_of_two(num_vfs) / pdn->m64_per_iov; | ||
1481 | |||
1482 | for (vf_group = 0; vf_group < M64_PER_IOV; vf_group++) { | ||
1483 | for (vf_index = vf_group * vf_per_group; | ||
1484 | vf_index < (vf_group + 1) * vf_per_group && | ||
1485 | vf_index < num_vfs; | ||
1486 | vf_index++) { | ||
1487 | for (vf_index1 = vf_group * vf_per_group; | ||
1488 | vf_index1 < (vf_group + 1) * vf_per_group && | ||
1489 | vf_index1 < num_vfs; | ||
1490 | vf_index1++) { | ||
1491 | |||
1492 | rc = opal_pci_set_peltv(phb->opal_id, | ||
1493 | pdn->offset + vf_index, | ||
1494 | pdn->offset + vf_index1, | ||
1495 | OPAL_ADD_PE_TO_DOMAIN); | ||
1496 | |||
1497 | if (rc) | ||
1498 | dev_warn(&pdev->dev, "%s: Failed to link same group PE#%d(%lld)\n", | ||
1499 | __func__, | ||
1500 | pdn->offset + vf_index1, rc); | ||
1501 | } | ||
1502 | } | ||
1503 | } | ||
1504 | } | ||
1505 | } | ||
1506 | |||
1507 | int pnv_pci_sriov_enable(struct pci_dev *pdev, u16 num_vfs) | ||
1508 | { | ||
1509 | struct pci_bus *bus; | ||
1510 | struct pci_controller *hose; | ||
1511 | struct pnv_phb *phb; | ||
1512 | struct pci_dn *pdn; | ||
1513 | int ret; | ||
1514 | |||
1515 | bus = pdev->bus; | ||
1516 | hose = pci_bus_to_host(bus); | ||
1517 | phb = hose->private_data; | ||
1518 | pdn = pci_get_pdn(pdev); | ||
1519 | |||
1520 | if (phb->type == PNV_PHB_IODA2) { | ||
1521 | /* Calculate available PE for required VFs */ | ||
1522 | mutex_lock(&phb->ioda.pe_alloc_mutex); | ||
1523 | pdn->offset = bitmap_find_next_zero_area( | ||
1524 | phb->ioda.pe_alloc, phb->ioda.total_pe, | ||
1525 | 0, num_vfs, 0); | ||
1526 | if (pdn->offset >= phb->ioda.total_pe) { | ||
1527 | mutex_unlock(&phb->ioda.pe_alloc_mutex); | ||
1528 | dev_info(&pdev->dev, "Failed to enable VF%d\n", num_vfs); | ||
1529 | pdn->offset = 0; | ||
1530 | return -EBUSY; | ||
1531 | } | ||
1532 | bitmap_set(phb->ioda.pe_alloc, pdn->offset, num_vfs); | ||
1533 | pdn->num_vfs = num_vfs; | ||
1534 | mutex_unlock(&phb->ioda.pe_alloc_mutex); | ||
1535 | |||
1536 | /* Assign M64 window accordingly */ | ||
1537 | ret = pnv_pci_vf_assign_m64(pdev, num_vfs); | ||
1538 | if (ret) { | ||
1539 | dev_info(&pdev->dev, "Not enough M64 window resources\n"); | ||
1540 | goto m64_failed; | ||
1541 | } | ||
1542 | |||
1543 | /* | ||
1544 | * When using one M64 BAR to map one IOV BAR, we need to shift | ||
1545 | * the IOV BAR according to the PE# allocated to the VFs. | ||
1546 | * Otherwise, the PE# for the VF will conflict with others. | ||
1547 | */ | ||
1548 | if (pdn->m64_per_iov == 1) { | ||
1549 | ret = pnv_pci_vf_resource_shift(pdev, pdn->offset); | ||
1550 | if (ret) | ||
1551 | goto m64_failed; | ||
1552 | } | ||
1553 | } | ||
1554 | |||
1555 | /* Setup VF PEs */ | ||
1556 | pnv_ioda_setup_vf_PE(pdev, num_vfs); | ||
1557 | |||
1558 | return 0; | ||
1559 | |||
1560 | m64_failed: | ||
1561 | bitmap_clear(phb->ioda.pe_alloc, pdn->offset, num_vfs); | ||
1562 | pdn->offset = 0; | ||
1563 | |||
1564 | return ret; | ||
1565 | } | ||
1566 | |||
1567 | int pcibios_sriov_disable(struct pci_dev *pdev) | ||
1568 | { | ||
1569 | pnv_pci_sriov_disable(pdev); | ||
1570 | |||
1571 | /* Release PCI data */ | ||
1572 | remove_dev_pci_data(pdev); | ||
1573 | return 0; | ||
1574 | } | ||
1575 | |||
1576 | int pcibios_sriov_enable(struct pci_dev *pdev, u16 num_vfs) | ||
1577 | { | ||
1578 | /* Allocate PCI data */ | ||
1579 | add_dev_pci_data(pdev); | ||
1580 | |||
1581 | pnv_pci_sriov_enable(pdev, num_vfs); | ||
1582 | return 0; | ||
1583 | } | ||
1584 | #endif /* CONFIG_PCI_IOV */ | ||
1585 | |||
977 | static void pnv_pci_ioda_dma_dev_setup(struct pnv_phb *phb, struct pci_dev *pdev) | 1586 | static void pnv_pci_ioda_dma_dev_setup(struct pnv_phb *phb, struct pci_dev *pdev) |
978 | { | 1587 | { |
979 | struct pci_dn *pdn = pci_get_pdn(pdev); | 1588 | struct pci_dn *pdn = pci_get_pdn(pdev); |
@@ -989,7 +1598,7 @@ static void pnv_pci_ioda_dma_dev_setup(struct pnv_phb *phb, struct pci_dev *pdev | |||
989 | 1598 | ||
990 | pe = &phb->ioda.pe_array[pdn->pe_number]; | 1599 | pe = &phb->ioda.pe_array[pdn->pe_number]; |
991 | WARN_ON(get_dma_ops(&pdev->dev) != &dma_iommu_ops); | 1600 | WARN_ON(get_dma_ops(&pdev->dev) != &dma_iommu_ops); |
992 | set_iommu_table_base_and_group(&pdev->dev, &pe->tce32_table); | 1601 | set_iommu_table_base_and_group(&pdev->dev, pe->tce32_table); |
993 | } | 1602 | } |
994 | 1603 | ||
995 | static int pnv_pci_ioda_dma_set_mask(struct pnv_phb *phb, | 1604 | static int pnv_pci_ioda_dma_set_mask(struct pnv_phb *phb, |
@@ -1016,7 +1625,7 @@ static int pnv_pci_ioda_dma_set_mask(struct pnv_phb *phb, | |||
1016 | } else { | 1625 | } else { |
1017 | dev_info(&pdev->dev, "Using 32-bit DMA via iommu\n"); | 1626 | dev_info(&pdev->dev, "Using 32-bit DMA via iommu\n"); |
1018 | set_dma_ops(&pdev->dev, &dma_iommu_ops); | 1627 | set_dma_ops(&pdev->dev, &dma_iommu_ops); |
1019 | set_iommu_table_base(&pdev->dev, &pe->tce32_table); | 1628 | set_iommu_table_base(&pdev->dev, pe->tce32_table); |
1020 | } | 1629 | } |
1021 | *pdev->dev.dma_mask = dma_mask; | 1630 | *pdev->dev.dma_mask = dma_mask; |
1022 | return 0; | 1631 | return 0; |
@@ -1053,9 +1662,9 @@ static void pnv_ioda_setup_bus_dma(struct pnv_ioda_pe *pe, | |||
1053 | list_for_each_entry(dev, &bus->devices, bus_list) { | 1662 | list_for_each_entry(dev, &bus->devices, bus_list) { |
1054 | if (add_to_iommu_group) | 1663 | if (add_to_iommu_group) |
1055 | set_iommu_table_base_and_group(&dev->dev, | 1664 | set_iommu_table_base_and_group(&dev->dev, |
1056 | &pe->tce32_table); | 1665 | pe->tce32_table); |
1057 | else | 1666 | else |
1058 | set_iommu_table_base(&dev->dev, &pe->tce32_table); | 1667 | set_iommu_table_base(&dev->dev, pe->tce32_table); |
1059 | 1668 | ||
1060 | if (dev->subordinate) | 1669 | if (dev->subordinate) |
1061 | pnv_ioda_setup_bus_dma(pe, dev->subordinate, | 1670 | pnv_ioda_setup_bus_dma(pe, dev->subordinate, |
@@ -1145,8 +1754,7 @@ static void pnv_pci_ioda2_tce_invalidate(struct pnv_ioda_pe *pe, | |||
1145 | void pnv_pci_ioda_tce_invalidate(struct iommu_table *tbl, | 1754 | void pnv_pci_ioda_tce_invalidate(struct iommu_table *tbl, |
1146 | __be64 *startp, __be64 *endp, bool rm) | 1755 | __be64 *startp, __be64 *endp, bool rm) |
1147 | { | 1756 | { |
1148 | struct pnv_ioda_pe *pe = container_of(tbl, struct pnv_ioda_pe, | 1757 | struct pnv_ioda_pe *pe = tbl->data; |
1149 | tce32_table); | ||
1150 | struct pnv_phb *phb = pe->phb; | 1758 | struct pnv_phb *phb = pe->phb; |
1151 | 1759 | ||
1152 | if (phb->type == PNV_PHB_IODA1) | 1760 | if (phb->type == PNV_PHB_IODA1) |
@@ -1167,9 +1775,6 @@ static void pnv_pci_ioda_setup_dma_pe(struct pnv_phb *phb, | |||
1167 | int64_t rc; | 1775 | int64_t rc; |
1168 | void *addr; | 1776 | void *addr; |
1169 | 1777 | ||
1170 | /* 256M DMA window, 4K TCE pages, 8 bytes TCE */ | ||
1171 | #define TCE32_TABLE_SIZE ((0x10000000 / 0x1000) * 8) | ||
1172 | |||
1173 | /* XXX FIXME: Handle 64-bit only DMA devices */ | 1778 | /* XXX FIXME: Handle 64-bit only DMA devices */ |
1174 | /* XXX FIXME: Provide 64-bit DMA facilities & non-4K TCE tables etc.. */ | 1779 | /* XXX FIXME: Provide 64-bit DMA facilities & non-4K TCE tables etc.. */ |
1175 | /* XXX FIXME: Allocate multi-level tables on PHB3 */ | 1780 | /* XXX FIXME: Allocate multi-level tables on PHB3 */ |
@@ -1212,7 +1817,7 @@ static void pnv_pci_ioda_setup_dma_pe(struct pnv_phb *phb, | |||
1212 | } | 1817 | } |
1213 | 1818 | ||
1214 | /* Setup linux iommu table */ | 1819 | /* Setup linux iommu table */ |
1215 | tbl = &pe->tce32_table; | 1820 | tbl = pe->tce32_table; |
1216 | pnv_pci_setup_iommu_table(tbl, addr, TCE32_TABLE_SIZE * segs, | 1821 | pnv_pci_setup_iommu_table(tbl, addr, TCE32_TABLE_SIZE * segs, |
1217 | base << 28, IOMMU_PAGE_SHIFT_4K); | 1822 | base << 28, IOMMU_PAGE_SHIFT_4K); |
1218 | 1823 | ||
@@ -1232,12 +1837,19 @@ static void pnv_pci_ioda_setup_dma_pe(struct pnv_phb *phb, | |||
1232 | TCE_PCI_SWINV_PAIR); | 1837 | TCE_PCI_SWINV_PAIR); |
1233 | } | 1838 | } |
1234 | iommu_init_table(tbl, phb->hose->node); | 1839 | iommu_init_table(tbl, phb->hose->node); |
1235 | iommu_register_group(tbl, phb->hose->global_number, pe->pe_number); | ||
1236 | 1840 | ||
1237 | if (pe->pdev) | 1841 | if (pe->flags & PNV_IODA_PE_DEV) { |
1842 | iommu_register_group(tbl, phb->hose->global_number, | ||
1843 | pe->pe_number); | ||
1238 | set_iommu_table_base_and_group(&pe->pdev->dev, tbl); | 1844 | set_iommu_table_base_and_group(&pe->pdev->dev, tbl); |
1239 | else | 1845 | } else if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL)) { |
1846 | iommu_register_group(tbl, phb->hose->global_number, | ||
1847 | pe->pe_number); | ||
1240 | pnv_ioda_setup_bus_dma(pe, pe->pbus, true); | 1848 | pnv_ioda_setup_bus_dma(pe, pe->pbus, true); |
1849 | } else if (pe->flags & PNV_IODA_PE_VF) { | ||
1850 | iommu_register_group(tbl, phb->hose->global_number, | ||
1851 | pe->pe_number); | ||
1852 | } | ||
1241 | 1853 | ||
1242 | return; | 1854 | return; |
1243 | fail: | 1855 | fail: |
@@ -1250,8 +1862,7 @@ static void pnv_pci_ioda_setup_dma_pe(struct pnv_phb *phb, | |||
1250 | 1862 | ||
1251 | static void pnv_pci_ioda2_set_bypass(struct iommu_table *tbl, bool enable) | 1863 | static void pnv_pci_ioda2_set_bypass(struct iommu_table *tbl, bool enable) |
1252 | { | 1864 | { |
1253 | struct pnv_ioda_pe *pe = container_of(tbl, struct pnv_ioda_pe, | 1865 | struct pnv_ioda_pe *pe = tbl->data; |
1254 | tce32_table); | ||
1255 | uint16_t window_id = (pe->pe_number << 1 ) + 1; | 1866 | uint16_t window_id = (pe->pe_number << 1 ) + 1; |
1256 | int64_t rc; | 1867 | int64_t rc; |
1257 | 1868 | ||
@@ -1296,10 +1907,10 @@ static void pnv_pci_ioda2_setup_bypass_pe(struct pnv_phb *phb, | |||
1296 | pe->tce_bypass_base = 1ull << 59; | 1907 | pe->tce_bypass_base = 1ull << 59; |
1297 | 1908 | ||
1298 | /* Install set_bypass callback for VFIO */ | 1909 | /* Install set_bypass callback for VFIO */ |
1299 | pe->tce32_table.set_bypass = pnv_pci_ioda2_set_bypass; | 1910 | pe->tce32_table->set_bypass = pnv_pci_ioda2_set_bypass; |
1300 | 1911 | ||
1301 | /* Enable bypass by default */ | 1912 | /* Enable bypass by default */ |
1302 | pnv_pci_ioda2_set_bypass(&pe->tce32_table, true); | 1913 | pnv_pci_ioda2_set_bypass(pe->tce32_table, true); |
1303 | } | 1914 | } |
1304 | 1915 | ||
1305 | static void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb, | 1916 | static void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb, |
@@ -1347,7 +1958,7 @@ static void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb, | |||
1347 | } | 1958 | } |
1348 | 1959 | ||
1349 | /* Setup linux iommu table */ | 1960 | /* Setup linux iommu table */ |
1350 | tbl = &pe->tce32_table; | 1961 | tbl = pe->tce32_table; |
1351 | pnv_pci_setup_iommu_table(tbl, addr, tce_table_size, 0, | 1962 | pnv_pci_setup_iommu_table(tbl, addr, tce_table_size, 0, |
1352 | IOMMU_PAGE_SHIFT_4K); | 1963 | IOMMU_PAGE_SHIFT_4K); |
1353 | 1964 | ||
@@ -1365,12 +1976,19 @@ static void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb, | |||
1365 | tbl->it_type |= (TCE_PCI_SWINV_CREATE | TCE_PCI_SWINV_FREE); | 1976 | tbl->it_type |= (TCE_PCI_SWINV_CREATE | TCE_PCI_SWINV_FREE); |
1366 | } | 1977 | } |
1367 | iommu_init_table(tbl, phb->hose->node); | 1978 | iommu_init_table(tbl, phb->hose->node); |
1368 | iommu_register_group(tbl, phb->hose->global_number, pe->pe_number); | ||
1369 | 1979 | ||
1370 | if (pe->pdev) | 1980 | if (pe->flags & PNV_IODA_PE_DEV) { |
1981 | iommu_register_group(tbl, phb->hose->global_number, | ||
1982 | pe->pe_number); | ||
1371 | set_iommu_table_base_and_group(&pe->pdev->dev, tbl); | 1983 | set_iommu_table_base_and_group(&pe->pdev->dev, tbl); |
1372 | else | 1984 | } else if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL)) { |
1985 | iommu_register_group(tbl, phb->hose->global_number, | ||
1986 | pe->pe_number); | ||
1373 | pnv_ioda_setup_bus_dma(pe, pe->pbus, true); | 1987 | pnv_ioda_setup_bus_dma(pe, pe->pbus, true); |
1988 | } else if (pe->flags & PNV_IODA_PE_VF) { | ||
1989 | iommu_register_group(tbl, phb->hose->global_number, | ||
1990 | pe->pe_number); | ||
1991 | } | ||
1374 | 1992 | ||
1375 | /* Also create a bypass window */ | 1993 | /* Also create a bypass window */ |
1376 | if (!pnv_iommu_bypass_disabled) | 1994 | if (!pnv_iommu_bypass_disabled) |
@@ -1731,6 +2349,73 @@ static void pnv_pci_init_ioda_msis(struct pnv_phb *phb) | |||
1731 | static void pnv_pci_init_ioda_msis(struct pnv_phb *phb) { } | 2349 | static void pnv_pci_init_ioda_msis(struct pnv_phb *phb) { } |
1732 | #endif /* CONFIG_PCI_MSI */ | 2350 | #endif /* CONFIG_PCI_MSI */ |
1733 | 2351 | ||
2352 | #ifdef CONFIG_PCI_IOV | ||
2353 | static void pnv_pci_ioda_fixup_iov_resources(struct pci_dev *pdev) | ||
2354 | { | ||
2355 | struct pci_controller *hose; | ||
2356 | struct pnv_phb *phb; | ||
2357 | struct resource *res; | ||
2358 | int i; | ||
2359 | resource_size_t size; | ||
2360 | struct pci_dn *pdn; | ||
2361 | int mul, total_vfs; | ||
2362 | |||
2363 | if (!pdev->is_physfn || pdev->is_added) | ||
2364 | return; | ||
2365 | |||
2366 | hose = pci_bus_to_host(pdev->bus); | ||
2367 | phb = hose->private_data; | ||
2368 | |||
2369 | pdn = pci_get_pdn(pdev); | ||
2370 | pdn->vfs_expanded = 0; | ||
2371 | |||
2372 | total_vfs = pci_sriov_get_totalvfs(pdev); | ||
2373 | pdn->m64_per_iov = 1; | ||
2374 | mul = phb->ioda.total_pe; | ||
2375 | |||
2376 | for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { | ||
2377 | res = &pdev->resource[i + PCI_IOV_RESOURCES]; | ||
2378 | if (!res->flags || res->parent) | ||
2379 | continue; | ||
2380 | if (!pnv_pci_is_mem_pref_64(res->flags)) { | ||
2381 | dev_warn(&pdev->dev, " non M64 VF BAR%d: %pR\n", | ||
2382 | i, res); | ||
2383 | continue; | ||
2384 | } | ||
2385 | |||
2386 | size = pci_iov_resource_size(pdev, i + PCI_IOV_RESOURCES); | ||
2387 | |||
2388 | /* bigger than 64M */ | ||
2389 | if (size > (1 << 26)) { | ||
2390 | dev_info(&pdev->dev, "PowerNV: VF BAR%d: %pR IOV size is bigger than 64M, roundup power2\n", | ||
2391 | i, res); | ||
2392 | pdn->m64_per_iov = M64_PER_IOV; | ||
2393 | mul = roundup_pow_of_two(total_vfs); | ||
2394 | break; | ||
2395 | } | ||
2396 | } | ||
2397 | |||
2398 | for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { | ||
2399 | res = &pdev->resource[i + PCI_IOV_RESOURCES]; | ||
2400 | if (!res->flags || res->parent) | ||
2401 | continue; | ||
2402 | if (!pnv_pci_is_mem_pref_64(res->flags)) { | ||
2403 | dev_warn(&pdev->dev, "Skipping expanding VF BAR%d: %pR\n", | ||
2404 | i, res); | ||
2405 | continue; | ||
2406 | } | ||
2407 | |||
2408 | dev_dbg(&pdev->dev, " Fixing VF BAR%d: %pR to\n", i, res); | ||
2409 | size = pci_iov_resource_size(pdev, i + PCI_IOV_RESOURCES); | ||
2410 | res->end = res->start + size * mul - 1; | ||
2411 | dev_dbg(&pdev->dev, " %pR\n", res); | ||
2412 | dev_info(&pdev->dev, "VF BAR%d: %pR (expanded to %d VFs for PE alignment)", | ||
2413 | i, res, mul); | ||
2414 | } | ||
2415 | pdn->vfs_expanded = mul; | ||
2416 | } | ||
2417 | #endif /* CONFIG_PCI_IOV */ | ||
2418 | |||
1734 | /* | 2419 | /* |
1735 | * This function is supposed to be called on basis of PE from top | 2420 | * This function is supposed to be called on basis of PE from top |
1736 | * to bottom style. So the the I/O or MMIO segment assigned to | 2421 | * to bottom style. So the the I/O or MMIO segment assigned to |
@@ -1777,7 +2462,8 @@ static void pnv_ioda_setup_pe_seg(struct pci_controller *hose, | |||
1777 | region.start += phb->ioda.io_segsize; | 2462 | region.start += phb->ioda.io_segsize; |
1778 | index++; | 2463 | index++; |
1779 | } | 2464 | } |
1780 | } else if (res->flags & IORESOURCE_MEM) { | 2465 | } else if ((res->flags & IORESOURCE_MEM) && |
2466 | !pnv_pci_is_mem_pref_64(res->flags)) { | ||
1781 | region.start = res->start - | 2467 | region.start = res->start - |
1782 | hose->mem_offset[0] - | 2468 | hose->mem_offset[0] - |
1783 | phb->ioda.m32_pci_base; | 2469 | phb->ioda.m32_pci_base; |
@@ -1907,10 +2593,29 @@ static resource_size_t pnv_pci_window_alignment(struct pci_bus *bus, | |||
1907 | return phb->ioda.io_segsize; | 2593 | return phb->ioda.io_segsize; |
1908 | } | 2594 | } |
1909 | 2595 | ||
2596 | #ifdef CONFIG_PCI_IOV | ||
2597 | static resource_size_t pnv_pci_iov_resource_alignment(struct pci_dev *pdev, | ||
2598 | int resno) | ||
2599 | { | ||
2600 | struct pci_dn *pdn = pci_get_pdn(pdev); | ||
2601 | resource_size_t align, iov_align; | ||
2602 | |||
2603 | iov_align = resource_size(&pdev->resource[resno]); | ||
2604 | if (iov_align) | ||
2605 | return iov_align; | ||
2606 | |||
2607 | align = pci_iov_resource_size(pdev, resno); | ||
2608 | if (pdn->vfs_expanded) | ||
2609 | return pdn->vfs_expanded * align; | ||
2610 | |||
2611 | return align; | ||
2612 | } | ||
2613 | #endif /* CONFIG_PCI_IOV */ | ||
2614 | |||
1910 | /* Prevent enabling devices for which we couldn't properly | 2615 | /* Prevent enabling devices for which we couldn't properly |
1911 | * assign a PE | 2616 | * assign a PE |
1912 | */ | 2617 | */ |
1913 | static int pnv_pci_enable_device_hook(struct pci_dev *dev) | 2618 | static bool pnv_pci_enable_device_hook(struct pci_dev *dev) |
1914 | { | 2619 | { |
1915 | struct pci_controller *hose = pci_bus_to_host(dev->bus); | 2620 | struct pci_controller *hose = pci_bus_to_host(dev->bus); |
1916 | struct pnv_phb *phb = hose->private_data; | 2621 | struct pnv_phb *phb = hose->private_data; |
@@ -1922,13 +2627,13 @@ static int pnv_pci_enable_device_hook(struct pci_dev *dev) | |||
1922 | * PEs isn't ready. | 2627 | * PEs isn't ready. |
1923 | */ | 2628 | */ |
1924 | if (!phb->initialized) | 2629 | if (!phb->initialized) |
1925 | return 0; | 2630 | return true; |
1926 | 2631 | ||
1927 | pdn = pci_get_pdn(dev); | 2632 | pdn = pci_get_pdn(dev); |
1928 | if (!pdn || pdn->pe_number == IODA_INVALID_PE) | 2633 | if (!pdn || pdn->pe_number == IODA_INVALID_PE) |
1929 | return -EINVAL; | 2634 | return false; |
1930 | 2635 | ||
1931 | return 0; | 2636 | return true; |
1932 | } | 2637 | } |
1933 | 2638 | ||
1934 | static u32 pnv_ioda_bdfn_to_pe(struct pnv_phb *phb, struct pci_bus *bus, | 2639 | static u32 pnv_ioda_bdfn_to_pe(struct pnv_phb *phb, struct pci_bus *bus, |
@@ -1988,9 +2693,11 @@ static void __init pnv_pci_init_ioda_phb(struct device_node *np, | |||
1988 | hose->last_busno = 0xff; | 2693 | hose->last_busno = 0xff; |
1989 | } | 2694 | } |
1990 | hose->private_data = phb; | 2695 | hose->private_data = phb; |
2696 | hose->controller_ops = pnv_pci_controller_ops; | ||
1991 | phb->hub_id = hub_id; | 2697 | phb->hub_id = hub_id; |
1992 | phb->opal_id = phb_id; | 2698 | phb->opal_id = phb_id; |
1993 | phb->type = ioda_type; | 2699 | phb->type = ioda_type; |
2700 | mutex_init(&phb->ioda.pe_alloc_mutex); | ||
1994 | 2701 | ||
1995 | /* Detect specific models for error handling */ | 2702 | /* Detect specific models for error handling */ |
1996 | if (of_device_is_compatible(np, "ibm,p7ioc-pciex")) | 2703 | if (of_device_is_compatible(np, "ibm,p7ioc-pciex")) |
@@ -2050,6 +2757,7 @@ static void __init pnv_pci_init_ioda_phb(struct device_node *np, | |||
2050 | 2757 | ||
2051 | INIT_LIST_HEAD(&phb->ioda.pe_dma_list); | 2758 | INIT_LIST_HEAD(&phb->ioda.pe_dma_list); |
2052 | INIT_LIST_HEAD(&phb->ioda.pe_list); | 2759 | INIT_LIST_HEAD(&phb->ioda.pe_list); |
2760 | mutex_init(&phb->ioda.pe_list_mutex); | ||
2053 | 2761 | ||
2054 | /* Calculate how many 32-bit TCE segments we have */ | 2762 | /* Calculate how many 32-bit TCE segments we have */ |
2055 | phb->ioda.tce32_count = phb->ioda.m32_pci_base >> 28; | 2763 | phb->ioda.tce32_count = phb->ioda.m32_pci_base >> 28; |
@@ -2078,9 +2786,6 @@ static void __init pnv_pci_init_ioda_phb(struct device_node *np, | |||
2078 | phb->get_pe_state = pnv_ioda_get_pe_state; | 2786 | phb->get_pe_state = pnv_ioda_get_pe_state; |
2079 | phb->freeze_pe = pnv_ioda_freeze_pe; | 2787 | phb->freeze_pe = pnv_ioda_freeze_pe; |
2080 | phb->unfreeze_pe = pnv_ioda_unfreeze_pe; | 2788 | phb->unfreeze_pe = pnv_ioda_unfreeze_pe; |
2081 | #ifdef CONFIG_EEH | ||
2082 | phb->eeh_ops = &ioda_eeh_ops; | ||
2083 | #endif | ||
2084 | 2789 | ||
2085 | /* Setup RID -> PE mapping function */ | 2790 | /* Setup RID -> PE mapping function */ |
2086 | phb->bdfn_to_pe = pnv_ioda_bdfn_to_pe; | 2791 | phb->bdfn_to_pe = pnv_ioda_bdfn_to_pe; |
@@ -2104,9 +2809,15 @@ static void __init pnv_pci_init_ioda_phb(struct device_node *np, | |||
2104 | * the child P2P bridges) can form individual PE. | 2809 | * the child P2P bridges) can form individual PE. |
2105 | */ | 2810 | */ |
2106 | ppc_md.pcibios_fixup = pnv_pci_ioda_fixup; | 2811 | ppc_md.pcibios_fixup = pnv_pci_ioda_fixup; |
2107 | ppc_md.pcibios_enable_device_hook = pnv_pci_enable_device_hook; | 2812 | pnv_pci_controller_ops.enable_device_hook = pnv_pci_enable_device_hook; |
2108 | ppc_md.pcibios_window_alignment = pnv_pci_window_alignment; | 2813 | pnv_pci_controller_ops.window_alignment = pnv_pci_window_alignment; |
2109 | ppc_md.pcibios_reset_secondary_bus = pnv_pci_reset_secondary_bus; | 2814 | pnv_pci_controller_ops.reset_secondary_bus = pnv_pci_reset_secondary_bus; |
2815 | |||
2816 | #ifdef CONFIG_PCI_IOV | ||
2817 | ppc_md.pcibios_fixup_sriov = pnv_pci_ioda_fixup_iov_resources; | ||
2818 | ppc_md.pcibios_iov_resource_alignment = pnv_pci_iov_resource_alignment; | ||
2819 | #endif | ||
2820 | |||
2110 | pci_add_flags(PCI_REASSIGN_ALL_RSRC); | 2821 | pci_add_flags(PCI_REASSIGN_ALL_RSRC); |
2111 | 2822 | ||
2112 | /* Reset IODA tables to a clean state */ | 2823 | /* Reset IODA tables to a clean state */ |
@@ -2121,8 +2832,8 @@ static void __init pnv_pci_init_ioda_phb(struct device_node *np, | |||
2121 | */ | 2832 | */ |
2122 | if (is_kdump_kernel()) { | 2833 | if (is_kdump_kernel()) { |
2123 | pr_info(" Issue PHB reset ...\n"); | 2834 | pr_info(" Issue PHB reset ...\n"); |
2124 | ioda_eeh_phb_reset(hose, EEH_RESET_FUNDAMENTAL); | 2835 | pnv_eeh_phb_reset(hose, EEH_RESET_FUNDAMENTAL); |
2125 | ioda_eeh_phb_reset(hose, EEH_RESET_DEACTIVATE); | 2836 | pnv_eeh_phb_reset(hose, EEH_RESET_DEACTIVATE); |
2126 | } | 2837 | } |
2127 | 2838 | ||
2128 | /* Remove M64 resource if we can't configure it successfully */ | 2839 | /* Remove M64 resource if we can't configure it successfully */ |