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-rw-r--r--arch/powerpc/platforms/pasemi/Kconfig19
-rw-r--r--arch/powerpc/platforms/pasemi/Makefile3
-rw-r--r--arch/powerpc/platforms/pasemi/cpufreq.c308
-rw-r--r--arch/powerpc/platforms/pasemi/gpio_mdio.c339
-rw-r--r--arch/powerpc/platforms/pasemi/idle.c9
-rw-r--r--arch/powerpc/platforms/pasemi/iommu.c6
-rw-r--r--arch/powerpc/platforms/pasemi/pasemi.h8
-rw-r--r--arch/powerpc/platforms/pasemi/pci.c16
-rw-r--r--arch/powerpc/platforms/pasemi/setup.c28
9 files changed, 719 insertions, 17 deletions
diff --git a/arch/powerpc/platforms/pasemi/Kconfig b/arch/powerpc/platforms/pasemi/Kconfig
index 68dc529dfd2f..eb4dbc705b06 100644
--- a/arch/powerpc/platforms/pasemi/Kconfig
+++ b/arch/powerpc/platforms/pasemi/Kconfig
@@ -1,3 +1,15 @@
1config PPC_PASEMI
2 depends on PPC_MULTIPLATFORM && PPC64
3 bool "PA Semi SoC-based platforms"
4 default n
5 select MPIC
6 select PPC_UDBG_16550
7 select GENERIC_TBSYNC
8 select PPC_NATIVE
9 help
10 This option enables support for PA Semi's PWRficient line
11 of SoC processors, including PA6T-1682M
12
1menu "PA Semi PWRficient options" 13menu "PA Semi PWRficient options"
2 depends on PPC_PASEMI 14 depends on PPC_PASEMI
3 15
@@ -7,4 +19,11 @@ config PPC_PASEMI_IOMMU
7 help 19 help
8 IOMMU support for PA6T-1682M 20 IOMMU support for PA6T-1682M
9 21
22config PPC_PASEMI_MDIO
23 depends on PHYLIB
24 tristate "MDIO support via GPIO"
25 default y
26 help
27 Driver for MDIO via GPIO on PWRficient platforms
28
10endmenu 29endmenu
diff --git a/arch/powerpc/platforms/pasemi/Makefile b/arch/powerpc/platforms/pasemi/Makefile
index e657ccae90a9..2cd2a4f26a48 100644
--- a/arch/powerpc/platforms/pasemi/Makefile
+++ b/arch/powerpc/platforms/pasemi/Makefile
@@ -1,2 +1,3 @@
1obj-y += setup.o pci.o time.o idle.o powersave.o iommu.o 1obj-y += setup.o pci.o time.o idle.o powersave.o iommu.o
2 2obj-$(CONFIG_PPC_PASEMI_MDIO) += gpio_mdio.o
3obj-$(CONFIG_PPC_PASEMI_CPUFREQ) += cpufreq.o
diff --git a/arch/powerpc/platforms/pasemi/cpufreq.c b/arch/powerpc/platforms/pasemi/cpufreq.c
new file mode 100644
index 000000000000..2a57d6023685
--- /dev/null
+++ b/arch/powerpc/platforms/pasemi/cpufreq.c
@@ -0,0 +1,308 @@
1/*
2 * Copyright (C) 2007 PA Semi, Inc
3 *
4 * Authors: Egor Martovetsky <egor@pasemi.com>
5 * Olof Johansson <olof@lixom.net>
6 *
7 * Maintained by: Olof Johansson <olof@lixom.net>
8 *
9 * Based on arch/powerpc/platforms/cell/cbe_cpufreq.c:
10 * (C) Copyright IBM Deutschland Entwicklung GmbH 2005
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2, or (at your option)
15 * any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 *
26 */
27
28#include <linux/cpufreq.h>
29#include <linux/timer.h>
30
31#include <asm/hw_irq.h>
32#include <asm/io.h>
33#include <asm/prom.h>
34
35#define SDCASR_REG 0x0100
36#define SDCASR_REG_STRIDE 0x1000
37#define SDCPWR_CFGA0_REG 0x0100
38#define SDCPWR_PWST0_REG 0x0000
39#define SDCPWR_GIZTIME_REG 0x0440
40
41/* SDCPWR_GIZTIME_REG fields */
42#define SDCPWR_GIZTIME_GR 0x80000000
43#define SDCPWR_GIZTIME_LONGLOCK 0x000000ff
44
45/* Offset of ASR registers from SDC base */
46#define SDCASR_OFFSET 0x120000
47
48static void __iomem *sdcpwr_mapbase;
49static void __iomem *sdcasr_mapbase;
50
51static DEFINE_MUTEX(pas_switch_mutex);
52
53/* Current astate, is used when waking up from power savings on
54 * one core, in case the other core has switched states during
55 * the idle time.
56 */
57static int current_astate;
58
59/* We support 5(A0-A4) power states excluding turbo(A5-A6) modes */
60static struct cpufreq_frequency_table pas_freqs[] = {
61 {0, 0},
62 {1, 0},
63 {2, 0},
64 {3, 0},
65 {4, 0},
66 {0, CPUFREQ_TABLE_END},
67};
68
69static struct freq_attr *pas_cpu_freqs_attr[] = {
70 &cpufreq_freq_attr_scaling_available_freqs,
71 NULL,
72};
73
74/*
75 * hardware specific functions
76 */
77
78static int get_astate_freq(int astate)
79{
80 u32 ret;
81 ret = in_le32(sdcpwr_mapbase + SDCPWR_CFGA0_REG + (astate * 0x10));
82
83 return ret & 0x3f;
84}
85
86static int get_cur_astate(int cpu)
87{
88 u32 ret;
89
90 ret = in_le32(sdcpwr_mapbase + SDCPWR_PWST0_REG);
91 ret = (ret >> (cpu * 4)) & 0x7;
92
93 return ret;
94}
95
96static int get_gizmo_latency(void)
97{
98 u32 giztime, ret;
99
100 giztime = in_le32(sdcpwr_mapbase + SDCPWR_GIZTIME_REG);
101
102 /* just provide the upper bound */
103 if (giztime & SDCPWR_GIZTIME_GR)
104 ret = (giztime & SDCPWR_GIZTIME_LONGLOCK) * 128000;
105 else
106 ret = (giztime & SDCPWR_GIZTIME_LONGLOCK) * 1000;
107
108 return ret;
109}
110
111static void set_astate(int cpu, unsigned int astate)
112{
113 u64 flags;
114
115 /* Return if called before init has run */
116 if (unlikely(!sdcasr_mapbase))
117 return;
118
119 local_irq_save(flags);
120
121 out_le32(sdcasr_mapbase + SDCASR_REG + SDCASR_REG_STRIDE*cpu, astate);
122
123 local_irq_restore(flags);
124}
125
126void restore_astate(int cpu)
127{
128 set_astate(cpu, current_astate);
129}
130
131/*
132 * cpufreq functions
133 */
134
135static int pas_cpufreq_cpu_init(struct cpufreq_policy *policy)
136{
137 const u32 *max_freqp;
138 u32 max_freq;
139 int i, cur_astate;
140 struct resource res;
141 struct device_node *cpu, *dn;
142 int err = -ENODEV;
143
144 cpu = of_get_cpu_node(policy->cpu, NULL);
145
146 if (!cpu)
147 goto out;
148
149 dn = of_find_compatible_node(NULL, "sdc", "1682m-sdc");
150 if (!dn)
151 goto out;
152 err = of_address_to_resource(dn, 0, &res);
153 of_node_put(dn);
154 if (err)
155 goto out;
156 sdcasr_mapbase = ioremap(res.start + SDCASR_OFFSET, 0x2000);
157 if (!sdcasr_mapbase) {
158 err = -EINVAL;
159 goto out;
160 }
161
162 dn = of_find_compatible_node(NULL, "gizmo", "1682m-gizmo");
163 if (!dn) {
164 err = -ENODEV;
165 goto out_unmap_sdcasr;
166 }
167 err = of_address_to_resource(dn, 0, &res);
168 of_node_put(dn);
169 if (err)
170 goto out_unmap_sdcasr;
171 sdcpwr_mapbase = ioremap(res.start, 0x1000);
172 if (!sdcpwr_mapbase) {
173 err = -EINVAL;
174 goto out_unmap_sdcasr;
175 }
176
177 pr_debug("init cpufreq on CPU %d\n", policy->cpu);
178
179 max_freqp = of_get_property(cpu, "clock-frequency", NULL);
180 if (!max_freqp) {
181 err = -EINVAL;
182 goto out_unmap_sdcpwr;
183 }
184
185 /* we need the freq in kHz */
186 max_freq = *max_freqp / 1000;
187
188 pr_debug("max clock-frequency is at %u kHz\n", max_freq);
189 pr_debug("initializing frequency table\n");
190
191 /* initialize frequency table */
192 for (i=0; pas_freqs[i].frequency!=CPUFREQ_TABLE_END; i++) {
193 pas_freqs[i].frequency = get_astate_freq(pas_freqs[i].index) * 100000;
194 pr_debug("%d: %d\n", i, pas_freqs[i].frequency);
195 }
196
197 policy->governor = CPUFREQ_DEFAULT_GOVERNOR;
198
199 policy->cpuinfo.transition_latency = get_gizmo_latency();
200
201 cur_astate = get_cur_astate(policy->cpu);
202 pr_debug("current astate is at %d\n",cur_astate);
203
204 policy->cur = pas_freqs[cur_astate].frequency;
205 policy->cpus = cpu_online_map;
206
207 cpufreq_frequency_table_get_attr(pas_freqs, policy->cpu);
208
209 /* this ensures that policy->cpuinfo_min and policy->cpuinfo_max
210 * are set correctly
211 */
212 return cpufreq_frequency_table_cpuinfo(policy, pas_freqs);
213
214out_unmap_sdcpwr:
215 iounmap(sdcpwr_mapbase);
216
217out_unmap_sdcasr:
218 iounmap(sdcasr_mapbase);
219out:
220 return err;
221}
222
223static int pas_cpufreq_cpu_exit(struct cpufreq_policy *policy)
224{
225 if (sdcasr_mapbase)
226 iounmap(sdcasr_mapbase);
227 if (sdcpwr_mapbase)
228 iounmap(sdcpwr_mapbase);
229
230 cpufreq_frequency_table_put_attr(policy->cpu);
231 return 0;
232}
233
234static int pas_cpufreq_verify(struct cpufreq_policy *policy)
235{
236 return cpufreq_frequency_table_verify(policy, pas_freqs);
237}
238
239static int pas_cpufreq_target(struct cpufreq_policy *policy,
240 unsigned int target_freq,
241 unsigned int relation)
242{
243 struct cpufreq_freqs freqs;
244 int pas_astate_new;
245 int i;
246
247 cpufreq_frequency_table_target(policy,
248 pas_freqs,
249 target_freq,
250 relation,
251 &pas_astate_new);
252
253 freqs.old = policy->cur;
254 freqs.new = pas_freqs[pas_astate_new].frequency;
255 freqs.cpu = policy->cpu;
256
257 mutex_lock(&pas_switch_mutex);
258 cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
259
260 pr_debug("setting frequency for cpu %d to %d kHz, 1/%d of max frequency\n",
261 policy->cpu,
262 pas_freqs[pas_astate_new].frequency,
263 pas_freqs[pas_astate_new].index);
264
265 current_astate = pas_astate_new;
266
267 for_each_online_cpu(i)
268 set_astate(i, pas_astate_new);
269
270 cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
271 mutex_unlock(&pas_switch_mutex);
272
273 return 0;
274}
275
276static struct cpufreq_driver pas_cpufreq_driver = {
277 .name = "pas-cpufreq",
278 .owner = THIS_MODULE,
279 .flags = CPUFREQ_CONST_LOOPS,
280 .init = pas_cpufreq_cpu_init,
281 .exit = pas_cpufreq_cpu_exit,
282 .verify = pas_cpufreq_verify,
283 .target = pas_cpufreq_target,
284 .attr = pas_cpu_freqs_attr,
285};
286
287/*
288 * module init and destoy
289 */
290
291static int __init pas_cpufreq_init(void)
292{
293 if (!machine_is_compatible("PA6T-1682M"))
294 return -ENODEV;
295
296 return cpufreq_register_driver(&pas_cpufreq_driver);
297}
298
299static void __exit pas_cpufreq_exit(void)
300{
301 cpufreq_unregister_driver(&pas_cpufreq_driver);
302}
303
304module_init(pas_cpufreq_init);
305module_exit(pas_cpufreq_exit);
306
307MODULE_LICENSE("GPL");
308MODULE_AUTHOR("Egor Martovetsky <egor@pasemi.com>, Olof Johansson <olof@lixom.net>");
diff --git a/arch/powerpc/platforms/pasemi/gpio_mdio.c b/arch/powerpc/platforms/pasemi/gpio_mdio.c
new file mode 100644
index 000000000000..c91a33593bb8
--- /dev/null
+++ b/arch/powerpc/platforms/pasemi/gpio_mdio.c
@@ -0,0 +1,339 @@
1/*
2 * Copyright (C) 2006-2007 PA Semi, Inc
3 *
4 * Author: Olof Johansson, PA Semi
5 *
6 * Maintained by: Olof Johansson <olof@lixom.net>
7 *
8 * Based on drivers/net/fs_enet/mii-bitbang.c.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 */
23
24#include <linux/io.h>
25#include <linux/module.h>
26#include <linux/types.h>
27#include <linux/sched.h>
28#include <linux/errno.h>
29#include <linux/ioport.h>
30#include <linux/interrupt.h>
31#include <linux/phy.h>
32#include <linux/platform_device.h>
33#include <asm/of_platform.h>
34
35#define DELAY 1
36
37static void __iomem *gpio_regs;
38
39struct gpio_priv {
40 int mdc_pin;
41 int mdio_pin;
42};
43
44#define MDC_PIN(bus) (((struct gpio_priv *)bus->priv)->mdc_pin)
45#define MDIO_PIN(bus) (((struct gpio_priv *)bus->priv)->mdio_pin)
46
47static inline void mdio_lo(struct mii_bus *bus)
48{
49 out_le32(gpio_regs+0x10, 1 << MDIO_PIN(bus));
50}
51
52static inline void mdio_hi(struct mii_bus *bus)
53{
54 out_le32(gpio_regs, 1 << MDIO_PIN(bus));
55}
56
57static inline void mdc_lo(struct mii_bus *bus)
58{
59 out_le32(gpio_regs+0x10, 1 << MDC_PIN(bus));
60}
61
62static inline void mdc_hi(struct mii_bus *bus)
63{
64 out_le32(gpio_regs, 1 << MDC_PIN(bus));
65}
66
67static inline void mdio_active(struct mii_bus *bus)
68{
69 out_le32(gpio_regs+0x20, (1 << MDC_PIN(bus)) | (1 << MDIO_PIN(bus)));
70}
71
72static inline void mdio_tristate(struct mii_bus *bus)
73{
74 out_le32(gpio_regs+0x30, (1 << MDIO_PIN(bus)));
75}
76
77static inline int mdio_read(struct mii_bus *bus)
78{
79 return !!(in_le32(gpio_regs+0x40) & (1 << MDIO_PIN(bus)));
80}
81
82static void clock_out(struct mii_bus *bus, int bit)
83{
84 if (bit)
85 mdio_hi(bus);
86 else
87 mdio_lo(bus);
88 udelay(DELAY);
89 mdc_hi(bus);
90 udelay(DELAY);
91 mdc_lo(bus);
92}
93
94/* Utility to send the preamble, address, and register (common to read and write). */
95static void bitbang_pre(struct mii_bus *bus, int read, u8 addr, u8 reg)
96{
97 int i;
98
99 /* CFE uses a really long preamble (40 bits). We'll do the same. */
100 mdio_active(bus);
101 for (i = 0; i < 40; i++) {
102 clock_out(bus, 1);
103 }
104
105 /* send the start bit (01) and the read opcode (10) or write (10) */
106 clock_out(bus, 0);
107 clock_out(bus, 1);
108
109 clock_out(bus, read);
110 clock_out(bus, !read);
111
112 /* send the PHY address */
113 for (i = 0; i < 5; i++) {
114 clock_out(bus, (addr & 0x10) != 0);
115 addr <<= 1;
116 }
117
118 /* send the register address */
119 for (i = 0; i < 5; i++) {
120 clock_out(bus, (reg & 0x10) != 0);
121 reg <<= 1;
122 }
123}
124
125static int gpio_mdio_read(struct mii_bus *bus, int phy_id, int location)
126{
127 u16 rdreg;
128 int ret, i;
129 u8 addr = phy_id & 0xff;
130 u8 reg = location & 0xff;
131
132 bitbang_pre(bus, 1, addr, reg);
133
134 /* tri-state our MDIO I/O pin so we can read */
135 mdio_tristate(bus);
136 udelay(DELAY);
137 mdc_hi(bus);
138 udelay(DELAY);
139 mdc_lo(bus);
140
141 /* read 16 bits of register data, MSB first */
142 rdreg = 0;
143 for (i = 0; i < 16; i++) {
144 mdc_lo(bus);
145 udelay(DELAY);
146 mdc_hi(bus);
147 udelay(DELAY);
148 mdc_lo(bus);
149 udelay(DELAY);
150 rdreg <<= 1;
151 rdreg |= mdio_read(bus);
152 }
153
154 mdc_hi(bus);
155 udelay(DELAY);
156 mdc_lo(bus);
157 udelay(DELAY);
158
159 ret = rdreg;
160
161 return ret;
162}
163
164static int gpio_mdio_write(struct mii_bus *bus, int phy_id, int location, u16 val)
165{
166 int i;
167
168 u8 addr = phy_id & 0xff;
169 u8 reg = location & 0xff;
170 u16 value = val & 0xffff;
171
172 bitbang_pre(bus, 0, addr, reg);
173
174 /* send the turnaround (10) */
175 mdc_lo(bus);
176 mdio_hi(bus);
177 udelay(DELAY);
178 mdc_hi(bus);
179 udelay(DELAY);
180 mdc_lo(bus);
181 mdio_lo(bus);
182 udelay(DELAY);
183 mdc_hi(bus);
184 udelay(DELAY);
185
186 /* write 16 bits of register data, MSB first */
187 for (i = 0; i < 16; i++) {
188 mdc_lo(bus);
189 if (value & 0x8000)
190 mdio_hi(bus);
191 else
192 mdio_lo(bus);
193 udelay(DELAY);
194 mdc_hi(bus);
195 udelay(DELAY);
196 value <<= 1;
197 }
198
199 /*
200 * Tri-state the MDIO line.
201 */
202 mdio_tristate(bus);
203 mdc_lo(bus);
204 udelay(DELAY);
205 mdc_hi(bus);
206 udelay(DELAY);
207 return 0;
208}
209
210static int gpio_mdio_reset(struct mii_bus *bus)
211{
212 /*nothing here - dunno how to reset it*/
213 return 0;
214}
215
216
217static int __devinit gpio_mdio_probe(struct of_device *ofdev,
218 const struct of_device_id *match)
219{
220 struct device *dev = &ofdev->dev;
221 struct device_node *np = ofdev->node;
222 struct device_node *gpio_np;
223 struct mii_bus *new_bus;
224 struct resource res;
225 struct gpio_priv *priv;
226 const unsigned int *prop;
227 int err = 0;
228 int i;
229
230 gpio_np = of_find_compatible_node(NULL, "gpio", "1682m-gpio");
231
232 if (!gpio_np)
233 return -ENODEV;
234
235 err = of_address_to_resource(gpio_np, 0, &res);
236 of_node_put(gpio_np);
237
238 if (err)
239 return -EINVAL;
240
241 if (!gpio_regs)
242 gpio_regs = ioremap(res.start, 0x100);
243
244 if (!gpio_regs)
245 return -EPERM;
246
247 priv = kzalloc(sizeof(struct gpio_priv), GFP_KERNEL);
248 if (priv == NULL)
249 return -ENOMEM;
250
251 new_bus = kzalloc(sizeof(struct mii_bus), GFP_KERNEL);
252
253 if (new_bus == NULL)
254 return -ENOMEM;
255
256 new_bus->name = "pasemi gpio mdio bus",
257 new_bus->read = &gpio_mdio_read,
258 new_bus->write = &gpio_mdio_write,
259 new_bus->reset = &gpio_mdio_reset,
260
261 prop = of_get_property(np, "reg", NULL);
262 new_bus->id = *prop;
263 new_bus->priv = priv;
264
265 new_bus->phy_mask = 0;
266
267 new_bus->irq = kmalloc(sizeof(int)*PHY_MAX_ADDR, GFP_KERNEL);
268 for(i = 0; i < PHY_MAX_ADDR; ++i)
269 new_bus->irq[i] = irq_create_mapping(NULL, 10);
270
271
272 prop = of_get_property(np, "mdc-pin", NULL);
273 priv->mdc_pin = *prop;
274
275 prop = of_get_property(np, "mdio-pin", NULL);
276 priv->mdio_pin = *prop;
277
278 new_bus->dev = dev;
279 dev_set_drvdata(dev, new_bus);
280
281 err = mdiobus_register(new_bus);
282
283 if (0 != err) {
284 printk(KERN_ERR "%s: Cannot register as MDIO bus, err %d\n",
285 new_bus->name, err);
286 goto bus_register_fail;
287 }
288
289 return 0;
290
291bus_register_fail:
292 kfree(new_bus);
293
294 return err;
295}
296
297
298static int gpio_mdio_remove(struct of_device *dev)
299{
300 struct mii_bus *bus = dev_get_drvdata(&dev->dev);
301
302 mdiobus_unregister(bus);
303
304 dev_set_drvdata(&dev->dev, NULL);
305
306 kfree(bus->priv);
307 bus->priv = NULL;
308 kfree(bus);
309
310 return 0;
311}
312
313static struct of_device_id gpio_mdio_match[] =
314{
315 {
316 .compatible = "gpio-mdio",
317 },
318 {},
319};
320
321static struct of_platform_driver gpio_mdio_driver =
322{
323 .name = "gpio-mdio-bitbang",
324 .match_table = gpio_mdio_match,
325 .probe = gpio_mdio_probe,
326 .remove = gpio_mdio_remove,
327};
328
329int gpio_mdio_init(void)
330{
331 return of_register_platform_driver(&gpio_mdio_driver);
332}
333
334void gpio_mdio_exit(void)
335{
336 of_unregister_platform_driver(&gpio_mdio_driver);
337}
338device_initcall(gpio_mdio_init);
339
diff --git a/arch/powerpc/platforms/pasemi/idle.c b/arch/powerpc/platforms/pasemi/idle.c
index 1ca3ff381591..5985ce0c5c48 100644
--- a/arch/powerpc/platforms/pasemi/idle.c
+++ b/arch/powerpc/platforms/pasemi/idle.c
@@ -61,6 +61,10 @@ static int pasemi_system_reset_exception(struct pt_regs *regs)
61 /* do system reset */ 61 /* do system reset */
62 return 0; 62 return 0;
63 } 63 }
64
65 /* Set higher astate since we come out of power savings at 0 */
66 restore_astate(hard_smp_processor_id());
67
64 /* everything handled */ 68 /* everything handled */
65 regs->msr |= MSR_RI; 69 regs->msr |= MSR_RI;
66 return 1; 70 return 1;
@@ -68,6 +72,11 @@ static int pasemi_system_reset_exception(struct pt_regs *regs)
68 72
69void __init pasemi_idle_init(void) 73void __init pasemi_idle_init(void)
70{ 74{
75#ifndef CONFIG_PPC_PASEMI_CPUFREQ
76 printk(KERN_WARNING "No cpufreq driver, powersavings modes disabled\n");
77 current_mode = 0;
78#endif
79
71 ppc_md.system_reset_exception = pasemi_system_reset_exception; 80 ppc_md.system_reset_exception = pasemi_system_reset_exception;
72 ppc_md.power_save = modes[current_mode].entry; 81 ppc_md.power_save = modes[current_mode].entry;
73 printk(KERN_INFO "Using PA6T idle loop (%s)\n", modes[current_mode].name); 82 printk(KERN_INFO "Using PA6T idle loop (%s)\n", modes[current_mode].name);
diff --git a/arch/powerpc/platforms/pasemi/iommu.c b/arch/powerpc/platforms/pasemi/iommu.c
index 71dbf1a56e13..95fa6a7d15ee 100644
--- a/arch/powerpc/platforms/pasemi/iommu.c
+++ b/arch/powerpc/platforms/pasemi/iommu.c
@@ -249,13 +249,13 @@ void iommu_init_early_pasemi(void)
249 iommu_off = 1; 249 iommu_off = 1;
250#else 250#else
251 iommu_off = of_chosen && 251 iommu_off = of_chosen &&
252 get_property(of_chosen, "linux,iommu-off", NULL); 252 of_get_property(of_chosen, "linux,iommu-off", NULL);
253#endif 253#endif
254 if (iommu_off) { 254 if (iommu_off) {
255 /* Direct I/O, IOMMU off */ 255 /* Direct I/O, IOMMU off */
256 ppc_md.pci_dma_dev_setup = pci_dma_dev_setup_null; 256 ppc_md.pci_dma_dev_setup = pci_dma_dev_setup_null;
257 ppc_md.pci_dma_bus_setup = pci_dma_bus_setup_null; 257 ppc_md.pci_dma_bus_setup = pci_dma_bus_setup_null;
258 pci_dma_ops = &dma_direct_ops; 258 set_pci_dma_ops(&dma_direct_ops);
259 259
260 return; 260 return;
261 } 261 }
@@ -266,7 +266,7 @@ void iommu_init_early_pasemi(void)
266 ppc_md.pci_dma_bus_setup = pci_dma_bus_setup_pasemi; 266 ppc_md.pci_dma_bus_setup = pci_dma_bus_setup_pasemi;
267 ppc_md.tce_build = iobmap_build; 267 ppc_md.tce_build = iobmap_build;
268 ppc_md.tce_free = iobmap_free; 268 ppc_md.tce_free = iobmap_free;
269 pci_dma_ops = &dma_iommu_ops; 269 set_pci_dma_ops(&dma_iommu_ops);
270} 270}
271 271
272void __init alloc_iobmap_l2(void) 272void __init alloc_iobmap_l2(void)
diff --git a/arch/powerpc/platforms/pasemi/pasemi.h b/arch/powerpc/platforms/pasemi/pasemi.h
index 2d3927e6edb0..be8495497611 100644
--- a/arch/powerpc/platforms/pasemi/pasemi.h
+++ b/arch/powerpc/platforms/pasemi/pasemi.h
@@ -14,6 +14,14 @@ extern void __init pasemi_idle_init(void);
14extern void idle_spin(void); 14extern void idle_spin(void);
15extern void idle_doze(void); 15extern void idle_doze(void);
16 16
17/* Restore astate to last set */
18#ifdef CONFIG_PPC_PASEMI_CPUFREQ
19extern void restore_astate(int cpu);
20#else
21static inline void restore_astate(int cpu)
22{
23}
24#endif
17 25
18 26
19#endif /* _PASEMI_PASEMI_H */ 27#endif /* _PASEMI_PASEMI_H */
diff --git a/arch/powerpc/platforms/pasemi/pci.c b/arch/powerpc/platforms/pasemi/pci.c
index 7ecb2ba24db9..056243da360b 100644
--- a/arch/powerpc/platforms/pasemi/pci.c
+++ b/arch/powerpc/platforms/pasemi/pci.c
@@ -33,7 +33,17 @@
33 33
34#define PA_PXP_CFA(bus, devfn, off) (((bus) << 20) | ((devfn) << 12) | (off)) 34#define PA_PXP_CFA(bus, devfn, off) (((bus) << 20) | ((devfn) << 12) | (off))
35 35
36#define CONFIG_OFFSET_VALID(off) ((off) < 4096) 36static inline int pa_pxp_offset_valid(u8 bus, u8 devfn, int offset)
37{
38 /* Device 0 Function 0 is special: It's config space spans function 1 as
39 * well, so allow larger offset. It's really a two-function device but the
40 * second function does not probe.
41 */
42 if (bus == 0 && devfn == 0)
43 return offset < 8192;
44 else
45 return offset < 4096;
46}
37 47
38static void volatile __iomem *pa_pxp_cfg_addr(struct pci_controller *hose, 48static void volatile __iomem *pa_pxp_cfg_addr(struct pci_controller *hose,
39 u8 bus, u8 devfn, int offset) 49 u8 bus, u8 devfn, int offset)
@@ -51,7 +61,7 @@ static int pa_pxp_read_config(struct pci_bus *bus, unsigned int devfn,
51 if (!hose) 61 if (!hose)
52 return PCIBIOS_DEVICE_NOT_FOUND; 62 return PCIBIOS_DEVICE_NOT_FOUND;
53 63
54 if (!CONFIG_OFFSET_VALID(offset)) 64 if (!pa_pxp_offset_valid(bus->number, devfn, offset))
55 return PCIBIOS_BAD_REGISTER_NUMBER; 65 return PCIBIOS_BAD_REGISTER_NUMBER;
56 66
57 addr = pa_pxp_cfg_addr(hose, bus->number, devfn, offset); 67 addr = pa_pxp_cfg_addr(hose, bus->number, devfn, offset);
@@ -85,7 +95,7 @@ static int pa_pxp_write_config(struct pci_bus *bus, unsigned int devfn,
85 if (!hose) 95 if (!hose)
86 return PCIBIOS_DEVICE_NOT_FOUND; 96 return PCIBIOS_DEVICE_NOT_FOUND;
87 97
88 if (!CONFIG_OFFSET_VALID(offset)) 98 if (!pa_pxp_offset_valid(bus->number, devfn, offset))
89 return PCIBIOS_BAD_REGISTER_NUMBER; 99 return PCIBIOS_BAD_REGISTER_NUMBER;
90 100
91 addr = pa_pxp_cfg_addr(hose, bus->number, devfn, offset); 101 addr = pa_pxp_cfg_addr(hose, bus->number, devfn, offset);
diff --git a/arch/powerpc/platforms/pasemi/setup.c b/arch/powerpc/platforms/pasemi/setup.c
index 449cf1a08291..f88f0ec4c8cb 100644
--- a/arch/powerpc/platforms/pasemi/setup.c
+++ b/arch/powerpc/platforms/pasemi/setup.c
@@ -35,6 +35,7 @@
35#include <asm/mpic.h> 35#include <asm/mpic.h>
36#include <asm/smp.h> 36#include <asm/smp.h>
37#include <asm/time.h> 37#include <asm/time.h>
38#include <asm/of_platform.h>
38 39
39#include "pasemi.h" 40#include "pasemi.h"
40 41
@@ -101,12 +102,6 @@ void __init pas_setup_arch(void)
101 pasemi_idle_init(); 102 pasemi_idle_init();
102} 103}
103 104
104/* No legacy IO on our parts */
105static int pas_check_legacy_ioport(unsigned int baseport)
106{
107 return -ENODEV;
108}
109
110static __init void pas_init_IRQ(void) 105static __init void pas_init_IRQ(void)
111{ 106{
112 struct device_node *np; 107 struct device_node *np;
@@ -136,8 +131,8 @@ static __init void pas_init_IRQ(void)
136 131
137 /* Find address list in /platform-open-pic */ 132 /* Find address list in /platform-open-pic */
138 root = of_find_node_by_path("/"); 133 root = of_find_node_by_path("/");
139 naddr = prom_n_addr_cells(root); 134 naddr = of_n_addr_cells(root);
140 opprop = get_property(root, "platform-open-pic", &opplen); 135 opprop = of_get_property(root, "platform-open-pic", &opplen);
141 if (!opprop) { 136 if (!opprop) {
142 printk(KERN_ERR "No platform-open-pic property.\n"); 137 printk(KERN_ERR "No platform-open-pic property.\n");
143 of_node_put(root); 138 of_node_put(root);
@@ -147,7 +142,7 @@ static __init void pas_init_IRQ(void)
147 printk(KERN_DEBUG "OpenPIC addr: %lx\n", openpic_addr); 142 printk(KERN_DEBUG "OpenPIC addr: %lx\n", openpic_addr);
148 143
149 mpic = mpic_alloc(mpic_node, openpic_addr, 144 mpic = mpic_alloc(mpic_node, openpic_addr,
150 MPIC_PRIMARY|MPIC_LARGE_VECTORS, 145 MPIC_PRIMARY|MPIC_LARGE_VECTORS|MPIC_WANTS_RESET,
151 0, 0, " PAS-OPIC "); 146 0, 0, " PAS-OPIC ");
152 BUG_ON(!mpic); 147 BUG_ON(!mpic);
153 148
@@ -209,6 +204,20 @@ static void __init pas_init_early(void)
209 iommu_init_early_pasemi(); 204 iommu_init_early_pasemi();
210} 205}
211 206
207static struct of_device_id pasemi_bus_ids[] = {
208 { .type = "sdc", },
209 {},
210};
211
212static int __init pasemi_publish_devices(void)
213{
214 /* Publish OF platform devices for southbridge IOs */
215 of_platform_bus_probe(NULL, pasemi_bus_ids, NULL);
216
217 return 0;
218}
219device_initcall(pasemi_publish_devices);
220
212 221
213/* 222/*
214 * Called very early, MMU is off, device-tree isn't unflattened 223 * Called very early, MMU is off, device-tree isn't unflattened
@@ -237,7 +246,6 @@ define_machine(pas) {
237 .restart = pas_restart, 246 .restart = pas_restart,
238 .get_boot_time = pas_get_boot_time, 247 .get_boot_time = pas_get_boot_time,
239 .calibrate_decr = generic_calibrate_decr, 248 .calibrate_decr = generic_calibrate_decr,
240 .check_legacy_ioport = pas_check_legacy_ioport,
241 .progress = pas_progress, 249 .progress = pas_progress,
242 .machine_check_exception = pas_machine_check_handler, 250 .machine_check_exception = pas_machine_check_handler,
243 .pci_irq_fixup = pas_pci_irq_fixup, 251 .pci_irq_fixup = pas_pci_irq_fixup,
generated by cgit v1.2.2 (git 2.25.0) at 2025-03-08 20:15:27 -0500