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-rw-r--r--arch/powerpc/platforms/iseries/exception.S27
1 files changed, 26 insertions, 1 deletions
diff --git a/arch/powerpc/platforms/iseries/exception.S b/arch/powerpc/platforms/iseries/exception.S
index c775cd4b3d6e..8ff330d026ca 100644
--- a/arch/powerpc/platforms/iseries/exception.S
+++ b/arch/powerpc/platforms/iseries/exception.S
@@ -59,8 +59,33 @@ system_reset_iSeries:
59 andc r4,r4,r5 59 andc r4,r4,r5
60 mtspr SPRN_CTRLT,r4 60 mtspr SPRN_CTRLT,r4
61 61
62/* Spin on __secondary_hold_spinloop until it is updated by the boot cpu. */
63/* In the UP case we'll yeild() later, and we will not access the paca anyway */
64#ifdef CONFIG_SMP
621: 651:
63 HMT_LOW 66 HMT_LOW
67 LOAD_REG_IMMEDIATE(r23, __secondary_hold_spinloop)
68 ld r23,0(r23)
69 sync
70 LOAD_REG_IMMEDIATE(r3,current_set)
71 sldi r28,r24,3 /* get current_set[cpu#] */
72 ldx r3,r3,r28
73 addi r1,r3,THREAD_SIZE
74 subi r1,r1,STACK_FRAME_OVERHEAD
75
76 cmpwi 0,r23,0 /* Keep poking the Hypervisor until */
77 bne 2f /* we're released */
78 /* Let the Hypervisor know we are alive */
79 /* 8002 is a call to HvCallCfg::getLps, a harmless Hypervisor function */
80 lis r3,0x8002
81 rldicr r3,r3,32,15 /* r0 = (r3 << 32) & 0xffff000000000000 */
82 li r0,-1 /* r0=-1 indicates a Hypervisor call */
83 sc /* Invoke the hypervisor via a system call */
84 b 1b
85#endif
86
872:
88 HMT_LOW
64#ifdef CONFIG_SMP 89#ifdef CONFIG_SMP
65 lbz r23,PACAPROCSTART(r13) /* Test if this processor 90 lbz r23,PACAPROCSTART(r13) /* Test if this processor
66 * should start */ 91 * should start */
@@ -91,7 +116,7 @@ iSeries_secondary_smp_loop:
91 li r0,-1 /* r0=-1 indicates a Hypervisor call */ 116 li r0,-1 /* r0=-1 indicates a Hypervisor call */
92 sc /* Invoke the hypervisor via a system call */ 117 sc /* Invoke the hypervisor via a system call */
93 mfspr r13,SPRN_SPRG3 /* Put r13 back ???? */ 118 mfspr r13,SPRN_SPRG3 /* Put r13 back ???? */
94 b 1b /* If SMP not configured, secondaries 119 b 2b /* If SMP not configured, secondaries
95 * loop forever */ 120 * loop forever */
96 121
97/*** ISeries-LPAR interrupt handlers ***/ 122/*** ISeries-LPAR interrupt handlers ***/