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-rw-r--r--arch/powerpc/platforms/iseries/pci.c903
1 files changed, 903 insertions, 0 deletions
diff --git a/arch/powerpc/platforms/iseries/pci.c b/arch/powerpc/platforms/iseries/pci.c
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index 000000000000..61a857218bc8
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+++ b/arch/powerpc/platforms/iseries/pci.c
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1/*
2 * Copyright (C) 2001 Allan Trautman, IBM Corporation
3 *
4 * iSeries specific routines for PCI.
5 *
6 * Based on code from pci.c and iSeries_pci.c 32bit
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 */
22#include <linux/kernel.h>
23#include <linux/list.h>
24#include <linux/string.h>
25#include <linux/init.h>
26#include <linux/module.h>
27#include <linux/ide.h>
28#include <linux/pci.h>
29
30#include <asm/io.h>
31#include <asm/irq.h>
32#include <asm/prom.h>
33#include <asm/machdep.h>
34#include <asm/pci-bridge.h>
35#include <asm/ppcdebug.h>
36#include <asm/iommu.h>
37
38#include <asm/iSeries/HvCallPci.h>
39#include <asm/iSeries/HvCallXm.h>
40#include <asm/iSeries/iSeries_irq.h>
41#include <asm/iSeries/iSeries_pci.h>
42#include <asm/iSeries/mf.h>
43
44#include <asm/ppc-pci.h>
45
46extern unsigned long io_page_mask;
47
48/*
49 * Forward declares of prototypes.
50 */
51static struct iSeries_Device_Node *find_Device_Node(int bus, int devfn);
52static void scan_PHB_slots(struct pci_controller *Phb);
53static void scan_EADS_bridge(HvBusNumber Bus, HvSubBusNumber SubBus, int IdSel);
54static int scan_bridge_slot(HvBusNumber Bus, struct HvCallPci_BridgeInfo *Info);
55
56LIST_HEAD(iSeries_Global_Device_List);
57
58static int DeviceCount;
59
60/* Counters and control flags. */
61static long Pci_Io_Read_Count;
62static long Pci_Io_Write_Count;
63#if 0
64static long Pci_Cfg_Read_Count;
65static long Pci_Cfg_Write_Count;
66#endif
67static long Pci_Error_Count;
68
69static int Pci_Retry_Max = 3; /* Only retry 3 times */
70static int Pci_Error_Flag = 1; /* Set Retry Error on. */
71
72static struct pci_ops iSeries_pci_ops;
73
74/*
75 * Table defines
76 * Each Entry size is 4 MB * 1024 Entries = 4GB I/O address space.
77 */
78#define IOMM_TABLE_MAX_ENTRIES 1024
79#define IOMM_TABLE_ENTRY_SIZE 0x0000000000400000UL
80#define BASE_IO_MEMORY 0xE000000000000000UL
81
82static unsigned long max_io_memory = 0xE000000000000000UL;
83static long current_iomm_table_entry;
84
85/*
86 * Lookup Tables.
87 */
88static struct iSeries_Device_Node **iomm_table;
89static u8 *iobar_table;
90
91/*
92 * Static and Global variables
93 */
94static char *pci_io_text = "iSeries PCI I/O";
95static DEFINE_SPINLOCK(iomm_table_lock);
96
97/*
98 * iomm_table_initialize
99 *
100 * Allocates and initalizes the Address Translation Table and Bar
101 * Tables to get them ready for use. Must be called before any
102 * I/O space is handed out to the device BARs.
103 */
104static void iomm_table_initialize(void)
105{
106 spin_lock(&iomm_table_lock);
107 iomm_table = kmalloc(sizeof(*iomm_table) * IOMM_TABLE_MAX_ENTRIES,
108 GFP_KERNEL);
109 iobar_table = kmalloc(sizeof(*iobar_table) * IOMM_TABLE_MAX_ENTRIES,
110 GFP_KERNEL);
111 spin_unlock(&iomm_table_lock);
112 if ((iomm_table == NULL) || (iobar_table == NULL))
113 panic("PCI: I/O tables allocation failed.\n");
114}
115
116/*
117 * iomm_table_allocate_entry
118 *
119 * Adds pci_dev entry in address translation table
120 *
121 * - Allocates the number of entries required in table base on BAR
122 * size.
123 * - Allocates starting at BASE_IO_MEMORY and increases.
124 * - The size is round up to be a multiple of entry size.
125 * - CurrentIndex is incremented to keep track of the last entry.
126 * - Builds the resource entry for allocated BARs.
127 */
128static void iomm_table_allocate_entry(struct pci_dev *dev, int bar_num)
129{
130 struct resource *bar_res = &dev->resource[bar_num];
131 long bar_size = pci_resource_len(dev, bar_num);
132
133 /*
134 * No space to allocate, quick exit, skip Allocation.
135 */
136 if (bar_size == 0)
137 return;
138 /*
139 * Set Resource values.
140 */
141 spin_lock(&iomm_table_lock);
142 bar_res->name = pci_io_text;
143 bar_res->start =
144 IOMM_TABLE_ENTRY_SIZE * current_iomm_table_entry;
145 bar_res->start += BASE_IO_MEMORY;
146 bar_res->end = bar_res->start + bar_size - 1;
147 /*
148 * Allocate the number of table entries needed for BAR.
149 */
150 while (bar_size > 0 ) {
151 iomm_table[current_iomm_table_entry] = dev->sysdata;
152 iobar_table[current_iomm_table_entry] = bar_num;
153 bar_size -= IOMM_TABLE_ENTRY_SIZE;
154 ++current_iomm_table_entry;
155 }
156 max_io_memory = BASE_IO_MEMORY +
157 (IOMM_TABLE_ENTRY_SIZE * current_iomm_table_entry);
158 spin_unlock(&iomm_table_lock);
159}
160
161/*
162 * allocate_device_bars
163 *
164 * - Allocates ALL pci_dev BAR's and updates the resources with the
165 * BAR value. BARS with zero length will have the resources
166 * The HvCallPci_getBarParms is used to get the size of the BAR
167 * space. It calls iomm_table_allocate_entry to allocate
168 * each entry.
169 * - Loops through The Bar resources(0 - 5) including the ROM
170 * is resource(6).
171 */
172static void allocate_device_bars(struct pci_dev *dev)
173{
174 struct resource *bar_res;
175 int bar_num;
176
177 for (bar_num = 0; bar_num <= PCI_ROM_RESOURCE; ++bar_num) {
178 bar_res = &dev->resource[bar_num];
179 iomm_table_allocate_entry(dev, bar_num);
180 }
181}
182
183/*
184 * Log error information to system console.
185 * Filter out the device not there errors.
186 * PCI: EADs Connect Failed 0x18.58.10 Rc: 0x00xx
187 * PCI: Read Vendor Failed 0x18.58.10 Rc: 0x00xx
188 * PCI: Connect Bus Unit Failed 0x18.58.10 Rc: 0x00xx
189 */
190static void pci_Log_Error(char *Error_Text, int Bus, int SubBus,
191 int AgentId, int HvRc)
192{
193 if (HvRc == 0x0302)
194 return;
195 printk(KERN_ERR "PCI: %s Failed: 0x%02X.%02X.%02X Rc: 0x%04X",
196 Error_Text, Bus, SubBus, AgentId, HvRc);
197}
198
199/*
200 * build_device_node(u16 Bus, int SubBus, u8 DevFn)
201 */
202static struct iSeries_Device_Node *build_device_node(HvBusNumber Bus,
203 HvSubBusNumber SubBus, int AgentId, int Function)
204{
205 struct iSeries_Device_Node *node;
206
207 PPCDBG(PPCDBG_BUSWALK,
208 "-build_device_node 0x%02X.%02X.%02X Function: %02X\n",
209 Bus, SubBus, AgentId, Function);
210
211 node = kmalloc(sizeof(struct iSeries_Device_Node), GFP_KERNEL);
212 if (node == NULL)
213 return NULL;
214
215 memset(node, 0, sizeof(struct iSeries_Device_Node));
216 list_add_tail(&node->Device_List, &iSeries_Global_Device_List);
217#if 0
218 node->DsaAddr = ((u64)Bus << 48) + ((u64)SubBus << 40) + ((u64)0x10 << 32);
219#endif
220 node->DsaAddr.DsaAddr = 0;
221 node->DsaAddr.Dsa.busNumber = Bus;
222 node->DsaAddr.Dsa.subBusNumber = SubBus;
223 node->DsaAddr.Dsa.deviceId = 0x10;
224 node->DevFn = PCI_DEVFN(ISERIES_ENCODE_DEVICE(AgentId), Function);
225 return node;
226}
227
228/*
229 * unsigned long __init find_and_init_phbs(void)
230 *
231 * Description:
232 * This function checks for all possible system PCI host bridges that connect
233 * PCI buses. The system hypervisor is queried as to the guest partition
234 * ownership status. A pci_controller is built for any bus which is partially
235 * owned or fully owned by this guest partition.
236 */
237unsigned long __init find_and_init_phbs(void)
238{
239 struct pci_controller *phb;
240 HvBusNumber bus;
241
242 PPCDBG(PPCDBG_BUSWALK, "find_and_init_phbs Entry\n");
243
244 /* Check all possible buses. */
245 for (bus = 0; bus < 256; bus++) {
246 int ret = HvCallXm_testBus(bus);
247 if (ret == 0) {
248 printk("bus %d appears to exist\n", bus);
249
250 phb = (struct pci_controller *)kmalloc(sizeof(struct pci_controller), GFP_KERNEL);
251 if (phb == NULL)
252 return -ENOMEM;
253 pci_setup_pci_controller(phb);
254
255 phb->pci_mem_offset = phb->local_number = bus;
256 phb->first_busno = bus;
257 phb->last_busno = bus;
258 phb->ops = &iSeries_pci_ops;
259
260 PPCDBG(PPCDBG_BUSWALK, "PCI:Create iSeries pci_controller(%p), Bus: %04X\n",
261 phb, bus);
262
263 /* Find and connect the devices. */
264 scan_PHB_slots(phb);
265 }
266 /*
267 * Check for Unexpected Return code, a clue that something
268 * has gone wrong.
269 */
270 else if (ret != 0x0301)
271 printk(KERN_ERR "Unexpected Return on Probe(0x%04X): 0x%04X",
272 bus, ret);
273 }
274 return 0;
275}
276
277/*
278 * iSeries_pcibios_init
279 *
280 * Chance to initialize and structures or variable before PCI Bus walk.
281 */
282void iSeries_pcibios_init(void)
283{
284 PPCDBG(PPCDBG_BUSWALK, "iSeries_pcibios_init Entry.\n");
285 iomm_table_initialize();
286 find_and_init_phbs();
287 io_page_mask = -1;
288 PPCDBG(PPCDBG_BUSWALK, "iSeries_pcibios_init Exit.\n");
289}
290
291/*
292 * iSeries_pci_final_fixup(void)
293 */
294void __init iSeries_pci_final_fixup(void)
295{
296 struct pci_dev *pdev = NULL;
297 struct iSeries_Device_Node *node;
298 int DeviceCount = 0;
299
300 PPCDBG(PPCDBG_BUSWALK, "iSeries_pcibios_fixup Entry.\n");
301
302 /* Fix up at the device node and pci_dev relationship */
303 mf_display_src(0xC9000100);
304
305 printk("pcibios_final_fixup\n");
306 for_each_pci_dev(pdev) {
307 node = find_Device_Node(pdev->bus->number, pdev->devfn);
308 printk("pci dev %p (%x.%x), node %p\n", pdev,
309 pdev->bus->number, pdev->devfn, node);
310
311 if (node != NULL) {
312 ++DeviceCount;
313 pdev->sysdata = (void *)node;
314 node->PciDev = pdev;
315 PPCDBG(PPCDBG_BUSWALK,
316 "pdev 0x%p <==> DevNode 0x%p\n",
317 pdev, node);
318 allocate_device_bars(pdev);
319 iSeries_Device_Information(pdev, DeviceCount);
320 iommu_devnode_init_iSeries(node);
321 } else
322 printk("PCI: Device Tree not found for 0x%016lX\n",
323 (unsigned long)pdev);
324 pdev->irq = node->Irq;
325 }
326 iSeries_activate_IRQs();
327 mf_display_src(0xC9000200);
328}
329
330void pcibios_fixup_bus(struct pci_bus *PciBus)
331{
332 PPCDBG(PPCDBG_BUSWALK, "iSeries_pcibios_fixup_bus(0x%04X) Entry.\n",
333 PciBus->number);
334}
335
336void pcibios_fixup_resources(struct pci_dev *pdev)
337{
338 PPCDBG(PPCDBG_BUSWALK, "fixup_resources pdev %p\n", pdev);
339}
340
341/*
342 * Loop through each node function to find usable EADs bridges.
343 */
344static void scan_PHB_slots(struct pci_controller *Phb)
345{
346 struct HvCallPci_DeviceInfo *DevInfo;
347 HvBusNumber bus = Phb->local_number; /* System Bus */
348 const HvSubBusNumber SubBus = 0; /* EADs is always 0. */
349 int HvRc = 0;
350 int IdSel;
351 const int MaxAgents = 8;
352
353 DevInfo = (struct HvCallPci_DeviceInfo*)
354 kmalloc(sizeof(struct HvCallPci_DeviceInfo), GFP_KERNEL);
355 if (DevInfo == NULL)
356 return;
357
358 /*
359 * Probe for EADs Bridges
360 */
361 for (IdSel = 1; IdSel < MaxAgents; ++IdSel) {
362 HvRc = HvCallPci_getDeviceInfo(bus, SubBus, IdSel,
363 ISERIES_HV_ADDR(DevInfo),
364 sizeof(struct HvCallPci_DeviceInfo));
365 if (HvRc == 0) {
366 if (DevInfo->deviceType == HvCallPci_NodeDevice)
367 scan_EADS_bridge(bus, SubBus, IdSel);
368 else
369 printk("PCI: Invalid System Configuration(0x%02X)"
370 " for bus 0x%02x id 0x%02x.\n",
371 DevInfo->deviceType, bus, IdSel);
372 }
373 else
374 pci_Log_Error("getDeviceInfo", bus, SubBus, IdSel, HvRc);
375 }
376 kfree(DevInfo);
377}
378
379static void scan_EADS_bridge(HvBusNumber bus, HvSubBusNumber SubBus,
380 int IdSel)
381{
382 struct HvCallPci_BridgeInfo *BridgeInfo;
383 HvAgentId AgentId;
384 int Function;
385 int HvRc;
386
387 BridgeInfo = (struct HvCallPci_BridgeInfo *)
388 kmalloc(sizeof(struct HvCallPci_BridgeInfo), GFP_KERNEL);
389 if (BridgeInfo == NULL)
390 return;
391
392 /* Note: hvSubBus and irq is always be 0 at this level! */
393 for (Function = 0; Function < 8; ++Function) {
394 AgentId = ISERIES_PCI_AGENTID(IdSel, Function);
395 HvRc = HvCallXm_connectBusUnit(bus, SubBus, AgentId, 0);
396 if (HvRc == 0) {
397 printk("found device at bus %d idsel %d func %d (AgentId %x)\n",
398 bus, IdSel, Function, AgentId);
399 /* Connect EADs: 0x18.00.12 = 0x00 */
400 PPCDBG(PPCDBG_BUSWALK,
401 "PCI:Connect EADs: 0x%02X.%02X.%02X\n",
402 bus, SubBus, AgentId);
403 HvRc = HvCallPci_getBusUnitInfo(bus, SubBus, AgentId,
404 ISERIES_HV_ADDR(BridgeInfo),
405 sizeof(struct HvCallPci_BridgeInfo));
406 if (HvRc == 0) {
407 printk("bridge info: type %x subbus %x maxAgents %x maxsubbus %x logslot %x\n",
408 BridgeInfo->busUnitInfo.deviceType,
409 BridgeInfo->subBusNumber,
410 BridgeInfo->maxAgents,
411 BridgeInfo->maxSubBusNumber,
412 BridgeInfo->logicalSlotNumber);
413 PPCDBG(PPCDBG_BUSWALK,
414 "PCI: BridgeInfo, Type:0x%02X, SubBus:0x%02X, MaxAgents:0x%02X, MaxSubBus: 0x%02X, LSlot: 0x%02X\n",
415 BridgeInfo->busUnitInfo.deviceType,
416 BridgeInfo->subBusNumber,
417 BridgeInfo->maxAgents,
418 BridgeInfo->maxSubBusNumber,
419 BridgeInfo->logicalSlotNumber);
420
421 if (BridgeInfo->busUnitInfo.deviceType ==
422 HvCallPci_BridgeDevice) {
423 /* Scan_Bridge_Slot...: 0x18.00.12 */
424 scan_bridge_slot(bus, BridgeInfo);
425 } else
426 printk("PCI: Invalid Bridge Configuration(0x%02X)",
427 BridgeInfo->busUnitInfo.deviceType);
428 }
429 } else if (HvRc != 0x000B)
430 pci_Log_Error("EADs Connect",
431 bus, SubBus, AgentId, HvRc);
432 }
433 kfree(BridgeInfo);
434}
435
436/*
437 * This assumes that the node slot is always on the primary bus!
438 */
439static int scan_bridge_slot(HvBusNumber Bus,
440 struct HvCallPci_BridgeInfo *BridgeInfo)
441{
442 struct iSeries_Device_Node *node;
443 HvSubBusNumber SubBus = BridgeInfo->subBusNumber;
444 u16 VendorId = 0;
445 int HvRc = 0;
446 u8 Irq = 0;
447 int IdSel = ISERIES_GET_DEVICE_FROM_SUBBUS(SubBus);
448 int Function = ISERIES_GET_FUNCTION_FROM_SUBBUS(SubBus);
449 HvAgentId EADsIdSel = ISERIES_PCI_AGENTID(IdSel, Function);
450
451 /* iSeries_allocate_IRQ.: 0x18.00.12(0xA3) */
452 Irq = iSeries_allocate_IRQ(Bus, 0, EADsIdSel);
453 PPCDBG(PPCDBG_BUSWALK,
454 "PCI:- allocate and assign IRQ 0x%02X.%02X.%02X = 0x%02X\n",
455 Bus, 0, EADsIdSel, Irq);
456
457 /*
458 * Connect all functions of any device found.
459 */
460 for (IdSel = 1; IdSel <= BridgeInfo->maxAgents; ++IdSel) {
461 for (Function = 0; Function < 8; ++Function) {
462 HvAgentId AgentId = ISERIES_PCI_AGENTID(IdSel, Function);
463 HvRc = HvCallXm_connectBusUnit(Bus, SubBus,
464 AgentId, Irq);
465 if (HvRc != 0) {
466 pci_Log_Error("Connect Bus Unit",
467 Bus, SubBus, AgentId, HvRc);
468 continue;
469 }
470
471 HvRc = HvCallPci_configLoad16(Bus, SubBus, AgentId,
472 PCI_VENDOR_ID, &VendorId);
473 if (HvRc != 0) {
474 pci_Log_Error("Read Vendor",
475 Bus, SubBus, AgentId, HvRc);
476 continue;
477 }
478 printk("read vendor ID: %x\n", VendorId);
479
480 /* FoundDevice: 0x18.28.10 = 0x12AE */
481 PPCDBG(PPCDBG_BUSWALK,
482 "PCI:- FoundDevice: 0x%02X.%02X.%02X = 0x%04X, irq %d\n",
483 Bus, SubBus, AgentId, VendorId, Irq);
484 HvRc = HvCallPci_configStore8(Bus, SubBus, AgentId,
485 PCI_INTERRUPT_LINE, Irq);
486 if (HvRc != 0)
487 pci_Log_Error("PciCfgStore Irq Failed!",
488 Bus, SubBus, AgentId, HvRc);
489
490 ++DeviceCount;
491 node = build_device_node(Bus, SubBus, EADsIdSel, Function);
492 node->Irq = Irq;
493 node->LogicalSlot = BridgeInfo->logicalSlotNumber;
494
495 } /* for (Function = 0; Function < 8; ++Function) */
496 } /* for (IdSel = 1; IdSel <= MaxAgents; ++IdSel) */
497 return HvRc;
498}
499
500/*
501 * I/0 Memory copy MUST use mmio commands on iSeries
502 * To do; For performance, include the hv call directly
503 */
504void iSeries_memset_io(volatile void __iomem *dest, char c, size_t Count)
505{
506 u8 ByteValue = c;
507 long NumberOfBytes = Count;
508
509 while (NumberOfBytes > 0) {
510 iSeries_Write_Byte(ByteValue, dest++);
511 -- NumberOfBytes;
512 }
513}
514EXPORT_SYMBOL(iSeries_memset_io);
515
516void iSeries_memcpy_toio(volatile void __iomem *dest, void *source, size_t count)
517{
518 char *src = source;
519 long NumberOfBytes = count;
520
521 while (NumberOfBytes > 0) {
522 iSeries_Write_Byte(*src++, dest++);
523 -- NumberOfBytes;
524 }
525}
526EXPORT_SYMBOL(iSeries_memcpy_toio);
527
528void iSeries_memcpy_fromio(void *dest, const volatile void __iomem *src, size_t count)
529{
530 char *dst = dest;
531 long NumberOfBytes = count;
532
533 while (NumberOfBytes > 0) {
534 *dst++ = iSeries_Read_Byte(src++);
535 -- NumberOfBytes;
536 }
537}
538EXPORT_SYMBOL(iSeries_memcpy_fromio);
539
540/*
541 * Look down the chain to find the matching Device Device
542 */
543static struct iSeries_Device_Node *find_Device_Node(int bus, int devfn)
544{
545 struct list_head *pos;
546
547 list_for_each(pos, &iSeries_Global_Device_List) {
548 struct iSeries_Device_Node *node =
549 list_entry(pos, struct iSeries_Device_Node, Device_List);
550
551 if ((bus == ISERIES_BUS(node)) && (devfn == node->DevFn))
552 return node;
553 }
554 return NULL;
555}
556
557#if 0
558/*
559 * Returns the device node for the passed pci_dev
560 * Sanity Check Node PciDev to passed pci_dev
561 * If none is found, returns a NULL which the client must handle.
562 */
563static struct iSeries_Device_Node *get_Device_Node(struct pci_dev *pdev)
564{
565 struct iSeries_Device_Node *node;
566
567 node = pdev->sysdata;
568 if (node == NULL || node->PciDev != pdev)
569 node = find_Device_Node(pdev->bus->number, pdev->devfn);
570 return node;
571}
572#endif
573
574/*
575 * Config space read and write functions.
576 * For now at least, we look for the device node for the bus and devfn
577 * that we are asked to access. It may be possible to translate the devfn
578 * to a subbus and deviceid more directly.
579 */
580static u64 hv_cfg_read_func[4] = {
581 HvCallPciConfigLoad8, HvCallPciConfigLoad16,
582 HvCallPciConfigLoad32, HvCallPciConfigLoad32
583};
584
585static u64 hv_cfg_write_func[4] = {
586 HvCallPciConfigStore8, HvCallPciConfigStore16,
587 HvCallPciConfigStore32, HvCallPciConfigStore32
588};
589
590/*
591 * Read PCI config space
592 */
593static int iSeries_pci_read_config(struct pci_bus *bus, unsigned int devfn,
594 int offset, int size, u32 *val)
595{
596 struct iSeries_Device_Node *node = find_Device_Node(bus->number, devfn);
597 u64 fn;
598 struct HvCallPci_LoadReturn ret;
599
600 if (node == NULL)
601 return PCIBIOS_DEVICE_NOT_FOUND;
602 if (offset > 255) {
603 *val = ~0;
604 return PCIBIOS_BAD_REGISTER_NUMBER;
605 }
606
607 fn = hv_cfg_read_func[(size - 1) & 3];
608 HvCall3Ret16(fn, &ret, node->DsaAddr.DsaAddr, offset, 0);
609
610 if (ret.rc != 0) {
611 *val = ~0;
612 return PCIBIOS_DEVICE_NOT_FOUND; /* or something */
613 }
614
615 *val = ret.value;
616 return 0;
617}
618
619/*
620 * Write PCI config space
621 */
622
623static int iSeries_pci_write_config(struct pci_bus *bus, unsigned int devfn,
624 int offset, int size, u32 val)
625{
626 struct iSeries_Device_Node *node = find_Device_Node(bus->number, devfn);
627 u64 fn;
628 u64 ret;
629
630 if (node == NULL)
631 return PCIBIOS_DEVICE_NOT_FOUND;
632 if (offset > 255)
633 return PCIBIOS_BAD_REGISTER_NUMBER;
634
635 fn = hv_cfg_write_func[(size - 1) & 3];
636 ret = HvCall4(fn, node->DsaAddr.DsaAddr, offset, val, 0);
637
638 if (ret != 0)
639 return PCIBIOS_DEVICE_NOT_FOUND;
640
641 return 0;
642}
643
644static struct pci_ops iSeries_pci_ops = {
645 .read = iSeries_pci_read_config,
646 .write = iSeries_pci_write_config
647};
648
649/*
650 * Check Return Code
651 * -> On Failure, print and log information.
652 * Increment Retry Count, if exceeds max, panic partition.
653 *
654 * PCI: Device 23.90 ReadL I/O Error( 0): 0x1234
655 * PCI: Device 23.90 ReadL Retry( 1)
656 * PCI: Device 23.90 ReadL Retry Successful(1)
657 */
658static int CheckReturnCode(char *TextHdr, struct iSeries_Device_Node *DevNode,
659 int *retry, u64 ret)
660{
661 if (ret != 0) {
662 ++Pci_Error_Count;
663 (*retry)++;
664 printk("PCI: %s: Device 0x%04X:%02X I/O Error(%2d): 0x%04X\n",
665 TextHdr, DevNode->DsaAddr.Dsa.busNumber, DevNode->DevFn,
666 *retry, (int)ret);
667 /*
668 * Bump the retry and check for retry count exceeded.
669 * If, Exceeded, panic the system.
670 */
671 if (((*retry) > Pci_Retry_Max) &&
672 (Pci_Error_Flag > 0)) {
673 mf_display_src(0xB6000103);
674 panic_timeout = 0;
675 panic("PCI: Hardware I/O Error, SRC B6000103, "
676 "Automatic Reboot Disabled.\n");
677 }
678 return -1; /* Retry Try */
679 }
680 return 0;
681}
682
683/*
684 * Translate the I/O Address into a device node, bar, and bar offset.
685 * Note: Make sure the passed variable end up on the stack to avoid
686 * the exposure of being device global.
687 */
688static inline struct iSeries_Device_Node *xlate_iomm_address(
689 const volatile void __iomem *IoAddress,
690 u64 *dsaptr, u64 *BarOffsetPtr)
691{
692 unsigned long OrigIoAddr;
693 unsigned long BaseIoAddr;
694 unsigned long TableIndex;
695 struct iSeries_Device_Node *DevNode;
696
697 OrigIoAddr = (unsigned long __force)IoAddress;
698 if ((OrigIoAddr < BASE_IO_MEMORY) || (OrigIoAddr >= max_io_memory))
699 return NULL;
700 BaseIoAddr = OrigIoAddr - BASE_IO_MEMORY;
701 TableIndex = BaseIoAddr / IOMM_TABLE_ENTRY_SIZE;
702 DevNode = iomm_table[TableIndex];
703
704 if (DevNode != NULL) {
705 int barnum = iobar_table[TableIndex];
706 *dsaptr = DevNode->DsaAddr.DsaAddr | (barnum << 24);
707 *BarOffsetPtr = BaseIoAddr % IOMM_TABLE_ENTRY_SIZE;
708 } else
709 panic("PCI: Invalid PCI IoAddress detected!\n");
710 return DevNode;
711}
712
713/*
714 * Read MM I/O Instructions for the iSeries
715 * On MM I/O error, all ones are returned and iSeries_pci_IoError is cal
716 * else, data is returned in big Endian format.
717 *
718 * iSeries_Read_Byte = Read Byte ( 8 bit)
719 * iSeries_Read_Word = Read Word (16 bit)
720 * iSeries_Read_Long = Read Long (32 bit)
721 */
722u8 iSeries_Read_Byte(const volatile void __iomem *IoAddress)
723{
724 u64 BarOffset;
725 u64 dsa;
726 int retry = 0;
727 struct HvCallPci_LoadReturn ret;
728 struct iSeries_Device_Node *DevNode =
729 xlate_iomm_address(IoAddress, &dsa, &BarOffset);
730
731 if (DevNode == NULL) {
732 static unsigned long last_jiffies;
733 static int num_printed;
734
735 if ((jiffies - last_jiffies) > 60 * HZ) {
736 last_jiffies = jiffies;
737 num_printed = 0;
738 }
739 if (num_printed++ < 10)
740 printk(KERN_ERR "iSeries_Read_Byte: invalid access at IO address %p\n", IoAddress);
741 return 0xff;
742 }
743 do {
744 ++Pci_Io_Read_Count;
745 HvCall3Ret16(HvCallPciBarLoad8, &ret, dsa, BarOffset, 0);
746 } while (CheckReturnCode("RDB", DevNode, &retry, ret.rc) != 0);
747
748 return (u8)ret.value;
749}
750EXPORT_SYMBOL(iSeries_Read_Byte);
751
752u16 iSeries_Read_Word(const volatile void __iomem *IoAddress)
753{
754 u64 BarOffset;
755 u64 dsa;
756 int retry = 0;
757 struct HvCallPci_LoadReturn ret;
758 struct iSeries_Device_Node *DevNode =
759 xlate_iomm_address(IoAddress, &dsa, &BarOffset);
760
761 if (DevNode == NULL) {
762 static unsigned long last_jiffies;
763 static int num_printed;
764
765 if ((jiffies - last_jiffies) > 60 * HZ) {
766 last_jiffies = jiffies;
767 num_printed = 0;
768 }
769 if (num_printed++ < 10)
770 printk(KERN_ERR "iSeries_Read_Word: invalid access at IO address %p\n", IoAddress);
771 return 0xffff;
772 }
773 do {
774 ++Pci_Io_Read_Count;
775 HvCall3Ret16(HvCallPciBarLoad16, &ret, dsa,
776 BarOffset, 0);
777 } while (CheckReturnCode("RDW", DevNode, &retry, ret.rc) != 0);
778
779 return swab16((u16)ret.value);
780}
781EXPORT_SYMBOL(iSeries_Read_Word);
782
783u32 iSeries_Read_Long(const volatile void __iomem *IoAddress)
784{
785 u64 BarOffset;
786 u64 dsa;
787 int retry = 0;
788 struct HvCallPci_LoadReturn ret;
789 struct iSeries_Device_Node *DevNode =
790 xlate_iomm_address(IoAddress, &dsa, &BarOffset);
791
792 if (DevNode == NULL) {
793 static unsigned long last_jiffies;
794 static int num_printed;
795
796 if ((jiffies - last_jiffies) > 60 * HZ) {
797 last_jiffies = jiffies;
798 num_printed = 0;
799 }
800 if (num_printed++ < 10)
801 printk(KERN_ERR "iSeries_Read_Long: invalid access at IO address %p\n", IoAddress);
802 return 0xffffffff;
803 }
804 do {
805 ++Pci_Io_Read_Count;
806 HvCall3Ret16(HvCallPciBarLoad32, &ret, dsa,
807 BarOffset, 0);
808 } while (CheckReturnCode("RDL", DevNode, &retry, ret.rc) != 0);
809
810 return swab32((u32)ret.value);
811}
812EXPORT_SYMBOL(iSeries_Read_Long);
813
814/*
815 * Write MM I/O Instructions for the iSeries
816 *
817 * iSeries_Write_Byte = Write Byte (8 bit)
818 * iSeries_Write_Word = Write Word(16 bit)
819 * iSeries_Write_Long = Write Long(32 bit)
820 */
821void iSeries_Write_Byte(u8 data, volatile void __iomem *IoAddress)
822{
823 u64 BarOffset;
824 u64 dsa;
825 int retry = 0;
826 u64 rc;
827 struct iSeries_Device_Node *DevNode =
828 xlate_iomm_address(IoAddress, &dsa, &BarOffset);
829
830 if (DevNode == NULL) {
831 static unsigned long last_jiffies;
832 static int num_printed;
833
834 if ((jiffies - last_jiffies) > 60 * HZ) {
835 last_jiffies = jiffies;
836 num_printed = 0;
837 }
838 if (num_printed++ < 10)
839 printk(KERN_ERR "iSeries_Write_Byte: invalid access at IO address %p\n", IoAddress);
840 return;
841 }
842 do {
843 ++Pci_Io_Write_Count;
844 rc = HvCall4(HvCallPciBarStore8, dsa, BarOffset, data, 0);
845 } while (CheckReturnCode("WWB", DevNode, &retry, rc) != 0);
846}
847EXPORT_SYMBOL(iSeries_Write_Byte);
848
849void iSeries_Write_Word(u16 data, volatile void __iomem *IoAddress)
850{
851 u64 BarOffset;
852 u64 dsa;
853 int retry = 0;
854 u64 rc;
855 struct iSeries_Device_Node *DevNode =
856 xlate_iomm_address(IoAddress, &dsa, &BarOffset);
857
858 if (DevNode == NULL) {
859 static unsigned long last_jiffies;
860 static int num_printed;
861
862 if ((jiffies - last_jiffies) > 60 * HZ) {
863 last_jiffies = jiffies;
864 num_printed = 0;
865 }
866 if (num_printed++ < 10)
867 printk(KERN_ERR "iSeries_Write_Word: invalid access at IO address %p\n", IoAddress);
868 return;
869 }
870 do {
871 ++Pci_Io_Write_Count;
872 rc = HvCall4(HvCallPciBarStore16, dsa, BarOffset, swab16(data), 0);
873 } while (CheckReturnCode("WWW", DevNode, &retry, rc) != 0);
874}
875EXPORT_SYMBOL(iSeries_Write_Word);
876
877void iSeries_Write_Long(u32 data, volatile void __iomem *IoAddress)
878{
879 u64 BarOffset;
880 u64 dsa;
881 int retry = 0;
882 u64 rc;
883 struct iSeries_Device_Node *DevNode =
884 xlate_iomm_address(IoAddress, &dsa, &BarOffset);
885
886 if (DevNode == NULL) {
887 static unsigned long last_jiffies;
888 static int num_printed;
889
890 if ((jiffies - last_jiffies) > 60 * HZ) {
891 last_jiffies = jiffies;
892 num_printed = 0;
893 }
894 if (num_printed++ < 10)
895 printk(KERN_ERR "iSeries_Write_Long: invalid access at IO address %p\n", IoAddress);
896 return;
897 }
898 do {
899 ++Pci_Io_Write_Count;
900 rc = HvCall4(HvCallPciBarStore32, dsa, BarOffset, swab32(data), 0);
901 } while (CheckReturnCode("WWL", DevNode, &retry, rc) != 0);
902}
903EXPORT_SYMBOL(iSeries_Write_Long);
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-31 00:59:35 -0500