8 files changed, 212 insertions, 54 deletions

diff --git a/arch/powerpc/platforms/embedded6xx/Kconfig b/arch/powerpc/platforms/embedded6xx/Kconfig
index 2d12f77e46bc..8924095a7928 100644
--- a/arch/powerpc/platforms/embedded6xx/Kconfig
+++ b/arch/powerpc/platforms/embedded6xx/Kconfig
@@ -1,9 +1,10 @@
-choice
-        prompt "Machine Type"
-        depends on EMBEDDED6xx
+config EMBEDDED6xx
+        bool "Embedded 6xx/7xx/7xxx-based boards"
+        depends on PPC32 && BROKEN_ON_SMP && PPC_MULTIPLATFORM
 
 config LINKSTATION
         bool "Linkstation / Kurobox(HG) from Buffalo"
+        depends on EMBEDDED6xx
         select MPIC
         select FSL_SOC
         select PPC_UDBG_16550 if SERIAL_8250
@@ -17,15 +18,18 @@ config LINKSTATION
 
 config MPC7448HPC2
         bool "Freescale MPC7448HPC2(Taiga)"
+        depends on EMBEDDED6xx
         select TSI108_BRIDGE
         select DEFAULT_UIMAGE
         select PPC_UDBG_16550
+        select WANT_DEVICE_TREE
         help
           Select MPC7448HPC2 if configuring for Freescale MPC7448HPC2 (Taiga)
           platform
 
 config PPC_HOLLY
         bool "PPC750GX/CL with TSI10x bridge (Hickory/Holly)"
+        depends on EMBEDDED6xx
         select TSI108_BRIDGE
         select PPC_UDBG_16550
         select WANT_DEVICE_TREE
@@ -35,12 +39,12 @@ config PPC_HOLLY
 
 config PPC_PRPMC2800
         bool "Motorola-PrPMC2800"
+        depends on EMBEDDED6xx
         select MV64X60
         select NOT_COHERENT_CACHE
         select WANT_DEVICE_TREE
         help
           This option enables support for the Motorola PrPMC2800 board
-endchoice
 
 config TSI108_BRIDGE
         bool
diff --git a/arch/powerpc/platforms/embedded6xx/holly.c b/arch/powerpc/platforms/embedded6xx/holly.c
index 6292e36dc577..b6de2b5223dd 100644
--- a/arch/powerpc/platforms/embedded6xx/holly.c
+++ b/arch/powerpc/platforms/embedded6xx/holly.c
@@ -113,23 +113,11 @@ static void holly_remap_bridge(void)
 
 static void __init holly_setup_arch(void)
 {
-        struct device_node *cpu;
         struct device_node *np;
 
         if (ppc_md.progress)
                 ppc_md.progress("holly_setup_arch():set_bridge", 0);
 
-        cpu = of_find_node_by_type(NULL, "cpu");
-        if (cpu) {
-                const unsigned int *fp;
-
-                fp = of_get_property(cpu, "clock-frequency", NULL);
-                if (fp)
-                        loops_per_jiffy = *fp / HZ;
-                else
-                        loops_per_jiffy = 50000000 / HZ;
-                of_node_put(cpu);
-        }
         tsi108_csr_vir_base = get_vir_csrbase();
 
         /* setup PCI host bridge */
@@ -147,7 +135,7 @@ static void __init holly_setup_arch(void)
 }
 
 /*
- * Interrupt setup and service.  Interrrupts on the holly come
+ * Interrupt setup and service.  Interrupts on the holly come
  * from the four external INT pins, PCI interrupts are routed via
  * PCI interrupt control registers, it generates internal IRQ23
  *
diff --git a/arch/powerpc/platforms/embedded6xx/linkstation.c b/arch/powerpc/platforms/embedded6xx/linkstation.c
index bd5ca58345a1..eb5d74e26fe9 100644
--- a/arch/powerpc/platforms/embedded6xx/linkstation.c
+++ b/arch/powerpc/platforms/embedded6xx/linkstation.c
@@ -11,16 +11,16 @@
  */
 
 #include <linux/kernel.h>
-#include <linux/pci.h>
 #include <linux/initrd.h>
 #include <linux/mtd/physmap.h>
 
 #include <asm/time.h>
 #include <asm/prom.h>
 #include <asm/mpic.h>
-#include <asm/mpc10x.h>
 #include <asm/pci-bridge.h>
 
+#include "mpc10x.h"
+
 static struct mtd_partition linkstation_physmap_partitions[] = {
         {
                 .name   = "mtd_firmimg",
@@ -91,7 +91,7 @@ static void __init linkstation_setup_arch(void)
 #endif
 
         /* Lookup PCI host bridges */
-        for (np = NULL; (np = of_find_node_by_type(np, "pci")) != NULL;)
+        for_each_compatible_node(np, "pci", "mpc10x-pci")
                 linkstation_add_bridge(np);
 
         printk(KERN_INFO "BUFFALO Network Attached Storage Series\n");
@@ -99,7 +99,7 @@ static void __init linkstation_setup_arch(void)
 }
 
 /*
- * Interrupt setup and service.  Interrrupts on the linkstation come
+ * Interrupt setup and service.  Interrupts on the linkstation come
  * from the four PCI slots plus onboard 8241 devices: I2C, DUART.
  */
 static void __init linkstation_init_IRQ(void)
diff --git a/arch/powerpc/platforms/embedded6xx/ls_uart.c b/arch/powerpc/platforms/embedded6xx/ls_uart.c
index d0bee9f19e4e..c99264cedda5 100644
--- a/arch/powerpc/platforms/embedded6xx/ls_uart.c
+++ b/arch/powerpc/platforms/embedded6xx/ls_uart.c
@@ -1,14 +1,25 @@
+/*
+ * AVR power-management chip interface for the Buffalo Linkstation /
+ * Kurobox Platform.
+ *
+ * Author: 2006 (c) G. Liakhovetski
+ *       g.liakhovetski@gmx.de
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2.  This program is licensed "as is" without any warranty of
+ * any kind, whether express or implied.
+ */
 #include <linux/workqueue.h>
 #include <linux/string.h>
 #include <linux/delay.h>
 #include <linux/serial_reg.h>
 #include <linux/serial_8250.h>
 #include <asm/io.h>
-#include <asm/mpc10x.h>
-#include <asm/ppc_sys.h>
 #include <asm/prom.h>
 #include <asm/termbits.h>
 
+#include "mpc10x.h"
+
 static void __iomem *avr_addr;
 static unsigned long avr_clock;
 
@@ -106,6 +117,9 @@ static int __init ls_uarts_init(void)
         phys_addr_t phys_addr;
         int len;
 
+        if (!machine_is(linkstation))
+                return 0;
+
         avr = of_find_node_by_path("/soc10x/serial@80004500");
         if (!avr)
                 return -EINVAL;
diff --git a/arch/powerpc/platforms/embedded6xx/mpc10x.h b/arch/powerpc/platforms/embedded6xx/mpc10x.h
new file mode 100644
index 000000000000..b30a6a3b5bd2
--- /dev/null
+++ b/arch/powerpc/platforms/embedded6xx/mpc10x.h
@@ -0,0 +1,180 @@
+/*
+ * Common routines for the Motorola SPS MPC106/8240/107 Host bridge/Mem
+ * ctlr/EPIC/etc.
+ *
+ * Author: Mark A. Greer
+ *         mgreer@mvista.com
+ *
+ * 2001 (c) MontaVista, Software, Inc.  This file is licensed under
+ * the terms of the GNU General Public License version 2.  This program
+ * is licensed "as is" without any warranty of any kind, whether express
+ * or implied.
+ */
+#ifndef __PPC_KERNEL_MPC10X_H
+#define __PPC_KERNEL_MPC10X_H
+
+#include <linux/pci_ids.h>
+#include <asm/pci-bridge.h>
+
+/*
+ * The values here don't completely map everything but should work in most
+ * cases.
+ *
+ * MAP A (PReP Map)
+ *   Processor: 0x80000000 - 0x807fffff -> PCI I/O: 0x00000000 - 0x007fffff
+ *   Processor: 0xc0000000 - 0xdfffffff -> PCI MEM: 0x00000000 - 0x1fffffff
+ *   PCI MEM:   0x80000000 -> Processor System Memory: 0x00000000
+ *   EUMB mapped to: ioremap_base - 0x00100000 (ioremap_base - 1 MB)
+ *
+ * MAP B (CHRP Map)
+ *   Processor: 0xfe000000 - 0xfebfffff -> PCI I/O: 0x00000000 - 0x00bfffff
+ *   Processor: 0x80000000 - 0xbfffffff -> PCI MEM: 0x80000000 - 0xbfffffff
+ *   PCI MEM:   0x00000000 -> Processor System Memory: 0x00000000
+ *   EUMB mapped to: ioremap_base - 0x00100000 (ioremap_base - 1 MB)
+ */
+
+/*
+ * Define the vendor/device IDs for the various bridges--should be added to
+ * <linux/pci_ids.h>
+ */
+#define MPC10X_BRIDGE_106       ((PCI_DEVICE_ID_MOTOROLA_MPC106 << 16) |  \
+                                  PCI_VENDOR_ID_MOTOROLA)
+#define MPC10X_BRIDGE_8240      ((0x0003 << 16) | PCI_VENDOR_ID_MOTOROLA)
+#define MPC10X_BRIDGE_107       ((0x0004 << 16) | PCI_VENDOR_ID_MOTOROLA)
+#define MPC10X_BRIDGE_8245      ((0x0006 << 16) | PCI_VENDOR_ID_MOTOROLA)
+
+/* Define the type of map to use */
+#define MPC10X_MEM_MAP_A                1
+#define MPC10X_MEM_MAP_B                2
+
+/* Map A (PReP Map) Defines */
+#define MPC10X_MAPA_CNFG_ADDR           0x80000cf8
+#define MPC10X_MAPA_CNFG_DATA           0x80000cfc
+
+#define MPC10X_MAPA_ISA_IO_BASE         0x80000000
+#define MPC10X_MAPA_ISA_MEM_BASE        0xc0000000
+#define MPC10X_MAPA_DRAM_OFFSET         0x80000000
+
+#define MPC10X_MAPA_PCI_INTACK_ADDR     0xbffffff0
+#define MPC10X_MAPA_PCI_IO_START        0x00000000
+#define MPC10X_MAPA_PCI_IO_END         (0x00800000 - 1)
+#define MPC10X_MAPA_PCI_MEM_START       0x00000000
+#define MPC10X_MAPA_PCI_MEM_END        (0x20000000 - 1)
+
+#define MPC10X_MAPA_PCI_MEM_OFFSET      (MPC10X_MAPA_ISA_MEM_BASE -     \
+                                         MPC10X_MAPA_PCI_MEM_START)
+
+/* Map B (CHRP Map) Defines */
+#define MPC10X_MAPB_CNFG_ADDR           0xfec00000
+#define MPC10X_MAPB_CNFG_DATA           0xfee00000
+
+#define MPC10X_MAPB_ISA_IO_BASE         0xfe000000
+#define MPC10X_MAPB_ISA_MEM_BASE        0x80000000
+#define MPC10X_MAPB_DRAM_OFFSET         0x00000000
+
+#define MPC10X_MAPB_PCI_INTACK_ADDR     0xfef00000
+#define MPC10X_MAPB_PCI_IO_START        0x00000000
+#define MPC10X_MAPB_PCI_IO_END         (0x00c00000 - 1)
+#define MPC10X_MAPB_PCI_MEM_START       0x80000000
+#define MPC10X_MAPB_PCI_MEM_END        (0xc0000000 - 1)
+
+#define MPC10X_MAPB_PCI_MEM_OFFSET      (MPC10X_MAPB_ISA_MEM_BASE -     \
+                                         MPC10X_MAPB_PCI_MEM_START)
+
+/* Set hose members to values appropriate for the mem map used */
+#define MPC10X_SETUP_HOSE(hose, map) {                                  \
+        (hose)->pci_mem_offset = MPC10X_MAP##map##_PCI_MEM_OFFSET;      \
+        (hose)->io_space.start = MPC10X_MAP##map##_PCI_IO_START;        \
+        (hose)->io_space.end = MPC10X_MAP##map##_PCI_IO_END;            \
+        (hose)->mem_space.start = MPC10X_MAP##map##_PCI_MEM_START;      \
+        (hose)->mem_space.end = MPC10X_MAP##map##_PCI_MEM_END;          \
+        (hose)->io_base_virt = (void *)MPC10X_MAP##map##_ISA_IO_BASE;   \
+}
+
+
+/* Miscellaneous Configuration register offsets */
+#define MPC10X_CFG_PIR_REG              0x09
+#define MPC10X_CFG_PIR_HOST_BRIDGE      0x00
+#define MPC10X_CFG_PIR_AGENT            0x01
+
+#define MPC10X_CFG_EUMBBAR              0x78
+
+#define MPC10X_CFG_PICR1_REG            0xa8
+#define MPC10X_CFG_PICR1_ADDR_MAP_MASK  0x00010000
+#define MPC10X_CFG_PICR1_ADDR_MAP_A     0x00010000
+#define MPC10X_CFG_PICR1_ADDR_MAP_B     0x00000000
+#define MPC10X_CFG_PICR1_SPEC_PCI_RD    0x00000004
+#define MPC10X_CFG_PICR1_ST_GATH_EN     0x00000040
+
+#define MPC10X_CFG_PICR2_REG            0xac
+#define MPC10X_CFG_PICR2_COPYBACK_OPT   0x00000001
+
+#define MPC10X_CFG_MAPB_OPTIONS_REG     0xe0
+#define MPC10X_CFG_MAPB_OPTIONS_CFAE    0x80    /* CPU_FD_ALIAS_EN */
+#define MPC10X_CFG_MAPB_OPTIONS_PFAE    0x40    /* PCI_FD_ALIAS_EN */
+#define MPC10X_CFG_MAPB_OPTIONS_DR      0x20    /* DLL_RESET */
+#define MPC10X_CFG_MAPB_OPTIONS_PCICH   0x08    /* PCI_COMPATIBILITY_HOLE */
+#define MPC10X_CFG_MAPB_OPTIONS_PROCCH  0x04    /* PROC_COMPATIBILITY_HOLE */
+
+/* Define offsets for the memory controller registers in the config space */
+#define MPC10X_MCTLR_MEM_START_1        0x80    /* Banks 0-3 */
+#define MPC10X_MCTLR_MEM_START_2        0x84    /* Banks 4-7 */
+#define MPC10X_MCTLR_EXT_MEM_START_1    0x88    /* Banks 0-3 */
+#define MPC10X_MCTLR_EXT_MEM_START_2    0x8c    /* Banks 4-7 */
+
+#define MPC10X_MCTLR_MEM_END_1          0x90    /* Banks 0-3 */
+#define MPC10X_MCTLR_MEM_END_2          0x94    /* Banks 4-7 */
+#define MPC10X_MCTLR_EXT_MEM_END_1      0x98    /* Banks 0-3 */
+#define MPC10X_MCTLR_EXT_MEM_END_2      0x9c    /* Banks 4-7 */
+
+#define MPC10X_MCTLR_MEM_BANK_ENABLES   0xa0
+
+/* Define some offset in the EUMB */
+#define MPC10X_EUMB_SIZE                0x00100000 /* Total EUMB size (1MB) */
+
+#define MPC10X_EUMB_MU_OFFSET           0x00000000 /* Msg Unit reg offset */
+#define MPC10X_EUMB_MU_SIZE             0x00001000 /* Msg Unit reg size */
+#define MPC10X_EUMB_DMA_OFFSET          0x00001000 /* DMA Unit reg offset */
+#define MPC10X_EUMB_DMA_SIZE            0x00001000 /* DMA Unit reg size  */
+#define MPC10X_EUMB_ATU_OFFSET          0x00002000 /* Addr xlate reg offset */
+#define MPC10X_EUMB_ATU_SIZE            0x00001000 /* Addr xlate reg size  */
+#define MPC10X_EUMB_I2C_OFFSET          0x00003000 /* I2C Unit reg offset */
+#define MPC10X_EUMB_I2C_SIZE            0x00001000 /* I2C Unit reg size  */
+#define MPC10X_EUMB_DUART_OFFSET        0x00004000 /* DUART Unit reg offset (8245) */
+#define MPC10X_EUMB_DUART_SIZE          0x00001000 /* DUART Unit reg size (8245) */
+#define MPC10X_EUMB_EPIC_OFFSET         0x00040000 /* EPIC offset in EUMB */
+#define MPC10X_EUMB_EPIC_SIZE           0x00030000 /* EPIC size */
+#define MPC10X_EUMB_PM_OFFSET           0x000fe000 /* Performance Monitor reg offset (8245) */
+#define MPC10X_EUMB_PM_SIZE             0x00001000 /* Performance Monitor reg size (8245) */
+#define MPC10X_EUMB_WP_OFFSET           0x000ff000 /* Data path diagnostic, watchpoint reg offset */
+#define MPC10X_EUMB_WP_SIZE             0x00001000 /* Data path diagnostic, watchpoint reg size */
+
+/*
+ * Define some recommended places to put the EUMB regs.
+ * For both maps, recommend putting the EUMB from 0xeff00000 to 0xefffffff.
+ */
+extern unsigned long                    ioremap_base;
+#define MPC10X_MAPA_EUMB_BASE           (ioremap_base - MPC10X_EUMB_SIZE)
+#define MPC10X_MAPB_EUMB_BASE           MPC10X_MAPA_EUMB_BASE
+
+enum ppc_sys_devices {
+        MPC10X_IIC1,
+        MPC10X_DMA0,
+        MPC10X_DMA1,
+        MPC10X_UART0,
+        MPC10X_UART1,
+        NUM_PPC_SYS_DEVS,
+};
+
+int mpc10x_bridge_init(struct pci_controller *hose,
+                       uint current_map,
+                       uint new_map,
+                       uint phys_eumb_base);
+unsigned long mpc10x_get_mem_size(uint mem_map);
+int mpc10x_enable_store_gathering(struct pci_controller *hose);
+int mpc10x_disable_store_gathering(struct pci_controller *hose);
+
+/* For MPC107 boards that use the built-in openpic */
+void mpc10x_set_openpic(void);
+
+#endif  /* __PPC_KERNEL_MPC10X_H */
diff --git a/arch/powerpc/platforms/embedded6xx/mpc7448_hpc2.c b/arch/powerpc/platforms/embedded6xx/mpc7448_hpc2.c
index 1e3cc69487b5..a2c04b9d42b1 100644
--- a/arch/powerpc/platforms/embedded6xx/mpc7448_hpc2.c
+++ b/arch/powerpc/platforms/embedded6xx/mpc7448_hpc2.c
@@ -40,7 +40,6 @@
 #include <asm/pci-bridge.h>
 #include <asm/reg.h>
 #include <mm/mmu_decl.h>
-#include "mpc7448_hpc2.h"
 #include <asm/tsi108_pci.h>
 #include <asm/tsi108_irq.h>
 #include <asm/mpic.h>
@@ -75,7 +74,7 @@ static void __init mpc7448_hpc2_setup_arch(void)
 
         /* setup PCI host bridge */
 #ifdef CONFIG_PCI
-        for (np = NULL; (np = of_find_node_by_type(np, "pci")) != NULL;)
+        for_each_compatible_node(np, "pci", "tsi108-pci")
                 tsi108_setup_pci(np, MPC7448HPC2_PCI_CFG_PHYS, 0);
 
         ppc_md.pci_exclude_device = mpc7448_hpc2_exclude_device;
@@ -91,7 +90,7 @@ static void __init mpc7448_hpc2_setup_arch(void)
 }
 
 /*
- * Interrupt setup and service.  Interrrupts on the mpc7448_hpc2 come
+ * Interrupt setup and service.  Interrupts on the mpc7448_hpc2 come
  * from the four external INT pins, PCI interrupts are routed via
  * PCI interrupt control registers, it generates internal IRQ23
  *
diff --git a/arch/powerpc/platforms/embedded6xx/mpc7448_hpc2.h b/arch/powerpc/platforms/embedded6xx/mpc7448_hpc2.h
deleted file mode 100644
index f7e0e0c7f8d8..000000000000
--- a/arch/powerpc/platforms/embedded6xx/mpc7448_hpc2.h
+++ /dev/null
@@ -1,21 +0,0 @@
-/*
- * mpc7448_hpc2.h
- *
- * Definitions for Freescale MPC7448_HPC2 platform
- *
- * Author: Jacob Pan
- *         jacob.pan@freescale.com
- * Maintainer: Roy Zang <roy.zang@freescale.com>
- *
- * 2006 (c) Freescale Semiconductor, Inc.  This file is licensed under
- * the terms of the GNU General Public License version 2.  This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-
-#ifndef __PPC_PLATFORMS_MPC7448_HPC2_H
-#define __PPC_PLATFORMS_MPC7448_HPC2_H
-
-#include <asm/ppcboot.h>
-
-#endif                          /* __PPC_PLATFORMS_MPC7448_HPC2_H */
diff --git a/arch/powerpc/platforms/embedded6xx/prpmc2800.c b/arch/powerpc/platforms/embedded6xx/prpmc2800.c
index 53420951dc53..e484cac75095 100644
--- a/arch/powerpc/platforms/embedded6xx/prpmc2800.c
+++ b/arch/powerpc/platforms/embedded6xx/prpmc2800.c
@@ -44,7 +44,6 @@ static void __init prpmc2800_setup_arch(void)
         struct device_node *np;
         phys_addr_t paddr;
         const unsigned int *reg;
-        const unsigned int *prop;
 
         /*
          * ioremap mpp and gpp registers in case they are later
@@ -62,12 +61,6 @@ static void __init prpmc2800_setup_arch(void)
         of_node_put(np);
         mv64x60_gpp_reg_base = ioremap(paddr, reg[1]);
 
-        np = of_find_node_by_type(NULL, "cpu");
-        prop = of_get_property(np, "clock-frequency", NULL);
-        if (prop)
-                loops_per_jiffy = *prop / HZ;
-        of_node_put(np);
-
 #ifdef CONFIG_PCI
         mv64x60_pci_init();
 #endif
@@ -158,6 +151,7 @@ define_machine(prpmc2800){
         .name                   = prpmc2800_platform_name,
         .probe                  = prpmc2800_probe,
         .setup_arch             = prpmc2800_setup_arch,
+        .init_early             = mv64x60_init_early,
         .show_cpuinfo           = prpmc2800_show_cpuinfo,
         .init_IRQ               = mv64x60_init_irq,
         .get_irq                = mv64x60_get_irq,