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-rw-r--r--arch/powerpc/platforms/8xx/Kconfig28
-rw-r--r--arch/powerpc/platforms/8xx/Makefile1
-rw-r--r--arch/powerpc/platforms/8xx/ep88xc.c176
-rw-r--r--arch/powerpc/platforms/8xx/m8xx_setup.c154
-rw-r--r--arch/powerpc/platforms/8xx/mpc86xads.h4
-rw-r--r--arch/powerpc/platforms/8xx/mpc86xads_setup.c25
-rw-r--r--arch/powerpc/platforms/8xx/mpc885ads.h42
-rw-r--r--arch/powerpc/platforms/8xx/mpc885ads_setup.c472
8 files changed, 412 insertions, 490 deletions
diff --git a/arch/powerpc/platforms/8xx/Kconfig b/arch/powerpc/platforms/8xx/Kconfig
index 39bb8c5ebe70..bd28655043a0 100644
--- a/arch/powerpc/platforms/8xx/Kconfig
+++ b/arch/powerpc/platforms/8xx/Kconfig
@@ -3,6 +3,7 @@ config FADS
3 3
4config CPM1 4config CPM1
5 bool 5 bool
6 select CPM
6 7
7choice 8choice
8 prompt "8xx Machine Type" 9 prompt "8xx Machine Type"
@@ -25,12 +26,23 @@ config MPC86XADS
25config MPC885ADS 26config MPC885ADS
26 bool "MPC885ADS" 27 bool "MPC885ADS"
27 select CPM1 28 select CPM1
29 select PPC_CPM_NEW_BINDING
28 help 30 help
29 Freescale Semiconductor MPC885 Application Development System (ADS). 31 Freescale Semiconductor MPC885 Application Development System (ADS).
30 Also known as DUET. 32 Also known as DUET.
31 The MPC885ADS is meant to serve as a platform for s/w and h/w 33 The MPC885ADS is meant to serve as a platform for s/w and h/w
32 development around the MPC885 processor family. 34 development around the MPC885 processor family.
33 35
36config PPC_EP88XC
37 bool "Embedded Planet EP88xC (a.k.a. CWH-PPC-885XN-VE)"
38 select CPM1
39 select PPC_CPM_NEW_BINDING
40 help
41 This enables support for the Embedded Planet EP88xC board.
42
43 This board is also resold by Freescale as the QUICCStart
44 MPC885 Evaluation System and/or the CWH-PPC-885XN-VE.
45
34endchoice 46endchoice
35 47
36menu "Freescale Ethernet driver platform-specific options" 48menu "Freescale Ethernet driver platform-specific options"
@@ -99,6 +111,22 @@ config 8xx_CPU6
99 111
100 If in doubt, say N here. 112 If in doubt, say N here.
101 113
114config 8xx_CPU15
115 bool "CPU15 Silicon Errata"
116 default y
117 help
118 This enables a workaround for erratum CPU15 on MPC8xx chips.
119 This bug can cause incorrect code execution under certain
120 circumstances. This workaround adds some overhead (a TLB miss
121 every time execution crosses a page boundary), and you may wish
122 to disable it if you have worked around the bug in the compiler
123 (by not placing conditional branches or branches to LR or CTR
124 in the last word of a page, with a target of the last cache
125 line in the next page), or if you have used some other
126 workaround.
127
128 If in doubt, say Y here.
129
102choice 130choice
103 prompt "Microcode patch selection" 131 prompt "Microcode patch selection"
104 default NO_UCODE_PATCH 132 default NO_UCODE_PATCH
diff --git a/arch/powerpc/platforms/8xx/Makefile b/arch/powerpc/platforms/8xx/Makefile
index 5e2dae3afd2f..8b7098018b59 100644
--- a/arch/powerpc/platforms/8xx/Makefile
+++ b/arch/powerpc/platforms/8xx/Makefile
@@ -4,3 +4,4 @@
4obj-$(CONFIG_PPC_8xx) += m8xx_setup.o 4obj-$(CONFIG_PPC_8xx) += m8xx_setup.o
5obj-$(CONFIG_MPC885ADS) += mpc885ads_setup.o 5obj-$(CONFIG_MPC885ADS) += mpc885ads_setup.o
6obj-$(CONFIG_MPC86XADS) += mpc86xads_setup.o 6obj-$(CONFIG_MPC86XADS) += mpc86xads_setup.o
7obj-$(CONFIG_PPC_EP88XC) += ep88xc.o
diff --git a/arch/powerpc/platforms/8xx/ep88xc.c b/arch/powerpc/platforms/8xx/ep88xc.c
new file mode 100644
index 000000000000..c518b6cc5fab
--- /dev/null
+++ b/arch/powerpc/platforms/8xx/ep88xc.c
@@ -0,0 +1,176 @@
1/*
2 * Platform setup for the Embedded Planet EP88xC board
3 *
4 * Author: Scott Wood <scottwood@freescale.com>
5 * Copyright 2007 Freescale Semiconductor, Inc.
6 *
7 * This file is licensed under the terms of the GNU General Public License
8 * version 2. This program is licensed "as is" without any warranty of any
9 * kind, whether express or implied.
10 */
11
12#include <linux/init.h>
13#include <linux/of_platform.h>
14
15#include <asm/machdep.h>
16#include <asm/io.h>
17#include <asm/udbg.h>
18#include <asm/commproc.h>
19
20#include <sysdev/commproc.h>
21
22struct cpm_pin {
23 int port, pin, flags;
24};
25
26static struct cpm_pin ep88xc_pins[] = {
27 /* SMC1 */
28 {1, 24, CPM_PIN_INPUT}, /* RX */
29 {1, 25, CPM_PIN_INPUT | CPM_PIN_SECONDARY}, /* TX */
30
31 /* SCC2 */
32 {0, 12, CPM_PIN_INPUT}, /* TX */
33 {0, 13, CPM_PIN_INPUT}, /* RX */
34 {2, 8, CPM_PIN_INPUT | CPM_PIN_SECONDARY | CPM_PIN_GPIO}, /* CD */
35 {2, 9, CPM_PIN_INPUT | CPM_PIN_SECONDARY | CPM_PIN_GPIO}, /* CTS */
36 {2, 14, CPM_PIN_INPUT}, /* RTS */
37
38 /* MII1 */
39 {0, 0, CPM_PIN_INPUT},
40 {0, 1, CPM_PIN_INPUT},
41 {0, 2, CPM_PIN_INPUT},
42 {0, 3, CPM_PIN_INPUT},
43 {0, 4, CPM_PIN_OUTPUT},
44 {0, 10, CPM_PIN_OUTPUT},
45 {0, 11, CPM_PIN_OUTPUT},
46 {1, 19, CPM_PIN_INPUT},
47 {1, 31, CPM_PIN_INPUT},
48 {2, 12, CPM_PIN_INPUT},
49 {2, 13, CPM_PIN_INPUT},
50 {3, 8, CPM_PIN_INPUT},
51 {4, 30, CPM_PIN_OUTPUT},
52 {4, 31, CPM_PIN_OUTPUT},
53
54 /* MII2 */
55 {4, 14, CPM_PIN_OUTPUT | CPM_PIN_SECONDARY},
56 {4, 15, CPM_PIN_OUTPUT | CPM_PIN_SECONDARY},
57 {4, 16, CPM_PIN_OUTPUT},
58 {4, 17, CPM_PIN_OUTPUT | CPM_PIN_SECONDARY},
59 {4, 18, CPM_PIN_OUTPUT | CPM_PIN_SECONDARY},
60 {4, 19, CPM_PIN_OUTPUT | CPM_PIN_SECONDARY},
61 {4, 20, CPM_PIN_OUTPUT | CPM_PIN_SECONDARY},
62 {4, 21, CPM_PIN_OUTPUT},
63 {4, 22, CPM_PIN_OUTPUT},
64 {4, 23, CPM_PIN_OUTPUT},
65 {4, 24, CPM_PIN_OUTPUT},
66 {4, 25, CPM_PIN_OUTPUT},
67 {4, 26, CPM_PIN_OUTPUT},
68 {4, 27, CPM_PIN_OUTPUT},
69 {4, 28, CPM_PIN_OUTPUT},
70 {4, 29, CPM_PIN_OUTPUT},
71
72 /* USB */
73 {0, 6, CPM_PIN_INPUT}, /* CLK2 */
74 {0, 14, CPM_PIN_INPUT}, /* USBOE */
75 {0, 15, CPM_PIN_INPUT}, /* USBRXD */
76 {2, 6, CPM_PIN_OUTPUT}, /* USBTXN */
77 {2, 7, CPM_PIN_OUTPUT}, /* USBTXP */
78 {2, 10, CPM_PIN_INPUT}, /* USBRXN */
79 {2, 11, CPM_PIN_INPUT}, /* USBRXP */
80
81 /* Misc */
82 {1, 26, CPM_PIN_INPUT}, /* BRGO2 */
83 {1, 27, CPM_PIN_INPUT}, /* BRGO1 */
84};
85
86static void __init init_ioports(void)
87{
88 int i;
89
90 for (i = 0; i < ARRAY_SIZE(ep88xc_pins); i++) {
91 struct cpm_pin *pin = &ep88xc_pins[i];
92 cpm1_set_pin(pin->port, pin->pin, pin->flags);
93 }
94
95 cpm1_clk_setup(CPM_CLK_SMC1, CPM_BRG1, CPM_CLK_RTX);
96 cpm1_clk_setup(CPM_CLK_SCC1, CPM_CLK2, CPM_CLK_TX); /* USB */
97 cpm1_clk_setup(CPM_CLK_SCC1, CPM_CLK2, CPM_CLK_RX);
98 cpm1_clk_setup(CPM_CLK_SCC2, CPM_BRG2, CPM_CLK_TX);
99 cpm1_clk_setup(CPM_CLK_SCC2, CPM_BRG2, CPM_CLK_RX);
100}
101
102static u8 __iomem *ep88xc_bcsr;
103
104#define BCSR7_SCC2_ENABLE 0x10
105
106#define BCSR8_PHY1_ENABLE 0x80
107#define BCSR8_PHY1_POWER 0x40
108#define BCSR8_PHY2_ENABLE 0x20
109#define BCSR8_PHY2_POWER 0x10
110
111#define BCSR9_USB_ENABLE 0x80
112#define BCSR9_USB_POWER 0x40
113#define BCSR9_USB_HOST 0x20
114#define BCSR9_USB_FULL_SPEED_TARGET 0x10
115
116static void __init ep88xc_setup_arch(void)
117{
118 struct device_node *np;
119
120 cpm_reset();
121 init_ioports();
122
123 np = of_find_compatible_node(NULL, NULL, "fsl,ep88xc-bcsr");
124 if (!np) {
125 printk(KERN_CRIT "Could not find fsl,ep88xc-bcsr node\n");
126 return;
127 }
128
129 ep88xc_bcsr = of_iomap(np, 0);
130 of_node_put(np);
131
132 if (!ep88xc_bcsr) {
133 printk(KERN_CRIT "Could not remap BCSR\n");
134 return;
135 }
136
137 setbits8(&ep88xc_bcsr[7], BCSR7_SCC2_ENABLE);
138 setbits8(&ep88xc_bcsr[8], BCSR8_PHY1_ENABLE | BCSR8_PHY1_POWER |
139 BCSR8_PHY2_ENABLE | BCSR8_PHY2_POWER);
140}
141
142static int __init ep88xc_probe(void)
143{
144 unsigned long root = of_get_flat_dt_root();
145 return of_flat_dt_is_compatible(root, "fsl,ep88xc");
146}
147
148static struct of_device_id __initdata of_bus_ids[] = {
149 { .name = "soc", },
150 { .name = "cpm", },
151 { .name = "localbus", },
152 {},
153};
154
155static int __init declare_of_platform_devices(void)
156{
157 /* Publish the QE devices */
158 if (machine_is(ep88xc))
159 of_platform_bus_probe(NULL, of_bus_ids, NULL);
160
161 return 0;
162}
163device_initcall(declare_of_platform_devices);
164
165define_machine(ep88xc) {
166 .name = "Embedded Planet EP88xC",
167 .probe = ep88xc_probe,
168 .setup_arch = ep88xc_setup_arch,
169 .init_IRQ = m8xx_pic_init,
170 .get_irq = mpc8xx_get_irq,
171 .restart = mpc8xx_restart,
172 .calibrate_decr = mpc8xx_calibrate_decr,
173 .set_rtc_time = mpc8xx_set_rtc_time,
174 .get_rtc_time = mpc8xx_get_rtc_time,
175 .progress = udbg_progress,
176};
diff --git a/arch/powerpc/platforms/8xx/m8xx_setup.c b/arch/powerpc/platforms/8xx/m8xx_setup.c
index f1693550c70c..d35eda80e9e6 100644
--- a/arch/powerpc/platforms/8xx/m8xx_setup.c
+++ b/arch/powerpc/platforms/8xx/m8xx_setup.c
@@ -10,57 +10,33 @@
10 * bootup setup stuff.. 10 * bootup setup stuff..
11 */ 11 */
12 12
13#include <linux/errno.h>
14#include <linux/sched.h>
15#include <linux/kernel.h> 13#include <linux/kernel.h>
16#include <linux/mm.h>
17#include <linux/stddef.h>
18#include <linux/unistd.h>
19#include <linux/ptrace.h>
20#include <linux/slab.h> 14#include <linux/slab.h>
21#include <linux/user.h>
22#include <linux/a.out.h>
23#include <linux/tty.h>
24#include <linux/major.h>
25#include <linux/interrupt.h> 15#include <linux/interrupt.h>
26#include <linux/reboot.h>
27#include <linux/init.h> 16#include <linux/init.h>
28#include <linux/initrd.h>
29#include <linux/ioport.h>
30#include <linux/bootmem.h>
31#include <linux/seq_file.h>
32#include <linux/root_dev.h>
33#include <linux/time.h> 17#include <linux/time.h>
34#include <linux/rtc.h> 18#include <linux/rtc.h>
35#include <linux/fsl_devices.h>
36 19
37#include <asm/mmu.h>
38#include <asm/reg.h>
39#include <asm/residual.h>
40#include <asm/io.h> 20#include <asm/io.h>
41#include <asm/pgtable.h>
42#include <asm/mpc8xx.h> 21#include <asm/mpc8xx.h>
43#include <asm/8xx_immap.h> 22#include <asm/8xx_immap.h>
44#include <asm/machdep.h>
45#include <asm/bootinfo.h>
46#include <asm/time.h>
47#include <asm/prom.h> 23#include <asm/prom.h>
48#include <asm/fs_pd.h> 24#include <asm/fs_pd.h>
49#include <mm/mmu_decl.h> 25#include <mm/mmu_decl.h>
50 26
51#include "sysdev/mpc8xx_pic.h" 27#include <sysdev/mpc8xx_pic.h>
28#include <sysdev/commproc.h>
52 29
53#ifdef CONFIG_PCMCIA_M8XX 30#ifdef CONFIG_PCMCIA_M8XX
54struct mpc8xx_pcmcia_ops m8xx_pcmcia_ops; 31struct mpc8xx_pcmcia_ops m8xx_pcmcia_ops;
55#endif 32#endif
56 33
57void m8xx_calibrate_decr(void); 34void m8xx_calibrate_decr(void);
58extern void m8xx_wdt_handler_install(bd_t *bp);
59extern int cpm_pic_init(void); 35extern int cpm_pic_init(void);
60extern int cpm_get_irq(void); 36extern int cpm_get_irq(void);
61 37
62/* A place holder for time base interrupts, if they are ever enabled. */ 38/* A place holder for time base interrupts, if they are ever enabled. */
63irqreturn_t timebase_interrupt(int irq, void * dev) 39static irqreturn_t timebase_interrupt(int irq, void *dev)
64{ 40{
65 printk ("timebase_interrupt()\n"); 41 printk ("timebase_interrupt()\n");
66 42
@@ -77,7 +53,7 @@ static struct irqaction tbint_irqaction = {
77void __init __attribute__ ((weak)) 53void __init __attribute__ ((weak))
78init_internal_rtc(void) 54init_internal_rtc(void)
79{ 55{
80 sit8xx_t *sys_tmr = (sit8xx_t *) immr_map(im_sit); 56 sit8xx_t __iomem *sys_tmr = immr_map(im_sit);
81 57
82 /* Disable the RTC one second and alarm interrupts. */ 58 /* Disable the RTC one second and alarm interrupts. */
83 clrbits16(&sys_tmr->sit_rtcsc, (RTCSC_SIE | RTCSC_ALE)); 59 clrbits16(&sys_tmr->sit_rtcsc, (RTCSC_SIE | RTCSC_ALE));
@@ -89,24 +65,24 @@ init_internal_rtc(void)
89 65
90static int __init get_freq(char *name, unsigned long *val) 66static int __init get_freq(char *name, unsigned long *val)
91{ 67{
92 struct device_node *cpu; 68 struct device_node *cpu;
93 const unsigned int *fp; 69 const unsigned int *fp;
94 int found = 0; 70 int found = 0;
95 71
96 /* The cpu node should have timebase and clock frequency properties */ 72 /* The cpu node should have timebase and clock frequency properties */
97 cpu = of_find_node_by_type(NULL, "cpu"); 73 cpu = of_find_node_by_type(NULL, "cpu");
98 74
99 if (cpu) { 75 if (cpu) {
100 fp = of_get_property(cpu, name, NULL); 76 fp = of_get_property(cpu, name, NULL);
101 if (fp) { 77 if (fp) {
102 found = 1; 78 found = 1;
103 *val = *fp; 79 *val = *fp;
104 } 80 }
105 81
106 of_node_put(cpu); 82 of_node_put(cpu);
107 } 83 }
108 84
109 return found; 85 return found;
110} 86}
111 87
112/* The decrementer counts at the system (internal) clock frequency divided by 88/* The decrementer counts at the system (internal) clock frequency divided by
@@ -116,13 +92,13 @@ static int __init get_freq(char *name, unsigned long *val)
116void __init mpc8xx_calibrate_decr(void) 92void __init mpc8xx_calibrate_decr(void)
117{ 93{
118 struct device_node *cpu; 94 struct device_node *cpu;
119 cark8xx_t *clk_r1; 95 cark8xx_t __iomem *clk_r1;
120 car8xx_t *clk_r2; 96 car8xx_t __iomem *clk_r2;
121 sitk8xx_t *sys_tmr1; 97 sitk8xx_t __iomem *sys_tmr1;
122 sit8xx_t *sys_tmr2; 98 sit8xx_t __iomem *sys_tmr2;
123 int irq, virq; 99 int irq, virq;
124 100
125 clk_r1 = (cark8xx_t *) immr_map(im_clkrstk); 101 clk_r1 = immr_map(im_clkrstk);
126 102
127 /* Unlock the SCCR. */ 103 /* Unlock the SCCR. */
128 out_be32(&clk_r1->cark_sccrk, ~KAPWR_KEY); 104 out_be32(&clk_r1->cark_sccrk, ~KAPWR_KEY);
@@ -130,24 +106,24 @@ void __init mpc8xx_calibrate_decr(void)
130 immr_unmap(clk_r1); 106 immr_unmap(clk_r1);
131 107
132 /* Force all 8xx processors to use divide by 16 processor clock. */ 108 /* Force all 8xx processors to use divide by 16 processor clock. */
133 clk_r2 = (car8xx_t *) immr_map(im_clkrst); 109 clk_r2 = immr_map(im_clkrst);
134 setbits32(&clk_r2->car_sccr, 0x02000000); 110 setbits32(&clk_r2->car_sccr, 0x02000000);
135 immr_unmap(clk_r2); 111 immr_unmap(clk_r2);
136 112
137 /* Processor frequency is MHz. 113 /* Processor frequency is MHz.
138 */ 114 */
139 ppc_tb_freq = 50000000; 115 ppc_tb_freq = 50000000;
140 if (!get_freq("bus-frequency", &ppc_tb_freq)) { 116 if (!get_freq("bus-frequency", &ppc_tb_freq)) {
141 printk(KERN_ERR "WARNING: Estimating decrementer frequency " 117 printk(KERN_ERR "WARNING: Estimating decrementer frequency "
142 "(not found)\n"); 118 "(not found)\n");
143 } 119 }
144 ppc_tb_freq /= 16; 120 ppc_tb_freq /= 16;
145 ppc_proc_freq = 50000000; 121 ppc_proc_freq = 50000000;
146 if (!get_freq("clock-frequency", &ppc_proc_freq)) 122 if (!get_freq("clock-frequency", &ppc_proc_freq))
147 printk(KERN_ERR "WARNING: Estimating processor frequency" 123 printk(KERN_ERR "WARNING: Estimating processor frequency"
148 "(not found)\n"); 124 "(not found)\n");
149 125
150 printk("Decrementer Frequency = 0x%lx\n", ppc_tb_freq); 126 printk("Decrementer Frequency = 0x%lx\n", ppc_tb_freq);
151 127
152 /* Perform some more timer/timebase initialization. This used 128 /* Perform some more timer/timebase initialization. This used
153 * to be done elsewhere, but other changes caused it to get 129 * to be done elsewhere, but other changes caused it to get
@@ -164,7 +140,7 @@ void __init mpc8xx_calibrate_decr(void)
164 * we guarantee the registers are locked, then we unlock them 140 * we guarantee the registers are locked, then we unlock them
165 * for our use. 141 * for our use.
166 */ 142 */
167 sys_tmr1 = (sitk8xx_t *) immr_map(im_sitk); 143 sys_tmr1 = immr_map(im_sitk);
168 out_be32(&sys_tmr1->sitk_tbscrk, ~KAPWR_KEY); 144 out_be32(&sys_tmr1->sitk_tbscrk, ~KAPWR_KEY);
169 out_be32(&sys_tmr1->sitk_rtcsck, ~KAPWR_KEY); 145 out_be32(&sys_tmr1->sitk_rtcsck, ~KAPWR_KEY);
170 out_be32(&sys_tmr1->sitk_tbk, ~KAPWR_KEY); 146 out_be32(&sys_tmr1->sitk_tbk, ~KAPWR_KEY);
@@ -180,24 +156,17 @@ void __init mpc8xx_calibrate_decr(void)
180 * we have to enable the timebase). The decrementer interrupt 156 * we have to enable the timebase). The decrementer interrupt
181 * is wired into the vector table, nothing to do here for that. 157 * is wired into the vector table, nothing to do here for that.
182 */ 158 */
183 cpu = of_find_node_by_type(NULL, "cpu"); 159 cpu = of_find_node_by_type(NULL, "cpu");
184 virq= irq_of_parse_and_map(cpu, 0); 160 virq= irq_of_parse_and_map(cpu, 0);
185 irq = irq_map[virq].hwirq; 161 irq = irq_map[virq].hwirq;
186 162
187 sys_tmr2 = (sit8xx_t *) immr_map(im_sit); 163 sys_tmr2 = immr_map(im_sit);
188 out_be16(&sys_tmr2->sit_tbscr, ((1 << (7 - (irq/2))) << 8) | 164 out_be16(&sys_tmr2->sit_tbscr, ((1 << (7 - (irq/2))) << 8) |
189 (TBSCR_TBF | TBSCR_TBE)); 165 (TBSCR_TBF | TBSCR_TBE));
190 immr_unmap(sys_tmr2); 166 immr_unmap(sys_tmr2);
191 167
192 if (setup_irq(virq, &tbint_irqaction)) 168 if (setup_irq(virq, &tbint_irqaction))
193 panic("Could not allocate timer IRQ!"); 169 panic("Could not allocate timer IRQ!");
194
195#ifdef CONFIG_8xx_WDT
196 /* Install watchdog timer handler early because it might be
197 * already enabled by the bootloader
198 */
199 m8xx_wdt_handler_install(binfo);
200#endif
201} 170}
202 171
203/* The RTC on the MPC8xx is an internal register. 172/* The RTC on the MPC8xx is an internal register.
@@ -207,14 +176,14 @@ void __init mpc8xx_calibrate_decr(void)
207 176
208int mpc8xx_set_rtc_time(struct rtc_time *tm) 177int mpc8xx_set_rtc_time(struct rtc_time *tm)
209{ 178{
210 sitk8xx_t *sys_tmr1; 179 sitk8xx_t __iomem *sys_tmr1;
211 sit8xx_t *sys_tmr2; 180 sit8xx_t __iomem *sys_tmr2;
212 int time; 181 int time;
213 182
214 sys_tmr1 = (sitk8xx_t *) immr_map(im_sitk); 183 sys_tmr1 = immr_map(im_sitk);
215 sys_tmr2 = (sit8xx_t *) immr_map(im_sit); 184 sys_tmr2 = immr_map(im_sit);
216 time = mktime(tm->tm_year+1900, tm->tm_mon+1, tm->tm_mday, 185 time = mktime(tm->tm_year+1900, tm->tm_mon+1, tm->tm_mday,
217 tm->tm_hour, tm->tm_min, tm->tm_sec); 186 tm->tm_hour, tm->tm_min, tm->tm_sec);
218 187
219 out_be32(&sys_tmr1->sitk_rtck, KAPWR_KEY); 188 out_be32(&sys_tmr1->sitk_rtck, KAPWR_KEY);
220 out_be32(&sys_tmr2->sit_rtc, time); 189 out_be32(&sys_tmr2->sit_rtc, time);
@@ -228,21 +197,20 @@ int mpc8xx_set_rtc_time(struct rtc_time *tm)
228void mpc8xx_get_rtc_time(struct rtc_time *tm) 197void mpc8xx_get_rtc_time(struct rtc_time *tm)
229{ 198{
230 unsigned long data; 199 unsigned long data;
231 sit8xx_t *sys_tmr = (sit8xx_t *) immr_map(im_sit); 200 sit8xx_t __iomem *sys_tmr = immr_map(im_sit);
232 201
233 /* Get time from the RTC. */ 202 /* Get time from the RTC. */
234 data = in_be32(&sys_tmr->sit_rtc); 203 data = in_be32(&sys_tmr->sit_rtc);
235 to_tm(data, tm); 204 to_tm(data, tm);
236 tm->tm_year -= 1900; 205 tm->tm_year -= 1900;
237 tm->tm_mon -= 1; 206 tm->tm_mon -= 1;
238 immr_unmap(sys_tmr); 207 immr_unmap(sys_tmr);
239 return; 208 return;
240} 209}
241 210
242void mpc8xx_restart(char *cmd) 211void mpc8xx_restart(char *cmd)
243{ 212{
244 __volatile__ unsigned char dummy; 213 car8xx_t __iomem *clk_r = immr_map(im_clkrst);
245 car8xx_t * clk_r = (car8xx_t *) immr_map(im_clkrst);
246 214
247 215
248 local_irq_disable(); 216 local_irq_disable();
@@ -252,26 +220,8 @@ void mpc8xx_restart(char *cmd)
252 */ 220 */
253 mtmsr(mfmsr() & ~0x1000); 221 mtmsr(mfmsr() & ~0x1000);
254 222
255 dummy = in_8(&clk_r->res[0]); 223 in_8(&clk_r->res[0]);
256 printk("Restart failed\n"); 224 panic("Restart failed\n");
257 while(1);
258}
259
260void mpc8xx_show_cpuinfo(struct seq_file *m)
261{
262 struct device_node *root;
263 uint memsize = total_memory;
264 const char *model = "";
265
266 seq_printf(m, "Vendor\t\t: Freescale Semiconductor\n");
267
268 root = of_find_node_by_path("/");
269 if (root)
270 model = of_get_property(root, "model", NULL);
271 seq_printf(m, "Machine\t\t: %s\n", model);
272 of_node_put(root);
273
274 seq_printf(m, "Memory\t\t: %d MB\n", memsize / (1024 * 1024));
275} 225}
276 226
277static void cpm_cascade(unsigned int irq, struct irq_desc *desc) 227static void cpm_cascade(unsigned int irq, struct irq_desc *desc)
@@ -298,7 +248,7 @@ void __init m8xx_pic_init(void)
298 int irq; 248 int irq;
299 249
300 if (mpc8xx_pic_init()) { 250 if (mpc8xx_pic_init()) {
301 printk(KERN_ERR "Failed interrupt 8xx controller initialization\n"); 251 printk(KERN_ERR "Failed interrupt 8xx controller initialization\n");
302 return; 252 return;
303 } 253 }
304 254
diff --git a/arch/powerpc/platforms/8xx/mpc86xads.h b/arch/powerpc/platforms/8xx/mpc86xads.h
index 59bad2f9ae51..cffa194ccf1f 100644
--- a/arch/powerpc/platforms/8xx/mpc86xads.h
+++ b/arch/powerpc/platforms/8xx/mpc86xads.h
@@ -15,7 +15,6 @@
15#ifndef __ASM_MPC86XADS_H__ 15#ifndef __ASM_MPC86XADS_H__
16#define __ASM_MPC86XADS_H__ 16#define __ASM_MPC86XADS_H__
17 17
18#include <asm/ppcboot.h>
19#include <sysdev/fsl_soc.h> 18#include <sysdev/fsl_soc.h>
20 19
21/* U-Boot maps BCSR to 0xff080000 */ 20/* U-Boot maps BCSR to 0xff080000 */
@@ -30,9 +29,6 @@
30#define CFG_PHYDEV_ADDR ((uint)0xff0a0000) 29#define CFG_PHYDEV_ADDR ((uint)0xff0a0000)
31#define BCSR5 ((uint)(CFG_PHYDEV_ADDR + 0x300)) 30#define BCSR5 ((uint)(CFG_PHYDEV_ADDR + 0x300))
32 31
33#define IMAP_ADDR (get_immrbase())
34#define IMAP_SIZE ((uint)(64 * 1024))
35
36#define MPC8xx_CPM_OFFSET (0x9c0) 32#define MPC8xx_CPM_OFFSET (0x9c0)
37#define CPM_MAP_ADDR (get_immrbase() + MPC8xx_CPM_OFFSET) 33#define CPM_MAP_ADDR (get_immrbase() + MPC8xx_CPM_OFFSET)
38#define CPM_IRQ_OFFSET 16 // for compability with cpm_uart driver 34#define CPM_IRQ_OFFSET 16 // for compability with cpm_uart driver
diff --git a/arch/powerpc/platforms/8xx/mpc86xads_setup.c b/arch/powerpc/platforms/8xx/mpc86xads_setup.c
index cf0e7bc8c2e7..49012835f453 100644
--- a/arch/powerpc/platforms/8xx/mpc86xads_setup.c
+++ b/arch/powerpc/platforms/8xx/mpc86xads_setup.c
@@ -31,21 +31,13 @@
31#include <asm/processor.h> 31#include <asm/processor.h>
32#include <asm/system.h> 32#include <asm/system.h>
33#include <asm/time.h> 33#include <asm/time.h>
34#include <asm/ppcboot.h>
35#include <asm/mpc8xx.h> 34#include <asm/mpc8xx.h>
36#include <asm/8xx_immap.h> 35#include <asm/8xx_immap.h>
37#include <asm/commproc.h> 36#include <asm/commproc.h>
38#include <asm/fs_pd.h> 37#include <asm/fs_pd.h>
39#include <asm/prom.h> 38#include <asm/prom.h>
40 39
41extern void cpm_reset(void); 40#include <sysdev/commproc.h>
42extern void mpc8xx_show_cpuinfo(struct seq_file*);
43extern void mpc8xx_restart(char *cmd);
44extern void mpc8xx_calibrate_decr(void);
45extern int mpc8xx_set_rtc_time(struct rtc_time *tm);
46extern void mpc8xx_get_rtc_time(struct rtc_time *tm);
47extern void m8xx_pic_init(void);
48extern unsigned int mpc8xx_get_irq(void);
49 41
50static void init_smc1_uart_ioports(struct fs_uart_platform_info* fpi); 42static void init_smc1_uart_ioports(struct fs_uart_platform_info* fpi);
51static void init_smc2_uart_ioports(struct fs_uart_platform_info* fpi); 43static void init_smc2_uart_ioports(struct fs_uart_platform_info* fpi);
@@ -254,20 +246,6 @@ int platform_device_skip(const char *model, int id)
254 246
255static void __init mpc86xads_setup_arch(void) 247static void __init mpc86xads_setup_arch(void)
256{ 248{
257 struct device_node *cpu;
258
259 cpu = of_find_node_by_type(NULL, "cpu");
260 if (cpu != 0) {
261 const unsigned int *fp;
262
263 fp = of_get_property(cpu, "clock-frequency", NULL);
264 if (fp != 0)
265 loops_per_jiffy = *fp / HZ;
266 else
267 loops_per_jiffy = 50000000 / HZ;
268 of_node_put(cpu);
269 }
270
271 cpm_reset(); 249 cpm_reset();
272 250
273 mpc86xads_board_setup(); 251 mpc86xads_board_setup();
@@ -292,7 +270,6 @@ define_machine(mpc86x_ads) {
292 .probe = mpc86xads_probe, 270 .probe = mpc86xads_probe,
293 .setup_arch = mpc86xads_setup_arch, 271 .setup_arch = mpc86xads_setup_arch,
294 .init_IRQ = m8xx_pic_init, 272 .init_IRQ = m8xx_pic_init,
295 .show_cpuinfo = mpc8xx_show_cpuinfo,
296 .get_irq = mpc8xx_get_irq, 273 .get_irq = mpc8xx_get_irq,
297 .restart = mpc8xx_restart, 274 .restart = mpc8xx_restart,
298 .calibrate_decr = mpc8xx_calibrate_decr, 275 .calibrate_decr = mpc8xx_calibrate_decr,
diff --git a/arch/powerpc/platforms/8xx/mpc885ads.h b/arch/powerpc/platforms/8xx/mpc885ads.h
index 7c31aec284c2..a5076668bad6 100644
--- a/arch/powerpc/platforms/8xx/mpc885ads.h
+++ b/arch/powerpc/platforms/8xx/mpc885ads.h
@@ -15,31 +15,12 @@
15#ifndef __ASM_MPC885ADS_H__ 15#ifndef __ASM_MPC885ADS_H__
16#define __ASM_MPC885ADS_H__ 16#define __ASM_MPC885ADS_H__
17 17
18#include <asm/ppcboot.h>
19#include <sysdev/fsl_soc.h> 18#include <sysdev/fsl_soc.h>
20 19
21/* U-Boot maps BCSR to 0xff080000 */
22#define BCSR_ADDR ((uint)0xff080000)
23#define BCSR_SIZE ((uint)32)
24#define BCSR0 ((uint)(BCSR_ADDR + 0x00))
25#define BCSR1 ((uint)(BCSR_ADDR + 0x04))
26#define BCSR2 ((uint)(BCSR_ADDR + 0x08))
27#define BCSR3 ((uint)(BCSR_ADDR + 0x0c))
28#define BCSR4 ((uint)(BCSR_ADDR + 0x10))
29
30#define CFG_PHYDEV_ADDR ((uint)0xff0a0000)
31#define BCSR5 ((uint)(CFG_PHYDEV_ADDR + 0x300))
32
33#define IMAP_ADDR (get_immrbase())
34#define IMAP_SIZE ((uint)(64 * 1024))
35
36#define MPC8xx_CPM_OFFSET (0x9c0) 20#define MPC8xx_CPM_OFFSET (0x9c0)
37#define CPM_MAP_ADDR (get_immrbase() + MPC8xx_CPM_OFFSET) 21#define CPM_MAP_ADDR (get_immrbase() + MPC8xx_CPM_OFFSET)
38#define CPM_IRQ_OFFSET 16 // for compability with cpm_uart driver 22#define CPM_IRQ_OFFSET 16 // for compability with cpm_uart driver
39 23
40#define PCMCIA_MEM_ADDR ((uint)0xff020000)
41#define PCMCIA_MEM_SIZE ((uint)(64 * 1024))
42
43/* Bits of interest in the BCSRs. 24/* Bits of interest in the BCSRs.
44 */ 25 */
45#define BCSR1_ETHEN ((uint)0x20000000) 26#define BCSR1_ETHEN ((uint)0x20000000)
@@ -68,28 +49,5 @@
68#define BCSR5_MII1_EN 0x02 49#define BCSR5_MII1_EN 0x02
69#define BCSR5_MII1_RST 0x01 50#define BCSR5_MII1_RST 0x01
70 51
71/* Interrupt level assignments */
72#define PHY_INTERRUPT SIU_IRQ7 /* PHY link change interrupt */
73#define SIU_INT_FEC1 SIU_LEVEL1 /* FEC1 interrupt */
74#define SIU_INT_FEC2 SIU_LEVEL3 /* FEC2 interrupt */
75#define FEC_INTERRUPT SIU_INT_FEC1 /* FEC interrupt */
76
77/* We don't use the 8259 */
78#define NR_8259_INTS 0
79
80/* CPM Ethernet through SCC3 */
81#define PA_ENET_RXD ((ushort)0x0040)
82#define PA_ENET_TXD ((ushort)0x0080)
83#define PE_ENET_TCLK ((uint)0x00004000)
84#define PE_ENET_RCLK ((uint)0x00008000)
85#define PE_ENET_TENA ((uint)0x00000010)
86#define PC_ENET_CLSN ((ushort)0x0400)
87#define PC_ENET_RENA ((ushort)0x0800)
88
89/* Control bits in the SICR to route TCLK (CLK5) and RCLK (CLK6) to
90 * SCC3. Also, make sure GR3 (bit 8) and SC3 (bit 9) are zero */
91#define SICR_ENET_MASK ((uint)0x00ff0000)
92#define SICR_ENET_CLKRT ((uint)0x002c0000)
93
94#endif /* __ASM_MPC885ADS_H__ */ 52#endif /* __ASM_MPC885ADS_H__ */
95#endif /* __KERNEL__ */ 53#endif /* __KERNEL__ */
diff --git a/arch/powerpc/platforms/8xx/mpc885ads_setup.c b/arch/powerpc/platforms/8xx/mpc885ads_setup.c
index 5a808d611ae3..2cf1b6a75173 100644
--- a/arch/powerpc/platforms/8xx/mpc885ads_setup.c
+++ b/arch/powerpc/platforms/8xx/mpc885ads_setup.c
@@ -1,11 +1,13 @@
1/*arch/powerpc/platforms/8xx/mpc885ads_setup.c 1/*
2 *
3 * Platform setup for the Freescale mpc885ads board 2 * Platform setup for the Freescale mpc885ads board
4 * 3 *
5 * Vitaly Bordug <vbordug@ru.mvista.com> 4 * Vitaly Bordug <vbordug@ru.mvista.com>
6 * 5 *
7 * Copyright 2005 MontaVista Software Inc. 6 * Copyright 2005 MontaVista Software Inc.
8 * 7 *
8 * Heavily modified by Scott Wood <scottwood@freescale.com>
9 * Copyright 2007 Freescale Semiconductor, Inc.
10 *
9 * This file is licensed under the terms of the GNU General Public License 11 * This file is licensed under the terms of the GNU General Public License
10 * version 2. This program is licensed "as is" without any warranty of any 12 * version 2. This program is licensed "as is" without any warranty of any
11 * kind, whether express or implied. 13 * kind, whether express or implied.
@@ -18,12 +20,12 @@
18#include <linux/ioport.h> 20#include <linux/ioport.h>
19#include <linux/device.h> 21#include <linux/device.h>
20#include <linux/delay.h> 22#include <linux/delay.h>
21#include <linux/root_dev.h>
22 23
23#include <linux/fs_enet_pd.h> 24#include <linux/fs_enet_pd.h>
24#include <linux/fs_uart_pd.h> 25#include <linux/fs_uart_pd.h>
25#include <linux/fsl_devices.h> 26#include <linux/fsl_devices.h>
26#include <linux/mii.h> 27#include <linux/mii.h>
28#include <linux/of_platform.h>
27 29
28#include <asm/delay.h> 30#include <asm/delay.h>
29#include <asm/io.h> 31#include <asm/io.h>
@@ -32,46 +34,28 @@
32#include <asm/processor.h> 34#include <asm/processor.h>
33#include <asm/system.h> 35#include <asm/system.h>
34#include <asm/time.h> 36#include <asm/time.h>
35#include <asm/ppcboot.h>
36#include <asm/mpc8xx.h> 37#include <asm/mpc8xx.h>
37#include <asm/8xx_immap.h> 38#include <asm/8xx_immap.h>
38#include <asm/commproc.h> 39#include <asm/commproc.h>
39#include <asm/fs_pd.h> 40#include <asm/fs_pd.h>
40#include <asm/prom.h> 41#include <asm/udbg.h>
41 42
42extern void cpm_reset(void); 43#include <sysdev/commproc.h>
43extern void mpc8xx_show_cpuinfo(struct seq_file *);
44extern void mpc8xx_restart(char *cmd);
45extern void mpc8xx_calibrate_decr(void);
46extern int mpc8xx_set_rtc_time(struct rtc_time *tm);
47extern void mpc8xx_get_rtc_time(struct rtc_time *tm);
48extern void m8xx_pic_init(void);
49extern unsigned int mpc8xx_get_irq(void);
50 44
51static void init_smc1_uart_ioports(struct fs_uart_platform_info *fpi); 45static u32 __iomem *bcsr, *bcsr5;
52static void init_smc2_uart_ioports(struct fs_uart_platform_info *fpi);
53static void init_scc3_ioports(struct fs_platform_info *ptr);
54 46
55#ifdef CONFIG_PCMCIA_M8XX 47#ifdef CONFIG_PCMCIA_M8XX
56static void pcmcia_hw_setup(int slot, int enable) 48static void pcmcia_hw_setup(int slot, int enable)
57{ 49{
58 unsigned *bcsr_io;
59
60 bcsr_io = ioremap(BCSR1, sizeof(unsigned long));
61 if (enable) 50 if (enable)
62 clrbits32(bcsr_io, BCSR1_PCCEN); 51 clrbits32(&bcsr[1], BCSR1_PCCEN);
63 else 52 else
64 setbits32(bcsr_io, BCSR1_PCCEN); 53 setbits32(&bcsr[1], BCSR1_PCCEN);
65
66 iounmap(bcsr_io);
67} 54}
68 55
69static int pcmcia_set_voltage(int slot, int vcc, int vpp) 56static int pcmcia_set_voltage(int slot, int vcc, int vpp)
70{ 57{
71 u32 reg = 0; 58 u32 reg = 0;
72 unsigned *bcsr_io;
73
74 bcsr_io = ioremap(BCSR1, sizeof(unsigned long));
75 59
76 switch (vcc) { 60 switch (vcc) {
77 case 0: 61 case 0:
@@ -106,344 +90,196 @@ static int pcmcia_set_voltage(int slot, int vcc, int vpp)
106 } 90 }
107 91
108 /* first, turn off all power */ 92 /* first, turn off all power */
109 clrbits32(bcsr_io, 0x00610000); 93 clrbits32(&bcsr[1], 0x00610000);
110 94
111 /* enable new powersettings */ 95 /* enable new powersettings */
112 setbits32(bcsr_io, reg); 96 setbits32(&bcsr[1], reg);
113 97
114 iounmap(bcsr_io);
115 return 0; 98 return 0;
116} 99}
117#endif 100#endif
118 101
119void __init mpc885ads_board_setup(void) 102struct cpm_pin {
120{ 103 int port, pin, flags;
121 cpm8xx_t *cp; 104};
122 unsigned int *bcsr_io;
123 u8 tmpval8;
124
125#ifdef CONFIG_FS_ENET
126 iop8xx_t *io_port;
127#endif
128
129 bcsr_io = ioremap(BCSR1, sizeof(unsigned long));
130 cp = (cpm8xx_t *) immr_map(im_cpm);
131
132 if (bcsr_io == NULL) {
133 printk(KERN_CRIT "Could not remap BCSR\n");
134 return;
135 }
136#ifdef CONFIG_SERIAL_CPM_SMC1
137 clrbits32(bcsr_io, BCSR1_RS232EN_1);
138 clrbits32(&cp->cp_simode, 0xe0000000 >> 17); /* brg1 */
139 tmpval8 = in_8(&(cp->cp_smc[0].smc_smcm)) | (SMCM_RX | SMCM_TX);
140 out_8(&(cp->cp_smc[0].smc_smcm), tmpval8);
141 clrbits16(&cp->cp_smc[0].smc_smcmr, SMCMR_REN | SMCMR_TEN); /* brg1 */
142#else
143 setbits32(bcsr_io, BCSR1_RS232EN_1);
144 out_be16(&cp->cp_smc[0].smc_smcmr, 0);
145 out_8(&cp->cp_smc[0].smc_smce, 0);
146#endif
147
148#ifdef CONFIG_SERIAL_CPM_SMC2
149 clrbits32(bcsr_io, BCSR1_RS232EN_2);
150 clrbits32(&cp->cp_simode, 0xe0000000 >> 1);
151 setbits32(&cp->cp_simode, 0x20000000 >> 1); /* brg2 */
152 tmpval8 = in_8(&(cp->cp_smc[1].smc_smcm)) | (SMCM_RX | SMCM_TX);
153 out_8(&(cp->cp_smc[1].smc_smcm), tmpval8);
154 clrbits16(&cp->cp_smc[1].smc_smcmr, SMCMR_REN | SMCMR_TEN);
155 105
156 init_smc2_uart_ioports(0); 106static struct cpm_pin mpc885ads_pins[] = {
157#else 107 /* SMC1 */
158 setbits32(bcsr_io, BCSR1_RS232EN_2); 108 {CPM_PORTB, 24, CPM_PIN_INPUT}, /* RX */
159 out_be16(&cp->cp_smc[1].smc_smcmr, 0); 109 {CPM_PORTB, 25, CPM_PIN_INPUT | CPM_PIN_SECONDARY}, /* TX */
160 out_8(&cp->cp_smc[1].smc_smce, 0);
161#endif
162 immr_unmap(cp);
163 iounmap(bcsr_io);
164
165#ifdef CONFIG_FS_ENET
166 /* use MDC for MII (common) */
167 io_port = (iop8xx_t *) immr_map(im_ioport);
168 setbits16(&io_port->iop_pdpar, 0x0080);
169 clrbits16(&io_port->iop_pddir, 0x0080);
170
171 bcsr_io = ioremap(BCSR5, sizeof(unsigned long));
172 clrbits32(bcsr_io, BCSR5_MII1_EN);
173 clrbits32(bcsr_io, BCSR5_MII1_RST);
174#ifndef CONFIG_FC_ENET_HAS_SCC
175 clrbits32(bcsr_io, BCSR5_MII2_EN);
176 clrbits32(bcsr_io, BCSR5_MII2_RST);
177 110
111 /* SMC2 */
112#ifndef CONFIG_MPC8xx_SECOND_ETH_FEC2
113 {CPM_PORTE, 21, CPM_PIN_INPUT}, /* RX */
114 {CPM_PORTE, 20, CPM_PIN_INPUT | CPM_PIN_SECONDARY}, /* TX */
178#endif 115#endif
179 iounmap(bcsr_io);
180 immr_unmap(io_port);
181 116
117 /* SCC3 */
118 {CPM_PORTA, 9, CPM_PIN_INPUT}, /* RX */
119 {CPM_PORTA, 8, CPM_PIN_INPUT}, /* TX */
120 {CPM_PORTC, 4, CPM_PIN_INPUT | CPM_PIN_SECONDARY | CPM_PIN_GPIO}, /* RENA */
121 {CPM_PORTC, 5, CPM_PIN_INPUT | CPM_PIN_SECONDARY | CPM_PIN_GPIO}, /* CLSN */
122 {CPM_PORTE, 27, CPM_PIN_INPUT | CPM_PIN_SECONDARY}, /* TENA */
123 {CPM_PORTE, 17, CPM_PIN_INPUT}, /* CLK5 */
124 {CPM_PORTE, 16, CPM_PIN_INPUT}, /* CLK6 */
125
126 /* MII1 */
127 {CPM_PORTA, 0, CPM_PIN_INPUT},
128 {CPM_PORTA, 1, CPM_PIN_INPUT},
129 {CPM_PORTA, 2, CPM_PIN_INPUT},
130 {CPM_PORTA, 3, CPM_PIN_INPUT},
131 {CPM_PORTA, 4, CPM_PIN_OUTPUT},
132 {CPM_PORTA, 10, CPM_PIN_OUTPUT},
133 {CPM_PORTA, 11, CPM_PIN_OUTPUT},
134 {CPM_PORTB, 19, CPM_PIN_INPUT},
135 {CPM_PORTB, 31, CPM_PIN_INPUT},
136 {CPM_PORTC, 12, CPM_PIN_INPUT},
137 {CPM_PORTC, 13, CPM_PIN_INPUT},
138 {CPM_PORTE, 30, CPM_PIN_OUTPUT},
139 {CPM_PORTE, 31, CPM_PIN_OUTPUT},
140
141 /* MII2 */
142#ifdef CONFIG_MPC8xx_SECOND_ETH_FEC2
143 {CPM_PORTE, 14, CPM_PIN_OUTPUT | CPM_PIN_SECONDARY},
144 {CPM_PORTE, 15, CPM_PIN_OUTPUT | CPM_PIN_SECONDARY},
145 {CPM_PORTE, 16, CPM_PIN_OUTPUT},
146 {CPM_PORTE, 17, CPM_PIN_OUTPUT | CPM_PIN_SECONDARY},
147 {CPM_PORTE, 18, CPM_PIN_OUTPUT | CPM_PIN_SECONDARY},
148 {CPM_PORTE, 19, CPM_PIN_OUTPUT | CPM_PIN_SECONDARY},
149 {CPM_PORTE, 20, CPM_PIN_OUTPUT | CPM_PIN_SECONDARY},
150 {CPM_PORTE, 21, CPM_PIN_OUTPUT},
151 {CPM_PORTE, 22, CPM_PIN_OUTPUT},
152 {CPM_PORTE, 23, CPM_PIN_OUTPUT},
153 {CPM_PORTE, 24, CPM_PIN_OUTPUT},
154 {CPM_PORTE, 25, CPM_PIN_OUTPUT},
155 {CPM_PORTE, 26, CPM_PIN_OUTPUT},
156 {CPM_PORTE, 27, CPM_PIN_OUTPUT},
157 {CPM_PORTE, 28, CPM_PIN_OUTPUT},
158 {CPM_PORTE, 29, CPM_PIN_OUTPUT},
182#endif 159#endif
160};
183 161
184#ifdef CONFIG_PCMCIA_M8XX 162static void __init init_ioports(void)
185 /*Set up board specific hook-ups */
186 m8xx_pcmcia_ops.hw_ctrl = pcmcia_hw_setup;
187 m8xx_pcmcia_ops.voltage_set = pcmcia_set_voltage;
188#endif
189}
190
191static void init_fec1_ioports(struct fs_platform_info *ptr)
192{ 163{
193 cpm8xx_t *cp = (cpm8xx_t *) immr_map(im_cpm); 164 int i;
194 iop8xx_t *io_port = (iop8xx_t *) immr_map(im_ioport);
195
196 /* configure FEC1 pins */
197 setbits16(&io_port->iop_papar, 0xf830);
198 setbits16(&io_port->iop_padir, 0x0830);
199 clrbits16(&io_port->iop_padir, 0xf000);
200 165
201 setbits32(&cp->cp_pbpar, 0x00001001); 166 for (i = 0; i < ARRAY_SIZE(mpc885ads_pins); i++) {
202 clrbits32(&cp->cp_pbdir, 0x00001001); 167 struct cpm_pin *pin = &mpc885ads_pins[i];
203 168 cpm1_set_pin(pin->port, pin->pin, pin->flags);
204 setbits16(&io_port->iop_pcpar, 0x000c); 169 }
205 clrbits16(&io_port->iop_pcdir, 0x000c);
206 170
207 setbits32(&cp->cp_pepar, 0x00000003); 171 cpm1_clk_setup(CPM_CLK_SMC1, CPM_BRG1, CPM_CLK_RTX);
208 setbits32(&cp->cp_pedir, 0x00000003); 172 cpm1_clk_setup(CPM_CLK_SMC2, CPM_BRG2, CPM_CLK_RTX);
209 clrbits32(&cp->cp_peso, 0x00000003); 173 cpm1_clk_setup(CPM_CLK_SCC3, CPM_CLK5, CPM_CLK_TX);
210 clrbits32(&cp->cp_cptr, 0x00000100); 174 cpm1_clk_setup(CPM_CLK_SCC3, CPM_CLK6, CPM_CLK_RX);
211 175
212 immr_unmap(io_port); 176 /* Set FEC1 and FEC2 to MII mode */
213 immr_unmap(cp); 177 clrbits32(&mpc8xx_immr->im_cpm.cp_cptr, 0x00000180);
214} 178}
215 179
216static void init_fec2_ioports(struct fs_platform_info *ptr) 180static void __init mpc885ads_setup_arch(void)
217{ 181{
218 cpm8xx_t *cp = (cpm8xx_t *) immr_map(im_cpm); 182 struct device_node *np;
219 iop8xx_t *io_port = (iop8xx_t *) immr_map(im_ioport);
220
221 /* configure FEC2 pins */
222 setbits32(&cp->cp_pepar, 0x0003fffc);
223 setbits32(&cp->cp_pedir, 0x0003fffc);
224 clrbits32(&cp->cp_peso, 0x000087fc);
225 setbits32(&cp->cp_peso, 0x00037800);
226 clrbits32(&cp->cp_cptr, 0x00000080);
227
228 immr_unmap(io_port);
229 immr_unmap(cp);
230}
231 183
232void init_fec_ioports(struct fs_platform_info *fpi) 184 cpm_reset();
233{ 185 init_ioports();
234 int fec_no = fs_get_fec_index(fpi->fs_no);
235 186
236 switch (fec_no) { 187 np = of_find_compatible_node(NULL, NULL, "fsl,mpc885ads-bcsr");
237 case 0: 188 if (!np) {
238 init_fec1_ioports(fpi); 189 printk(KERN_CRIT "Could not find fsl,mpc885ads-bcsr node\n");
239 break;
240 case 1:
241 init_fec2_ioports(fpi);
242 break;
243 default:
244 printk(KERN_ERR "init_fec_ioports: invalid FEC number\n");
245 return; 190 return;
246 } 191 }
247}
248
249static void init_scc3_ioports(struct fs_platform_info *fpi)
250{
251 unsigned *bcsr_io;
252 iop8xx_t *io_port;
253 cpm8xx_t *cp;
254 192
255 bcsr_io = ioremap(BCSR_ADDR, BCSR_SIZE); 193 bcsr = of_iomap(np, 0);
256 io_port = (iop8xx_t *) immr_map(im_ioport); 194 bcsr5 = of_iomap(np, 1);
257 cp = (cpm8xx_t *) immr_map(im_cpm); 195 of_node_put(np);
258 196
259 if (bcsr_io == NULL) { 197 if (!bcsr || !bcsr5) {
260 printk(KERN_CRIT "Could not remap BCSR\n"); 198 printk(KERN_CRIT "Could not remap BCSR\n");
261 return; 199 return;
262 } 200 }
263 201
264 /* Enable the PHY. 202 clrbits32(&bcsr[1], BCSR1_RS232EN_1);
265 */ 203#ifdef CONFIG_MPC8xx_SECOND_ETH_FEC2
266 clrbits32(bcsr_io + 4, BCSR4_ETH10_RST); 204 setbits32(&bcsr[1], BCSR1_RS232EN_2);
267 udelay(1000); 205#else
268 setbits32(bcsr_io + 4, BCSR4_ETH10_RST); 206 clrbits32(&bcsr[1], BCSR1_RS232EN_2);
269 /* Configure port A pins for Txd and Rxd. 207#endif
270 */
271 setbits16(&io_port->iop_papar, PA_ENET_RXD | PA_ENET_TXD);
272 clrbits16(&io_port->iop_padir, PA_ENET_RXD | PA_ENET_TXD);
273 208
274 /* Configure port C pins to enable CLSN and RENA. 209 clrbits32(bcsr5, BCSR5_MII1_EN);
275 */ 210 setbits32(bcsr5, BCSR5_MII1_RST);
276 clrbits16(&io_port->iop_pcpar, PC_ENET_CLSN | PC_ENET_RENA); 211 udelay(1000);
277 clrbits16(&io_port->iop_pcdir, PC_ENET_CLSN | PC_ENET_RENA); 212 clrbits32(bcsr5, BCSR5_MII1_RST);
278 setbits16(&io_port->iop_pcso, PC_ENET_CLSN | PC_ENET_RENA);
279 213
280 /* Configure port E for TCLK and RCLK. 214#ifdef CONFIG_MPC8xx_SECOND_ETH_FEC2
281 */ 215 clrbits32(bcsr5, BCSR5_MII2_EN);
282 setbits32(&cp->cp_pepar, PE_ENET_TCLK | PE_ENET_RCLK); 216 setbits32(bcsr5, BCSR5_MII2_RST);
283 clrbits32(&cp->cp_pepar, PE_ENET_TENA); 217 udelay(1000);
284 clrbits32(&cp->cp_pedir, PE_ENET_TCLK | PE_ENET_RCLK | PE_ENET_TENA); 218 clrbits32(bcsr5, BCSR5_MII2_RST);
285 clrbits32(&cp->cp_peso, PE_ENET_TCLK | PE_ENET_RCLK); 219#else
286 setbits32(&cp->cp_peso, PE_ENET_TENA); 220 setbits32(bcsr5, BCSR5_MII2_EN);
287 221#endif
288 /* Configure Serial Interface clock routing.
289 * First, clear all SCC bits to zero, then set the ones we want.
290 */
291 clrbits32(&cp->cp_sicr, SICR_ENET_MASK);
292 setbits32(&cp->cp_sicr, SICR_ENET_CLKRT);
293 222
294 /* Disable Rx and Tx. SMC1 sshould be stopped if SCC3 eternet are used. 223#ifdef CONFIG_MPC8xx_SECOND_ETH_SCC3
295 */ 224 clrbits32(&bcsr[4], BCSR4_ETH10_RST);
296 clrbits16(&cp->cp_smc[0].smc_smcmr, SMCMR_REN | SMCMR_TEN); 225 udelay(1000);
297 /* On the MPC885ADS SCC ethernet PHY is initialized in the full duplex mode 226 setbits32(&bcsr[4], BCSR4_ETH10_RST);
298 * by H/W setting after reset. SCC ethernet controller support only half duplex.
299 * This discrepancy of modes causes a lot of carrier lost errors.
300 */
301 227
302 /* In the original SCC enet driver the following code is placed at 228 setbits32(&bcsr[1], BCSR1_ETHEN);
303 the end of the initialization */
304 setbits32(&cp->cp_pepar, PE_ENET_TENA);
305 clrbits32(&cp->cp_pedir, PE_ENET_TENA);
306 setbits32(&cp->cp_peso, PE_ENET_TENA);
307 229
308 setbits32(bcsr_io + 4, BCSR1_ETHEN); 230 np = of_find_node_by_path("/soc@ff000000/cpm@9c0/serial@a80");
309 iounmap(bcsr_io); 231#else
310 immr_unmap(io_port); 232 np = of_find_node_by_path("/soc@ff000000/cpm@9c0/ethernet@a40");
311 immr_unmap(cp); 233#endif
312}
313 234
314void init_scc_ioports(struct fs_platform_info *fpi) 235 /* The SCC3 enet registers overlap the SMC1 registers, so
315{ 236 * one of the two must be removed from the device tree.
316 int scc_no = fs_get_scc_index(fpi->fs_no); 237 */
317 238
318 switch (scc_no) { 239 if (np) {
319 case 2: 240 of_detach_node(np);
320 init_scc3_ioports(fpi); 241 of_node_put(np);
321 break;
322 default:
323 printk(KERN_ERR "init_scc_ioports: invalid SCC number\n");
324 return;
325 } 242 }
326}
327 243
328static void init_smc1_uart_ioports(struct fs_uart_platform_info *ptr) 244#ifdef CONFIG_PCMCIA_M8XX
329{ 245 /* Set up board specific hook-ups.*/
330 unsigned *bcsr_io; 246 m8xx_pcmcia_ops.hw_ctrl = pcmcia_hw_setup;
331 cpm8xx_t *cp; 247 m8xx_pcmcia_ops.voltage_set = pcmcia_set_voltage;
332 248#endif
333 cp = (cpm8xx_t *) immr_map(im_cpm);
334 setbits32(&cp->cp_pepar, 0x000000c0);
335 clrbits32(&cp->cp_pedir, 0x000000c0);
336 clrbits32(&cp->cp_peso, 0x00000040);
337 setbits32(&cp->cp_peso, 0x00000080);
338 immr_unmap(cp);
339
340 bcsr_io = ioremap(BCSR1, sizeof(unsigned long));
341
342 if (bcsr_io == NULL) {
343 printk(KERN_CRIT "Could not remap BCSR1\n");
344 return;
345 }
346 clrbits32(bcsr_io, BCSR1_RS232EN_1);
347 iounmap(bcsr_io);
348} 249}
349 250
350static void init_smc2_uart_ioports(struct fs_uart_platform_info *fpi) 251static int __init mpc885ads_probe(void)
351{ 252{
352 unsigned *bcsr_io; 253 unsigned long root = of_get_flat_dt_root();
353 cpm8xx_t *cp; 254 return of_flat_dt_is_compatible(root, "fsl,mpc885ads");
354
355 cp = (cpm8xx_t *) immr_map(im_cpm);
356 setbits32(&cp->cp_pepar, 0x00000c00);
357 clrbits32(&cp->cp_pedir, 0x00000c00);
358 clrbits32(&cp->cp_peso, 0x00000400);
359 setbits32(&cp->cp_peso, 0x00000800);
360 immr_unmap(cp);
361
362 bcsr_io = ioremap(BCSR1, sizeof(unsigned long));
363
364 if (bcsr_io == NULL) {
365 printk(KERN_CRIT "Could not remap BCSR1\n");
366 return;
367 }
368 clrbits32(bcsr_io, BCSR1_RS232EN_2);
369 iounmap(bcsr_io);
370} 255}
371 256
372void init_smc_ioports(struct fs_uart_platform_info *data) 257static struct of_device_id __initdata of_bus_ids[] = {
373{ 258 { .name = "soc", },
374 int smc_no = fs_uart_id_fsid2smc(data->fs_no); 259 { .name = "cpm", },
260 { .name = "localbus", },
261 {},
262};
375 263
376 switch (smc_no) { 264static int __init declare_of_platform_devices(void)
377 case 0:
378 init_smc1_uart_ioports(data);
379 data->brg = data->clk_rx;
380 break;
381 case 1:
382 init_smc2_uart_ioports(data);
383 data->brg = data->clk_rx;
384 break;
385 default:
386 printk(KERN_ERR "init_scc_ioports: invalid SCC number\n");
387 return;
388 }
389}
390
391int platform_device_skip(const char *model, int id)
392{ 265{
393#ifdef CONFIG_MPC8xx_SECOND_ETH_SCC3 266 /* Publish the QE devices */
394 const char *dev = "FEC"; 267 if (machine_is(mpc885_ads))
395 int n = 2; 268 of_platform_bus_probe(NULL, of_bus_ids, NULL);
396#else
397 const char *dev = "SCC";
398 int n = 3;
399#endif
400
401 if (!strcmp(model, dev) && n == id)
402 return 1;
403 269
404 return 0; 270 return 0;
405} 271}
406 272device_initcall(declare_of_platform_devices);
407static void __init mpc885ads_setup_arch(void) 273
408{ 274define_machine(mpc885_ads) {
409 struct device_node *cpu; 275 .name = "Freescale MPC885 ADS",
410 276 .probe = mpc885ads_probe,
411 cpu = of_find_node_by_type(NULL, "cpu"); 277 .setup_arch = mpc885ads_setup_arch,
412 if (cpu != 0) { 278 .init_IRQ = m8xx_pic_init,
413 const unsigned int *fp; 279 .get_irq = mpc8xx_get_irq,
414 280 .restart = mpc8xx_restart,
415 fp = of_get_property(cpu, "clock-frequency", NULL); 281 .calibrate_decr = mpc8xx_calibrate_decr,
416 if (fp != 0) 282 .set_rtc_time = mpc8xx_set_rtc_time,
417 loops_per_jiffy = *fp / HZ; 283 .get_rtc_time = mpc8xx_get_rtc_time,
418 else 284 .progress = udbg_progress,
419 loops_per_jiffy = 50000000 / HZ; 285};
420 of_node_put(cpu);
421 }
422
423 cpm_reset();
424
425 mpc885ads_board_setup();
426
427 ROOT_DEV = Root_NFS;
428}
429
430static int __init mpc885ads_probe(void)
431{
432 char *model = of_get_flat_dt_prop(of_get_flat_dt_root(),
433 "model", NULL);
434 if (model == NULL)
435 return 0;
436 if (strcmp(model, "MPC885ADS"))
437 return 0;
438
439 return 1;
440}
441
442define_machine(mpc885_ads)
443{
444.name = "MPC885 ADS",.probe = mpc885ads_probe,.setup_arch =
445 mpc885ads_setup_arch,.init_IRQ =
446 m8xx_pic_init,.show_cpuinfo = mpc8xx_show_cpuinfo,.get_irq =
447 mpc8xx_get_irq,.restart = mpc8xx_restart,.calibrate_decr =
448 mpc8xx_calibrate_decr,.set_rtc_time =
449 mpc8xx_set_rtc_time,.get_rtc_time = mpc8xx_get_rtc_time,};
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-17 00:07:54 -0500