1 files changed, 0 insertions, 38 deletions

diff --git a/arch/powerpc/platforms/8xx/mpc885ads.h b/arch/powerpc/platforms/8xx/mpc885ads.h
index a21e528f26c6..a5076668bad6 100644
--- a/arch/powerpc/platforms/8xx/mpc885ads.h
+++ b/arch/powerpc/platforms/8xx/mpc885ads.h
@@ -17,25 +17,10 @@
 
 #include <sysdev/fsl_soc.h>
 
-/* U-Boot maps BCSR to 0xff080000 */
-#define BCSR_ADDR               ((uint)0xff080000)
-#define BCSR_SIZE               ((uint)32)
-#define BCSR0                   ((uint)(BCSR_ADDR + 0x00))
-#define BCSR1                   ((uint)(BCSR_ADDR + 0x04))
-#define BCSR2                   ((uint)(BCSR_ADDR + 0x08))
-#define BCSR3                   ((uint)(BCSR_ADDR + 0x0c))
-#define BCSR4                   ((uint)(BCSR_ADDR + 0x10))
-
-#define CFG_PHYDEV_ADDR         ((uint)0xff0a0000)
-#define BCSR5                   ((uint)(CFG_PHYDEV_ADDR + 0x300))
-
 #define MPC8xx_CPM_OFFSET       (0x9c0)
 #define CPM_MAP_ADDR            (get_immrbase() + MPC8xx_CPM_OFFSET)
 #define CPM_IRQ_OFFSET          16     // for compability with cpm_uart driver
 
-#define PCMCIA_MEM_ADDR         ((uint)0xff020000)
-#define PCMCIA_MEM_SIZE         ((uint)(64 * 1024))
-
 /* Bits of interest in the BCSRs.
  */
 #define BCSR1_ETHEN             ((uint)0x20000000)
@@ -64,28 +49,5 @@
 #define BCSR5_MII1_EN           0x02
 #define BCSR5_MII1_RST          0x01
 
-/* Interrupt level assignments */
-#define PHY_INTERRUPT   SIU_IRQ7        /* PHY link change interrupt */
-#define SIU_INT_FEC1    SIU_LEVEL1      /* FEC1 interrupt */
-#define SIU_INT_FEC2    SIU_LEVEL3      /* FEC2 interrupt */
-#define FEC_INTERRUPT   SIU_INT_FEC1    /* FEC interrupt */
-
-/* We don't use the 8259 */
-#define NR_8259_INTS    0
-
-/* CPM Ethernet through SCC3 */
-#define PA_ENET_RXD     ((ushort)0x0040)
-#define PA_ENET_TXD     ((ushort)0x0080)
-#define PE_ENET_TCLK    ((uint)0x00004000)
-#define PE_ENET_RCLK    ((uint)0x00008000)
-#define PE_ENET_TENA    ((uint)0x00000010)
-#define PC_ENET_CLSN    ((ushort)0x0400)
-#define PC_ENET_RENA    ((ushort)0x0800)
-
-/* Control bits in the SICR to route TCLK (CLK5) and RCLK (CLK6) to
- * SCC3.  Also, make sure GR3 (bit 8) and SC3 (bit 9) are zero */
-#define SICR_ENET_MASK  ((uint)0x00ff0000)
-#define SICR_ENET_CLKRT ((uint)0x002c0000)
-
 #endif /* __ASM_MPC885ADS_H__ */
 #endif /* __KERNEL__ */