8 files changed, 1069 insertions, 0 deletions

diff --git a/arch/powerpc/platforms/86xx/Kconfig b/arch/powerpc/platforms/86xx/Kconfig
new file mode 100644
index 000000000000..3a87863d2876
--- /dev/null
+++ b/arch/powerpc/platforms/86xx/Kconfig
@@ -0,0 +1,36 @@
+menu "Platform Support"
+        depends on PPC_86xx
+
+choice
+        prompt "Machine Type"
+        default MPC8641_HPCN
+
+config MPC8641_HPCN
+        bool "Freescale MPC8641 HPCN"
+        help
+          This option enables support for the MPC8641 HPCN board.
+
+endchoice
+
+
+config MPC8641
+        bool
+        select PPC_INDIRECT_PCI
+        select PPC_UDBG_16550
+        default y if MPC8641_HPCN
+
+config MPIC
+        bool
+        default y
+
+config PPC_INDIRECT_PCI_BE
+        bool
+        depends on PPC_86xx
+        default y
+
+config PPC_STD_MMU
+        bool
+        depends on PPC_86xx
+        default y
+
+endmenu
diff --git a/arch/powerpc/platforms/86xx/Makefile b/arch/powerpc/platforms/86xx/Makefile
new file mode 100644
index 000000000000..7be796c5d5c9
--- /dev/null
+++ b/arch/powerpc/platforms/86xx/Makefile
@@ -0,0 +1,10 @@
+#
+# Makefile for the PowerPC 86xx linux kernel.
+#
+
+
+ifeq ($(CONFIG_PPC_86xx),y)
+obj-$(CONFIG_SMP)               += mpc86xx_smp.o
+endif
+obj-$(CONFIG_MPC8641_HPCN)      += mpc86xx_hpcn.o
+obj-$(CONFIG_PCI)               += pci.o mpc86xx_pcie.o
diff --git a/arch/powerpc/platforms/86xx/mpc8641_hpcn.h b/arch/powerpc/platforms/86xx/mpc8641_hpcn.h
new file mode 100644
index 000000000000..5042253758b7
--- /dev/null
+++ b/arch/powerpc/platforms/86xx/mpc8641_hpcn.h
@@ -0,0 +1,54 @@
+/*
+ * MPC8641 HPCN board definitions
+ *
+ * Copyright 2006 Freescale Semiconductor Inc.
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ *
+ * Author: Xianghua Xiao <x.xiao@freescale.com>
+ */
+
+#ifndef __MPC8641_HPCN_H__
+#define __MPC8641_HPCN_H__
+
+#include <linux/config.h>
+#include <linux/init.h>
+
+/* PCI interrupt controller */
+#define PIRQA           3
+#define PIRQB           4
+#define PIRQC           5
+#define PIRQD           6
+#define PIRQ7           7
+#define PIRQE           9
+#define PIRQF           10
+#define PIRQG           11
+#define PIRQH           12
+
+/* PCI-Express memory map */
+#define MPC86XX_PCIE_LOWER_IO        0x00000000
+#define MPC86XX_PCIE_UPPER_IO        0x00ffffff
+
+#define MPC86XX_PCIE_LOWER_MEM       0x80000000
+#define MPC86XX_PCIE_UPPER_MEM       0x9fffffff
+
+#define MPC86XX_PCIE_IO_BASE         0xe2000000
+#define MPC86XX_PCIE_MEM_OFFSET      0x00000000
+
+#define MPC86XX_PCIE_IO_SIZE         0x01000000
+
+#define PCIE1_CFG_ADDR_OFFSET    (0x8000)
+#define PCIE1_CFG_DATA_OFFSET    (0x8004)
+
+#define PCIE2_CFG_ADDR_OFFSET    (0x9000)
+#define PCIE2_CFG_DATA_OFFSET    (0x9004)
+
+#define MPC86xx_PCIE_OFFSET PCIE1_CFG_ADDR_OFFSET
+#define MPC86xx_PCIE_SIZE       (0x1000)
+
+#define MPC86XX_RSTCR_OFFSET    (0xe00b0)       /* Reset Control Register */
+
+#endif  /* __MPC8641_HPCN_H__ */
diff --git a/arch/powerpc/platforms/86xx/mpc86xx.h b/arch/powerpc/platforms/86xx/mpc86xx.h
new file mode 100644
index 000000000000..e3c9e4f417d3
--- /dev/null
+++ b/arch/powerpc/platforms/86xx/mpc86xx.h
@@ -0,0 +1,28 @@
+/*
+ * Copyright 2006 Freescale Semiconductor Inc.
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#ifndef __MPC86XX_H__
+#define __MPC86XX_H__
+
+/*
+ * Declaration for the various functions exported by the
+ * mpc86xx_* files. Mostly for use by mpc86xx_setup().
+ */
+
+extern int __init add_bridge(struct device_node *dev);
+
+extern void __init setup_indirect_pcie(struct pci_controller *hose,
+                                       u32 cfg_addr, u32 cfg_data);
+extern void __init setup_indirect_pcie_nomap(struct pci_controller *hose,
+                                             void __iomem *cfg_addr,
+                                             void __iomem *cfg_data);
+
+extern void __init mpc86xx_smp_init(void);
+
+#endif  /* __MPC86XX_H__ */
diff --git a/arch/powerpc/platforms/86xx/mpc86xx_hpcn.c b/arch/powerpc/platforms/86xx/mpc86xx_hpcn.c
new file mode 100644
index 000000000000..483c21df181e
--- /dev/null
+++ b/arch/powerpc/platforms/86xx/mpc86xx_hpcn.c
@@ -0,0 +1,326 @@
+/*
+ * MPC86xx HPCN board specific routines
+ *
+ * Recode: ZHANG WEI <wei.zhang@freescale.com>
+ * Initial author: Xianghua Xiao <x.xiao@freescale.com>
+ *
+ * Copyright 2006 Freescale Semiconductor Inc.
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#include <linux/config.h>
+#include <linux/stddef.h>
+#include <linux/kernel.h>
+#include <linux/pci.h>
+#include <linux/kdev_t.h>
+#include <linux/delay.h>
+#include <linux/seq_file.h>
+#include <linux/root_dev.h>
+
+#include <asm/system.h>
+#include <asm/time.h>
+#include <asm/machdep.h>
+#include <asm/pci-bridge.h>
+#include <asm/mpc86xx.h>
+#include <asm/prom.h>
+#include <mm/mmu_decl.h>
+#include <asm/udbg.h>
+#include <asm/i8259.h>
+
+#include <asm/mpic.h>
+
+#include <sysdev/fsl_soc.h>
+
+#include "mpc86xx.h"
+
+#ifndef CONFIG_PCI
+unsigned long isa_io_base = 0;
+unsigned long isa_mem_base = 0;
+unsigned long pci_dram_offset = 0;
+#endif
+
+
+/*
+ * Internal interrupts are all Level Sensitive, and Positive Polarity
+ */
+
+static u_char mpc86xx_hpcn_openpic_initsenses[] __initdata = {
+        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal  0: Reserved */
+        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal  1: MCM */
+        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal  2: DDR DRAM */
+        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal  3: LBIU */
+        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal  4: DMA 0 */
+        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal  5: DMA 1 */
+        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal  6: DMA 2 */
+        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal  7: DMA 3 */
+        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal  8: PCIE1 */
+        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal  9: PCIE2 */
+        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 10: Reserved */
+        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 11: Reserved */
+        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 12: DUART2 */
+        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 13: TSEC 1 Transmit */
+        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 14: TSEC 1 Receive */
+        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 15: TSEC 3 transmit */
+        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 16: TSEC 3 receive */
+        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 17: TSEC 3 error */
+        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 18: TSEC 1 Receive/Transmit Error */
+        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 19: TSEC 2 Transmit */
+        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 20: TSEC 2 Receive */
+        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 21: TSEC 4 transmit */
+        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 22: TSEC 4 receive */
+        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 23: TSEC 4 error */
+        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 24: TSEC 2 Receive/Transmit Error */
+        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 25: Unused */
+        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 26: DUART1 */
+        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 27: I2C */
+        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 28: Performance Monitor */
+        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 29: Unused */
+        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 30: Unused */
+        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 31: Unused */
+        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 32: SRIO error/write-port unit */
+        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 33: SRIO outbound doorbell */
+        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 34: SRIO inbound doorbell */
+        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 35: Unused */
+        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 36: Unused */
+        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 37: SRIO outbound message unit 1 */
+        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 38: SRIO inbound message unit 1 */
+        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 39: SRIO outbound message unit 2 */
+        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 40: SRIO inbound message unit 2 */
+        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 41: Unused */
+        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 42: Unused */
+        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 43: Unused */
+        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 44: Unused */
+        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 45: Unused */
+        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 46: Unused */
+        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 47: Unused */
+        0x0,                                            /* External  0: */
+        0x0,                                            /* External  1: */
+        0x0,                                            /* External  2: */
+        0x0,                                            /* External  3: */
+        0x0,                                            /* External  4: */
+        0x0,                                            /* External  5: */
+        0x0,                                            /* External  6: */
+        0x0,                                            /* External  7: */
+        (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* External  8: Pixis FPGA */
+        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* External  9: ULI 8259 INTR Cascade */
+        (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* External 10: Quad ETH PHY */
+        0x0,                                            /* External 11: */
+        0x0,
+        0x0,
+        0x0,
+        0x0,
+};
+
+
+void __init
+mpc86xx_hpcn_init_irq(void)
+{
+        struct mpic *mpic1;
+        phys_addr_t openpic_paddr;
+
+        /* Determine the Physical Address of the OpenPIC regs */
+        openpic_paddr = get_immrbase() + MPC86xx_OPENPIC_OFFSET;
+
+        /* Alloc mpic structure and per isu has 16 INT entries. */
+        mpic1 = mpic_alloc(openpic_paddr,
+                        MPIC_PRIMARY | MPIC_WANTS_RESET | MPIC_BIG_ENDIAN,
+                        16, MPC86xx_OPENPIC_IRQ_OFFSET, 0, 250,
+                        mpc86xx_hpcn_openpic_initsenses,
+                        sizeof(mpc86xx_hpcn_openpic_initsenses),
+                        " MPIC     ");
+        BUG_ON(mpic1 == NULL);
+
+        /* 48 Internal Interrupts */
+        mpic_assign_isu(mpic1, 0, openpic_paddr + 0x10200);
+        mpic_assign_isu(mpic1, 1, openpic_paddr + 0x10400);
+        mpic_assign_isu(mpic1, 2, openpic_paddr + 0x10600);
+
+        /* 16 External interrupts */
+        mpic_assign_isu(mpic1, 3, openpic_paddr + 0x10000);
+
+        mpic_init(mpic1);
+
+#ifdef CONFIG_PCI
+        mpic_setup_cascade(MPC86xx_IRQ_EXT9, i8259_irq_cascade, NULL);
+        i8259_init(0, I8259_OFFSET);
+#endif
+}
+
+
+
+#ifdef CONFIG_PCI
+/*
+ * interrupt routing
+ */
+
+int
+mpc86xx_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
+{
+        static char pci_irq_table[][4] = {
+                /*
+                 *      PCI IDSEL/INTPIN->INTLINE
+                 *       A      B      C      D
+                 */
+                {PIRQA, PIRQB, PIRQC, PIRQD},   /* IDSEL 17 -- PCI Slot 1 */
+                {PIRQB, PIRQC, PIRQD, PIRQA},   /* IDSEL 18 -- PCI Slot 2 */
+                {0, 0, 0, 0},                   /* IDSEL 19 */
+                {0, 0, 0, 0},                   /* IDSEL 20 */
+                {0, 0, 0, 0},                   /* IDSEL 21 */
+                {0, 0, 0, 0},                   /* IDSEL 22 */
+                {0, 0, 0, 0},                   /* IDSEL 23 */
+                {0, 0, 0, 0},                   /* IDSEL 24 */
+                {0, 0, 0, 0},                   /* IDSEL 25 */
+                {PIRQD, PIRQA, PIRQB, PIRQC},   /* IDSEL 26 -- PCI Bridge*/
+                {PIRQC, 0, 0, 0},               /* IDSEL 27 -- LAN */
+                {PIRQE, PIRQF, PIRQH, PIRQ7},   /* IDSEL 28 -- USB 1.1 */
+                {PIRQE, PIRQF, PIRQG, 0},       /* IDSEL 29 -- Audio & Modem */
+                {PIRQH, 0, 0, 0},               /* IDSEL 30 -- LPC & PMU*/
+                {PIRQD, 0, 0, 0},               /* IDSEL 31 -- ATA */
+        };
+
+        const long min_idsel = 17, max_idsel = 31, irqs_per_slot = 4;
+        return PCI_IRQ_TABLE_LOOKUP + I8259_OFFSET;
+}
+
+
+int
+mpc86xx_exclude_device(u_char bus, u_char devfn)
+{
+#if !defined(CONFIG_PCI)
+        if (bus == 0 && PCI_SLOT(devfn) == 0)
+                return PCIBIOS_DEVICE_NOT_FOUND;
+#endif
+
+        return PCIBIOS_SUCCESSFUL;
+}
+#endif /* CONFIG_PCI */
+
+
+static void __init
+mpc86xx_hpcn_setup_arch(void)
+{
+        struct device_node *np;
+
+        if (ppc_md.progress)
+                ppc_md.progress("mpc86xx_hpcn_setup_arch()", 0);
+
+        np = of_find_node_by_type(NULL, "cpu");
+        if (np != 0) {
+                unsigned int *fp;
+
+                fp = (int *)get_property(np, "clock-frequency", NULL);
+                if (fp != 0)
+                        loops_per_jiffy = *fp / HZ;
+                else
+                        loops_per_jiffy = 50000000 / HZ;
+                of_node_put(np);
+        }
+
+#ifdef CONFIG_PCI
+        for (np = NULL; (np = of_find_node_by_type(np, "pci")) != NULL;)
+                add_bridge(np);
+
+        ppc_md.pci_swizzle = common_swizzle;
+        ppc_md.pci_map_irq = mpc86xx_map_irq;
+        ppc_md.pci_exclude_device = mpc86xx_exclude_device;
+#endif
+
+        printk("MPC86xx HPCN board from Freescale Semiconductor\n");
+
+#ifdef  CONFIG_ROOT_NFS
+        ROOT_DEV = Root_NFS;
+#else
+        ROOT_DEV = Root_HDA1;
+#endif
+
+#ifdef CONFIG_SMP
+        mpc86xx_smp_init();
+#endif
+}
+
+
+void
+mpc86xx_hpcn_show_cpuinfo(struct seq_file *m)
+{
+        struct device_node *root;
+        uint memsize = total_memory;
+        const char *model = "";
+        uint svid = mfspr(SPRN_SVR);
+
+        seq_printf(m, "Vendor\t\t: Freescale Semiconductor\n");
+
+        root = of_find_node_by_path("/");
+        if (root)
+                model = get_property(root, "model", NULL);
+        seq_printf(m, "Machine\t\t: %s\n", model);
+        of_node_put(root);
+
+        seq_printf(m, "SVR\t\t: 0x%x\n", svid);
+        seq_printf(m, "Memory\t\t: %d MB\n", memsize / (1024 * 1024));
+}
+
+
+/*
+ * Called very early, device-tree isn't unflattened
+ */
+static int __init mpc86xx_hpcn_probe(void)
+{
+        unsigned long root = of_get_flat_dt_root();
+
+        if (of_flat_dt_is_compatible(root, "mpc86xx"))
+                return 1;       /* Looks good */
+
+        return 0;
+}
+
+
+void
+mpc86xx_restart(char *cmd)
+{
+        void __iomem *rstcr;
+
+        rstcr = ioremap(get_immrbase() + MPC86XX_RSTCR_OFFSET, 0x100);
+
+        local_irq_disable();
+
+        /* Assert reset request to Reset Control Register */
+        out_be32(rstcr, 0x2);
+
+        /* not reached */
+}
+
+
+long __init
+mpc86xx_time_init(void)
+{
+        unsigned int temp;
+
+        /* Set the time base to zero */
+        mtspr(SPRN_TBWL, 0);
+        mtspr(SPRN_TBWU, 0);
+
+        temp = mfspr(SPRN_HID0);
+        temp |= HID0_TBEN;
+        mtspr(SPRN_HID0, temp);
+        asm volatile("isync");
+
+        return 0;
+}
+
+
+define_machine(mpc86xx_hpcn) {
+        .name                   = "MPC86xx HPCN",
+        .probe                  = mpc86xx_hpcn_probe,
+        .setup_arch             = mpc86xx_hpcn_setup_arch,
+        .init_IRQ               = mpc86xx_hpcn_init_irq,
+        .show_cpuinfo           = mpc86xx_hpcn_show_cpuinfo,
+        .get_irq                = mpic_get_irq,
+        .restart                = mpc86xx_restart,
+        .time_init              = mpc86xx_time_init,
+        .calibrate_decr         = generic_calibrate_decr,
+        .progress               = udbg_progress,
+};
diff --git a/arch/powerpc/platforms/86xx/mpc86xx_pcie.c b/arch/powerpc/platforms/86xx/mpc86xx_pcie.c
new file mode 100644
index 000000000000..a2f4f730213e
--- /dev/null
+++ b/arch/powerpc/platforms/86xx/mpc86xx_pcie.c
@@ -0,0 +1,173 @@
+/*
+ * Support for indirect PCI bridges.
+ *
+ * Copyright (C) 1998 Gabriel Paubert.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ *
+ * "Temporary" MPC8548 Errata file -
+ * The standard indirect_pci code should work with future silicon versions.
+ */
+
+#include <linux/kernel.h>
+#include <linux/pci.h>
+#include <linux/delay.h>
+#include <linux/string.h>
+#include <linux/init.h>
+#include <linux/bootmem.h>
+
+#include <asm/io.h>
+#include <asm/prom.h>
+#include <asm/pci-bridge.h>
+#include <asm/machdep.h>
+
+#include "mpc86xx.h"
+
+#define PCI_CFG_OUT out_be32
+
+/* ERRATA PCI-Ex 14 PCIE Controller timeout */
+#define PCIE_FIX                out_be32(hose->cfg_addr+0x4, 0x0400ffff)
+
+
+static int
+indirect_read_config_pcie(struct pci_bus *bus, unsigned int devfn, int offset,
+                     int len, u32 *val)
+{
+        struct pci_controller *hose = bus->sysdata;
+        volatile void __iomem *cfg_data;
+        u32 temp;
+
+        if (ppc_md.pci_exclude_device)
+                if (ppc_md.pci_exclude_device(bus->number, devfn))
+                        return PCIBIOS_DEVICE_NOT_FOUND;
+
+        /* Possible artifact of CDCpp50937 needs further investigation */
+        if (devfn != 0x0 && bus->number == 0xff)
+                return PCIBIOS_DEVICE_NOT_FOUND;
+
+        PCIE_FIX;
+        if (bus->number == 0xff) {
+                PCI_CFG_OUT(hose->cfg_addr,
+                            (0x80000000 | ((offset & 0xf00) << 16) |
+                             ((bus->number - hose->bus_offset) << 16)
+                             | (devfn << 8) | ((offset & 0xfc) )));
+        } else {
+                PCI_CFG_OUT(hose->cfg_addr,
+                            (0x80000001 | ((offset & 0xf00) << 16) |
+                             ((bus->number - hose->bus_offset) << 16)
+                             | (devfn << 8) | ((offset & 0xfc) )));
+        }
+
+        /*
+         * Note: the caller has already checked that offset is
+         * suitably aligned and that len is 1, 2 or 4.
+         */
+        /* ERRATA PCI-Ex 12 - Configuration Address/Data Alignment */
+        cfg_data = hose->cfg_data;
+        PCIE_FIX;
+        temp = in_le32(cfg_data);
+        switch (len) {
+        case 1:
+                *val = (temp >> (((offset & 3))*8)) & 0xff;
+                break;
+        case 2:
+                *val = (temp >> (((offset & 3))*8)) & 0xffff;
+                break;
+        default:
+                *val = temp;
+                break;
+        }
+        return PCIBIOS_SUCCESSFUL;
+}
+
+static int
+indirect_write_config_pcie(struct pci_bus *bus, unsigned int devfn, int offset,
+                      int len, u32 val)
+{
+        struct pci_controller *hose = bus->sysdata;
+        volatile void __iomem *cfg_data;
+        u32 temp;
+
+        if (ppc_md.pci_exclude_device)
+                if (ppc_md.pci_exclude_device(bus->number, devfn))
+                        return PCIBIOS_DEVICE_NOT_FOUND;
+
+        /* Possible artifact of CDCpp50937 needs further investigation */
+        if (devfn != 0x0 && bus->number == 0xff)
+                return PCIBIOS_DEVICE_NOT_FOUND;
+
+        PCIE_FIX;
+        if (bus->number == 0xff) {
+                PCI_CFG_OUT(hose->cfg_addr,
+                            (0x80000000 | ((offset & 0xf00) << 16) |
+                             ((bus->number - hose->bus_offset) << 16)
+                             | (devfn << 8) | ((offset & 0xfc) )));
+        } else {
+                PCI_CFG_OUT(hose->cfg_addr,
+                            (0x80000001 | ((offset & 0xf00) << 16) |
+                             ((bus->number - hose->bus_offset) << 16)
+                             | (devfn << 8) | ((offset & 0xfc) )));
+        }
+
+        /*
+         * Note: the caller has already checked that offset is
+         * suitably aligned and that len is 1, 2 or 4.
+         */
+        /* ERRATA PCI-Ex 12 - Configuration Address/Data Alignment */
+        cfg_data = hose->cfg_data;
+        switch (len) {
+        case 1:
+                PCIE_FIX;
+                temp = in_le32(cfg_data);
+                temp = (temp & ~(0xff << ((offset & 3) * 8))) |
+                        (val << ((offset & 3) * 8));
+                PCIE_FIX;
+                out_le32(cfg_data, temp);
+                break;
+        case 2:
+                PCIE_FIX;
+                temp = in_le32(cfg_data);
+                temp = (temp & ~(0xffff << ((offset & 3) * 8)));
+                temp |= (val << ((offset & 3) * 8)) ;
+                PCIE_FIX;
+                out_le32(cfg_data, temp);
+                break;
+        default:
+                PCIE_FIX;
+                out_le32(cfg_data, val);
+                break;
+        }
+        PCIE_FIX;
+        return PCIBIOS_SUCCESSFUL;
+}
+
+static struct pci_ops indirect_pcie_ops = {
+        indirect_read_config_pcie,
+        indirect_write_config_pcie
+};
+
+void __init
+setup_indirect_pcie_nomap(struct pci_controller* hose, void __iomem * cfg_addr,
+        void __iomem * cfg_data)
+{
+        hose->cfg_addr = cfg_addr;
+        hose->cfg_data = cfg_data;
+        hose->ops = &indirect_pcie_ops;
+}
+
+void __init
+setup_indirect_pcie(struct pci_controller* hose, u32 cfg_addr, u32 cfg_data)
+{
+        unsigned long base = cfg_addr & PAGE_MASK;
+        void __iomem *mbase, *addr, *data;
+
+        mbase = ioremap(base, PAGE_SIZE);
+        addr = mbase + (cfg_addr & ~PAGE_MASK);
+        if ((cfg_data & PAGE_MASK) != base)
+                mbase = ioremap(cfg_data & PAGE_MASK, PAGE_SIZE);
+        data = mbase + (cfg_data & ~PAGE_MASK);
+        setup_indirect_pcie_nomap(hose, addr, data);
+}
diff --git a/arch/powerpc/platforms/86xx/mpc86xx_smp.c b/arch/powerpc/platforms/86xx/mpc86xx_smp.c
new file mode 100644
index 000000000000..944ec4b71416
--- /dev/null
+++ b/arch/powerpc/platforms/86xx/mpc86xx_smp.c
@@ -0,0 +1,117 @@
+/*
+ * Author: Xianghua Xiao <x.xiao@freescale.com>
+ *         Zhang Wei <wei.zhang@freescale.com>
+ *
+ * Copyright 2006 Freescale Semiconductor Inc.
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#include <linux/config.h>
+#include <linux/stddef.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/delay.h>
+
+#include <asm/pgtable.h>
+#include <asm/page.h>
+#include <asm/pci-bridge.h>
+#include <asm-powerpc/mpic.h>
+#include <asm/mpc86xx.h>
+#include <asm/cacheflush.h>
+
+#include <sysdev/fsl_soc.h>
+
+#include "mpc86xx.h"
+
+extern void __secondary_start_mpc86xx(void);
+extern unsigned long __secondary_hold_acknowledge;
+
+
+static void __init
+smp_86xx_release_core(int nr)
+{
+        void *mcm_vaddr;
+        unsigned long vaddr, pcr;
+
+        if (nr < 0 || nr >= NR_CPUS)
+                return;
+
+        /*
+         * Startup Core #nr.
+         */
+        mcm_vaddr = ioremap(get_immrbase() + MPC86xx_MCM_OFFSET,
+                            MPC86xx_MCM_SIZE);
+        vaddr = (unsigned long)mcm_vaddr +  MCM_PORT_CONFIG_OFFSET;
+        pcr = in_be32((volatile unsigned *)vaddr);
+        pcr |= 1 << (nr + 24);
+        out_be32((volatile unsigned *)vaddr, pcr);
+}
+
+
+static void __init
+smp_86xx_kick_cpu(int nr)
+{
+        unsigned int save_vector;
+        unsigned long target, flags;
+        int n = 0;
+        volatile unsigned int *vector
+                 = (volatile unsigned int *)(KERNELBASE + 0x100);
+
+        if (nr < 0 || nr >= NR_CPUS)
+                return;
+
+        pr_debug("smp_86xx_kick_cpu: kick CPU #%d\n", nr);
+
+        local_irq_save(flags);
+        local_irq_disable();
+
+        /* Save reset vector */
+        save_vector = *vector;
+
+        /* Setup fake reset vector to call __secondary_start_mpc86xx. */
+        target = (unsigned long) __secondary_start_mpc86xx;
+        create_branch((unsigned long)vector, target, BRANCH_SET_LINK);
+
+        /* Kick that CPU */
+        smp_86xx_release_core(nr);
+
+        /* Wait a bit for the CPU to take the exception. */
+        while ((__secondary_hold_acknowledge != nr) && (n++, n < 1000))
+                mdelay(1);
+
+        /* Restore the exception vector */
+        *vector = save_vector;
+        flush_icache_range((unsigned long) vector, (unsigned long) vector + 4);
+
+        local_irq_restore(flags);
+
+        pr_debug("wait CPU #%d for %d msecs.\n", nr, n);
+}
+
+
+static void __init
+smp_86xx_setup_cpu(int cpu_nr)
+{
+        mpic_setup_this_cpu();
+}
+
+
+struct smp_ops_t smp_86xx_ops = {
+        .message_pass = smp_mpic_message_pass,
+        .probe = smp_mpic_probe,
+        .kick_cpu = smp_86xx_kick_cpu,
+        .setup_cpu = smp_86xx_setup_cpu,
+        .take_timebase = smp_generic_take_timebase,
+        .give_timebase = smp_generic_give_timebase,
+};
+
+
+void __init
+mpc86xx_smp_init(void)
+{
+        smp_ops = &smp_86xx_ops;
+}
diff --git a/arch/powerpc/platforms/86xx/pci.c b/arch/powerpc/platforms/86xx/pci.c
new file mode 100644
index 000000000000..5180df7c75bc
--- /dev/null
+++ b/arch/powerpc/platforms/86xx/pci.c
@@ -0,0 +1,325 @@
+/*
+ * MPC86XX pci setup code
+ *
+ * Recode: ZHANG WEI <wei.zhang@freescale.com>
+ * Initial author: Xianghua Xiao <x.xiao@freescale.com>
+ *
+ * Copyright 2006 Freescale Semiconductor Inc.
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#include <linux/config.h>
+#include <linux/types.h>
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/pci.h>
+#include <linux/serial.h>
+
+#include <asm/system.h>
+#include <asm/atomic.h>
+#include <asm/io.h>
+#include <asm/prom.h>
+#include <asm/immap_86xx.h>
+#include <asm/pci-bridge.h>
+#include <sysdev/fsl_soc.h>
+
+#include "mpc86xx.h"
+
+#undef DEBUG
+
+#ifdef DEBUG
+#define DBG(fmt, args...) printk(KERN_ERR "%s: " fmt, __FUNCTION__, ## args)
+#else
+#define DBG(fmt, args...)
+#endif
+
+struct pcie_outbound_window_regs {
+        uint    pexotar;               /* 0x.0 - PCI Express outbound translation address register */
+        uint    pexotear;              /* 0x.4 - PCI Express outbound translation extended address register */
+        uint    pexowbar;              /* 0x.8 - PCI Express outbound window base address register */
+        char    res1[4];
+        uint    pexowar;               /* 0x.10 - PCI Express outbound window attributes register */
+        char    res2[12];
+};
+
+struct pcie_inbound_window_regs {
+        uint    pexitar;               /* 0x.0 - PCI Express inbound translation address register */
+        char    res1[4];
+        uint    pexiwbar;              /* 0x.8 - PCI Express inbound window base address register */
+        uint    pexiwbear;             /* 0x.c - PCI Express inbound window base extended address register */
+        uint    pexiwar;               /* 0x.10 - PCI Express inbound window attributes register */
+        char    res2[12];
+};
+
+static void __init setup_pcie_atmu(struct pci_controller *hose, struct resource *rsrc)
+{
+        volatile struct ccsr_pex *pcie;
+        volatile struct pcie_outbound_window_regs *pcieow;
+        volatile struct pcie_inbound_window_regs *pcieiw;
+        int i = 0;
+
+        DBG("PCIE memory map start 0x%x, size 0x%x\n", rsrc->start,
+                        rsrc->end - rsrc->start + 1);
+        pcie = ioremap(rsrc->start, rsrc->end - rsrc->start + 1);
+
+        /* Disable all windows (except pexowar0 since its ignored) */
+        pcie->pexowar1 = 0;
+        pcie->pexowar2 = 0;
+        pcie->pexowar3 = 0;
+        pcie->pexowar4 = 0;
+        pcie->pexiwar1 = 0;
+        pcie->pexiwar2 = 0;
+        pcie->pexiwar3 = 0;
+
+        pcieow = (struct pcie_outbound_window_regs *)&pcie->pexotar1;
+        pcieiw = (struct pcie_inbound_window_regs *)&pcie->pexitar1;
+
+        /* Setup outbound MEM window */
+        for(i = 0; i < 3; i++)
+                if (hose->mem_resources[i].flags & IORESOURCE_MEM){
+                        DBG("PCIE MEM resource start 0x%08x, size 0x%08x.\n",
+                                hose->mem_resources[i].start,
+                                hose->mem_resources[i].end
+                                  - hose->mem_resources[i].start + 1);
+                        pcieow->pexotar = (hose->mem_resources[i].start) >> 12
+                                & 0x000fffff;
+                        pcieow->pexotear = 0;
+                        pcieow->pexowbar = (hose->mem_resources[i].start) >> 12
+                                & 0x000fffff;
+                        /* Enable, Mem R/W */
+                        pcieow->pexowar = 0x80044000 |
+                                (__ilog2(hose->mem_resources[i].end
+                                         - hose->mem_resources[i].start + 1)
+                                 - 1);
+                        pcieow++;
+                }
+
+        /* Setup outbound IO window */
+        if (hose->io_resource.flags & IORESOURCE_IO){
+                DBG("PCIE IO resource start 0x%08x, size 0x%08x, phy base 0x%08x.\n",
+                        hose->io_resource.start,
+                        hose->io_resource.end - hose->io_resource.start + 1,
+                        hose->io_base_phys);
+                pcieow->pexotar = (hose->io_resource.start) >> 12 & 0x000fffff;
+                pcieow->pexotear = 0;
+                pcieow->pexowbar = (hose->io_base_phys) >> 12 & 0x000fffff;
+                /* Enable, IO R/W */
+                pcieow->pexowar = 0x80088000 | (__ilog2(hose->io_resource.end
+                                        - hose->io_resource.start + 1) - 1);
+        }
+
+        /* Setup 2G inbound Memory Window @ 0 */
+        pcieiw->pexitar = 0x00000000;
+        pcieiw->pexiwbar = 0x00000000;
+        /* Enable, Prefetch, Local Mem, Snoop R/W, 2G */
+        pcieiw->pexiwar = 0xa0f5501e;
+}
+
+static void __init
+mpc86xx_setup_pcie(struct pci_controller *hose, u32 pcie_offset, u32 pcie_size)
+{
+        volatile struct ccsr_pex *pcie;
+        u16 cmd;
+        unsigned int temps;
+
+        DBG("PCIE host controller register offset 0x%08x, size 0x%08x.\n",
+                        pcie_offset, pcie_size);
+
+        pcie = ioremap(pcie_offset, pcie_size);
+
+        early_read_config_word(hose, 0, 0, PCI_COMMAND, &cmd);
+        cmd |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY
+            | PCI_COMMAND_IO;
+        early_write_config_word(hose, 0, 0, PCI_COMMAND, cmd);
+
+        early_write_config_byte(hose, 0, 0, PCI_LATENCY_TIMER, 0x80);
+
+        /* PCIE Bus, Fix the MPC8641D host bridge's location to bus 0xFF. */
+        early_read_config_dword(hose, 0, 0, PCI_PRIMARY_BUS, &temps);
+        temps = (temps & 0xff000000) | (0xff) | (0x0 << 8) | (0xfe << 16);
+        early_write_config_dword(hose, 0, 0, PCI_PRIMARY_BUS, temps);
+}
+
+int __init add_bridge(struct device_node *dev)
+{
+        int len;
+        struct pci_controller *hose;
+        struct resource rsrc;
+        int *bus_range;
+        int has_address = 0;
+        int primary = 0;
+
+        DBG("Adding PCIE host bridge %s\n", dev->full_name);
+
+        /* Fetch host bridge registers address */
+        has_address = (of_address_to_resource(dev, 0, &rsrc) == 0);
+
+        /* Get bus range if any */
+        bus_range = (int *) get_property(dev, "bus-range", &len);
+        if (bus_range == NULL || len < 2 * sizeof(int))
+                printk(KERN_WARNING "Can't get bus-range for %s, assume"
+                       " bus 0\n", dev->full_name);
+
+        hose = pcibios_alloc_controller();
+        if (!hose)
+                return -ENOMEM;
+        hose->arch_data = dev;
+        hose->set_cfg_type = 1;
+
+        /* last_busno = 0xfe cause by MPC8641 PCIE bug */
+        hose->first_busno = bus_range ? bus_range[0] : 0x0;
+        hose->last_busno = bus_range ? bus_range[1] : 0xfe;
+
+        setup_indirect_pcie(hose, rsrc.start, rsrc.start + 0x4);
+
+        /* Setup the PCIE host controller. */
+        mpc86xx_setup_pcie(hose, rsrc.start, rsrc.end - rsrc.start + 1);
+
+        if ((rsrc.start & 0xfffff) == 0x8000)
+                primary = 1;
+
+        printk(KERN_INFO "Found MPC86xx PCIE host bridge at 0x%08lx. "
+               "Firmware bus number: %d->%d\n",
+                rsrc.start, hose->first_busno, hose->last_busno);
+
+        DBG(" ->Hose at 0x%p, cfg_addr=0x%p,cfg_data=0x%p\n",
+                hose, hose->cfg_addr, hose->cfg_data);
+
+        /* Interpret the "ranges" property */
+        /* This also maps the I/O region and sets isa_io/mem_base */
+        pci_process_bridge_OF_ranges(hose, dev, primary);
+
+        /* Setup PEX window registers */
+        setup_pcie_atmu(hose, &rsrc);
+
+        return 0;
+}
+
+static void __devinit quirk_ali1575(struct pci_dev *dev)
+{
+        unsigned short temp;
+
+        /*
+         * ALI1575 interrupts route table setup:
+         *
+         * IRQ pin   IRQ#
+         * PIRQA ---- 3
+         * PIRQB ---- 4
+         * PIRQC ---- 5
+         * PIRQD ---- 6
+         * PIRQE ---- 9
+         * PIRQF ---- 10
+         * PIRQG ---- 11
+         * PIRQH ---- 12
+         *
+         * interrupts for PCI slot0 -- PIRQA / PIRQB / PIRQC / PIRQD
+         *                PCI slot1 -- PIRQB / PIRQC / PIRQD / PIRQA
+         */
+        pci_write_config_dword(dev, 0x48, 0xb9317542);
+
+        /* USB 1.1 OHCI controller 1, interrupt: PIRQE */
+        pci_write_config_byte(dev, 0x86, 0x0c);
+
+        /* USB 1.1 OHCI controller 2, interrupt: PIRQF */
+        pci_write_config_byte(dev, 0x87, 0x0d);
+
+        /* USB 1.1 OHCI controller 3, interrupt: PIRQH */
+        pci_write_config_byte(dev, 0x88, 0x0f);
+
+        /* USB 2.0 controller, interrupt: PIRQ7 */
+        pci_write_config_byte(dev, 0x74, 0x06);
+
+        /* Audio controller, interrupt: PIRQE */
+        pci_write_config_byte(dev, 0x8a, 0x0c);
+
+        /* Modem controller, interrupt: PIRQF */
+        pci_write_config_byte(dev, 0x8b, 0x0d);
+
+        /* HD audio controller, interrupt: PIRQG */
+        pci_write_config_byte(dev, 0x8c, 0x0e);
+
+        /* Serial ATA interrupt: PIRQD */
+        pci_write_config_byte(dev, 0x8d, 0x0b);
+
+        /* SMB interrupt: PIRQH */
+        pci_write_config_byte(dev, 0x8e, 0x0f);
+
+        /* PMU ACPI SCI interrupt: PIRQH */
+        pci_write_config_byte(dev, 0x8f, 0x0f);
+
+        /* Primary PATA IDE IRQ: 14
+         * Secondary PATA IDE IRQ: 15
+         */
+        pci_write_config_byte(dev, 0x44, 0x3d);
+        pci_write_config_byte(dev, 0x75, 0x0f);
+
+        /* Set IRQ14 and IRQ15 to legacy IRQs */
+        pci_read_config_word(dev, 0x46, &temp);
+        temp |= 0xc000;
+        pci_write_config_word(dev, 0x46, temp);
+
+        /* Set i8259 interrupt trigger
+         * IRQ 3:  Level
+         * IRQ 4:  Level
+         * IRQ 5:  Level
+         * IRQ 6:  Level
+         * IRQ 7:  Level
+         * IRQ 9:  Level
+         * IRQ 10: Level
+         * IRQ 11: Level
+         * IRQ 12: Level
+         * IRQ 14: Edge
+         * IRQ 15: Edge
+         */
+        outb(0xfa, 0x4d0);
+        outb(0x1e, 0x4d1);
+}
+
+static void __devinit quirk_uli5288(struct pci_dev *dev)
+{
+        unsigned char c;
+
+        pci_read_config_byte(dev,0x83,&c);
+        c |= 0x80;
+        pci_write_config_byte(dev, 0x83, c);
+
+        pci_write_config_byte(dev, 0x09, 0x01);
+        pci_write_config_byte(dev, 0x0a, 0x06);
+
+        pci_read_config_byte(dev,0x83,&c);
+        c &= 0x7f;
+        pci_write_config_byte(dev, 0x83, c);
+
+        pci_read_config_byte(dev,0x84,&c);
+        c |= 0x01;
+        pci_write_config_byte(dev, 0x84, c);
+}
+
+static void __devinit quirk_uli5229(struct pci_dev *dev)
+{
+        unsigned short temp;
+        pci_write_config_word(dev, 0x04, 0x0405);
+        pci_read_config_word(dev, 0x4a, &temp);
+        temp |= 0x1000;
+        pci_write_config_word(dev, 0x4a, temp);
+}
+
+static void __devinit early_uli5249(struct pci_dev *dev)
+{
+        unsigned char temp;
+        pci_write_config_word(dev, 0x04, 0x0007);
+        pci_read_config_byte(dev, 0x7c, &temp);
+        pci_write_config_byte(dev, 0x7c, 0x80);
+        pci_write_config_byte(dev, 0x09, 0x01);
+        pci_write_config_byte(dev, 0x7c, temp);
+        dev->class |= 0x1;
+}
+
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, 0x1575, quirk_ali1575);
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, 0x5288, quirk_uli5288);
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, 0x5229, quirk_uli5229);
+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AL, 0x5249, early_uli5249);