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-rw-r--r--arch/powerpc/platforms/85xx/Kconfig1
-rw-r--r--arch/powerpc/platforms/85xx/mpc8544_ds.c214
2 files changed, 16 insertions, 199 deletions
diff --git a/arch/powerpc/platforms/85xx/Kconfig b/arch/powerpc/platforms/85xx/Kconfig
index f58184086c8c..f620171ad6b1 100644
--- a/arch/powerpc/platforms/85xx/Kconfig
+++ b/arch/powerpc/platforms/85xx/Kconfig
@@ -33,6 +33,7 @@ config MPC8544_DS
33 bool "Freescale MPC8544 DS" 33 bool "Freescale MPC8544 DS"
34 select PPC_I8259 34 select PPC_I8259
35 select DEFAULT_UIMAGE 35 select DEFAULT_UIMAGE
36 select FSL_ULI1575
36 help 37 help
37 This option enables support for the MPC8544 DS board 38 This option enables support for the MPC8544 DS board
38 39
diff --git a/arch/powerpc/platforms/85xx/mpc8544_ds.c b/arch/powerpc/platforms/85xx/mpc8544_ds.c
index 4905f6f8903b..0f834d8be444 100644
--- a/arch/powerpc/platforms/85xx/mpc8544_ds.c
+++ b/arch/powerpc/platforms/85xx/mpc8544_ds.c
@@ -114,211 +114,25 @@ void __init mpc8544_ds_pic_init(void)
114} 114}
115 115
116#ifdef CONFIG_PCI 116#ifdef CONFIG_PCI
117enum pirq { PIRQA = 8, PIRQB, PIRQC, PIRQD, PIRQE, PIRQF, PIRQG, PIRQH }; 117extern int uses_fsl_uli_m1575;
118extern int uli_exclude_device(struct pci_controller *hose,
119 u_char bus, u_char devfn);
118 120
119/* 121static int mpc85xx_exclude_device(struct pci_controller *hose,
120 * Value in table -- IRQ number 122 u_char bus, u_char devfn)
121 */
122const unsigned char uli1575_irq_route_table[16] = {
123 0, /* 0: Reserved */
124 0x8,
125 0, /* 2: Reserved */
126 0x2,
127 0x4,
128 0x5,
129 0x7,
130 0x6,
131 0, /* 8: Reserved */
132 0x1,
133 0x3,
134 0x9,
135 0xb,
136 0, /* 13: Reserved */
137 0xd,
138 0xf,
139};
140
141static int __devinit
142get_pci_irq_from_of(struct pci_controller *hose, int slot, int pin)
143{
144 struct of_irq oirq;
145 u32 laddr[3];
146 struct device_node *hosenode = hose ? hose->arch_data : NULL;
147
148 if (!hosenode)
149 return -EINVAL;
150
151 laddr[0] = (hose->first_busno << 16) | (PCI_DEVFN(slot, 0) << 8);
152 laddr[1] = laddr[2] = 0;
153 of_irq_map_raw(hosenode, &pin, 1, laddr, &oirq);
154 DBG("mpc8544_ds: pci irq addr %x, slot %d, pin %d, irq %d\n",
155 laddr[0], slot, pin, oirq.specifier[0]);
156 return oirq.specifier[0];
157}
158
159/*8259*/
160static void __devinit quirk_uli1575(struct pci_dev *dev)
161{
162 unsigned short temp;
163 struct pci_controller *hose = pci_bus_to_host(dev->bus);
164 unsigned char irq2pin[16];
165 unsigned long pirq_map_word = 0;
166 u32 irq;
167 int i;
168
169 /*
170 * ULI1575 interrupts route setup
171 */
172 memset(irq2pin, 0, 16); /* Initialize default value 0 */
173
174 irq2pin[6]=PIRQA+3; /* enabled mapping for IRQ6 to PIRQD, used by SATA */
175
176 /*
177 * PIRQE -> PIRQF mapping set manually
178 *
179 * IRQ pin IRQ#
180 * PIRQE ---- 9
181 * PIRQF ---- 10
182 * PIRQG ---- 11
183 * PIRQH ---- 12
184 */
185 for (i = 0; i < 4; i++)
186 irq2pin[i + 9] = PIRQE + i;
187
188 /* Set IRQ-PIRQ Mapping to ULI1575 */
189 for (i = 0; i < 16; i++)
190 if (irq2pin[i])
191 pirq_map_word |= (uli1575_irq_route_table[i] & 0xf)
192 << ((irq2pin[i] - PIRQA) * 4);
193
194 pirq_map_word |= 1<<26; /* disable INTx in EP mode*/
195
196 /* ULI1575 IRQ mapping conf register default value is 0xb9317542 */
197 DBG("Setup ULI1575 IRQ mapping configuration register value = 0x%x\n",
198 (int)pirq_map_word);
199 pci_write_config_dword(dev, 0x48, pirq_map_word);
200
201#define ULI1575_SET_DEV_IRQ(slot, pin, reg) \
202 do { \
203 int irq; \
204 irq = get_pci_irq_from_of(hose, slot, pin); \
205 if (irq > 0 && irq < 16) \
206 pci_write_config_byte(dev, reg, irq2pin[irq]); \
207 else \
208 printk(KERN_WARNING "ULI1575 device" \
209 "(slot %d, pin %d) irq %d is invalid.\n", \
210 slot, pin, irq); \
211 } while(0)
212
213 /* USB 1.1 OHCI controller 1, slot 28, pin 1 */
214 ULI1575_SET_DEV_IRQ(28, 1, 0x86);
215
216 /* USB 1.1 OHCI controller 2, slot 28, pin 2 */
217 ULI1575_SET_DEV_IRQ(28, 2, 0x87);
218
219 /* USB 1.1 OHCI controller 3, slot 28, pin 3 */
220 ULI1575_SET_DEV_IRQ(28, 3, 0x88);
221
222 /* USB 2.0 controller, slot 28, pin 4 */
223 irq = get_pci_irq_from_of(hose, 28, 4);
224 if (irq >= 0 && irq <= 15)
225 pci_write_config_dword(dev, 0x74, uli1575_irq_route_table[irq]);
226
227 /* Audio controller, slot 29, pin 1 */
228 ULI1575_SET_DEV_IRQ(29, 1, 0x8a);
229
230 /* Modem controller, slot 29, pin 2 */
231 ULI1575_SET_DEV_IRQ(29, 2, 0x8b);
232
233 /* HD audio controller, slot 29, pin 3 */
234 ULI1575_SET_DEV_IRQ(29, 3, 0x8c);
235
236 /* SMB interrupt: slot 30, pin 1 */
237 ULI1575_SET_DEV_IRQ(30, 1, 0x8e);
238
239 /* PMU ACPI SCI interrupt: slot 30, pin 2 */
240 ULI1575_SET_DEV_IRQ(30, 2, 0x8f);
241
242 /* Serial ATA interrupt: slot 31, pin 1 */
243 ULI1575_SET_DEV_IRQ(31, 1, 0x8d);
244
245 /* Primary PATA IDE IRQ: 14
246 * Secondary PATA IDE IRQ: 15
247 */
248 pci_write_config_byte(dev, 0x44, 0x30 | uli1575_irq_route_table[14]);
249 pci_write_config_byte(dev, 0x75, uli1575_irq_route_table[15]);
250
251 /* Set IRQ14 and IRQ15 to legacy IRQs */
252 pci_read_config_word(dev, 0x46, &temp);
253 temp |= 0xc000;
254 pci_write_config_word(dev, 0x46, temp);
255
256 /* Set i8259 interrupt trigger
257 * IRQ 3: Level
258 * IRQ 4: Level
259 * IRQ 5: Level
260 * IRQ 6: Level
261 * IRQ 7: Level
262 * IRQ 9: Level
263 * IRQ 10: Level
264 * IRQ 11: Level
265 * IRQ 12: Level
266 * IRQ 14: Edge
267 * IRQ 15: Edge
268 */
269 outb(0xfa, 0x4d0);
270 outb(0x1e, 0x4d1);
271
272#undef ULI1575_SET_DEV_IRQ
273}
274
275/* SATA */
276static void __devinit quirk_uli5288(struct pci_dev *dev)
277{ 123{
278 unsigned char c; 124 struct device_node* node;
279 125 struct resource rsrc;
280 pci_read_config_byte(dev, 0x83, &c);
281 c |= 0x80; /* read/write lock */
282 pci_write_config_byte(dev, 0x83, c);
283
284 pci_write_config_byte(dev, 0x09, 0x01); /* Base class code: storage */
285 pci_write_config_byte(dev, 0x0a, 0x06); /* IDE disk */
286 126
287 pci_read_config_byte(dev, 0x83, &c); 127 node = (struct device_node *)hose->arch_data;
288 c &= 0x7f; 128 of_address_to_resource(node, 0, &rsrc);
289 pci_write_config_byte(dev, 0x83, c);
290
291 pci_read_config_byte(dev, 0x84, &c);
292 c |= 0x01; /* emulated PATA mode enabled */
293 pci_write_config_byte(dev, 0x84, c);
294}
295 129
296/* PATA */ 130 if ((rsrc.start & 0xfffff) == 0xb000) {
297static void __devinit quirk_uli5229(struct pci_dev *dev) 131 return uli_exclude_device(hose, bus, devfn);
298{ 132 }
299 unsigned short temp;
300 pci_write_config_word(dev, 0x04, 0x0405); /* MEM IO MSI */
301 pci_read_config_word(dev, 0x4a, &temp);
302 temp |= 0x1000; /* Enable Native IRQ 14/15 */
303 pci_write_config_word(dev, 0x4a, temp);
304}
305 133
306/*Bridge*/ 134 return PCIBIOS_SUCCESSFUL;
307static void __devinit early_uli5249(struct pci_dev *dev)
308{
309 unsigned char temp;
310 pci_write_config_word(dev, 0x04, 0x0007); /* mem access */
311 pci_read_config_byte(dev, 0x7c, &temp);
312 pci_write_config_byte(dev, 0x7c, 0x80); /* R/W lock control */
313 pci_write_config_byte(dev, 0x09, 0x01); /* set as pci-pci bridge */
314 pci_write_config_byte(dev, 0x7c, temp); /* restore pci bus debug control */
315 dev->class |= 0x1;
316} 135}
317
318DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, 0x1575, quirk_uli1575);
319DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, 0x5288, quirk_uli5288);
320DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, 0x5229, quirk_uli5229);
321DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AL, 0x5249, early_uli5249);
322#endif /* CONFIG_PCI */ 136#endif /* CONFIG_PCI */
323 137
324/* 138/*
@@ -342,6 +156,8 @@ static void __init mpc8544_ds_setup_arch(void)
342 else 156 else
343 fsl_add_bridge(np, 0); 157 fsl_add_bridge(np, 0);
344 } 158 }
159 uses_fsl_uli_m1575 = 1;
160 ppc_md.pci_exclude_device = mpc85xx_exclude_device;
345#endif 161#endif
346 162
347 printk("MPC8544 DS board from Freescale Semiconductor\n"); 163 printk("MPC8544 DS board from Freescale Semiconductor\n");
generated by cgit v1.2.2 (git 2.25.0) at 2025-03-07 21:55:36 -0500