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-rw-r--r--arch/powerpc/oprofile/Makefile2
-rw-r--r--arch/powerpc/oprofile/common.c3
-rw-r--r--arch/powerpc/oprofile/op_model_rs64.c222
3 files changed, 1 insertions, 226 deletions
diff --git a/arch/powerpc/oprofile/Makefile b/arch/powerpc/oprofile/Makefile
index 751ec7bd5018..cedbbeced632 100644
--- a/arch/powerpc/oprofile/Makefile
+++ b/arch/powerpc/oprofile/Makefile
@@ -14,6 +14,6 @@ oprofile-y := $(DRIVER_OBJS) common.o backtrace.o
14oprofile-$(CONFIG_OPROFILE_CELL) += op_model_cell.o \ 14oprofile-$(CONFIG_OPROFILE_CELL) += op_model_cell.o \
15 cell/spu_profiler.o cell/vma_map.o \ 15 cell/spu_profiler.o cell/vma_map.o \
16 cell/spu_task_sync.o 16 cell/spu_task_sync.o
17oprofile-$(CONFIG_PPC_BOOK3S_64) += op_model_rs64.o op_model_power4.o op_model_pa6t.o 17oprofile-$(CONFIG_PPC_BOOK3S_64) += op_model_power4.o op_model_pa6t.o
18oprofile-$(CONFIG_FSL_EMB_PERFMON) += op_model_fsl_emb.o 18oprofile-$(CONFIG_FSL_EMB_PERFMON) += op_model_fsl_emb.o
19oprofile-$(CONFIG_6xx) += op_model_7450.o 19oprofile-$(CONFIG_6xx) += op_model_7450.o
diff --git a/arch/powerpc/oprofile/common.c b/arch/powerpc/oprofile/common.c
index c77348c5d463..bf094c5a4bd9 100644
--- a/arch/powerpc/oprofile/common.c
+++ b/arch/powerpc/oprofile/common.c
@@ -205,9 +205,6 @@ int __init oprofile_arch_init(struct oprofile_operations *ops)
205 ops->sync_stop = model->sync_stop; 205 ops->sync_stop = model->sync_stop;
206 break; 206 break;
207#endif 207#endif
208 case PPC_OPROFILE_RS64:
209 model = &op_model_rs64;
210 break;
211 case PPC_OPROFILE_POWER4: 208 case PPC_OPROFILE_POWER4:
212 model = &op_model_power4; 209 model = &op_model_power4;
213 break; 210 break;
diff --git a/arch/powerpc/oprofile/op_model_rs64.c b/arch/powerpc/oprofile/op_model_rs64.c
deleted file mode 100644
index 7e5b8ed3a1b7..000000000000
--- a/arch/powerpc/oprofile/op_model_rs64.c
+++ /dev/null
@@ -1,222 +0,0 @@
1/*
2 * Copyright (C) 2004 Anton Blanchard <anton@au.ibm.com>, IBM
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version
7 * 2 of the License, or (at your option) any later version.
8 */
9
10#include <linux/oprofile.h>
11#include <linux/smp.h>
12#include <asm/ptrace.h>
13#include <asm/processor.h>
14#include <asm/cputable.h>
15#include <asm/oprofile_impl.h>
16
17#define dbg(args...)
18
19static void ctrl_write(unsigned int i, unsigned int val)
20{
21 unsigned int tmp = 0;
22 unsigned long shift = 0, mask = 0;
23
24 dbg("ctrl_write %d %x\n", i, val);
25
26 switch(i) {
27 case 0:
28 tmp = mfspr(SPRN_MMCR0);
29 shift = 6;
30 mask = 0x7F;
31 break;
32 case 1:
33 tmp = mfspr(SPRN_MMCR0);
34 shift = 0;
35 mask = 0x3F;
36 break;
37 case 2:
38 tmp = mfspr(SPRN_MMCR1);
39 shift = 31 - 4;
40 mask = 0x1F;
41 break;
42 case 3:
43 tmp = mfspr(SPRN_MMCR1);
44 shift = 31 - 9;
45 mask = 0x1F;
46 break;
47 case 4:
48 tmp = mfspr(SPRN_MMCR1);
49 shift = 31 - 14;
50 mask = 0x1F;
51 break;
52 case 5:
53 tmp = mfspr(SPRN_MMCR1);
54 shift = 31 - 19;
55 mask = 0x1F;
56 break;
57 case 6:
58 tmp = mfspr(SPRN_MMCR1);
59 shift = 31 - 24;
60 mask = 0x1F;
61 break;
62 case 7:
63 tmp = mfspr(SPRN_MMCR1);
64 shift = 31 - 28;
65 mask = 0xF;
66 break;
67 }
68
69 tmp = tmp & ~(mask << shift);
70 tmp |= val << shift;
71
72 switch(i) {
73 case 0:
74 case 1:
75 mtspr(SPRN_MMCR0, tmp);
76 break;
77 default:
78 mtspr(SPRN_MMCR1, tmp);
79 }
80
81 dbg("ctrl_write mmcr0 %lx mmcr1 %lx\n", mfspr(SPRN_MMCR0),
82 mfspr(SPRN_MMCR1));
83}
84
85static unsigned long reset_value[OP_MAX_COUNTER];
86
87static int num_counters;
88
89static int rs64_reg_setup(struct op_counter_config *ctr,
90 struct op_system_config *sys,
91 int num_ctrs)
92{
93 int i;
94
95 num_counters = num_ctrs;
96
97 for (i = 0; i < num_counters; ++i)
98 reset_value[i] = 0x80000000UL - ctr[i].count;
99
100 /* XXX setup user and kernel profiling */
101 return 0;
102}
103
104static int rs64_cpu_setup(struct op_counter_config *ctr)
105{
106 unsigned int mmcr0;
107
108 /* reset MMCR0 and set the freeze bit */
109 mmcr0 = MMCR0_FC;
110 mtspr(SPRN_MMCR0, mmcr0);
111
112 /* reset MMCR1, MMCRA */
113 mtspr(SPRN_MMCR1, 0);
114
115 if (cpu_has_feature(CPU_FTR_MMCRA))
116 mtspr(SPRN_MMCRA, 0);
117
118 mmcr0 |= MMCR0_FCM1|MMCR0_PMXE|MMCR0_FCECE;
119 /* Only applies to POWER3, but should be safe on RS64 */
120 mmcr0 |= MMCR0_PMC1CE|MMCR0_PMCjCE;
121 mtspr(SPRN_MMCR0, mmcr0);
122
123 dbg("setup on cpu %d, mmcr0 %lx\n", smp_processor_id(),
124 mfspr(SPRN_MMCR0));
125 dbg("setup on cpu %d, mmcr1 %lx\n", smp_processor_id(),
126 mfspr(SPRN_MMCR1));
127
128 return 0;
129}
130
131static int rs64_start(struct op_counter_config *ctr)
132{
133 int i;
134 unsigned int mmcr0;
135
136 /* set the PMM bit (see comment below) */
137 mtmsrd(mfmsr() | MSR_PMM);
138
139 for (i = 0; i < num_counters; ++i) {
140 if (ctr[i].enabled) {
141 classic_ctr_write(i, reset_value[i]);
142 ctrl_write(i, ctr[i].event);
143 } else {
144 classic_ctr_write(i, 0);
145 }
146 }
147
148 mmcr0 = mfspr(SPRN_MMCR0);
149
150 /*
151 * now clear the freeze bit, counting will not start until we
152 * rfid from this excetion, because only at that point will
153 * the PMM bit be cleared
154 */
155 mmcr0 &= ~MMCR0_FC;
156 mtspr(SPRN_MMCR0, mmcr0);
157
158 dbg("start on cpu %d, mmcr0 %x\n", smp_processor_id(), mmcr0);
159 return 0;
160}
161
162static void rs64_stop(void)
163{
164 unsigned int mmcr0;
165
166 /* freeze counters */
167 mmcr0 = mfspr(SPRN_MMCR0);
168 mmcr0 |= MMCR0_FC;
169 mtspr(SPRN_MMCR0, mmcr0);
170
171 dbg("stop on cpu %d, mmcr0 %x\n", smp_processor_id(), mmcr0);
172
173 mb();
174}
175
176static void rs64_handle_interrupt(struct pt_regs *regs,
177 struct op_counter_config *ctr)
178{
179 unsigned int mmcr0;
180 int is_kernel;
181 int val;
182 int i;
183 unsigned long pc = mfspr(SPRN_SIAR);
184
185 is_kernel = is_kernel_addr(pc);
186
187 /* set the PMM bit (see comment below) */
188 mtmsrd(mfmsr() | MSR_PMM);
189
190 for (i = 0; i < num_counters; ++i) {
191 val = classic_ctr_read(i);
192 if (val < 0) {
193 if (ctr[i].enabled) {
194 oprofile_add_ext_sample(pc, regs, i, is_kernel);
195 classic_ctr_write(i, reset_value[i]);
196 } else {
197 classic_ctr_write(i, 0);
198 }
199 }
200 }
201
202 mmcr0 = mfspr(SPRN_MMCR0);
203
204 /* reset the perfmon trigger */
205 mmcr0 |= MMCR0_PMXE;
206
207 /*
208 * now clear the freeze bit, counting will not start until we
209 * rfid from this exception, because only at that point will
210 * the PMM bit be cleared
211 */
212 mmcr0 &= ~MMCR0_FC;
213 mtspr(SPRN_MMCR0, mmcr0);
214}
215
216struct op_powerpc_model op_model_rs64 = {
217 .reg_setup = rs64_reg_setup,
218 .cpu_setup = rs64_cpu_setup,
219 .start = rs64_start,
220 .stop = rs64_stop,
221 .handle_interrupt = rs64_handle_interrupt,
222};
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-28 12:16:02 -0500