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-rw-r--r--arch/powerpc/oprofile/op_model_cell.c6
-rw-r--r--arch/powerpc/oprofile/op_model_power4.c2
2 files changed, 4 insertions, 4 deletions
diff --git a/arch/powerpc/oprofile/op_model_cell.c b/arch/powerpc/oprofile/op_model_cell.c
index c4d2b7167568..cb515cff745c 100644
--- a/arch/powerpc/oprofile/op_model_cell.c
+++ b/arch/powerpc/oprofile/op_model_cell.c
@@ -67,7 +67,7 @@
67 67
68#define MAX_SPU_COUNT 0xFFFFFF /* maximum 24 bit LFSR value */ 68#define MAX_SPU_COUNT 0xFFFFFF /* maximum 24 bit LFSR value */
69 69
70/* Minumum HW interval timer setting to send value to trace buffer is 10 cycle. 70/* Minimum HW interval timer setting to send value to trace buffer is 10 cycle.
71 * To configure counter to send value every N cycles set counter to 71 * To configure counter to send value every N cycles set counter to
72 * 2^32 - 1 - N. 72 * 2^32 - 1 - N.
73 */ 73 */
@@ -1470,7 +1470,7 @@ static int cell_global_start(struct op_counter_config *ctr)
1470 * trace buffer at the maximum rate possible. The trace buffer is configured 1470 * trace buffer at the maximum rate possible. The trace buffer is configured
1471 * to store the PCs, wrapping when it is full. The performance counter is 1471 * to store the PCs, wrapping when it is full. The performance counter is
1472 * initialized to the max hardware count minus the number of events, N, between 1472 * initialized to the max hardware count minus the number of events, N, between
1473 * samples. Once the N events have occured, a HW counter overflow occurs 1473 * samples. Once the N events have occurred, a HW counter overflow occurs
1474 * causing the generation of a HW counter interrupt which also stops the 1474 * causing the generation of a HW counter interrupt which also stops the
1475 * writing of the SPU PC values to the trace buffer. Hence the last PC 1475 * writing of the SPU PC values to the trace buffer. Hence the last PC
1476 * written to the trace buffer is the SPU PC that we want. Unfortunately, 1476 * written to the trace buffer is the SPU PC that we want. Unfortunately,
@@ -1656,7 +1656,7 @@ static void cell_handle_interrupt_ppu(struct pt_regs *regs,
1656 * The counters were frozen by the interrupt. 1656 * The counters were frozen by the interrupt.
1657 * Reenable the interrupt and restart the counters. 1657 * Reenable the interrupt and restart the counters.
1658 * If there was a race between the interrupt handler and 1658 * If there was a race between the interrupt handler and
1659 * the virtual counter routine. The virutal counter 1659 * the virtual counter routine. The virtual counter
1660 * routine may have cleared the interrupts. Hence must 1660 * routine may have cleared the interrupts. Hence must
1661 * use the virt_cntr_inter_mask to re-enable the interrupts. 1661 * use the virt_cntr_inter_mask to re-enable the interrupts.
1662 */ 1662 */
diff --git a/arch/powerpc/oprofile/op_model_power4.c b/arch/powerpc/oprofile/op_model_power4.c
index 80774092db77..8ee51a252cf1 100644
--- a/arch/powerpc/oprofile/op_model_power4.c
+++ b/arch/powerpc/oprofile/op_model_power4.c
@@ -207,7 +207,7 @@ static unsigned long get_pc(struct pt_regs *regs)
207 unsigned long mmcra; 207 unsigned long mmcra;
208 unsigned long slot; 208 unsigned long slot;
209 209
210 /* Cant do much about it */ 210 /* Can't do much about it */
211 if (!cur_cpu_spec->oprofile_mmcra_sihv) 211 if (!cur_cpu_spec->oprofile_mmcra_sihv)
212 return pc; 212 return pc;
213 213