3 files changed, 7 insertions, 2 deletions

diff --git a/arch/powerpc/mm/hash_utils_64.c b/arch/powerpc/mm/hash_utils_64.c
index f09730bf3a33..cbbd8b0bc8f4 100644
--- a/arch/powerpc/mm/hash_utils_64.c
+++ b/arch/powerpc/mm/hash_utils_64.c
@@ -96,6 +96,7 @@ int mmu_vmalloc_psize = MMU_PAGE_4K;
 int mmu_io_psize = MMU_PAGE_4K;
 int mmu_kernel_ssize = MMU_SEGSIZE_256M;
 int mmu_highuser_ssize = MMU_SEGSIZE_256M;
+u16 mmu_slb_size = 64;
 #ifdef CONFIG_HUGETLB_PAGE
 int mmu_huge_psize = MMU_PAGE_16M;
 unsigned int HPAGE_SHIFT;
diff --git a/arch/powerpc/mm/slb.c b/arch/powerpc/mm/slb.c
index 27922dff8b94..3cf0802cd2b6 100644
--- a/arch/powerpc/mm/slb.c
+++ b/arch/powerpc/mm/slb.c
@@ -256,6 +256,7 @@ void slb_initialize(void)
         static int slb_encoding_inited;
         extern unsigned int *slb_miss_kernel_load_linear;
         extern unsigned int *slb_miss_kernel_load_io;
+        extern unsigned int *slb_compare_rr_to_size;
 
         /* Prepare our SLB miss handler based on our page size */
         linear_llp = mmu_psize_defs[mmu_linear_psize].sllp;
@@ -269,6 +270,8 @@ void slb_initialize(void)
                                    SLB_VSID_KERNEL | linear_llp);
                 patch_slb_encoding(slb_miss_kernel_load_io,
                                    SLB_VSID_KERNEL | io_llp);
+                patch_slb_encoding(slb_compare_rr_to_size,
+                                   mmu_slb_size);
 
                 DBG("SLB: linear  LLP = %04x\n", linear_llp);
                 DBG("SLB: io      LLP = %04x\n", io_llp);
diff --git a/arch/powerpc/mm/slb_low.S b/arch/powerpc/mm/slb_low.S
index 1328a81a84aa..657f6b37e9df 100644
--- a/arch/powerpc/mm/slb_low.S
+++ b/arch/powerpc/mm/slb_low.S
@@ -227,8 +227,9 @@ END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES)
 
 7:      ld      r10,PACASTABRR(r13)
         addi    r10,r10,1
-        /* use a cpu feature mask if we ever change our slb size */
-        cmpldi  r10,SLB_NUM_ENTRIES
+        /* This gets soft patched on boot. */
+_GLOBAL(slb_compare_rr_to_size)
+        cmpldi  r10,0
 
         blt+    4f
         li      r10,SLB_NUM_BOLTED