2 files changed, 21 insertions, 1 deletions

diff --git a/arch/powerpc/mm/dma-noncoherent.c b/arch/powerpc/mm/dma-noncoherent.c
index 757c0bed9a91..b42f76c4948d 100644
--- a/arch/powerpc/mm/dma-noncoherent.c
+++ b/arch/powerpc/mm/dma-noncoherent.c
@@ -399,3 +399,23 @@ void __dma_sync_page(struct page *page, unsigned long offset,
 #endif
 }
 EXPORT_SYMBOL(__dma_sync_page);
+
+/*
+ * Return the PFN for a given cpu virtual address returned by
+ * __dma_alloc_coherent. This is used by dma_mmap_coherent()
+ */
+unsigned long __dma_get_coherent_pfn(unsigned long cpu_addr)
+{
+        /* This should always be populated, so we don't test every
+         * level. If that fails, we'll have a nice crash which
+         * will be as good as a BUG_ON()
+         */
+        pgd_t *pgd = pgd_offset_k(cpu_addr);
+        pud_t *pud = pud_offset(pgd, cpu_addr);
+        pmd_t *pmd = pmd_offset(pud, cpu_addr);
+        pte_t *ptep = pte_offset_kernel(pmd, cpu_addr);
+
+        if (pte_none(*ptep) || !pte_present(*ptep))
+                return 0;
+        return pte_pfn(*ptep);
+}
diff --git a/arch/powerpc/mm/tlb_low_64e.S b/arch/powerpc/mm/tlb_low_64e.S
index 8526bd9d2aa3..222815112e45 100644
--- a/arch/powerpc/mm/tlb_low_64e.S
+++ b/arch/powerpc/mm/tlb_low_64e.S
@@ -431,7 +431,7 @@ virt_page_table_tlb_miss_fault:
          * The thing is, we know that in normal circumstances, this is
          * always called as a second level tlb miss for SW load or as a first
          * level TLB miss for HW load, so we should be able to peek at the
-         * relevant informations in the first exception frame in the PACA.
+         * relevant information in the first exception frame in the PACA.
          *
          * However, we do need to double check that, because we may just hit
          * a stray kernel pointer or a userland attack trying to hit those