3 files changed, 12 insertions, 20 deletions

diff --git a/arch/powerpc/mm/hugetlbpage.c b/arch/powerpc/mm/hugetlbpage.c
index 1bb20d841080..8c77c791f87e 100644
--- a/arch/powerpc/mm/hugetlbpage.c
+++ b/arch/powerpc/mm/hugetlbpage.c
@@ -1014,7 +1014,6 @@ repeat:
 
                 /* Primary is full, try the secondary */
                 if (unlikely(slot == -1)) {
-                        new_pte |= _PAGE_F_SECOND;
                         hpte_group = ((~hash & htab_hash_mask) *
                                       HPTES_PER_GROUP) & ~0x7UL; 
                         slot = ppc_md.hpte_insert(hpte_group, va, pa, rflags,
@@ -1033,7 +1032,7 @@ repeat:
                 if (unlikely(slot == -2))
                         panic("hash_huge_page: pte_insert failed\n");
 
-                new_pte |= (slot << 12) & _PAGE_F_GIX;
+                new_pte |= (slot << 12) & (_PAGE_F_SECOND | _PAGE_F_GIX);
         }
 
         /*
diff --git a/arch/powerpc/mm/mem.c b/arch/powerpc/mm/mem.c
index d1c0758c5611..77b4637097e9 100644
--- a/arch/powerpc/mm/mem.c
+++ b/arch/powerpc/mm/mem.c
@@ -61,10 +61,6 @@ unsigned long memory_limit;
 extern void hash_preload(struct mm_struct *mm, unsigned long ea,
                          unsigned long access, unsigned long trap);
 
-/*
- * This is called by /dev/mem to know if a given address has to
- * be mapped non-cacheable or not
- */
 int page_is_ram(unsigned long pfn)
 {
         unsigned long paddr = (pfn << PAGE_SHIFT);
@@ -490,19 +486,19 @@ void update_mmu_cache(struct vm_area_struct *vma, unsigned long address,
             !cpu_has_feature(CPU_FTR_NOEXECUTE) &&
             pfn_valid(pfn)) {
                 struct page *page = pfn_to_page(pfn);
+#ifdef CONFIG_8xx
+                /* On 8xx, cache control instructions (particularly
+                 * "dcbst" from flush_dcache_icache) fault as write
+                 * operation if there is an unpopulated TLB entry
+                 * for the address in question. To workaround that,
+                 * we invalidate the TLB here, thus avoiding dcbst
+                 * misbehaviour.
+                 */
+                _tlbie(address);
+#endif
                 if (!PageReserved(page)
                     && !test_bit(PG_arch_1, &page->flags)) {
                         if (vma->vm_mm == current->active_mm) {
-#ifdef CONFIG_8xx
-                        /* On 8xx, cache control instructions (particularly 
-                         * "dcbst" from flush_dcache_icache) fault as write 
-                         * operation if there is an unpopulated TLB entry 
-                         * for the address in question. To workaround that, 
-                         * we invalidate the TLB here, thus avoiding dcbst 
-                         * misbehaviour.
-                         */
-                                _tlbie(address);
-#endif
                                 __flush_dcache_icache((void *) address);
                         } else
                                 flush_dcache_icache_page(page);
diff --git a/arch/powerpc/mm/pgtable_32.c b/arch/powerpc/mm/pgtable_32.c
index 1891dbeeb8e9..bd02272bcb0f 100644
--- a/arch/powerpc/mm/pgtable_32.c
+++ b/arch/powerpc/mm/pgtable_32.c
@@ -294,11 +294,8 @@ void __init mapin_ram(void)
         }
 }
 
-/* is x a power of 2? */
-#define is_power_of_2(x)        ((x) != 0 && (((x) & ((x) - 1)) == 0))
-
 /* is x a power of 4? */
-#define is_power_of_4(x)        ((x) != 0 && (((x) & (x-1)) == 0) && (ffs(x) & 1))
+#define is_power_of_4(x)        is_power_of_2(x) && (ffs(x) & 1))
 
 /*
  * Set up a mapping for a block of I/O.