1 files changed, 5 insertions, 5 deletions

diff --git a/arch/powerpc/mm/slb.c b/arch/powerpc/mm/slb.c
index 1d98ecc8eecd..e22276cb67a4 100644
--- a/arch/powerpc/mm/slb.c
+++ b/arch/powerpc/mm/slb.c
@@ -24,6 +24,7 @@
 #include <asm/firmware.h>
 #include <linux/compiler.h>
 #include <asm/udbg.h>
+#include <asm/code-patching.h>
 
 
 extern void slb_allocate_realmode(unsigned long ea);
@@ -166,7 +167,7 @@ static inline int esids_match(unsigned long addr1, unsigned long addr2)
         int esid_1t_count;
 
         /* System is not 1T segment size capable. */
-        if (!cpu_has_feature(CPU_FTR_1T_SEGMENT))
+        if (!mmu_has_feature(MMU_FTR_1T_SEGMENT))
                 return (GET_ESID(addr1) == GET_ESID(addr2));
 
         esid_1t_count = (((addr1 >> SID_SHIFT_1T) != 0) +
@@ -201,7 +202,7 @@ void switch_slb(struct task_struct *tsk, struct mm_struct *mm)
          */
         hard_irq_disable();
         offset = get_paca()->slb_cache_ptr;
-        if (!cpu_has_feature(CPU_FTR_NO_SLBIE_B) &&
+        if (!mmu_has_feature(MMU_FTR_NO_SLBIE_B) &&
             offset <= SLB_CACHE_ENTRIES) {
                 int i;
                 asm volatile("isync" : : : "memory");
@@ -249,9 +250,8 @@ void switch_slb(struct task_struct *tsk, struct mm_struct *mm)
 static inline void patch_slb_encoding(unsigned int *insn_addr,
                                       unsigned int immed)
 {
-        *insn_addr = (*insn_addr & 0xffff0000) | immed;
-        flush_icache_range((unsigned long)insn_addr, 4+
-                           (unsigned long)insn_addr);
+        int insn = (*insn_addr & 0xffff0000) | immed;
+        patch_instruction(insn_addr, insn);
 }
 
 void slb_set_size(u16 size)