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-rw-r--r--arch/powerpc/mm/ppc_mmu_32.c10
1 files changed, 0 insertions, 10 deletions
diff --git a/arch/powerpc/mm/ppc_mmu_32.c b/arch/powerpc/mm/ppc_mmu_32.c
index 1df731e42b50..ab5cd724b122 100644
--- a/arch/powerpc/mm/ppc_mmu_32.c
+++ b/arch/powerpc/mm/ppc_mmu_32.c
@@ -42,11 +42,7 @@ unsigned long _SDR1;
42 42
43union ubat { /* BAT register values to be loaded */ 43union ubat { /* BAT register values to be loaded */
44 BAT bat; 44 BAT bat;
45#ifdef CONFIG_PPC64BRIDGE
46 u64 word[2];
47#else
48 u32 word[2]; 45 u32 word[2];
49#endif
50} BATS[4][2]; /* 4 pairs of IBAT, DBAT */ 46} BATS[4][2]; /* 4 pairs of IBAT, DBAT */
51 47
52struct batrange { /* stores address ranges mapped by BATs */ 48struct batrange { /* stores address ranges mapped by BATs */
@@ -220,15 +216,9 @@ void __init MMU_init_hw(void)
220 216
221 if ( ppc_md.progress ) ppc_md.progress("hash:enter", 0x105); 217 if ( ppc_md.progress ) ppc_md.progress("hash:enter", 0x105);
222 218
223#ifdef CONFIG_PPC64BRIDGE
224#define LG_HPTEG_SIZE 7 /* 128 bytes per HPTEG */
225#define SDR1_LOW_BITS (lg_n_hpteg - 11)
226#define MIN_N_HPTEG 2048 /* min 256kB hash table */
227#else
228#define LG_HPTEG_SIZE 6 /* 64 bytes per HPTEG */ 219#define LG_HPTEG_SIZE 6 /* 64 bytes per HPTEG */
229#define SDR1_LOW_BITS ((n_hpteg - 1) >> 10) 220#define SDR1_LOW_BITS ((n_hpteg - 1) >> 10)
230#define MIN_N_HPTEG 1024 /* min 64kB hash table */ 221#define MIN_N_HPTEG 1024 /* min 64kB hash table */
231#endif
232 222
233 /* 223 /*
234 * Allow 1 HPTE (1/8 HPTEG) for each page of memory. 224 * Allow 1 HPTE (1/8 HPTEG) for each page of memory.